ixgbe_dcb.c revision 1.1.2.3
1 1.1.2.2 skrll /****************************************************************************** 2 1.1.2.2 skrll 3 1.1.2.3 skrll Copyright (c) 2001-2015, Intel Corporation 4 1.1.2.2 skrll All rights reserved. 5 1.1.2.2 skrll 6 1.1.2.2 skrll Redistribution and use in source and binary forms, with or without 7 1.1.2.2 skrll modification, are permitted provided that the following conditions are met: 8 1.1.2.2 skrll 9 1.1.2.2 skrll 1. Redistributions of source code must retain the above copyright notice, 10 1.1.2.2 skrll this list of conditions and the following disclaimer. 11 1.1.2.2 skrll 12 1.1.2.2 skrll 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll 16 1.1.2.2 skrll 3. Neither the name of the Intel Corporation nor the names of its 17 1.1.2.2 skrll contributors may be used to endorse or promote products derived from 18 1.1.2.2 skrll this software without specific prior written permission. 19 1.1.2.2 skrll 20 1.1.2.2 skrll THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.1.2.2 skrll AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.1.2.2 skrll IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.1.2.2 skrll ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.1.2.2 skrll LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.1.2.2 skrll CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.1.2.2 skrll SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.1.2.2 skrll INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.1.2.2 skrll CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.1.2.2 skrll ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.1.2.2 skrll POSSIBILITY OF SUCH DAMAGE. 31 1.1.2.2 skrll 32 1.1.2.2 skrll ******************************************************************************/ 33 1.1.2.3 skrll /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_dcb.c 292674 2015-12-23 22:45:17Z sbruno $*/ 34 1.1.2.2 skrll 35 1.1.2.2 skrll 36 1.1.2.2 skrll #include "ixgbe_type.h" 37 1.1.2.2 skrll #include "ixgbe_dcb.h" 38 1.1.2.2 skrll #include "ixgbe_dcb_82598.h" 39 1.1.2.2 skrll #include "ixgbe_dcb_82599.h" 40 1.1.2.2 skrll 41 1.1.2.2 skrll /** 42 1.1.2.2 skrll * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class 43 1.1.2.2 skrll * credits from the configured bandwidth percentages. Credits 44 1.1.2.2 skrll * are the smallest unit programmable into the underlying 45 1.1.2.2 skrll * hardware. The IEEE 802.1Qaz specification do not use bandwidth 46 1.1.2.2 skrll * groups so this is much simplified from the CEE case. 47 1.1.2.2 skrll */ 48 1.1.2.2 skrll s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max, 49 1.1.2.2 skrll int max_frame_size) 50 1.1.2.2 skrll { 51 1.1.2.2 skrll int min_percent = 100; 52 1.1.2.2 skrll int min_credit, multiplier; 53 1.1.2.2 skrll int i; 54 1.1.2.2 skrll 55 1.1.2.2 skrll min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) / 56 1.1.2.2 skrll IXGBE_DCB_CREDIT_QUANTUM; 57 1.1.2.2 skrll 58 1.1.2.2 skrll for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 59 1.1.2.2 skrll if (bw[i] < min_percent && bw[i]) 60 1.1.2.2 skrll min_percent = bw[i]; 61 1.1.2.2 skrll } 62 1.1.2.2 skrll 63 1.1.2.2 skrll multiplier = (min_credit / min_percent) + 1; 64 1.1.2.2 skrll 65 1.1.2.2 skrll /* Find out the hw credits for each TC */ 66 1.1.2.2 skrll for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 67 1.1.2.2 skrll int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL); 68 1.1.2.2 skrll 69 1.1.2.2 skrll if (val < min_credit) 70 1.1.2.2 skrll val = min_credit; 71 1.1.2.2 skrll refill[i] = (u16)val; 72 1.1.2.2 skrll 73 1.1.2.2 skrll max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit; 74 1.1.2.2 skrll } 75 1.1.2.2 skrll 76 1.1.2.2 skrll return 0; 77 1.1.2.2 skrll } 78 1.1.2.2 skrll 79 1.1.2.2 skrll /** 80 1.1.2.2 skrll * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits 81 1.1.2.2 skrll * @ixgbe_dcb_config: Struct containing DCB settings. 82 1.1.2.2 skrll * @direction: Configuring either Tx or Rx. 83 1.1.2.2 skrll * 84 1.1.2.2 skrll * This function calculates the credits allocated to each traffic class. 85 1.1.2.2 skrll * It should be called only after the rules are checked by 86 1.1.2.2 skrll * ixgbe_dcb_check_config_cee(). 87 1.1.2.2 skrll */ 88 1.1.2.2 skrll s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw, 89 1.1.2.2 skrll struct ixgbe_dcb_config *dcb_config, 90 1.1.2.2 skrll u32 max_frame_size, u8 direction) 91 1.1.2.2 skrll { 92 1.1.2.2 skrll struct ixgbe_dcb_tc_path *p; 93 1.1.2.2 skrll u32 min_multiplier = 0; 94 1.1.2.2 skrll u16 min_percent = 100; 95 1.1.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 96 1.1.2.2 skrll /* Initialization values default for Tx settings */ 97 1.1.2.2 skrll u32 min_credit = 0; 98 1.1.2.2 skrll u32 credit_refill = 0; 99 1.1.2.2 skrll u32 credit_max = 0; 100 1.1.2.2 skrll u16 link_percentage = 0; 101 1.1.2.2 skrll u8 bw_percent = 0; 102 1.1.2.2 skrll u8 i; 103 1.1.2.2 skrll 104 1.1.2.2 skrll if (dcb_config == NULL) { 105 1.1.2.2 skrll ret_val = IXGBE_ERR_CONFIG; 106 1.1.2.2 skrll goto out; 107 1.1.2.2 skrll } 108 1.1.2.2 skrll 109 1.1.2.2 skrll min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) / 110 1.1.2.2 skrll IXGBE_DCB_CREDIT_QUANTUM; 111 1.1.2.2 skrll 112 1.1.2.2 skrll /* Find smallest link percentage */ 113 1.1.2.2 skrll for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 114 1.1.2.2 skrll p = &dcb_config->tc_config[i].path[direction]; 115 1.1.2.2 skrll bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 116 1.1.2.2 skrll link_percentage = p->bwg_percent; 117 1.1.2.2 skrll 118 1.1.2.2 skrll link_percentage = (link_percentage * bw_percent) / 100; 119 1.1.2.2 skrll 120 1.1.2.2 skrll if (link_percentage && link_percentage < min_percent) 121 1.1.2.2 skrll min_percent = link_percentage; 122 1.1.2.2 skrll } 123 1.1.2.2 skrll 124 1.1.2.2 skrll /* 125 1.1.2.2 skrll * The ratio between traffic classes will control the bandwidth 126 1.1.2.2 skrll * percentages seen on the wire. To calculate this ratio we use 127 1.1.2.2 skrll * a multiplier. It is required that the refill credits must be 128 1.1.2.2 skrll * larger than the max frame size so here we find the smallest 129 1.1.2.2 skrll * multiplier that will allow all bandwidth percentages to be 130 1.1.2.2 skrll * greater than the max frame size. 131 1.1.2.2 skrll */ 132 1.1.2.2 skrll min_multiplier = (min_credit / min_percent) + 1; 133 1.1.2.2 skrll 134 1.1.2.2 skrll /* Find out the link percentage for each TC first */ 135 1.1.2.2 skrll for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 136 1.1.2.2 skrll p = &dcb_config->tc_config[i].path[direction]; 137 1.1.2.2 skrll bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 138 1.1.2.2 skrll 139 1.1.2.2 skrll link_percentage = p->bwg_percent; 140 1.1.2.2 skrll /* Must be careful of integer division for very small nums */ 141 1.1.2.2 skrll link_percentage = (link_percentage * bw_percent) / 100; 142 1.1.2.2 skrll if (p->bwg_percent > 0 && link_percentage == 0) 143 1.1.2.2 skrll link_percentage = 1; 144 1.1.2.2 skrll 145 1.1.2.2 skrll /* Save link_percentage for reference */ 146 1.1.2.2 skrll p->link_percent = (u8)link_percentage; 147 1.1.2.2 skrll 148 1.1.2.2 skrll /* Calculate credit refill ratio using multiplier */ 149 1.1.2.2 skrll credit_refill = min(link_percentage * min_multiplier, 150 1.1.2.2 skrll (u32)IXGBE_DCB_MAX_CREDIT_REFILL); 151 1.1.2.3 skrll 152 1.1.2.3 skrll /* Refill at least minimum credit */ 153 1.1.2.3 skrll if (credit_refill < min_credit) 154 1.1.2.3 skrll credit_refill = min_credit; 155 1.1.2.3 skrll 156 1.1.2.2 skrll p->data_credits_refill = (u16)credit_refill; 157 1.1.2.2 skrll 158 1.1.2.2 skrll /* Calculate maximum credit for the TC */ 159 1.1.2.2 skrll credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100; 160 1.1.2.2 skrll 161 1.1.2.2 skrll /* 162 1.1.2.2 skrll * Adjustment based on rule checking, if the percentage 163 1.1.2.2 skrll * of a TC is too small, the maximum credit may not be 164 1.1.2.2 skrll * enough to send out a jumbo frame in data plane arbitration. 165 1.1.2.2 skrll */ 166 1.1.2.3 skrll if (credit_max < min_credit) 167 1.1.2.2 skrll credit_max = min_credit; 168 1.1.2.2 skrll 169 1.1.2.2 skrll if (direction == IXGBE_DCB_TX_CONFIG) { 170 1.1.2.2 skrll /* 171 1.1.2.2 skrll * Adjustment based on rule checking, if the 172 1.1.2.2 skrll * percentage of a TC is too small, the maximum 173 1.1.2.2 skrll * credit may not be enough to send out a TSO 174 1.1.2.2 skrll * packet in descriptor plane arbitration. 175 1.1.2.2 skrll */ 176 1.1.2.2 skrll if (credit_max && (credit_max < 177 1.1.2.2 skrll IXGBE_DCB_MIN_TSO_CREDIT) 178 1.1.2.2 skrll && (hw->mac.type == ixgbe_mac_82598EB)) 179 1.1.2.2 skrll credit_max = IXGBE_DCB_MIN_TSO_CREDIT; 180 1.1.2.2 skrll 181 1.1.2.2 skrll dcb_config->tc_config[i].desc_credits_max = 182 1.1.2.2 skrll (u16)credit_max; 183 1.1.2.2 skrll } 184 1.1.2.2 skrll 185 1.1.2.2 skrll p->data_credits_max = (u16)credit_max; 186 1.1.2.2 skrll } 187 1.1.2.2 skrll 188 1.1.2.2 skrll out: 189 1.1.2.2 skrll return ret_val; 190 1.1.2.2 skrll } 191 1.1.2.2 skrll 192 1.1.2.2 skrll /** 193 1.1.2.2 skrll * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info 194 1.1.2.2 skrll * @cfg: dcb configuration to unpack into hardware consumable fields 195 1.1.2.2 skrll * @map: user priority to traffic class map 196 1.1.2.2 skrll * @pfc_up: u8 to store user priority PFC bitmask 197 1.1.2.2 skrll * 198 1.1.2.2 skrll * This unpacks the dcb configuration PFC info which is stored per 199 1.1.2.2 skrll * traffic class into a 8bit user priority bitmask that can be 200 1.1.2.2 skrll * consumed by hardware routines. The priority to tc map must be 201 1.1.2.2 skrll * updated before calling this routine to use current up-to maps. 202 1.1.2.2 skrll */ 203 1.1.2.2 skrll void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up) 204 1.1.2.2 skrll { 205 1.1.2.2 skrll struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 206 1.1.2.2 skrll int up; 207 1.1.2.2 skrll 208 1.1.2.2 skrll /* 209 1.1.2.2 skrll * If the TC for this user priority has PFC enabled then set the 210 1.1.2.2 skrll * matching bit in 'pfc_up' to reflect that PFC is enabled. 211 1.1.2.2 skrll */ 212 1.1.2.2 skrll for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) { 213 1.1.2.2 skrll if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled) 214 1.1.2.2 skrll *pfc_up |= 1 << up; 215 1.1.2.2 skrll } 216 1.1.2.2 skrll } 217 1.1.2.2 skrll 218 1.1.2.2 skrll void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction, 219 1.1.2.2 skrll u16 *refill) 220 1.1.2.2 skrll { 221 1.1.2.2 skrll struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 222 1.1.2.2 skrll int tc; 223 1.1.2.2 skrll 224 1.1.2.2 skrll for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 225 1.1.2.2 skrll refill[tc] = tc_config[tc].path[direction].data_credits_refill; 226 1.1.2.2 skrll } 227 1.1.2.2 skrll 228 1.1.2.2 skrll void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max) 229 1.1.2.2 skrll { 230 1.1.2.2 skrll struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 231 1.1.2.2 skrll int tc; 232 1.1.2.2 skrll 233 1.1.2.2 skrll for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 234 1.1.2.2 skrll max[tc] = tc_config[tc].desc_credits_max; 235 1.1.2.2 skrll } 236 1.1.2.2 skrll 237 1.1.2.2 skrll void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction, 238 1.1.2.2 skrll u8 *bwgid) 239 1.1.2.2 skrll { 240 1.1.2.2 skrll struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 241 1.1.2.2 skrll int tc; 242 1.1.2.2 skrll 243 1.1.2.2 skrll for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 244 1.1.2.2 skrll bwgid[tc] = tc_config[tc].path[direction].bwg_id; 245 1.1.2.2 skrll } 246 1.1.2.2 skrll 247 1.1.2.2 skrll void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction, 248 1.1.2.2 skrll u8 *tsa) 249 1.1.2.2 skrll { 250 1.1.2.2 skrll struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 251 1.1.2.2 skrll int tc; 252 1.1.2.2 skrll 253 1.1.2.2 skrll for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 254 1.1.2.2 skrll tsa[tc] = tc_config[tc].path[direction].tsa; 255 1.1.2.2 skrll } 256 1.1.2.2 skrll 257 1.1.2.2 skrll u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up) 258 1.1.2.2 skrll { 259 1.1.2.2 skrll struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 260 1.1.2.2 skrll u8 prio_mask = 1 << up; 261 1.1.2.2 skrll u8 tc = cfg->num_tcs.pg_tcs; 262 1.1.2.2 skrll 263 1.1.2.2 skrll /* If tc is 0 then DCB is likely not enabled or supported */ 264 1.1.2.2 skrll if (!tc) 265 1.1.2.2 skrll goto out; 266 1.1.2.2 skrll 267 1.1.2.2 skrll /* 268 1.1.2.2 skrll * Test from maximum TC to 1 and report the first match we find. If 269 1.1.2.2 skrll * we find no match we can assume that the TC is 0 since the TC must 270 1.1.2.2 skrll * be set for all user priorities 271 1.1.2.2 skrll */ 272 1.1.2.2 skrll for (tc--; tc; tc--) { 273 1.1.2.2 skrll if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap) 274 1.1.2.2 skrll break; 275 1.1.2.2 skrll } 276 1.1.2.2 skrll out: 277 1.1.2.2 skrll return tc; 278 1.1.2.2 skrll } 279 1.1.2.2 skrll 280 1.1.2.2 skrll void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction, 281 1.1.2.2 skrll u8 *map) 282 1.1.2.2 skrll { 283 1.1.2.2 skrll u8 up; 284 1.1.2.2 skrll 285 1.1.2.2 skrll for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) 286 1.1.2.2 skrll map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up); 287 1.1.2.2 skrll } 288 1.1.2.2 skrll 289 1.1.2.2 skrll /** 290 1.1.2.2 skrll * ixgbe_dcb_config - Struct containing DCB settings. 291 1.1.2.2 skrll * @dcb_config: Pointer to DCB config structure 292 1.1.2.2 skrll * 293 1.1.2.2 skrll * This function checks DCB rules for DCB settings. 294 1.1.2.2 skrll * The following rules are checked: 295 1.1.2.2 skrll * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%. 296 1.1.2.2 skrll * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth 297 1.1.2.2 skrll * Group must total 100. 298 1.1.2.2 skrll * 3. A Traffic Class should not be set to both Link Strict Priority 299 1.1.2.2 skrll * and Group Strict Priority. 300 1.1.2.2 skrll * 4. Link strict Bandwidth Groups can only have link strict traffic classes 301 1.1.2.2 skrll * with zero bandwidth. 302 1.1.2.2 skrll */ 303 1.1.2.2 skrll s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config) 304 1.1.2.2 skrll { 305 1.1.2.2 skrll struct ixgbe_dcb_tc_path *p; 306 1.1.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 307 1.1.2.2 skrll u8 i, j, bw = 0, bw_id; 308 1.1.2.2 skrll u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP]; 309 1.1.2.2 skrll bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP]; 310 1.1.2.2 skrll 311 1.1.2.2 skrll memset(bw_sum, 0, sizeof(bw_sum)); 312 1.1.2.2 skrll memset(link_strict, 0, sizeof(link_strict)); 313 1.1.2.2 skrll 314 1.1.2.2 skrll /* First Tx, then Rx */ 315 1.1.2.2 skrll for (i = 0; i < 2; i++) { 316 1.1.2.2 skrll /* Check each traffic class for rule violation */ 317 1.1.2.2 skrll for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) { 318 1.1.2.2 skrll p = &dcb_config->tc_config[j].path[i]; 319 1.1.2.2 skrll 320 1.1.2.2 skrll bw = p->bwg_percent; 321 1.1.2.2 skrll bw_id = p->bwg_id; 322 1.1.2.2 skrll 323 1.1.2.2 skrll if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) { 324 1.1.2.2 skrll ret_val = IXGBE_ERR_CONFIG; 325 1.1.2.2 skrll goto err_config; 326 1.1.2.2 skrll } 327 1.1.2.2 skrll if (p->tsa == ixgbe_dcb_tsa_strict) { 328 1.1.2.2 skrll link_strict[i][bw_id] = TRUE; 329 1.1.2.2 skrll /* Link strict should have zero bandwidth */ 330 1.1.2.2 skrll if (bw) { 331 1.1.2.2 skrll ret_val = IXGBE_ERR_CONFIG; 332 1.1.2.2 skrll goto err_config; 333 1.1.2.2 skrll } 334 1.1.2.2 skrll } else if (!bw) { 335 1.1.2.2 skrll /* 336 1.1.2.2 skrll * Traffic classes without link strict 337 1.1.2.2 skrll * should have non-zero bandwidth. 338 1.1.2.2 skrll */ 339 1.1.2.2 skrll ret_val = IXGBE_ERR_CONFIG; 340 1.1.2.2 skrll goto err_config; 341 1.1.2.2 skrll } 342 1.1.2.2 skrll bw_sum[i][bw_id] += bw; 343 1.1.2.2 skrll } 344 1.1.2.2 skrll 345 1.1.2.2 skrll bw = 0; 346 1.1.2.2 skrll 347 1.1.2.2 skrll /* Check each bandwidth group for rule violation */ 348 1.1.2.2 skrll for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) { 349 1.1.2.2 skrll bw += dcb_config->bw_percentage[i][j]; 350 1.1.2.2 skrll /* 351 1.1.2.2 skrll * Sum of bandwidth percentages of all traffic classes 352 1.1.2.2 skrll * within a Bandwidth Group must total 100 except for 353 1.1.2.2 skrll * link strict group (zero bandwidth). 354 1.1.2.2 skrll */ 355 1.1.2.2 skrll if (link_strict[i][j]) { 356 1.1.2.2 skrll if (bw_sum[i][j]) { 357 1.1.2.2 skrll /* 358 1.1.2.2 skrll * Link strict group should have zero 359 1.1.2.2 skrll * bandwidth. 360 1.1.2.2 skrll */ 361 1.1.2.2 skrll ret_val = IXGBE_ERR_CONFIG; 362 1.1.2.2 skrll goto err_config; 363 1.1.2.2 skrll } 364 1.1.2.2 skrll } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT && 365 1.1.2.2 skrll bw_sum[i][j] != 0) { 366 1.1.2.2 skrll ret_val = IXGBE_ERR_CONFIG; 367 1.1.2.2 skrll goto err_config; 368 1.1.2.2 skrll } 369 1.1.2.2 skrll } 370 1.1.2.2 skrll 371 1.1.2.2 skrll if (bw != IXGBE_DCB_BW_PERCENT) { 372 1.1.2.2 skrll ret_val = IXGBE_ERR_CONFIG; 373 1.1.2.2 skrll goto err_config; 374 1.1.2.2 skrll } 375 1.1.2.2 skrll } 376 1.1.2.2 skrll 377 1.1.2.2 skrll err_config: 378 1.1.2.2 skrll DEBUGOUT2("DCB error code %d while checking %s settings.\n", 379 1.1.2.2 skrll ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx"); 380 1.1.2.2 skrll 381 1.1.2.2 skrll return ret_val; 382 1.1.2.2 skrll } 383 1.1.2.2 skrll 384 1.1.2.2 skrll /** 385 1.1.2.2 skrll * ixgbe_dcb_get_tc_stats - Returns status of each traffic class 386 1.1.2.2 skrll * @hw: pointer to hardware structure 387 1.1.2.2 skrll * @stats: pointer to statistics structure 388 1.1.2.2 skrll * @tc_count: Number of elements in bwg_array. 389 1.1.2.2 skrll * 390 1.1.2.2 skrll * This function returns the status data for each of the Traffic Classes in use. 391 1.1.2.2 skrll */ 392 1.1.2.2 skrll s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, 393 1.1.2.2 skrll u8 tc_count) 394 1.1.2.2 skrll { 395 1.1.2.2 skrll s32 ret = IXGBE_NOT_IMPLEMENTED; 396 1.1.2.2 skrll switch (hw->mac.type) { 397 1.1.2.2 skrll case ixgbe_mac_82598EB: 398 1.1.2.2 skrll ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count); 399 1.1.2.2 skrll break; 400 1.1.2.2 skrll case ixgbe_mac_82599EB: 401 1.1.2.2 skrll case ixgbe_mac_X540: 402 1.1.2.3 skrll case ixgbe_mac_X550: 403 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 404 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 405 1.1.2.2 skrll ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count); 406 1.1.2.2 skrll break; 407 1.1.2.2 skrll #endif 408 1.1.2.2 skrll default: 409 1.1.2.2 skrll break; 410 1.1.2.2 skrll } 411 1.1.2.2 skrll return ret; 412 1.1.2.2 skrll } 413 1.1.2.2 skrll 414 1.1.2.2 skrll /** 415 1.1.2.2 skrll * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class 416 1.1.2.2 skrll * @hw: pointer to hardware structure 417 1.1.2.2 skrll * @stats: pointer to statistics structure 418 1.1.2.2 skrll * @tc_count: Number of elements in bwg_array. 419 1.1.2.2 skrll * 420 1.1.2.2 skrll * This function returns the CBFC status data for each of the Traffic Classes. 421 1.1.2.2 skrll */ 422 1.1.2.2 skrll s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, 423 1.1.2.2 skrll u8 tc_count) 424 1.1.2.2 skrll { 425 1.1.2.2 skrll s32 ret = IXGBE_NOT_IMPLEMENTED; 426 1.1.2.2 skrll switch (hw->mac.type) { 427 1.1.2.2 skrll case ixgbe_mac_82598EB: 428 1.1.2.2 skrll ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count); 429 1.1.2.2 skrll break; 430 1.1.2.2 skrll case ixgbe_mac_82599EB: 431 1.1.2.2 skrll case ixgbe_mac_X540: 432 1.1.2.3 skrll case ixgbe_mac_X550: 433 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 434 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 435 1.1.2.2 skrll ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count); 436 1.1.2.2 skrll break; 437 1.1.2.2 skrll #endif 438 1.1.2.2 skrll default: 439 1.1.2.2 skrll break; 440 1.1.2.2 skrll } 441 1.1.2.2 skrll return ret; 442 1.1.2.2 skrll } 443 1.1.2.2 skrll 444 1.1.2.2 skrll /** 445 1.1.2.2 skrll * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter 446 1.1.2.2 skrll * @hw: pointer to hardware structure 447 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 448 1.1.2.2 skrll * 449 1.1.2.2 skrll * Configure Rx Data Arbiter and credits for each traffic class. 450 1.1.2.2 skrll */ 451 1.1.2.2 skrll s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw, 452 1.1.2.2 skrll struct ixgbe_dcb_config *dcb_config) 453 1.1.2.2 skrll { 454 1.1.2.2 skrll s32 ret = IXGBE_NOT_IMPLEMENTED; 455 1.1.2.2 skrll u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 456 1.1.2.2 skrll u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 457 1.1.2.2 skrll u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 458 1.1.2.2 skrll u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 459 1.1.2.2 skrll u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 460 1.1.2.2 skrll 461 1.1.2.2 skrll ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 462 1.1.2.2 skrll ixgbe_dcb_unpack_max_cee(dcb_config, max); 463 1.1.2.2 skrll ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 464 1.1.2.2 skrll ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 465 1.1.2.2 skrll ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 466 1.1.2.2 skrll 467 1.1.2.2 skrll switch (hw->mac.type) { 468 1.1.2.2 skrll case ixgbe_mac_82598EB: 469 1.1.2.2 skrll ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 470 1.1.2.2 skrll break; 471 1.1.2.2 skrll case ixgbe_mac_82599EB: 472 1.1.2.2 skrll case ixgbe_mac_X540: 473 1.1.2.3 skrll case ixgbe_mac_X550: 474 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 475 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 476 1.1.2.2 skrll ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid, 477 1.1.2.2 skrll tsa, map); 478 1.1.2.2 skrll break; 479 1.1.2.2 skrll #endif 480 1.1.2.2 skrll default: 481 1.1.2.2 skrll break; 482 1.1.2.2 skrll } 483 1.1.2.2 skrll return ret; 484 1.1.2.2 skrll } 485 1.1.2.2 skrll 486 1.1.2.2 skrll /** 487 1.1.2.2 skrll * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter 488 1.1.2.2 skrll * @hw: pointer to hardware structure 489 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 490 1.1.2.2 skrll * 491 1.1.2.2 skrll * Configure Tx Descriptor Arbiter and credits for each traffic class. 492 1.1.2.2 skrll */ 493 1.1.2.2 skrll s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw, 494 1.1.2.2 skrll struct ixgbe_dcb_config *dcb_config) 495 1.1.2.2 skrll { 496 1.1.2.2 skrll s32 ret = IXGBE_NOT_IMPLEMENTED; 497 1.1.2.2 skrll u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 498 1.1.2.2 skrll u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 499 1.1.2.2 skrll u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 500 1.1.2.2 skrll u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 501 1.1.2.2 skrll 502 1.1.2.2 skrll ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 503 1.1.2.2 skrll ixgbe_dcb_unpack_max_cee(dcb_config, max); 504 1.1.2.2 skrll ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 505 1.1.2.2 skrll ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 506 1.1.2.2 skrll 507 1.1.2.2 skrll switch (hw->mac.type) { 508 1.1.2.2 skrll case ixgbe_mac_82598EB: 509 1.1.2.2 skrll ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 510 1.1.2.2 skrll bwgid, tsa); 511 1.1.2.2 skrll break; 512 1.1.2.2 skrll case ixgbe_mac_82599EB: 513 1.1.2.2 skrll case ixgbe_mac_X540: 514 1.1.2.3 skrll case ixgbe_mac_X550: 515 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 516 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 517 1.1.2.2 skrll ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 518 1.1.2.2 skrll bwgid, tsa); 519 1.1.2.2 skrll break; 520 1.1.2.2 skrll #endif 521 1.1.2.2 skrll default: 522 1.1.2.2 skrll break; 523 1.1.2.2 skrll } 524 1.1.2.2 skrll return ret; 525 1.1.2.2 skrll } 526 1.1.2.2 skrll 527 1.1.2.2 skrll /** 528 1.1.2.2 skrll * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter 529 1.1.2.2 skrll * @hw: pointer to hardware structure 530 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 531 1.1.2.2 skrll * 532 1.1.2.2 skrll * Configure Tx Data Arbiter and credits for each traffic class. 533 1.1.2.2 skrll */ 534 1.1.2.2 skrll s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw, 535 1.1.2.2 skrll struct ixgbe_dcb_config *dcb_config) 536 1.1.2.2 skrll { 537 1.1.2.2 skrll s32 ret = IXGBE_NOT_IMPLEMENTED; 538 1.1.2.2 skrll u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 539 1.1.2.2 skrll u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 540 1.1.2.2 skrll u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 541 1.1.2.2 skrll u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 542 1.1.2.2 skrll u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 543 1.1.2.2 skrll 544 1.1.2.2 skrll ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 545 1.1.2.2 skrll ixgbe_dcb_unpack_max_cee(dcb_config, max); 546 1.1.2.2 skrll ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 547 1.1.2.2 skrll ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 548 1.1.2.2 skrll ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 549 1.1.2.2 skrll 550 1.1.2.2 skrll switch (hw->mac.type) { 551 1.1.2.2 skrll case ixgbe_mac_82598EB: 552 1.1.2.2 skrll ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 553 1.1.2.2 skrll bwgid, tsa); 554 1.1.2.2 skrll break; 555 1.1.2.2 skrll case ixgbe_mac_82599EB: 556 1.1.2.2 skrll case ixgbe_mac_X540: 557 1.1.2.3 skrll case ixgbe_mac_X550: 558 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 559 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 560 1.1.2.2 skrll ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 561 1.1.2.2 skrll bwgid, tsa, 562 1.1.2.2 skrll map); 563 1.1.2.2 skrll break; 564 1.1.2.2 skrll #endif 565 1.1.2.2 skrll default: 566 1.1.2.2 skrll break; 567 1.1.2.2 skrll } 568 1.1.2.2 skrll return ret; 569 1.1.2.2 skrll } 570 1.1.2.2 skrll 571 1.1.2.2 skrll /** 572 1.1.2.2 skrll * ixgbe_dcb_config_pfc_cee - Config priority flow control 573 1.1.2.2 skrll * @hw: pointer to hardware structure 574 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 575 1.1.2.2 skrll * 576 1.1.2.2 skrll * Configure Priority Flow Control for each traffic class. 577 1.1.2.2 skrll */ 578 1.1.2.2 skrll s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw, 579 1.1.2.2 skrll struct ixgbe_dcb_config *dcb_config) 580 1.1.2.2 skrll { 581 1.1.2.2 skrll s32 ret = IXGBE_NOT_IMPLEMENTED; 582 1.1.2.2 skrll u8 pfc_en; 583 1.1.2.2 skrll u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 584 1.1.2.2 skrll 585 1.1.2.2 skrll ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 586 1.1.2.2 skrll ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en); 587 1.1.2.2 skrll 588 1.1.2.2 skrll switch (hw->mac.type) { 589 1.1.2.2 skrll case ixgbe_mac_82598EB: 590 1.1.2.2 skrll ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en); 591 1.1.2.2 skrll break; 592 1.1.2.2 skrll case ixgbe_mac_82599EB: 593 1.1.2.2 skrll case ixgbe_mac_X540: 594 1.1.2.3 skrll case ixgbe_mac_X550: 595 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 596 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 597 1.1.2.2 skrll ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map); 598 1.1.2.2 skrll break; 599 1.1.2.2 skrll #endif 600 1.1.2.2 skrll default: 601 1.1.2.2 skrll break; 602 1.1.2.2 skrll } 603 1.1.2.2 skrll return ret; 604 1.1.2.2 skrll } 605 1.1.2.2 skrll 606 1.1.2.2 skrll /** 607 1.1.2.2 skrll * ixgbe_dcb_config_tc_stats - Config traffic class statistics 608 1.1.2.2 skrll * @hw: pointer to hardware structure 609 1.1.2.2 skrll * 610 1.1.2.2 skrll * Configure queue statistics registers, all queues belonging to same traffic 611 1.1.2.2 skrll * class uses a single set of queue statistics counters. 612 1.1.2.2 skrll */ 613 1.1.2.2 skrll s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw) 614 1.1.2.2 skrll { 615 1.1.2.2 skrll s32 ret = IXGBE_NOT_IMPLEMENTED; 616 1.1.2.2 skrll switch (hw->mac.type) { 617 1.1.2.2 skrll case ixgbe_mac_82598EB: 618 1.1.2.2 skrll ret = ixgbe_dcb_config_tc_stats_82598(hw); 619 1.1.2.2 skrll break; 620 1.1.2.2 skrll case ixgbe_mac_82599EB: 621 1.1.2.2 skrll case ixgbe_mac_X540: 622 1.1.2.3 skrll case ixgbe_mac_X550: 623 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 624 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 625 1.1.2.2 skrll ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL); 626 1.1.2.2 skrll break; 627 1.1.2.2 skrll #endif 628 1.1.2.2 skrll default: 629 1.1.2.2 skrll break; 630 1.1.2.2 skrll } 631 1.1.2.2 skrll return ret; 632 1.1.2.2 skrll } 633 1.1.2.2 skrll 634 1.1.2.2 skrll /** 635 1.1.2.2 skrll * ixgbe_dcb_hw_config_cee - Config and enable DCB 636 1.1.2.2 skrll * @hw: pointer to hardware structure 637 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 638 1.1.2.2 skrll * 639 1.1.2.2 skrll * Configure dcb settings and enable dcb mode. 640 1.1.2.2 skrll */ 641 1.1.2.2 skrll s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw, 642 1.1.2.2 skrll struct ixgbe_dcb_config *dcb_config) 643 1.1.2.2 skrll { 644 1.1.2.2 skrll s32 ret = IXGBE_NOT_IMPLEMENTED; 645 1.1.2.2 skrll u8 pfc_en; 646 1.1.2.2 skrll u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 647 1.1.2.2 skrll u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 648 1.1.2.2 skrll u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 649 1.1.2.2 skrll u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 650 1.1.2.2 skrll u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 651 1.1.2.2 skrll 652 1.1.2.2 skrll /* Unpack CEE standard containers */ 653 1.1.2.2 skrll ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 654 1.1.2.2 skrll ixgbe_dcb_unpack_max_cee(dcb_config, max); 655 1.1.2.2 skrll ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 656 1.1.2.2 skrll ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 657 1.1.2.2 skrll ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 658 1.1.2.2 skrll 659 1.1.2.2 skrll hw->mac.ops.setup_rxpba(hw, dcb_config->num_tcs.pg_tcs, 660 1.1.2.2 skrll 0, dcb_config->rx_pba_cfg); 661 1.1.2.2 skrll 662 1.1.2.2 skrll switch (hw->mac.type) { 663 1.1.2.2 skrll case ixgbe_mac_82598EB: 664 1.1.2.2 skrll ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed, 665 1.1.2.2 skrll refill, max, bwgid, tsa); 666 1.1.2.2 skrll break; 667 1.1.2.2 skrll case ixgbe_mac_82599EB: 668 1.1.2.2 skrll case ixgbe_mac_X540: 669 1.1.2.3 skrll case ixgbe_mac_X550: 670 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 671 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 672 1.1.2.2 skrll ixgbe_dcb_config_82599(hw, dcb_config); 673 1.1.2.2 skrll ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed, 674 1.1.2.2 skrll refill, max, bwgid, 675 1.1.2.2 skrll tsa, map); 676 1.1.2.2 skrll 677 1.1.2.2 skrll ixgbe_dcb_config_tc_stats_82599(hw, dcb_config); 678 1.1.2.2 skrll break; 679 1.1.2.2 skrll #endif 680 1.1.2.2 skrll default: 681 1.1.2.2 skrll break; 682 1.1.2.2 skrll } 683 1.1.2.2 skrll 684 1.1.2.2 skrll if (!ret && dcb_config->pfc_mode_enable) { 685 1.1.2.2 skrll ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en); 686 1.1.2.2 skrll ret = ixgbe_dcb_config_pfc(hw, pfc_en, map); 687 1.1.2.2 skrll } 688 1.1.2.2 skrll 689 1.1.2.2 skrll return ret; 690 1.1.2.2 skrll } 691 1.1.2.2 skrll 692 1.1.2.2 skrll /* Helper routines to abstract HW specifics from DCB netlink ops */ 693 1.1.2.2 skrll s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map) 694 1.1.2.2 skrll { 695 1.1.2.2 skrll int ret = IXGBE_ERR_PARAM; 696 1.1.2.2 skrll 697 1.1.2.2 skrll switch (hw->mac.type) { 698 1.1.2.2 skrll case ixgbe_mac_82598EB: 699 1.1.2.2 skrll ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en); 700 1.1.2.2 skrll break; 701 1.1.2.2 skrll case ixgbe_mac_82599EB: 702 1.1.2.2 skrll case ixgbe_mac_X540: 703 1.1.2.3 skrll case ixgbe_mac_X550: 704 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 705 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 706 1.1.2.2 skrll ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map); 707 1.1.2.2 skrll break; 708 1.1.2.2 skrll #endif 709 1.1.2.2 skrll default: 710 1.1.2.2 skrll break; 711 1.1.2.2 skrll } 712 1.1.2.2 skrll return ret; 713 1.1.2.2 skrll } 714 1.1.2.2 skrll 715 1.1.2.2 skrll s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, 716 1.1.2.2 skrll u8 *bwg_id, u8 *tsa, u8 *map) 717 1.1.2.2 skrll { 718 1.1.2.2 skrll switch (hw->mac.type) { 719 1.1.2.2 skrll case ixgbe_mac_82598EB: 720 1.1.2.2 skrll ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 721 1.1.2.2 skrll ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, 722 1.1.2.2 skrll tsa); 723 1.1.2.2 skrll ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, 724 1.1.2.2 skrll tsa); 725 1.1.2.2 skrll break; 726 1.1.2.2 skrll case ixgbe_mac_82599EB: 727 1.1.2.2 skrll case ixgbe_mac_X540: 728 1.1.2.3 skrll case ixgbe_mac_X550: 729 1.1.2.3 skrll case ixgbe_mac_X550EM_x: 730 1.1.2.2 skrll #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 731 1.1.2.2 skrll ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 732 1.1.2.2 skrll tsa, map); 733 1.1.2.2 skrll ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, 734 1.1.2.2 skrll tsa); 735 1.1.2.2 skrll ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, 736 1.1.2.2 skrll tsa, map); 737 1.1.2.2 skrll break; 738 1.1.2.2 skrll #endif 739 1.1.2.2 skrll default: 740 1.1.2.2 skrll break; 741 1.1.2.2 skrll } 742 1.1.2.2 skrll return 0; 743 1.1.2.2 skrll } 744
Indexes created Thu Oct 23 22:10:10 GMT 2025