ixgbe_dcb_82598.c revision 1.1.2.3
1 1.1.2.2 skrll /****************************************************************************** 2 1.1.2.2 skrll 3 1.1.2.3 skrll Copyright (c) 2001-2015, Intel Corporation 4 1.1.2.2 skrll All rights reserved. 5 1.1.2.2 skrll 6 1.1.2.2 skrll Redistribution and use in source and binary forms, with or without 7 1.1.2.2 skrll modification, are permitted provided that the following conditions are met: 8 1.1.2.2 skrll 9 1.1.2.2 skrll 1. Redistributions of source code must retain the above copyright notice, 10 1.1.2.2 skrll this list of conditions and the following disclaimer. 11 1.1.2.2 skrll 12 1.1.2.2 skrll 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll 16 1.1.2.2 skrll 3. Neither the name of the Intel Corporation nor the names of its 17 1.1.2.2 skrll contributors may be used to endorse or promote products derived from 18 1.1.2.2 skrll this software without specific prior written permission. 19 1.1.2.2 skrll 20 1.1.2.2 skrll THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.1.2.2 skrll AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.1.2.2 skrll IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.1.2.2 skrll ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.1.2.2 skrll LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.1.2.2 skrll CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.1.2.2 skrll SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.1.2.2 skrll INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.1.2.2 skrll CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.1.2.2 skrll ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.1.2.2 skrll POSSIBILITY OF SUCH DAMAGE. 31 1.1.2.2 skrll 32 1.1.2.2 skrll ******************************************************************************/ 33 1.1.2.3 skrll /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_dcb_82598.c 282289 2015-04-30 22:53:27Z erj $*/ 34 1.1.2.2 skrll 35 1.1.2.2 skrll 36 1.1.2.2 skrll #include "ixgbe_type.h" 37 1.1.2.2 skrll #include "ixgbe_dcb.h" 38 1.1.2.2 skrll #include "ixgbe_dcb_82598.h" 39 1.1.2.2 skrll 40 1.1.2.2 skrll /** 41 1.1.2.2 skrll * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class 42 1.1.2.2 skrll * @hw: pointer to hardware structure 43 1.1.2.2 skrll * @stats: pointer to statistics structure 44 1.1.2.2 skrll * @tc_count: Number of elements in bwg_array. 45 1.1.2.2 skrll * 46 1.1.2.2 skrll * This function returns the status data for each of the Traffic Classes in use. 47 1.1.2.2 skrll */ 48 1.1.2.2 skrll s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw, 49 1.1.2.2 skrll struct ixgbe_hw_stats *stats, 50 1.1.2.2 skrll u8 tc_count) 51 1.1.2.2 skrll { 52 1.1.2.2 skrll int tc; 53 1.1.2.2 skrll 54 1.1.2.2 skrll DEBUGFUNC("dcb_get_tc_stats"); 55 1.1.2.2 skrll 56 1.1.2.2 skrll if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS) 57 1.1.2.2 skrll return IXGBE_ERR_PARAM; 58 1.1.2.2 skrll 59 1.1.2.2 skrll /* Statistics pertaining to each traffic class */ 60 1.1.2.2 skrll for (tc = 0; tc < tc_count; tc++) { 61 1.1.2.2 skrll /* Transmitted Packets */ 62 1.1.2.2 skrll stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); 63 1.1.2.2 skrll /* Transmitted Bytes */ 64 1.1.2.2 skrll stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc)); 65 1.1.2.2 skrll /* Received Packets */ 66 1.1.2.2 skrll stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); 67 1.1.2.2 skrll /* Received Bytes */ 68 1.1.2.2 skrll stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc)); 69 1.1.2.2 skrll 70 1.1.2.2 skrll #if 0 71 1.1.2.2 skrll /* Can we get rid of these?? Consequently, getting rid 72 1.1.2.2 skrll * of the tc_stats structure. 73 1.1.2.2 skrll */ 74 1.1.2.2 skrll tc_stats_array[up]->in_overflow_discards = 0; 75 1.1.2.2 skrll tc_stats_array[up]->out_overflow_discards = 0; 76 1.1.2.2 skrll #endif 77 1.1.2.2 skrll } 78 1.1.2.2 skrll 79 1.1.2.2 skrll return IXGBE_SUCCESS; 80 1.1.2.2 skrll } 81 1.1.2.2 skrll 82 1.1.2.2 skrll /** 83 1.1.2.2 skrll * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data 84 1.1.2.2 skrll * @hw: pointer to hardware structure 85 1.1.2.2 skrll * @stats: pointer to statistics structure 86 1.1.2.2 skrll * @tc_count: Number of elements in bwg_array. 87 1.1.2.2 skrll * 88 1.1.2.2 skrll * This function returns the CBFC status data for each of the Traffic Classes. 89 1.1.2.2 skrll */ 90 1.1.2.2 skrll s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw, 91 1.1.2.2 skrll struct ixgbe_hw_stats *stats, 92 1.1.2.2 skrll u8 tc_count) 93 1.1.2.2 skrll { 94 1.1.2.2 skrll int tc; 95 1.1.2.2 skrll 96 1.1.2.2 skrll DEBUGFUNC("dcb_get_pfc_stats"); 97 1.1.2.2 skrll 98 1.1.2.2 skrll if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS) 99 1.1.2.2 skrll return IXGBE_ERR_PARAM; 100 1.1.2.2 skrll 101 1.1.2.2 skrll for (tc = 0; tc < tc_count; tc++) { 102 1.1.2.2 skrll /* Priority XOFF Transmitted */ 103 1.1.2.2 skrll stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc)); 104 1.1.2.2 skrll /* Priority XOFF Received */ 105 1.1.2.2 skrll stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc)); 106 1.1.2.2 skrll } 107 1.1.2.2 skrll 108 1.1.2.2 skrll return IXGBE_SUCCESS; 109 1.1.2.2 skrll } 110 1.1.2.2 skrll 111 1.1.2.2 skrll /** 112 1.1.2.2 skrll * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter 113 1.1.2.2 skrll * @hw: pointer to hardware structure 114 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 115 1.1.2.2 skrll * 116 1.1.2.2 skrll * Configure Rx Data Arbiter and credits for each traffic class. 117 1.1.2.2 skrll */ 118 1.1.2.2 skrll s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill, 119 1.1.2.2 skrll u16 *max, u8 *tsa) 120 1.1.2.2 skrll { 121 1.1.2.2 skrll u32 reg = 0; 122 1.1.2.2 skrll u32 credit_refill = 0; 123 1.1.2.2 skrll u32 credit_max = 0; 124 1.1.2.2 skrll u8 i = 0; 125 1.1.2.2 skrll 126 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; 127 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); 128 1.1.2.2 skrll 129 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 130 1.1.2.2 skrll /* Enable Arbiter */ 131 1.1.2.2 skrll reg &= ~IXGBE_RMCS_ARBDIS; 132 1.1.2.2 skrll /* Enable Receive Recycle within the BWG */ 133 1.1.2.2 skrll reg |= IXGBE_RMCS_RRM; 134 1.1.2.2 skrll /* Enable Deficit Fixed Priority arbitration*/ 135 1.1.2.2 skrll reg |= IXGBE_RMCS_DFP; 136 1.1.2.2 skrll 137 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 138 1.1.2.2 skrll 139 1.1.2.2 skrll /* Configure traffic class credits and priority */ 140 1.1.2.2 skrll for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 141 1.1.2.2 skrll credit_refill = refill[i]; 142 1.1.2.2 skrll credit_max = max[i]; 143 1.1.2.2 skrll 144 1.1.2.2 skrll reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); 145 1.1.2.2 skrll 146 1.1.2.2 skrll if (tsa[i] == ixgbe_dcb_tsa_strict) 147 1.1.2.2 skrll reg |= IXGBE_RT2CR_LSP; 148 1.1.2.2 skrll 149 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); 150 1.1.2.2 skrll } 151 1.1.2.2 skrll 152 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 153 1.1.2.2 skrll reg |= IXGBE_RDRXCTL_RDMTS_1_2; 154 1.1.2.2 skrll reg |= IXGBE_RDRXCTL_MPBEN; 155 1.1.2.2 skrll reg |= IXGBE_RDRXCTL_MCEN; 156 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 157 1.1.2.2 skrll 158 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 159 1.1.2.2 skrll /* Make sure there is enough descriptors before arbitration */ 160 1.1.2.2 skrll reg &= ~IXGBE_RXCTRL_DMBYPS; 161 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); 162 1.1.2.2 skrll 163 1.1.2.2 skrll return IXGBE_SUCCESS; 164 1.1.2.2 skrll } 165 1.1.2.2 skrll 166 1.1.2.2 skrll /** 167 1.1.2.2 skrll * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter 168 1.1.2.2 skrll * @hw: pointer to hardware structure 169 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 170 1.1.2.2 skrll * 171 1.1.2.2 skrll * Configure Tx Descriptor Arbiter and credits for each traffic class. 172 1.1.2.2 skrll */ 173 1.1.2.2 skrll s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 174 1.1.2.2 skrll u16 *refill, u16 *max, u8 *bwg_id, 175 1.1.2.2 skrll u8 *tsa) 176 1.1.2.2 skrll { 177 1.1.2.2 skrll u32 reg, max_credits; 178 1.1.2.2 skrll u8 i; 179 1.1.2.2 skrll 180 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); 181 1.1.2.2 skrll 182 1.1.2.2 skrll /* Enable arbiter */ 183 1.1.2.2 skrll reg &= ~IXGBE_DPMCS_ARBDIS; 184 1.1.2.2 skrll reg |= IXGBE_DPMCS_TSOEF; 185 1.1.2.2 skrll 186 1.1.2.2 skrll /* Configure Max TSO packet size 34KB including payload and headers */ 187 1.1.2.2 skrll reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); 188 1.1.2.2 skrll 189 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); 190 1.1.2.2 skrll 191 1.1.2.2 skrll /* Configure traffic class credits and priority */ 192 1.1.2.2 skrll for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 193 1.1.2.2 skrll max_credits = max[i]; 194 1.1.2.2 skrll reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; 195 1.1.2.2 skrll reg |= refill[i]; 196 1.1.2.2 skrll reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; 197 1.1.2.2 skrll 198 1.1.2.2 skrll if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee) 199 1.1.2.2 skrll reg |= IXGBE_TDTQ2TCCR_GSP; 200 1.1.2.2 skrll 201 1.1.2.2 skrll if (tsa[i] == ixgbe_dcb_tsa_strict) 202 1.1.2.2 skrll reg |= IXGBE_TDTQ2TCCR_LSP; 203 1.1.2.2 skrll 204 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); 205 1.1.2.2 skrll } 206 1.1.2.2 skrll 207 1.1.2.2 skrll return IXGBE_SUCCESS; 208 1.1.2.2 skrll } 209 1.1.2.2 skrll 210 1.1.2.2 skrll /** 211 1.1.2.2 skrll * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter 212 1.1.2.2 skrll * @hw: pointer to hardware structure 213 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 214 1.1.2.2 skrll * 215 1.1.2.2 skrll * Configure Tx Data Arbiter and credits for each traffic class. 216 1.1.2.2 skrll */ 217 1.1.2.2 skrll s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 218 1.1.2.2 skrll u16 *refill, u16 *max, u8 *bwg_id, 219 1.1.2.2 skrll u8 *tsa) 220 1.1.2.2 skrll { 221 1.1.2.2 skrll u32 reg; 222 1.1.2.2 skrll u8 i; 223 1.1.2.2 skrll 224 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); 225 1.1.2.2 skrll /* Enable Data Plane Arbiter */ 226 1.1.2.2 skrll reg &= ~IXGBE_PDPMCS_ARBDIS; 227 1.1.2.2 skrll /* Enable DFP and Transmit Recycle Mode */ 228 1.1.2.2 skrll reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); 229 1.1.2.2 skrll 230 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); 231 1.1.2.2 skrll 232 1.1.2.2 skrll /* Configure traffic class credits and priority */ 233 1.1.2.2 skrll for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 234 1.1.2.2 skrll reg = refill[i]; 235 1.1.2.2 skrll reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; 236 1.1.2.2 skrll reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; 237 1.1.2.2 skrll 238 1.1.2.2 skrll if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee) 239 1.1.2.2 skrll reg |= IXGBE_TDPT2TCCR_GSP; 240 1.1.2.2 skrll 241 1.1.2.2 skrll if (tsa[i] == ixgbe_dcb_tsa_strict) 242 1.1.2.2 skrll reg |= IXGBE_TDPT2TCCR_LSP; 243 1.1.2.2 skrll 244 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); 245 1.1.2.2 skrll } 246 1.1.2.2 skrll 247 1.1.2.2 skrll /* Enable Tx packet buffer division */ 248 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 249 1.1.2.2 skrll reg |= IXGBE_DTXCTL_ENDBUBD; 250 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); 251 1.1.2.2 skrll 252 1.1.2.2 skrll return IXGBE_SUCCESS; 253 1.1.2.2 skrll } 254 1.1.2.2 skrll 255 1.1.2.2 skrll /** 256 1.1.2.2 skrll * ixgbe_dcb_config_pfc_82598 - Config priority flow control 257 1.1.2.2 skrll * @hw: pointer to hardware structure 258 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 259 1.1.2.2 skrll * 260 1.1.2.2 skrll * Configure Priority Flow Control for each traffic class. 261 1.1.2.2 skrll */ 262 1.1.2.2 skrll s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) 263 1.1.2.2 skrll { 264 1.1.2.2 skrll u32 fcrtl, reg; 265 1.1.2.2 skrll u8 i; 266 1.1.2.2 skrll 267 1.1.2.2 skrll /* Enable Transmit Priority Flow Control */ 268 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 269 1.1.2.2 skrll reg &= ~IXGBE_RMCS_TFCE_802_3X; 270 1.1.2.2 skrll reg |= IXGBE_RMCS_TFCE_PRIORITY; 271 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 272 1.1.2.2 skrll 273 1.1.2.2 skrll /* Enable Receive Priority Flow Control */ 274 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 275 1.1.2.2 skrll reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); 276 1.1.2.2 skrll 277 1.1.2.2 skrll if (pfc_en) 278 1.1.2.2 skrll reg |= IXGBE_FCTRL_RPFCE; 279 1.1.2.2 skrll 280 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); 281 1.1.2.2 skrll 282 1.1.2.2 skrll /* Configure PFC Tx thresholds per TC */ 283 1.1.2.2 skrll for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 284 1.1.2.2 skrll if (!(pfc_en & (1 << i))) { 285 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 286 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 287 1.1.2.2 skrll continue; 288 1.1.2.2 skrll } 289 1.1.2.2 skrll 290 1.1.2.2 skrll fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 291 1.1.2.2 skrll reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 292 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 293 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 294 1.1.2.2 skrll } 295 1.1.2.2 skrll 296 1.1.2.2 skrll /* Configure pause time */ 297 1.1.2.2 skrll reg = hw->fc.pause_time | (hw->fc.pause_time << 16); 298 1.1.2.2 skrll for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 299 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 300 1.1.2.2 skrll 301 1.1.2.2 skrll /* Configure flow control refresh threshold value */ 302 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 303 1.1.2.2 skrll 304 1.1.2.2 skrll return IXGBE_SUCCESS; 305 1.1.2.2 skrll } 306 1.1.2.2 skrll 307 1.1.2.2 skrll /** 308 1.1.2.2 skrll * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics 309 1.1.2.2 skrll * @hw: pointer to hardware structure 310 1.1.2.2 skrll * 311 1.1.2.2 skrll * Configure queue statistics registers, all queues belonging to same traffic 312 1.1.2.2 skrll * class uses a single set of queue statistics counters. 313 1.1.2.2 skrll */ 314 1.1.2.2 skrll s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) 315 1.1.2.2 skrll { 316 1.1.2.2 skrll u32 reg = 0; 317 1.1.2.2 skrll u8 i = 0; 318 1.1.2.2 skrll u8 j = 0; 319 1.1.2.2 skrll 320 1.1.2.2 skrll /* Receive Queues stats setting - 8 queues per statistics reg */ 321 1.1.2.2 skrll for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) { 322 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); 323 1.1.2.2 skrll reg |= ((0x1010101) * j); 324 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 325 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); 326 1.1.2.2 skrll reg |= ((0x1010101) * j); 327 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); 328 1.1.2.2 skrll } 329 1.1.2.2 skrll /* Transmit Queues stats setting - 4 queues per statistics reg*/ 330 1.1.2.2 skrll for (i = 0; i < 8; i++) { 331 1.1.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); 332 1.1.2.2 skrll reg |= ((0x1010101) * i); 333 1.1.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); 334 1.1.2.2 skrll } 335 1.1.2.2 skrll 336 1.1.2.2 skrll return IXGBE_SUCCESS; 337 1.1.2.2 skrll } 338 1.1.2.2 skrll 339 1.1.2.2 skrll /** 340 1.1.2.2 skrll * ixgbe_dcb_hw_config_82598 - Config and enable DCB 341 1.1.2.2 skrll * @hw: pointer to hardware structure 342 1.1.2.2 skrll * @dcb_config: pointer to ixgbe_dcb_config structure 343 1.1.2.2 skrll * 344 1.1.2.2 skrll * Configure dcb settings and enable dcb mode. 345 1.1.2.2 skrll */ 346 1.1.2.2 skrll s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed, 347 1.1.2.2 skrll u16 *refill, u16 *max, u8 *bwg_id, 348 1.1.2.2 skrll u8 *tsa) 349 1.1.2.2 skrll { 350 1.1.2.3 skrll UNREFERENCED_1PARAMETER(link_speed); 351 1.1.2.3 skrll 352 1.1.2.2 skrll ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 353 1.1.2.2 skrll ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, 354 1.1.2.2 skrll tsa); 355 1.1.2.2 skrll ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, 356 1.1.2.2 skrll tsa); 357 1.1.2.2 skrll ixgbe_dcb_config_tc_stats_82598(hw); 358 1.1.2.2 skrll 359 1.1.2.2 skrll 360 1.1.2.2 skrll return IXGBE_SUCCESS; 361 1.1.2.2 skrll } 362
Indexes created Mon Oct 27 08:10:08 GMT 2025