ixgbe_dcb_82598.h revision 1.1.2.2
1 1.1.2.2 skrll /****************************************************************************** 2 1.1.2.2 skrll 3 1.1.2.2 skrll Copyright (c) 2001-2013, Intel Corporation 4 1.1.2.2 skrll All rights reserved. 5 1.1.2.2 skrll 6 1.1.2.2 skrll Redistribution and use in source and binary forms, with or without 7 1.1.2.2 skrll modification, are permitted provided that the following conditions are met: 8 1.1.2.2 skrll 9 1.1.2.2 skrll 1. Redistributions of source code must retain the above copyright notice, 10 1.1.2.2 skrll this list of conditions and the following disclaimer. 11 1.1.2.2 skrll 12 1.1.2.2 skrll 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll 16 1.1.2.2 skrll 3. Neither the name of the Intel Corporation nor the names of its 17 1.1.2.2 skrll contributors may be used to endorse or promote products derived from 18 1.1.2.2 skrll this software without specific prior written permission. 19 1.1.2.2 skrll 20 1.1.2.2 skrll THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.1.2.2 skrll AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.1.2.2 skrll IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.1.2.2 skrll ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.1.2.2 skrll LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.1.2.2 skrll CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.1.2.2 skrll SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.1.2.2 skrll INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.1.2.2 skrll CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.1.2.2 skrll ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.1.2.2 skrll POSSIBILITY OF SUCH DAMAGE. 31 1.1.2.2 skrll 32 1.1.2.2 skrll ******************************************************************************/ 33 1.1.2.2 skrll /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_dcb_82598.h 251964 2013-06-18 21:28:19Z jfv $*/ 34 1.1.2.2 skrll 35 1.1.2.2 skrll #ifndef _IXGBE_DCB_82598_H_ 36 1.1.2.2 skrll #define _IXGBE_DCB_82598_H_ 37 1.1.2.2 skrll 38 1.1.2.2 skrll /* DCB register definitions */ 39 1.1.2.2 skrll 40 1.1.2.2 skrll #define IXGBE_DPMCS_MTSOS_SHIFT 16 41 1.1.2.2 skrll #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 42 1.1.2.2 skrll * 1 DFP - Deficit Fixed Priority */ 43 1.1.2.2 skrll #define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */ 44 1.1.2.2 skrll #define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 45 1.1.2.2 skrll #define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */ 46 1.1.2.2 skrll 47 1.1.2.2 skrll #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */ 48 1.1.2.2 skrll 49 1.1.2.2 skrll #define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 50 1.1.2.2 skrll #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */ 51 1.1.2.2 skrll 52 1.1.2.2 skrll #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 53 1.1.2.2 skrll * buffers enable */ 54 1.1.2.2 skrll #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 55 1.1.2.2 skrll * (RSS) enable */ 56 1.1.2.2 skrll 57 1.1.2.2 skrll #define IXGBE_TDTQ2TCCR_MCL_SHIFT 12 58 1.1.2.2 skrll #define IXGBE_TDTQ2TCCR_BWG_SHIFT 9 59 1.1.2.2 skrll #define IXGBE_TDTQ2TCCR_GSP 0x40000000 60 1.1.2.2 skrll #define IXGBE_TDTQ2TCCR_LSP 0x80000000 61 1.1.2.2 skrll 62 1.1.2.2 skrll #define IXGBE_TDPT2TCCR_MCL_SHIFT 12 63 1.1.2.2 skrll #define IXGBE_TDPT2TCCR_BWG_SHIFT 9 64 1.1.2.2 skrll #define IXGBE_TDPT2TCCR_GSP 0x40000000 65 1.1.2.2 skrll #define IXGBE_TDPT2TCCR_LSP 0x80000000 66 1.1.2.2 skrll 67 1.1.2.2 skrll #define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 68 1.1.2.2 skrll * 1 DFP - Deficit Fixed Priority */ 69 1.1.2.2 skrll #define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */ 70 1.1.2.2 skrll #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */ 71 1.1.2.2 skrll 72 1.1.2.2 skrll #define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */ 73 1.1.2.2 skrll 74 1.1.2.2 skrll #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 75 1.1.2.2 skrll #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 76 1.1.2.2 skrll #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 77 1.1.2.2 skrll #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 78 1.1.2.2 skrll 79 1.1.2.2 skrll /* DCB driver APIs */ 80 1.1.2.2 skrll 81 1.1.2.2 skrll /* DCB PFC */ 82 1.1.2.2 skrll s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8); 83 1.1.2.2 skrll 84 1.1.2.2 skrll /* DCB stats */ 85 1.1.2.2 skrll s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *); 86 1.1.2.2 skrll s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *, 87 1.1.2.2 skrll struct ixgbe_hw_stats *, u8); 88 1.1.2.2 skrll s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *, 89 1.1.2.2 skrll struct ixgbe_hw_stats *, u8); 90 1.1.2.2 skrll 91 1.1.2.2 skrll /* DCB config arbiters */ 92 1.1.2.2 skrll s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, 93 1.1.2.2 skrll u8 *, u8 *); 94 1.1.2.2 skrll s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, 95 1.1.2.2 skrll u8 *, u8 *); 96 1.1.2.2 skrll s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *); 97 1.1.2.2 skrll 98 1.1.2.2 skrll /* DCB initialization */ 99 1.1.2.2 skrll s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *); 100 1.1.2.2 skrll #endif /* _IXGBE_DCB_82958_H_ */ 101
Indexes created Sun Oct 26 21:10:03 GMT 2025