ixgbe_dcb_82599.h revision 1.1.2.3
1 1.1.2.2 skrll /****************************************************************************** 2 1.1.2.2 skrll 3 1.1.2.3 skrll Copyright (c) 2001-2015, Intel Corporation 4 1.1.2.2 skrll All rights reserved. 5 1.1.2.2 skrll 6 1.1.2.2 skrll Redistribution and use in source and binary forms, with or without 7 1.1.2.2 skrll modification, are permitted provided that the following conditions are met: 8 1.1.2.2 skrll 9 1.1.2.2 skrll 1. Redistributions of source code must retain the above copyright notice, 10 1.1.2.2 skrll this list of conditions and the following disclaimer. 11 1.1.2.2 skrll 12 1.1.2.2 skrll 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll 16 1.1.2.2 skrll 3. Neither the name of the Intel Corporation nor the names of its 17 1.1.2.2 skrll contributors may be used to endorse or promote products derived from 18 1.1.2.2 skrll this software without specific prior written permission. 19 1.1.2.2 skrll 20 1.1.2.2 skrll THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.1.2.2 skrll AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.1.2.2 skrll IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.1.2.2 skrll ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.1.2.2 skrll LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.1.2.2 skrll CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.1.2.2 skrll SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.1.2.2 skrll INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.1.2.2 skrll CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.1.2.2 skrll ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.1.2.2 skrll POSSIBILITY OF SUCH DAMAGE. 31 1.1.2.2 skrll 32 1.1.2.2 skrll ******************************************************************************/ 33 1.1.2.3 skrll /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_dcb_82599.h 282289 2015-04-30 22:53:27Z erj $*/ 34 1.1.2.2 skrll 35 1.1.2.2 skrll #ifndef _IXGBE_DCB_82599_H_ 36 1.1.2.2 skrll #define _IXGBE_DCB_82599_H_ 37 1.1.2.2 skrll 38 1.1.2.2 skrll /* DCB register definitions */ 39 1.1.2.2 skrll #define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin, 40 1.1.2.2 skrll * 1 WSP - Weighted Strict Priority 41 1.1.2.2 skrll */ 42 1.1.2.2 skrll #define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin, 43 1.1.2.2 skrll * 1 WRR - Weighted Round Robin 44 1.1.2.2 skrll */ 45 1.1.2.2 skrll #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */ 46 1.1.2.2 skrll #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */ 47 1.1.2.2 skrll #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must 48 1.1.2.2 skrll * clear! 49 1.1.2.2 skrll */ 50 1.1.2.2 skrll #define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */ 51 1.1.2.2 skrll 52 1.1.2.2 skrll /* Receive UP2TC mapping */ 53 1.1.2.2 skrll #define IXGBE_RTRUP2TC_UP_SHIFT 3 54 1.1.2.2 skrll #define IXGBE_RTRUP2TC_UP_MASK 7 55 1.1.2.2 skrll /* Transmit UP2TC mapping */ 56 1.1.2.2 skrll #define IXGBE_RTTUP2TC_UP_SHIFT 3 57 1.1.2.2 skrll 58 1.1.2.2 skrll #define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 59 1.1.2.2 skrll #define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */ 60 1.1.2.2 skrll #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */ 61 1.1.2.2 skrll #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */ 62 1.1.2.2 skrll 63 1.1.2.2 skrll #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 64 1.1.2.2 skrll * buffers enable 65 1.1.2.2 skrll */ 66 1.1.2.2 skrll #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 67 1.1.2.2 skrll * (RSS) enable 68 1.1.2.2 skrll */ 69 1.1.2.2 skrll 70 1.1.2.2 skrll /* RTRPCS Bit Masks */ 71 1.1.2.2 skrll #define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 72 1.1.2.2 skrll /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 73 1.1.2.2 skrll #define IXGBE_RTRPCS_RAC 0x00000004 74 1.1.2.2 skrll #define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 75 1.1.2.2 skrll 76 1.1.2.2 skrll /* RTTDT2C Bit Masks */ 77 1.1.2.2 skrll #define IXGBE_RTTDT2C_MCL_SHIFT 12 78 1.1.2.2 skrll #define IXGBE_RTTDT2C_BWG_SHIFT 9 79 1.1.2.2 skrll #define IXGBE_RTTDT2C_GSP 0x40000000 80 1.1.2.2 skrll #define IXGBE_RTTDT2C_LSP 0x80000000 81 1.1.2.2 skrll 82 1.1.2.2 skrll #define IXGBE_RTTPT2C_MCL_SHIFT 12 83 1.1.2.2 skrll #define IXGBE_RTTPT2C_BWG_SHIFT 9 84 1.1.2.2 skrll #define IXGBE_RTTPT2C_GSP 0x40000000 85 1.1.2.2 skrll #define IXGBE_RTTPT2C_LSP 0x80000000 86 1.1.2.2 skrll 87 1.1.2.2 skrll /* RTTPCS Bit Masks */ 88 1.1.2.2 skrll #define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin, 89 1.1.2.2 skrll * 1 SP - Strict Priority 90 1.1.2.2 skrll */ 91 1.1.2.2 skrll #define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */ 92 1.1.2.2 skrll #define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */ 93 1.1.2.2 skrll #define IXGBE_RTTPCS_ARBD_SHIFT 22 94 1.1.2.2 skrll #define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */ 95 1.1.2.2 skrll 96 1.1.2.2 skrll #define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */ 97 1.1.2.2 skrll 98 1.1.2.2 skrll /* SECTXMINIFG DCB */ 99 1.1.2.2 skrll #define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer SEC IFG */ 100 1.1.2.2 skrll 101 1.1.2.2 skrll /* BCN register definitions */ 102 1.1.2.2 skrll #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 103 1.1.2.2 skrll #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 104 1.1.2.2 skrll 105 1.1.2.2 skrll #define IXGBE_RTTBCNCR_MNG_CMTGI 0x00000001 106 1.1.2.2 skrll #define IXGBE_RTTBCNCR_MGN_BCNA_MODE 0x00000002 107 1.1.2.2 skrll #define IXGBE_RTTBCNCR_RSV7_11_SHIFT 5 108 1.1.2.2 skrll #define IXGBE_RTTBCNCR_G 0x00000400 109 1.1.2.2 skrll #define IXGBE_RTTBCNCR_I 0x00000800 110 1.1.2.2 skrll #define IXGBE_RTTBCNCR_H 0x00001000 111 1.1.2.2 skrll #define IXGBE_RTTBCNCR_VER_SHIFT 14 112 1.1.2.2 skrll #define IXGBE_RTTBCNCR_CMT_ETH_SHIFT 16 113 1.1.2.2 skrll 114 1.1.2.2 skrll #define IXGBE_RTTBCNACL_SMAC_L_SHIFT 16 115 1.1.2.2 skrll 116 1.1.2.2 skrll #define IXGBE_RTTBCNTG_BCNA_MODE 0x80000000 117 1.1.2.2 skrll 118 1.1.2.2 skrll #define IXGBE_RTTBCNRTT_TS_SHIFT 3 119 1.1.2.2 skrll #define IXGBE_RTTBCNRTT_TXQ_IDX_SHIFT 16 120 1.1.2.2 skrll 121 1.1.2.2 skrll #define IXGBE_RTTBCNRD_BCN_CLEAR_ALL 0x00000002 122 1.1.2.2 skrll #define IXGBE_RTTBCNRD_DRIFT_FAC_SHIFT 2 123 1.1.2.2 skrll #define IXGBE_RTTBCNRD_DRIFT_INT_SHIFT 16 124 1.1.2.2 skrll #define IXGBE_RTTBCNRD_DRIFT_ENA 0x80000000 125 1.1.2.2 skrll 126 1.1.2.2 skrll 127 1.1.2.2 skrll /* DCB driver APIs */ 128 1.1.2.2 skrll 129 1.1.2.2 skrll /* DCB PFC */ 130 1.1.2.2 skrll s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *); 131 1.1.2.2 skrll 132 1.1.2.2 skrll /* DCB stats */ 133 1.1.2.2 skrll s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *, 134 1.1.2.2 skrll struct ixgbe_dcb_config *); 135 1.1.2.2 skrll s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *, 136 1.1.2.2 skrll struct ixgbe_hw_stats *, u8); 137 1.1.2.2 skrll s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *, 138 1.1.2.2 skrll struct ixgbe_hw_stats *, u8); 139 1.1.2.2 skrll 140 1.1.2.2 skrll /* DCB config arbiters */ 141 1.1.2.2 skrll s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 142 1.1.2.2 skrll u8 *, u8 *); 143 1.1.2.2 skrll s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 144 1.1.2.2 skrll u8 *, u8 *, u8 *); 145 1.1.2.2 skrll s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *, 146 1.1.2.2 skrll u8 *, u8 *); 147 1.1.2.2 skrll 148 1.1.2.2 skrll /* DCB initialization */ 149 1.1.2.2 skrll s32 ixgbe_dcb_config_82599(struct ixgbe_hw *, 150 1.1.2.2 skrll struct ixgbe_dcb_config *); 151 1.1.2.2 skrll 152 1.1.2.2 skrll s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, 153 1.1.2.2 skrll u8 *, u8 *); 154 1.1.2.2 skrll #endif /* _IXGBE_DCB_82959_H_ */ 155
Indexes created Sat Nov 01 05:10:12 GMT 2025