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ixgbe_osdep.c revision 1.1
      1  1.1  msaitoh /******************************************************************************
      2  1.1  msaitoh 
      3  1.1  msaitoh   Copyright (c) 2001-2015, Intel Corporation
      4  1.1  msaitoh   All rights reserved.
      5  1.1  msaitoh 
      6  1.1  msaitoh   Redistribution and use in source and binary forms, with or without
      7  1.1  msaitoh   modification, are permitted provided that the following conditions are met:
      8  1.1  msaitoh 
      9  1.1  msaitoh    1. Redistributions of source code must retain the above copyright notice,
     10  1.1  msaitoh       this list of conditions and the following disclaimer.
     11  1.1  msaitoh 
     12  1.1  msaitoh    2. Redistributions in binary form must reproduce the above copyright
     13  1.1  msaitoh       notice, this list of conditions and the following disclaimer in the
     14  1.1  msaitoh       documentation and/or other materials provided with the distribution.
     15  1.1  msaitoh 
     16  1.1  msaitoh    3. Neither the name of the Intel Corporation nor the names of its
     17  1.1  msaitoh       contributors may be used to endorse or promote products derived from
     18  1.1  msaitoh       this software without specific prior written permission.
     19  1.1  msaitoh 
     20  1.1  msaitoh   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     21  1.1  msaitoh   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     22  1.1  msaitoh   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     23  1.1  msaitoh   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     24  1.1  msaitoh   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25  1.1  msaitoh   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26  1.1  msaitoh   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27  1.1  msaitoh   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28  1.1  msaitoh   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29  1.1  msaitoh   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30  1.1  msaitoh   POSSIBILITY OF SUCH DAMAGE.
     31  1.1  msaitoh 
     32  1.1  msaitoh ******************************************************************************/
     33  1.1  msaitoh /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_osdep.c 292674 2015-12-23 22:45:17Z sbruno $*/
     34  1.1  msaitoh 
     35  1.1  msaitoh #include "ixgbe_osdep.h"
     36  1.1  msaitoh #include "ixgbe.h"
     37  1.1  msaitoh 
     38  1.1  msaitoh inline device_t
     39  1.1  msaitoh ixgbe_dev_from_hw(struct ixgbe_hw *hw)
     40  1.1  msaitoh {
     41  1.1  msaitoh 	return ((struct adapter *)hw->back)->dev;
     42  1.1  msaitoh }
     43  1.1  msaitoh 
     44  1.1  msaitoh u16
     45  1.1  msaitoh ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)
     46  1.1  msaitoh {
     47  1.1  msaitoh 	pci_chipset_tag_t  pc = hw->back->osdep.pc;
     48  1.1  msaitoh 	pcitag_t           tag = hw->back->osdep.tag;
     49  1.1  msaitoh 
     50  1.1  msaitoh 	switch (reg % 4) {
     51  1.1  msaitoh 	case 0:
     52  1.1  msaitoh 		return pci_conf_read(pc, tag, reg) & __BITS(15, 0);
     53  1.1  msaitoh 	case 2:
     54  1.1  msaitoh 		return __SHIFTOUT(pci_conf_read(pc, tag, reg - 2),
     55  1.1  msaitoh 		    __BITS(31, 16));
     56  1.1  msaitoh 	default:
     57  1.1  msaitoh 		panic("%s: invalid register (%" PRIx32, __func__, reg);
     58  1.1  msaitoh 		break;
     59  1.1  msaitoh 	}
     60  1.1  msaitoh }
     61  1.1  msaitoh 
     62  1.1  msaitoh void
     63  1.1  msaitoh ixgbe_write_pci_cfg(struct ixgbe_hw *hw, u32 reg, u16 value)
     64  1.1  msaitoh {
     65  1.1  msaitoh 	pci_chipset_tag_t  pc = hw->back->osdep.pc;
     66  1.1  msaitoh 	pcitag_t           tag = hw->back->osdep.tag;
     67  1.1  msaitoh 	pcireg_t old;
     68  1.1  msaitoh 
     69  1.1  msaitoh 	switch (reg % 4) {
     70  1.1  msaitoh 	case 0:
     71  1.1  msaitoh 		old = pci_conf_read(pc, tag, reg) & __BITS(31, 16);
     72  1.1  msaitoh 		pci_conf_write(pc, tag, reg, value | old);
     73  1.1  msaitoh 		break;
     74  1.1  msaitoh 	case 2:
     75  1.1  msaitoh 		old = pci_conf_read(pc, tag, reg - 2) & __BITS(15, 0);
     76  1.1  msaitoh 		pci_conf_write(pc, tag, reg - 2,
     77  1.1  msaitoh 		    __SHIFTIN(value, __BITS(31, 16)) | old);
     78  1.1  msaitoh 		break;
     79  1.1  msaitoh 	default:
     80  1.1  msaitoh 		panic("%s: invalid register (%" PRIx32, __func__, reg);
     81  1.1  msaitoh 		break;
     82  1.1  msaitoh 	}
     83  1.1  msaitoh 
     84  1.1  msaitoh 	return;
     85  1.1  msaitoh }
     86  1.1  msaitoh 
     87  1.1  msaitoh inline u32
     88  1.1  msaitoh ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
     89  1.1  msaitoh {
     90  1.1  msaitoh 	return bus_space_read_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
     91  1.1  msaitoh 	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
     92  1.1  msaitoh 	    reg);
     93  1.1  msaitoh }
     94  1.1  msaitoh 
     95  1.1  msaitoh inline void
     96  1.1  msaitoh ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 val)
     97  1.1  msaitoh {
     98  1.1  msaitoh 	bus_space_write_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
     99  1.1  msaitoh 	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
    100  1.1  msaitoh 	    reg, val);
    101  1.1  msaitoh }
    102  1.1  msaitoh 
    103  1.1  msaitoh inline u32
    104  1.1  msaitoh ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset)
    105  1.1  msaitoh {
    106  1.1  msaitoh 	return bus_space_read_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
    107  1.1  msaitoh 	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
    108  1.1  msaitoh 	    reg + (offset << 2));
    109  1.1  msaitoh }
    110  1.1  msaitoh 
    111  1.1  msaitoh inline void
    112  1.1  msaitoh ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)
    113  1.1  msaitoh {
    114  1.1  msaitoh 	bus_space_write_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
    115  1.1  msaitoh 	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
    116  1.1  msaitoh 	    reg + (offset << 2), val);
    117  1.1  msaitoh }
    118