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ixgbe_osdep.c revision 1.3
      1  1.3  msaitoh /* $NetBSD: ixgbe_osdep.c,v 1.3 2018/03/15 06:48:51 msaitoh Exp $ */
      2  1.2  msaitoh 
      3  1.1  msaitoh /******************************************************************************
      4  1.1  msaitoh 
      5  1.3  msaitoh   Copyright (c) 2001-2017, Intel Corporation
      6  1.1  msaitoh   All rights reserved.
      7  1.3  msaitoh 
      8  1.3  msaitoh   Redistribution and use in source and binary forms, with or without
      9  1.1  msaitoh   modification, are permitted provided that the following conditions are met:
     10  1.3  msaitoh 
     11  1.3  msaitoh    1. Redistributions of source code must retain the above copyright notice,
     12  1.1  msaitoh       this list of conditions and the following disclaimer.
     13  1.3  msaitoh 
     14  1.3  msaitoh    2. Redistributions in binary form must reproduce the above copyright
     15  1.3  msaitoh       notice, this list of conditions and the following disclaimer in the
     16  1.1  msaitoh       documentation and/or other materials provided with the distribution.
     17  1.3  msaitoh 
     18  1.3  msaitoh    3. Neither the name of the Intel Corporation nor the names of its
     19  1.3  msaitoh       contributors may be used to endorse or promote products derived from
     20  1.1  msaitoh       this software without specific prior written permission.
     21  1.3  msaitoh 
     22  1.1  msaitoh   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     23  1.3  msaitoh   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  1.3  msaitoh   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  1.3  msaitoh   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     26  1.3  msaitoh   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     27  1.3  msaitoh   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     28  1.3  msaitoh   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     29  1.3  msaitoh   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     30  1.3  msaitoh   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     31  1.1  msaitoh   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     32  1.1  msaitoh   POSSIBILITY OF SUCH DAMAGE.
     33  1.1  msaitoh 
     34  1.1  msaitoh ******************************************************************************/
     35  1.2  msaitoh /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_osdep.c 320688 2017-07-05 17:27:03Z erj $*/
     36  1.1  msaitoh 
     37  1.1  msaitoh #include "ixgbe_osdep.h"
     38  1.1  msaitoh #include "ixgbe.h"
     39  1.1  msaitoh 
     40  1.1  msaitoh inline device_t
     41  1.1  msaitoh ixgbe_dev_from_hw(struct ixgbe_hw *hw)
     42  1.1  msaitoh {
     43  1.1  msaitoh 	return ((struct adapter *)hw->back)->dev;
     44  1.1  msaitoh }
     45  1.1  msaitoh 
     46  1.1  msaitoh u16
     47  1.1  msaitoh ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)
     48  1.1  msaitoh {
     49  1.1  msaitoh 	pci_chipset_tag_t  pc = hw->back->osdep.pc;
     50  1.1  msaitoh 	pcitag_t           tag = hw->back->osdep.tag;
     51  1.1  msaitoh 
     52  1.1  msaitoh 	switch (reg % 4) {
     53  1.1  msaitoh 	case 0:
     54  1.1  msaitoh 		return pci_conf_read(pc, tag, reg) & __BITS(15, 0);
     55  1.1  msaitoh 	case 2:
     56  1.1  msaitoh 		return __SHIFTOUT(pci_conf_read(pc, tag, reg - 2),
     57  1.1  msaitoh 		    __BITS(31, 16));
     58  1.1  msaitoh 	default:
     59  1.1  msaitoh 		panic("%s: invalid register (%" PRIx32, __func__, reg);
     60  1.1  msaitoh 		break;
     61  1.1  msaitoh 	}
     62  1.1  msaitoh }
     63  1.1  msaitoh 
     64  1.1  msaitoh void
     65  1.1  msaitoh ixgbe_write_pci_cfg(struct ixgbe_hw *hw, u32 reg, u16 value)
     66  1.1  msaitoh {
     67  1.1  msaitoh 	pci_chipset_tag_t  pc = hw->back->osdep.pc;
     68  1.1  msaitoh 	pcitag_t           tag = hw->back->osdep.tag;
     69  1.1  msaitoh 	pcireg_t old;
     70  1.1  msaitoh 
     71  1.1  msaitoh 	switch (reg % 4) {
     72  1.1  msaitoh 	case 0:
     73  1.1  msaitoh 		old = pci_conf_read(pc, tag, reg) & __BITS(31, 16);
     74  1.1  msaitoh 		pci_conf_write(pc, tag, reg, value | old);
     75  1.1  msaitoh 		break;
     76  1.1  msaitoh 	case 2:
     77  1.1  msaitoh 		old = pci_conf_read(pc, tag, reg - 2) & __BITS(15, 0);
     78  1.1  msaitoh 		pci_conf_write(pc, tag, reg - 2,
     79  1.1  msaitoh 		    __SHIFTIN(value, __BITS(31, 16)) | old);
     80  1.1  msaitoh 		break;
     81  1.1  msaitoh 	default:
     82  1.1  msaitoh 		panic("%s: invalid register (%" PRIx32, __func__, reg);
     83  1.1  msaitoh 		break;
     84  1.1  msaitoh 	}
     85  1.1  msaitoh 
     86  1.1  msaitoh 	return;
     87  1.1  msaitoh }
     88  1.1  msaitoh 
     89  1.1  msaitoh inline u32
     90  1.1  msaitoh ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
     91  1.1  msaitoh {
     92  1.1  msaitoh 	return bus_space_read_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
     93  1.2  msaitoh 	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle, reg);
     94  1.1  msaitoh }
     95  1.1  msaitoh 
     96  1.1  msaitoh inline void
     97  1.1  msaitoh ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 val)
     98  1.1  msaitoh {
     99  1.1  msaitoh 	bus_space_write_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
    100  1.1  msaitoh 	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
    101  1.1  msaitoh 	    reg, val);
    102  1.1  msaitoh }
    103  1.1  msaitoh 
    104  1.1  msaitoh inline u32
    105  1.1  msaitoh ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset)
    106  1.1  msaitoh {
    107  1.1  msaitoh 	return bus_space_read_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
    108  1.1  msaitoh 	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
    109  1.1  msaitoh 	    reg + (offset << 2));
    110  1.1  msaitoh }
    111  1.1  msaitoh 
    112  1.1  msaitoh inline void
    113  1.1  msaitoh ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)
    114  1.1  msaitoh {
    115  1.1  msaitoh 	bus_space_write_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
    116  1.1  msaitoh 	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
    117  1.1  msaitoh 	    reg + (offset << 2), val);
    118  1.1  msaitoh }
    119