ixgbe_phy.c revision 1.12
1 /* $NetBSD: ixgbe_phy.c,v 1.12 2017/08/30 08:49:18 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2017, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 320688 2017-07-05 17:27:03Z erj $*/ 36 37 #include "ixgbe_api.h" 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 41 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 42 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 43 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 44 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 45 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 46 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 47 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 48 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 50 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 51 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 52 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 53 u8 *sff8472_data); 54 55 /** 56 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 57 * @hw: pointer to the hardware structure 58 * @byte: byte to send 59 * 60 * Returns an error code on error. 61 */ 62 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 63 { 64 s32 status; 65 66 status = ixgbe_clock_out_i2c_byte(hw, byte); 67 if (status) 68 return status; 69 return ixgbe_get_i2c_ack(hw); 70 } 71 72 /** 73 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 74 * @hw: pointer to the hardware structure 75 * @byte: pointer to a u8 to receive the byte 76 * 77 * Returns an error code on error. 78 */ 79 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 80 { 81 s32 status; 82 83 status = ixgbe_clock_in_i2c_byte(hw, byte); 84 if (status) 85 return status; 86 /* ACK */ 87 return ixgbe_clock_out_i2c_bit(hw, FALSE); 88 } 89 90 /** 91 * ixgbe_ones_comp_byte_add - Perform one's complement addition 92 * @add1 - addend 1 93 * @add2 - addend 2 94 * 95 * Returns one's complement 8-bit sum. 96 */ 97 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 98 { 99 u16 sum = add1 + add2; 100 101 sum = (sum & 0xFF) + (sum >> 8); 102 return sum & 0xFF; 103 } 104 105 /** 106 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 107 * @hw: pointer to the hardware structure 108 * @addr: I2C bus address to read from 109 * @reg: I2C device register to read from 110 * @val: pointer to location to receive read value 111 * @lock: TRUE if to take and release semaphore 112 * 113 * Returns an error code on error. 114 */ 115 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 116 u16 *val, bool lock) 117 { 118 u32 swfw_mask = hw->phy.phy_semaphore_mask; 119 int max_retry = 3; 120 int retry = 0; 121 u8 csum_byte; 122 u8 high_bits; 123 u8 low_bits; 124 u8 reg_high; 125 u8 csum; 126 127 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 128 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 129 csum = ~csum; 130 do { 131 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 132 return IXGBE_ERR_SWFW_SYNC; 133 ixgbe_i2c_start(hw); 134 /* Device Address and write indication */ 135 if (ixgbe_out_i2c_byte_ack(hw, addr)) 136 goto fail; 137 /* Write bits 14:8 */ 138 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 139 goto fail; 140 /* Write bits 7:0 */ 141 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 142 goto fail; 143 /* Write csum */ 144 if (ixgbe_out_i2c_byte_ack(hw, csum)) 145 goto fail; 146 /* Re-start condition */ 147 ixgbe_i2c_start(hw); 148 /* Device Address and read indication */ 149 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 150 goto fail; 151 /* Get upper bits */ 152 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 153 goto fail; 154 /* Get low bits */ 155 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 156 goto fail; 157 /* Get csum */ 158 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 159 goto fail; 160 /* NACK */ 161 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 162 goto fail; 163 ixgbe_i2c_stop(hw); 164 if (lock) 165 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 166 *val = (high_bits << 8) | low_bits; 167 return 0; 168 169 fail: 170 ixgbe_i2c_bus_clear(hw); 171 if (lock) 172 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 173 retry++; 174 if (retry < max_retry) 175 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 176 else 177 DEBUGOUT("I2C byte read combined error.\n"); 178 } while (retry < max_retry); 179 180 return IXGBE_ERR_I2C; 181 } 182 183 /** 184 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 185 * @hw: pointer to the hardware structure 186 * @addr: I2C bus address to write to 187 * @reg: I2C device register to write to 188 * @val: value to write 189 * @lock: TRUE if to take and release semaphore 190 * 191 * Returns an error code on error. 192 */ 193 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 194 u16 val, bool lock) 195 { 196 u32 swfw_mask = hw->phy.phy_semaphore_mask; 197 int max_retry = 1; 198 int retry = 0; 199 u8 reg_high; 200 u8 csum; 201 202 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 203 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 204 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 205 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 206 csum = ~csum; 207 do { 208 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 209 return IXGBE_ERR_SWFW_SYNC; 210 ixgbe_i2c_start(hw); 211 /* Device Address and write indication */ 212 if (ixgbe_out_i2c_byte_ack(hw, addr)) 213 goto fail; 214 /* Write bits 14:8 */ 215 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 216 goto fail; 217 /* Write bits 7:0 */ 218 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 219 goto fail; 220 /* Write data 15:8 */ 221 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 222 goto fail; 223 /* Write data 7:0 */ 224 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 225 goto fail; 226 /* Write csum */ 227 if (ixgbe_out_i2c_byte_ack(hw, csum)) 228 goto fail; 229 ixgbe_i2c_stop(hw); 230 if (lock) 231 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 232 return 0; 233 234 fail: 235 ixgbe_i2c_bus_clear(hw); 236 if (lock) 237 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 238 retry++; 239 if (retry < max_retry) 240 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 241 else 242 DEBUGOUT("I2C byte write combined error.\n"); 243 } while (retry < max_retry); 244 245 return IXGBE_ERR_I2C; 246 } 247 248 /** 249 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 250 * @hw: pointer to the hardware structure 251 * 252 * Initialize the function pointers. 253 **/ 254 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 255 { 256 struct ixgbe_phy_info *phy = &hw->phy; 257 258 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 259 260 /* PHY */ 261 phy->ops.identify = ixgbe_identify_phy_generic; 262 phy->ops.reset = ixgbe_reset_phy_generic; 263 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 264 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 265 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 266 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 267 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 268 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 269 phy->ops.check_link = NULL; 270 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 271 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 272 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 273 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 274 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 275 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 276 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 277 phy->ops.identify_sfp = ixgbe_identify_module_generic; 278 phy->sfp_type = ixgbe_sfp_type_unknown; 279 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 280 phy->ops.write_i2c_byte_unlocked = 281 ixgbe_write_i2c_byte_generic_unlocked; 282 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 283 return IXGBE_SUCCESS; 284 } 285 286 /** 287 * ixgbe_probe_phy - Probe a single address for a PHY 288 * @hw: pointer to hardware structure 289 * @phy_addr: PHY address to probe 290 * 291 * Returns TRUE if PHY found 292 */ 293 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 294 { 295 u16 ext_ability = 0; 296 297 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 298 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 299 phy_addr); 300 return FALSE; 301 } 302 303 if (ixgbe_get_phy_id(hw)) 304 return FALSE; 305 306 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 307 308 if (hw->phy.type == ixgbe_phy_unknown) { 309 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 310 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 311 if (ext_ability & 312 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 313 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 314 hw->phy.type = ixgbe_phy_cu_unknown; 315 else 316 hw->phy.type = ixgbe_phy_generic; 317 } 318 319 return TRUE; 320 } 321 322 /** 323 * ixgbe_identify_phy_generic - Get physical layer module 324 * @hw: pointer to hardware structure 325 * 326 * Determines the physical layer module found on the current adapter. 327 **/ 328 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 329 { 330 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 331 u16 phy_addr; 332 333 DEBUGFUNC("ixgbe_identify_phy_generic"); 334 335 if (!hw->phy.phy_semaphore_mask) { 336 if (hw->bus.lan_id) 337 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 338 else 339 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 340 } 341 342 if (hw->phy.type != ixgbe_phy_unknown) 343 return IXGBE_SUCCESS; 344 345 if (hw->phy.nw_mng_if_sel) { 346 phy_addr = (hw->phy.nw_mng_if_sel & 347 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 348 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 349 if (ixgbe_probe_phy(hw, phy_addr)) 350 return IXGBE_SUCCESS; 351 else 352 return IXGBE_ERR_PHY_ADDR_INVALID; 353 } 354 355 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 356 if (ixgbe_probe_phy(hw, phy_addr)) { 357 status = IXGBE_SUCCESS; 358 break; 359 } 360 } 361 362 /* Certain media types do not have a phy so an address will not 363 * be found and the code will take this path. Caller has to 364 * decide if it is an error or not. 365 */ 366 if (status != IXGBE_SUCCESS) 367 hw->phy.addr = 0; 368 369 return status; 370 } 371 372 /** 373 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 374 * @hw: pointer to the hardware structure 375 * 376 * This function checks the MMNGC.MNG_VETO bit to see if there are 377 * any constraints on link from manageability. For MAC's that don't 378 * have this bit just return faluse since the link can not be blocked 379 * via this method. 380 **/ 381 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 382 { 383 u32 mmngc; 384 385 DEBUGFUNC("ixgbe_check_reset_blocked"); 386 387 /* If we don't have this bit, it can't be blocking */ 388 if (hw->mac.type == ixgbe_mac_82598EB) 389 return FALSE; 390 391 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 392 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 393 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 394 "MNG_VETO bit detected.\n"); 395 return TRUE; 396 } 397 398 return FALSE; 399 } 400 401 /** 402 * ixgbe_validate_phy_addr - Determines phy address is valid 403 * @hw: pointer to hardware structure 404 * 405 **/ 406 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 407 { 408 u16 phy_id = 0; 409 bool valid = FALSE; 410 411 DEBUGFUNC("ixgbe_validate_phy_addr"); 412 413 hw->phy.addr = phy_addr; 414 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 415 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 416 417 if (phy_id != 0xFFFF && phy_id != 0x0) 418 valid = TRUE; 419 420 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 421 422 return valid; 423 } 424 425 /** 426 * ixgbe_get_phy_id - Get the phy type 427 * @hw: pointer to hardware structure 428 * 429 **/ 430 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 431 { 432 u32 status; 433 u16 phy_id_high = 0; 434 u16 phy_id_low = 0; 435 436 DEBUGFUNC("ixgbe_get_phy_id"); 437 438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 439 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 440 &phy_id_high); 441 442 if (status == IXGBE_SUCCESS) { 443 hw->phy.id = (u32)(phy_id_high << 16); 444 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 445 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 446 &phy_id_low); 447 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 448 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 449 } 450 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 451 phy_id_high, phy_id_low); 452 453 return status; 454 } 455 456 /** 457 * ixgbe_get_phy_type_from_id - Get the phy type 458 * @phy_id: PHY ID information 459 * 460 **/ 461 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 462 { 463 enum ixgbe_phy_type phy_type; 464 465 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 466 467 switch (phy_id) { 468 case TN1010_PHY_ID: 469 phy_type = ixgbe_phy_tn; 470 break; 471 case X550_PHY_ID2: 472 case X550_PHY_ID3: 473 case X540_PHY_ID: 474 phy_type = ixgbe_phy_aq; 475 break; 476 case QT2022_PHY_ID: 477 phy_type = ixgbe_phy_qt; 478 break; 479 case ATH_PHY_ID: 480 phy_type = ixgbe_phy_nl; 481 break; 482 case X557_PHY_ID: 483 case X557_PHY_ID2: 484 phy_type = ixgbe_phy_x550em_ext_t; 485 break; 486 case IXGBE_M88E1500_E_PHY_ID: 487 case IXGBE_M88E1543_E_PHY_ID: 488 phy_type = ixgbe_phy_ext_1g_t; 489 break; 490 default: 491 phy_type = ixgbe_phy_unknown; 492 break; 493 } 494 return phy_type; 495 } 496 497 /** 498 * ixgbe_reset_phy_generic - Performs a PHY reset 499 * @hw: pointer to hardware structure 500 **/ 501 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 502 { 503 u32 i; 504 u16 ctrl = 0; 505 s32 status = IXGBE_SUCCESS; 506 507 DEBUGFUNC("ixgbe_reset_phy_generic"); 508 509 if (hw->phy.type == ixgbe_phy_unknown) 510 status = ixgbe_identify_phy_generic(hw); 511 512 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 513 goto out; 514 515 /* Don't reset PHY if it's shut down due to overtemp. */ 516 if (!hw->phy.reset_if_overtemp && 517 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 518 goto out; 519 520 /* Blocked by MNG FW so bail */ 521 if (ixgbe_check_reset_blocked(hw)) 522 goto out; 523 524 /* 525 * Perform soft PHY reset to the PHY_XS. 526 * This will cause a soft reset to the PHY 527 */ 528 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 529 IXGBE_MDIO_PHY_XS_DEV_TYPE, 530 IXGBE_MDIO_PHY_XS_RESET); 531 532 /* 533 * Poll for reset bit to self-clear indicating reset is complete. 534 * Some PHYs could take up to 3 seconds to complete and need about 535 * 1.7 usec delay after the reset is complete. 536 */ 537 for (i = 0; i < 30; i++) { 538 msec_delay(100); 539 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 540 status = hw->phy.ops.read_reg(hw, 541 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 542 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 543 &ctrl); 544 if (status != IXGBE_SUCCESS) 545 return status; 546 547 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 548 usec_delay(2); 549 break; 550 } 551 } else { 552 status = hw->phy.ops.read_reg(hw, 553 IXGBE_MDIO_PHY_XS_CONTROL, 554 IXGBE_MDIO_PHY_XS_DEV_TYPE, 555 &ctrl); 556 if (status != IXGBE_SUCCESS) 557 return status; 558 559 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 560 usec_delay(2); 561 break; 562 } 563 } 564 } 565 566 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 567 status = IXGBE_ERR_RESET_FAILED; 568 ERROR_REPORT1(IXGBE_ERROR_POLLING, 569 "PHY reset polling failed to complete.\n"); 570 } 571 572 out: 573 return status; 574 } 575 576 /** 577 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 578 * the SWFW lock 579 * @hw: pointer to hardware structure 580 * @reg_addr: 32 bit address of PHY register to read 581 * @phy_data: Pointer to read data from PHY register 582 **/ 583 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 584 u16 *phy_data) 585 { 586 u32 i, data, command; 587 588 /* Setup and write the address cycle command */ 589 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 590 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 591 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 592 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 593 594 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 595 596 /* 597 * Check every 10 usec to see if the address cycle completed. 598 * The MDI Command bit will clear when the operation is 599 * complete 600 */ 601 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 602 usec_delay(10); 603 604 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 605 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 606 break; 607 } 608 609 610 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 611 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 612 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 613 return IXGBE_ERR_PHY; 614 } 615 616 /* 617 * Address cycle complete, setup and write the read 618 * command 619 */ 620 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 621 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 622 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 623 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 624 625 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 626 627 /* 628 * Check every 10 usec to see if the address cycle 629 * completed. The MDI Command bit will clear when the 630 * operation is complete 631 */ 632 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 633 usec_delay(10); 634 635 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 636 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 637 break; 638 } 639 640 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 641 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 642 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 643 return IXGBE_ERR_PHY; 644 } 645 646 /* 647 * Read operation is complete. Get the data 648 * from MSRWD 649 */ 650 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 651 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 652 *phy_data = (u16)(data); 653 654 return IXGBE_SUCCESS; 655 } 656 657 /** 658 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 659 * using the SWFW lock - this function is needed in most cases 660 * @hw: pointer to hardware structure 661 * @reg_addr: 32 bit address of PHY register to read 662 * @phy_data: Pointer to read data from PHY register 663 **/ 664 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 665 u32 device_type, u16 *phy_data) 666 { 667 s32 status; 668 u32 gssr = hw->phy.phy_semaphore_mask; 669 670 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 671 672 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 673 return IXGBE_ERR_SWFW_SYNC; 674 675 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 676 677 hw->mac.ops.release_swfw_sync(hw, gssr); 678 679 return status; 680 } 681 682 /** 683 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 684 * without SWFW lock 685 * @hw: pointer to hardware structure 686 * @reg_addr: 32 bit PHY register to write 687 * @device_type: 5 bit device type 688 * @phy_data: Data to write to the PHY register 689 **/ 690 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 691 u32 device_type, u16 phy_data) 692 { 693 u32 i, command; 694 695 /* Put the data in the MDI single read and write data register*/ 696 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 697 698 /* Setup and write the address cycle command */ 699 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 700 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 701 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 702 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 703 704 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 705 706 /* 707 * Check every 10 usec to see if the address cycle completed. 708 * The MDI Command bit will clear when the operation is 709 * complete 710 */ 711 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 712 usec_delay(10); 713 714 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 715 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 716 break; 717 } 718 719 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 720 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 721 return IXGBE_ERR_PHY; 722 } 723 724 /* 725 * Address cycle complete, setup and write the write 726 * command 727 */ 728 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 729 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 730 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 731 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 732 733 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 734 735 /* 736 * Check every 10 usec to see if the address cycle 737 * completed. The MDI Command bit will clear when the 738 * operation is complete 739 */ 740 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 741 usec_delay(10); 742 743 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 744 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 745 break; 746 } 747 748 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 749 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 750 return IXGBE_ERR_PHY; 751 } 752 753 return IXGBE_SUCCESS; 754 } 755 756 /** 757 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 758 * using SWFW lock- this function is needed in most cases 759 * @hw: pointer to hardware structure 760 * @reg_addr: 32 bit PHY register to write 761 * @device_type: 5 bit device type 762 * @phy_data: Data to write to the PHY register 763 **/ 764 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 765 u32 device_type, u16 phy_data) 766 { 767 s32 status; 768 u32 gssr = hw->phy.phy_semaphore_mask; 769 770 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 771 772 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 773 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 774 phy_data); 775 hw->mac.ops.release_swfw_sync(hw, gssr); 776 } else { 777 status = IXGBE_ERR_SWFW_SYNC; 778 } 779 780 return status; 781 } 782 783 /** 784 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 785 * @hw: pointer to hardware structure 786 * 787 * Restart auto-negotiation and PHY and waits for completion. 788 **/ 789 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 790 { 791 s32 status = IXGBE_SUCCESS; 792 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 793 bool autoneg = FALSE; 794 ixgbe_link_speed speed; 795 796 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 797 798 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 799 800 /* Set or unset auto-negotiation 10G advertisement */ 801 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 802 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 803 &autoneg_reg); 804 805 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 806 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 807 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 808 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 809 810 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 811 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 812 autoneg_reg); 813 814 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 815 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 816 &autoneg_reg); 817 818 if (hw->mac.type == ixgbe_mac_X550) { 819 /* Set or unset auto-negotiation 5G advertisement */ 820 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 822 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 823 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 824 825 /* Set or unset auto-negotiation 2.5G advertisement */ 826 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 827 if ((hw->phy.autoneg_advertised & 828 IXGBE_LINK_SPEED_2_5GB_FULL) && 829 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 830 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 831 } 832 833 /* Set or unset auto-negotiation 1G advertisement */ 834 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 835 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 836 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 837 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 838 839 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 840 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 841 autoneg_reg); 842 843 /* Set or unset auto-negotiation 100M advertisement */ 844 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 845 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 846 &autoneg_reg); 847 848 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 849 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 850 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 851 (speed & IXGBE_LINK_SPEED_100_FULL)) 852 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 853 854 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 855 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 856 autoneg_reg); 857 858 /* Blocked by MNG FW so don't reset PHY */ 859 if (ixgbe_check_reset_blocked(hw)) 860 return status; 861 862 /* Restart PHY auto-negotiation. */ 863 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 864 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 865 866 autoneg_reg |= IXGBE_MII_RESTART; 867 868 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 869 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 870 871 return status; 872 } 873 874 /** 875 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 876 * @hw: pointer to hardware structure 877 * @speed: new link speed 878 **/ 879 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 880 ixgbe_link_speed speed, 881 bool autoneg_wait_to_complete) 882 { 883 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 884 885 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 886 887 /* 888 * Clear autoneg_advertised and set new values based on input link 889 * speed. 890 */ 891 hw->phy.autoneg_advertised = 0; 892 893 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 894 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 895 896 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 897 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 898 899 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 901 902 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 904 905 if (speed & IXGBE_LINK_SPEED_100_FULL) 906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 907 908 if (speed & IXGBE_LINK_SPEED_10_FULL) 909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 910 911 /* Setup link based on the new speed settings */ 912 ixgbe_setup_phy_link(hw); 913 914 return IXGBE_SUCCESS; 915 } 916 917 /** 918 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 919 * @hw: pointer to hardware structure 920 * 921 * Determines the supported link capabilities by reading the PHY auto 922 * negotiation register. 923 **/ 924 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 925 { 926 s32 status; 927 u16 speed_ability; 928 929 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 930 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 931 &speed_ability); 932 if (status) 933 return status; 934 935 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 936 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 937 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 938 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 939 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 940 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 941 942 switch (hw->mac.type) { 943 case ixgbe_mac_X550: 944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 945 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 946 break; 947 case ixgbe_mac_X550EM_x: 948 case ixgbe_mac_X550EM_a: 949 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 950 break; 951 default: 952 break; 953 } 954 955 return status; 956 } 957 958 /** 959 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 960 * @hw: pointer to hardware structure 961 * @speed: pointer to link speed 962 * @autoneg: boolean auto-negotiation value 963 **/ 964 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 965 ixgbe_link_speed *speed, 966 bool *autoneg) 967 { 968 s32 status = IXGBE_SUCCESS; 969 970 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 971 972 *autoneg = TRUE; 973 if (!hw->phy.speeds_supported) 974 status = ixgbe_get_copper_speeds_supported(hw); 975 976 *speed = hw->phy.speeds_supported; 977 return status; 978 } 979 980 /** 981 * ixgbe_check_phy_link_tnx - Determine link and speed status 982 * @hw: pointer to hardware structure 983 * 984 * Reads the VS1 register to determine if link is up and the current speed for 985 * the PHY. 986 **/ 987 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 988 bool *link_up) 989 { 990 s32 status = IXGBE_SUCCESS; 991 u32 time_out; 992 u32 max_time_out = 10; 993 u16 phy_link = 0; 994 u16 phy_speed = 0; 995 u16 phy_data = 0; 996 997 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 998 999 /* Initialize speed and link to default case */ 1000 *link_up = FALSE; 1001 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1002 1003 /* 1004 * Check current speed and link status of the PHY register. 1005 * This is a vendor specific register and may have to 1006 * be changed for other copper PHYs. 1007 */ 1008 for (time_out = 0; time_out < max_time_out; time_out++) { 1009 usec_delay(10); 1010 status = hw->phy.ops.read_reg(hw, 1011 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1012 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1013 &phy_data); 1014 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1015 phy_speed = phy_data & 1016 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1017 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1018 *link_up = TRUE; 1019 if (phy_speed == 1020 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1021 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1022 break; 1023 } 1024 } 1025 1026 return status; 1027 } 1028 1029 /** 1030 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1031 * @hw: pointer to hardware structure 1032 * 1033 * Restart auto-negotiation and PHY and waits for completion. 1034 **/ 1035 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1036 { 1037 s32 status = IXGBE_SUCCESS; 1038 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1039 bool autoneg = FALSE; 1040 ixgbe_link_speed speed; 1041 1042 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1043 1044 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1045 1046 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1047 /* Set or unset auto-negotiation 10G advertisement */ 1048 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1049 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1050 &autoneg_reg); 1051 1052 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1053 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1054 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1055 1056 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1057 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1058 autoneg_reg); 1059 } 1060 1061 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1062 /* Set or unset auto-negotiation 1G advertisement */ 1063 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1064 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1065 &autoneg_reg); 1066 1067 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1068 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1069 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1070 1071 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1072 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1073 autoneg_reg); 1074 } 1075 1076 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1077 /* Set or unset auto-negotiation 100M advertisement */ 1078 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1079 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1080 &autoneg_reg); 1081 1082 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1083 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1084 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1085 1086 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1088 autoneg_reg); 1089 } 1090 1091 /* Blocked by MNG FW so don't reset PHY */ 1092 if (ixgbe_check_reset_blocked(hw)) 1093 return status; 1094 1095 /* Restart PHY auto-negotiation. */ 1096 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1097 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1098 1099 autoneg_reg |= IXGBE_MII_RESTART; 1100 1101 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1102 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1103 1104 return status; 1105 } 1106 1107 /** 1108 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1109 * @hw: pointer to hardware structure 1110 * @firmware_version: pointer to the PHY Firmware Version 1111 **/ 1112 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1113 u16 *firmware_version) 1114 { 1115 s32 status; 1116 1117 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1118 1119 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1120 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1121 firmware_version); 1122 1123 return status; 1124 } 1125 1126 /** 1127 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1128 * @hw: pointer to hardware structure 1129 * @firmware_version: pointer to the PHY Firmware Version 1130 **/ 1131 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1132 u16 *firmware_version) 1133 { 1134 s32 status; 1135 1136 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1137 1138 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1139 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1140 firmware_version); 1141 1142 return status; 1143 } 1144 1145 /** 1146 * ixgbe_reset_phy_nl - Performs a PHY reset 1147 * @hw: pointer to hardware structure 1148 **/ 1149 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1150 { 1151 u16 phy_offset, control, eword, edata, block_crc; 1152 bool end_data = FALSE; 1153 u16 list_offset, data_offset; 1154 u16 phy_data = 0; 1155 s32 ret_val = IXGBE_SUCCESS; 1156 u32 i; 1157 1158 DEBUGFUNC("ixgbe_reset_phy_nl"); 1159 1160 /* Blocked by MNG FW so bail */ 1161 if (ixgbe_check_reset_blocked(hw)) 1162 goto out; 1163 1164 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1165 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1166 1167 /* reset the PHY and poll for completion */ 1168 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1169 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1170 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1171 1172 for (i = 0; i < 100; i++) { 1173 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1174 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1175 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1176 break; 1177 msec_delay(10); 1178 } 1179 1180 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1181 DEBUGOUT("PHY reset did not complete.\n"); 1182 ret_val = IXGBE_ERR_PHY; 1183 goto out; 1184 } 1185 1186 /* Get init offsets */ 1187 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1188 &data_offset); 1189 if (ret_val != IXGBE_SUCCESS) 1190 goto out; 1191 1192 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1193 data_offset++; 1194 while (!end_data) { 1195 /* 1196 * Read control word from PHY init contents offset 1197 */ 1198 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1199 if (ret_val) 1200 goto err_eeprom; 1201 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1202 IXGBE_CONTROL_SHIFT_NL; 1203 edata = eword & IXGBE_DATA_MASK_NL; 1204 switch (control) { 1205 case IXGBE_DELAY_NL: 1206 data_offset++; 1207 DEBUGOUT1("DELAY: %d MS\n", edata); 1208 msec_delay(edata); 1209 break; 1210 case IXGBE_DATA_NL: 1211 DEBUGOUT("DATA:\n"); 1212 data_offset++; 1213 ret_val = hw->eeprom.ops.read(hw, data_offset, 1214 &phy_offset); 1215 if (ret_val) 1216 goto err_eeprom; 1217 data_offset++; 1218 for (i = 0; i < edata; i++) { 1219 ret_val = hw->eeprom.ops.read(hw, data_offset, 1220 &eword); 1221 if (ret_val) 1222 goto err_eeprom; 1223 hw->phy.ops.write_reg(hw, phy_offset, 1224 IXGBE_TWINAX_DEV, eword); 1225 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1226 phy_offset); 1227 data_offset++; 1228 phy_offset++; 1229 } 1230 break; 1231 case IXGBE_CONTROL_NL: 1232 data_offset++; 1233 DEBUGOUT("CONTROL:\n"); 1234 if (edata == IXGBE_CONTROL_EOL_NL) { 1235 DEBUGOUT("EOL\n"); 1236 end_data = TRUE; 1237 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1238 DEBUGOUT("SOL\n"); 1239 } else { 1240 DEBUGOUT("Bad control value\n"); 1241 ret_val = IXGBE_ERR_PHY; 1242 goto out; 1243 } 1244 break; 1245 default: 1246 DEBUGOUT("Bad control type\n"); 1247 ret_val = IXGBE_ERR_PHY; 1248 goto out; 1249 } 1250 } 1251 1252 out: 1253 return ret_val; 1254 1255 err_eeprom: 1256 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1257 "eeprom read at offset %d failed", data_offset); 1258 return IXGBE_ERR_PHY; 1259 } 1260 1261 /** 1262 * ixgbe_identify_module_generic - Identifies module type 1263 * @hw: pointer to hardware structure 1264 * 1265 * Determines HW type and calls appropriate function. 1266 **/ 1267 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1268 { 1269 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1270 1271 DEBUGFUNC("ixgbe_identify_module_generic"); 1272 1273 switch (hw->mac.ops.get_media_type(hw)) { 1274 case ixgbe_media_type_fiber: 1275 status = ixgbe_identify_sfp_module_generic(hw); 1276 break; 1277 1278 case ixgbe_media_type_fiber_qsfp: 1279 status = ixgbe_identify_qsfp_module_generic(hw); 1280 break; 1281 1282 default: 1283 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1284 status = IXGBE_ERR_SFP_NOT_PRESENT; 1285 break; 1286 } 1287 1288 return status; 1289 } 1290 1291 /** 1292 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1293 * @hw: pointer to hardware structure 1294 * 1295 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1296 **/ 1297 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1298 { 1299 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1300 u32 vendor_oui = 0; 1301 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1302 u8 identifier = 0; 1303 u8 comp_codes_1g = 0; 1304 u8 comp_codes_10g = 0; 1305 u8 oui_bytes[3] = {0, 0, 0}; 1306 u8 cable_tech = 0; 1307 u8 cable_spec = 0; 1308 u16 enforce_sfp = 0; 1309 1310 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1311 1312 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1313 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1314 status = IXGBE_ERR_SFP_NOT_PRESENT; 1315 goto out; 1316 } 1317 1318 /* LAN ID is needed for I2C access */ 1319 hw->mac.ops.set_lan_id(hw); 1320 1321 status = hw->phy.ops.read_i2c_eeprom(hw, 1322 IXGBE_SFF_IDENTIFIER, 1323 &identifier); 1324 1325 if (status != IXGBE_SUCCESS) 1326 goto err_read_i2c_eeprom; 1327 1328 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1329 hw->phy.type = ixgbe_phy_sfp_unsupported; 1330 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1331 } else { 1332 status = hw->phy.ops.read_i2c_eeprom(hw, 1333 IXGBE_SFF_1GBE_COMP_CODES, 1334 &comp_codes_1g); 1335 1336 if (status != IXGBE_SUCCESS) 1337 goto err_read_i2c_eeprom; 1338 1339 status = hw->phy.ops.read_i2c_eeprom(hw, 1340 IXGBE_SFF_10GBE_COMP_CODES, 1341 &comp_codes_10g); 1342 1343 if (status != IXGBE_SUCCESS) 1344 goto err_read_i2c_eeprom; 1345 status = hw->phy.ops.read_i2c_eeprom(hw, 1346 IXGBE_SFF_CABLE_TECHNOLOGY, 1347 &cable_tech); 1348 1349 if (status != IXGBE_SUCCESS) 1350 goto err_read_i2c_eeprom; 1351 1352 /* ID Module 1353 * ========= 1354 * 0 SFP_DA_CU 1355 * 1 SFP_SR 1356 * 2 SFP_LR 1357 * 3 SFP_DA_CORE0 - 82599-specific 1358 * 4 SFP_DA_CORE1 - 82599-specific 1359 * 5 SFP_SR/LR_CORE0 - 82599-specific 1360 * 6 SFP_SR/LR_CORE1 - 82599-specific 1361 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1362 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1363 * 9 SFP_1g_cu_CORE0 - 82599-specific 1364 * 10 SFP_1g_cu_CORE1 - 82599-specific 1365 * 11 SFP_1g_sx_CORE0 - 82599-specific 1366 * 12 SFP_1g_sx_CORE1 - 82599-specific 1367 */ 1368 if (hw->mac.type == ixgbe_mac_82598EB) { 1369 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1370 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1371 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1372 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1373 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1374 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1375 else 1376 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1377 } else { 1378 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1379 if (hw->bus.lan_id == 0) 1380 hw->phy.sfp_type = 1381 ixgbe_sfp_type_da_cu_core0; 1382 else 1383 hw->phy.sfp_type = 1384 ixgbe_sfp_type_da_cu_core1; 1385 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1386 hw->phy.ops.read_i2c_eeprom( 1387 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1388 &cable_spec); 1389 if (cable_spec & 1390 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1391 if (hw->bus.lan_id == 0) 1392 hw->phy.sfp_type = 1393 ixgbe_sfp_type_da_act_lmt_core0; 1394 else 1395 hw->phy.sfp_type = 1396 ixgbe_sfp_type_da_act_lmt_core1; 1397 } else { 1398 hw->phy.sfp_type = 1399 ixgbe_sfp_type_unknown; 1400 } 1401 } else if (comp_codes_10g & 1402 (IXGBE_SFF_10GBASESR_CAPABLE | 1403 IXGBE_SFF_10GBASELR_CAPABLE)) { 1404 if (hw->bus.lan_id == 0) 1405 hw->phy.sfp_type = 1406 ixgbe_sfp_type_srlr_core0; 1407 else 1408 hw->phy.sfp_type = 1409 ixgbe_sfp_type_srlr_core1; 1410 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1411 if (hw->bus.lan_id == 0) 1412 hw->phy.sfp_type = 1413 ixgbe_sfp_type_1g_cu_core0; 1414 else 1415 hw->phy.sfp_type = 1416 ixgbe_sfp_type_1g_cu_core1; 1417 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1418 if (hw->bus.lan_id == 0) 1419 hw->phy.sfp_type = 1420 ixgbe_sfp_type_1g_sx_core0; 1421 else 1422 hw->phy.sfp_type = 1423 ixgbe_sfp_type_1g_sx_core1; 1424 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1425 if (hw->bus.lan_id == 0) 1426 hw->phy.sfp_type = 1427 ixgbe_sfp_type_1g_lx_core0; 1428 else 1429 hw->phy.sfp_type = 1430 ixgbe_sfp_type_1g_lx_core1; 1431 } else { 1432 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1433 } 1434 } 1435 1436 if (hw->phy.sfp_type != stored_sfp_type) 1437 hw->phy.sfp_setup_needed = TRUE; 1438 1439 /* Determine if the SFP+ PHY is dual speed or not. */ 1440 hw->phy.multispeed_fiber = FALSE; 1441 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1442 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1443 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1444 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1445 hw->phy.multispeed_fiber = TRUE; 1446 1447 /* Determine PHY vendor */ 1448 if (hw->phy.type != ixgbe_phy_nl) { 1449 hw->phy.id = identifier; 1450 status = hw->phy.ops.read_i2c_eeprom(hw, 1451 IXGBE_SFF_VENDOR_OUI_BYTE0, 1452 &oui_bytes[0]); 1453 1454 if (status != IXGBE_SUCCESS) 1455 goto err_read_i2c_eeprom; 1456 1457 status = hw->phy.ops.read_i2c_eeprom(hw, 1458 IXGBE_SFF_VENDOR_OUI_BYTE1, 1459 &oui_bytes[1]); 1460 1461 if (status != IXGBE_SUCCESS) 1462 goto err_read_i2c_eeprom; 1463 1464 status = hw->phy.ops.read_i2c_eeprom(hw, 1465 IXGBE_SFF_VENDOR_OUI_BYTE2, 1466 &oui_bytes[2]); 1467 1468 if (status != IXGBE_SUCCESS) 1469 goto err_read_i2c_eeprom; 1470 1471 vendor_oui = 1472 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1473 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1474 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1475 1476 switch (vendor_oui) { 1477 case IXGBE_SFF_VENDOR_OUI_TYCO: 1478 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1479 hw->phy.type = 1480 ixgbe_phy_sfp_passive_tyco; 1481 break; 1482 case IXGBE_SFF_VENDOR_OUI_FTL: 1483 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1484 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1485 else 1486 hw->phy.type = ixgbe_phy_sfp_ftl; 1487 break; 1488 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1489 hw->phy.type = ixgbe_phy_sfp_avago; 1490 break; 1491 case IXGBE_SFF_VENDOR_OUI_INTEL: 1492 hw->phy.type = ixgbe_phy_sfp_intel; 1493 break; 1494 default: 1495 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1496 hw->phy.type = 1497 ixgbe_phy_sfp_passive_unknown; 1498 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1499 hw->phy.type = 1500 ixgbe_phy_sfp_active_unknown; 1501 else 1502 hw->phy.type = ixgbe_phy_sfp_unknown; 1503 break; 1504 } 1505 } 1506 1507 /* Allow any DA cable vendor */ 1508 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1509 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1510 status = IXGBE_SUCCESS; 1511 goto out; 1512 } 1513 1514 /* Verify supported 1G SFP modules */ 1515 if (comp_codes_10g == 0 && 1516 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1517 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1518 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1520 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1521 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1522 hw->phy.type = ixgbe_phy_sfp_unsupported; 1523 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1524 goto out; 1525 } 1526 1527 /* Anything else 82598-based is supported */ 1528 if (hw->mac.type == ixgbe_mac_82598EB) { 1529 status = IXGBE_SUCCESS; 1530 goto out; 1531 } 1532 1533 ixgbe_get_device_caps(hw, &enforce_sfp); 1534 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1535 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1537 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1539 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1540 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1541 /* Make sure we're a supported PHY type */ 1542 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1543 status = IXGBE_SUCCESS; 1544 } else { 1545 if (hw->allow_unsupported_sfp == TRUE) { 1546 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1547 status = IXGBE_SUCCESS; 1548 } else { 1549 DEBUGOUT("SFP+ module not supported\n"); 1550 hw->phy.type = 1551 ixgbe_phy_sfp_unsupported; 1552 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1553 } 1554 } 1555 } else { 1556 status = IXGBE_SUCCESS; 1557 } 1558 } 1559 1560 out: 1561 return status; 1562 1563 err_read_i2c_eeprom: 1564 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1565 if (hw->phy.type != ixgbe_phy_nl) { 1566 hw->phy.id = 0; 1567 hw->phy.type = ixgbe_phy_unknown; 1568 } 1569 return IXGBE_ERR_SFP_NOT_PRESENT; 1570 } 1571 1572 /** 1573 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1574 * @hw: pointer to hardware structure 1575 * 1576 * Determines physical layer capabilities of the current SFP. 1577 */ 1578 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1579 { 1580 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1581 u8 comp_codes_10g = 0; 1582 u8 comp_codes_1g = 0; 1583 1584 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1585 1586 hw->phy.ops.identify_sfp(hw); 1587 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1588 return physical_layer; 1589 1590 switch (hw->phy.type) { 1591 case ixgbe_phy_sfp_passive_tyco: 1592 case ixgbe_phy_sfp_passive_unknown: 1593 case ixgbe_phy_qsfp_passive_unknown: 1594 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1595 break; 1596 case ixgbe_phy_sfp_ftl_active: 1597 case ixgbe_phy_sfp_active_unknown: 1598 case ixgbe_phy_qsfp_active_unknown: 1599 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1600 break; 1601 case ixgbe_phy_sfp_avago: 1602 case ixgbe_phy_sfp_ftl: 1603 case ixgbe_phy_sfp_intel: 1604 case ixgbe_phy_sfp_unknown: 1605 hw->phy.ops.read_i2c_eeprom(hw, 1606 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1607 hw->phy.ops.read_i2c_eeprom(hw, 1608 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1609 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1610 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1611 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1612 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1613 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1614 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1615 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1616 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1617 break; 1618 case ixgbe_phy_qsfp_intel: 1619 case ixgbe_phy_qsfp_unknown: 1620 hw->phy.ops.read_i2c_eeprom(hw, 1621 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1622 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1623 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1624 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1625 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1626 break; 1627 default: 1628 break; 1629 } 1630 1631 return physical_layer; 1632 } 1633 1634 /** 1635 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1636 * @hw: pointer to hardware structure 1637 * 1638 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1639 **/ 1640 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1641 { 1642 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1643 u32 vendor_oui = 0; 1644 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1645 u8 identifier = 0; 1646 u8 comp_codes_1g = 0; 1647 u8 comp_codes_10g = 0; 1648 u8 oui_bytes[3] = {0, 0, 0}; 1649 u16 enforce_sfp = 0; 1650 u8 connector = 0; 1651 u8 cable_length = 0; 1652 u8 device_tech = 0; 1653 bool active_cable = FALSE; 1654 1655 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1656 1657 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1658 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1659 status = IXGBE_ERR_SFP_NOT_PRESENT; 1660 goto out; 1661 } 1662 1663 /* LAN ID is needed for I2C access */ 1664 hw->mac.ops.set_lan_id(hw); 1665 1666 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1667 &identifier); 1668 1669 if (status != IXGBE_SUCCESS) 1670 goto err_read_i2c_eeprom; 1671 1672 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1673 hw->phy.type = ixgbe_phy_sfp_unsupported; 1674 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1675 goto out; 1676 } 1677 1678 hw->phy.id = identifier; 1679 1680 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1681 &comp_codes_10g); 1682 1683 if (status != IXGBE_SUCCESS) 1684 goto err_read_i2c_eeprom; 1685 1686 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1687 &comp_codes_1g); 1688 1689 if (status != IXGBE_SUCCESS) 1690 goto err_read_i2c_eeprom; 1691 1692 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1693 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1694 if (hw->bus.lan_id == 0) 1695 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1696 else 1697 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1698 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1699 IXGBE_SFF_10GBASELR_CAPABLE)) { 1700 if (hw->bus.lan_id == 0) 1701 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1702 else 1703 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1704 } else { 1705 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1706 active_cable = TRUE; 1707 1708 if (!active_cable) { 1709 /* check for active DA cables that pre-date 1710 * SFF-8436 v3.6 */ 1711 hw->phy.ops.read_i2c_eeprom(hw, 1712 IXGBE_SFF_QSFP_CONNECTOR, 1713 &connector); 1714 1715 hw->phy.ops.read_i2c_eeprom(hw, 1716 IXGBE_SFF_QSFP_CABLE_LENGTH, 1717 &cable_length); 1718 1719 hw->phy.ops.read_i2c_eeprom(hw, 1720 IXGBE_SFF_QSFP_DEVICE_TECH, 1721 &device_tech); 1722 1723 if ((connector == 1724 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1725 (cable_length > 0) && 1726 ((device_tech >> 4) == 1727 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1728 active_cable = TRUE; 1729 } 1730 1731 if (active_cable) { 1732 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1733 if (hw->bus.lan_id == 0) 1734 hw->phy.sfp_type = 1735 ixgbe_sfp_type_da_act_lmt_core0; 1736 else 1737 hw->phy.sfp_type = 1738 ixgbe_sfp_type_da_act_lmt_core1; 1739 } else { 1740 /* unsupported module type */ 1741 hw->phy.type = ixgbe_phy_sfp_unsupported; 1742 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1743 goto out; 1744 } 1745 } 1746 1747 if (hw->phy.sfp_type != stored_sfp_type) 1748 hw->phy.sfp_setup_needed = TRUE; 1749 1750 /* Determine if the QSFP+ PHY is dual speed or not. */ 1751 hw->phy.multispeed_fiber = FALSE; 1752 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1753 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1754 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1755 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1756 hw->phy.multispeed_fiber = TRUE; 1757 1758 /* Determine PHY vendor for optical modules */ 1759 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1760 IXGBE_SFF_10GBASELR_CAPABLE)) { 1761 status = hw->phy.ops.read_i2c_eeprom(hw, 1762 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1763 &oui_bytes[0]); 1764 1765 if (status != IXGBE_SUCCESS) 1766 goto err_read_i2c_eeprom; 1767 1768 status = hw->phy.ops.read_i2c_eeprom(hw, 1769 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1770 &oui_bytes[1]); 1771 1772 if (status != IXGBE_SUCCESS) 1773 goto err_read_i2c_eeprom; 1774 1775 status = hw->phy.ops.read_i2c_eeprom(hw, 1776 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1777 &oui_bytes[2]); 1778 1779 if (status != IXGBE_SUCCESS) 1780 goto err_read_i2c_eeprom; 1781 1782 vendor_oui = 1783 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1784 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1785 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1786 1787 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1788 hw->phy.type = ixgbe_phy_qsfp_intel; 1789 else 1790 hw->phy.type = ixgbe_phy_qsfp_unknown; 1791 1792 ixgbe_get_device_caps(hw, &enforce_sfp); 1793 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1794 /* Make sure we're a supported PHY type */ 1795 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1796 status = IXGBE_SUCCESS; 1797 } else { 1798 if (hw->allow_unsupported_sfp == TRUE) { 1799 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1800 status = IXGBE_SUCCESS; 1801 } else { 1802 DEBUGOUT("QSFP module not supported\n"); 1803 hw->phy.type = 1804 ixgbe_phy_sfp_unsupported; 1805 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1806 } 1807 } 1808 } else { 1809 status = IXGBE_SUCCESS; 1810 } 1811 } 1812 1813 out: 1814 return status; 1815 1816 err_read_i2c_eeprom: 1817 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1818 hw->phy.id = 0; 1819 hw->phy.type = ixgbe_phy_unknown; 1820 1821 return IXGBE_ERR_SFP_NOT_PRESENT; 1822 } 1823 1824 /** 1825 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1826 * @hw: pointer to hardware structure 1827 * @list_offset: offset to the SFP ID list 1828 * @data_offset: offset to the SFP data block 1829 * 1830 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1831 * so it returns the offsets to the phy init sequence block. 1832 **/ 1833 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1834 u16 *list_offset, 1835 u16 *data_offset) 1836 { 1837 u16 sfp_id; 1838 u16 sfp_type = hw->phy.sfp_type; 1839 1840 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1841 1842 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1843 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1844 1845 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1846 return IXGBE_ERR_SFP_NOT_PRESENT; 1847 1848 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1849 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1850 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1851 1852 /* 1853 * Limiting active cables and 1G Phys must be initialized as 1854 * SR modules 1855 */ 1856 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1857 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1858 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1859 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1860 sfp_type = ixgbe_sfp_type_srlr_core0; 1861 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1862 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1863 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1864 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1865 sfp_type = ixgbe_sfp_type_srlr_core1; 1866 1867 /* Read offset to PHY init contents */ 1868 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1869 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1870 "eeprom read at offset %d failed", 1871 IXGBE_PHY_INIT_OFFSET_NL); 1872 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1873 } 1874 1875 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1876 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1877 1878 /* Shift offset to first ID word */ 1879 (*list_offset)++; 1880 1881 /* 1882 * Find the matching SFP ID in the EEPROM 1883 * and program the init sequence 1884 */ 1885 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1886 goto err_phy; 1887 1888 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1889 if (sfp_id == sfp_type) { 1890 (*list_offset)++; 1891 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1892 goto err_phy; 1893 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1894 DEBUGOUT("SFP+ module not supported\n"); 1895 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1896 } else { 1897 break; 1898 } 1899 } else { 1900 (*list_offset) += 2; 1901 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1902 goto err_phy; 1903 } 1904 } 1905 1906 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1907 DEBUGOUT("No matching SFP+ module found\n"); 1908 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1909 } 1910 1911 return IXGBE_SUCCESS; 1912 1913 err_phy: 1914 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1915 "eeprom read at offset %d failed", *list_offset); 1916 return IXGBE_ERR_PHY; 1917 } 1918 1919 /** 1920 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1921 * @hw: pointer to hardware structure 1922 * @byte_offset: EEPROM byte offset to read 1923 * @eeprom_data: value read 1924 * 1925 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1926 **/ 1927 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1928 u8 *eeprom_data) 1929 { 1930 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1931 1932 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1933 IXGBE_I2C_EEPROM_DEV_ADDR, 1934 eeprom_data); 1935 } 1936 1937 /** 1938 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1939 * @hw: pointer to hardware structure 1940 * @byte_offset: byte offset at address 0xA2 1941 * @eeprom_data: value read 1942 * 1943 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1944 **/ 1945 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1946 u8 *sff8472_data) 1947 { 1948 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1949 IXGBE_I2C_EEPROM_DEV_ADDR2, 1950 sff8472_data); 1951 } 1952 1953 /** 1954 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1955 * @hw: pointer to hardware structure 1956 * @byte_offset: EEPROM byte offset to write 1957 * @eeprom_data: value to write 1958 * 1959 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1960 **/ 1961 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1962 u8 eeprom_data) 1963 { 1964 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1965 1966 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1967 IXGBE_I2C_EEPROM_DEV_ADDR, 1968 eeprom_data); 1969 } 1970 1971 /** 1972 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1973 * @hw: pointer to hardware structure 1974 * @offset: eeprom offset to be read 1975 * @addr: I2C address to be read 1976 */ 1977 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1978 { 1979 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1980 offset == IXGBE_SFF_IDENTIFIER && 1981 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1982 return TRUE; 1983 return FALSE; 1984 } 1985 1986 /** 1987 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1988 * @hw: pointer to hardware structure 1989 * @byte_offset: byte offset to read 1990 * @data: value read 1991 * @lock: TRUE if to take and release semaphore 1992 * 1993 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1994 * a specified device address. 1995 **/ 1996 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 1997 u8 dev_addr, u8 *data, bool lock) 1998 { 1999 s32 status; 2000 u32 max_retry = 10; 2001 u32 retry = 0; 2002 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2003 bool nack = 1; 2004 *data = 0; 2005 2006 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2007 2008 if (hw->mac.type >= ixgbe_mac_X550) 2009 max_retry = 3; 2010 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2011 max_retry = IXGBE_SFP_DETECT_RETRIES; 2012 2013 do { 2014 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2015 return IXGBE_ERR_SWFW_SYNC; 2016 2017 ixgbe_i2c_start(hw); 2018 2019 /* Device Address and write indication */ 2020 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2021 if (status != IXGBE_SUCCESS) 2022 goto fail; 2023 2024 status = ixgbe_get_i2c_ack(hw); 2025 if (status != IXGBE_SUCCESS) 2026 goto fail; 2027 2028 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2029 if (status != IXGBE_SUCCESS) 2030 goto fail; 2031 2032 status = ixgbe_get_i2c_ack(hw); 2033 if (status != IXGBE_SUCCESS) 2034 goto fail; 2035 2036 ixgbe_i2c_start(hw); 2037 2038 /* Device Address and read indication */ 2039 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2040 if (status != IXGBE_SUCCESS) 2041 goto fail; 2042 2043 status = ixgbe_get_i2c_ack(hw); 2044 if (status != IXGBE_SUCCESS) 2045 goto fail; 2046 2047 status = ixgbe_clock_in_i2c_byte(hw, data); 2048 if (status != IXGBE_SUCCESS) 2049 goto fail; 2050 2051 status = ixgbe_clock_out_i2c_bit(hw, nack); 2052 if (status != IXGBE_SUCCESS) 2053 goto fail; 2054 2055 ixgbe_i2c_stop(hw); 2056 if (lock) 2057 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2058 return IXGBE_SUCCESS; 2059 2060 fail: 2061 ixgbe_i2c_bus_clear(hw); 2062 if (lock) { 2063 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2064 msec_delay(100); 2065 } 2066 retry++; 2067 if (retry < max_retry) 2068 DEBUGOUT("I2C byte read error - Retrying.\n"); 2069 else 2070 DEBUGOUT("I2C byte read error.\n"); 2071 2072 } while (retry < max_retry); 2073 2074 return status; 2075 } 2076 2077 /** 2078 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2079 * @hw: pointer to hardware structure 2080 * @byte_offset: byte offset to read 2081 * @data: value read 2082 * 2083 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2084 * a specified device address. 2085 **/ 2086 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2087 u8 dev_addr, u8 *data) 2088 { 2089 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2090 data, TRUE); 2091 } 2092 2093 /** 2094 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2095 * @hw: pointer to hardware structure 2096 * @byte_offset: byte offset to read 2097 * @data: value read 2098 * 2099 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2100 * a specified device address. 2101 **/ 2102 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2103 u8 dev_addr, u8 *data) 2104 { 2105 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2106 data, FALSE); 2107 } 2108 2109 /** 2110 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2111 * @hw: pointer to hardware structure 2112 * @byte_offset: byte offset to write 2113 * @data: value to write 2114 * @lock: TRUE if to take and release semaphore 2115 * 2116 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2117 * a specified device address. 2118 **/ 2119 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2120 u8 dev_addr, u8 data, bool lock) 2121 { 2122 s32 status; 2123 u32 max_retry = 2; 2124 u32 retry = 0; 2125 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2126 2127 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2128 2129 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2130 IXGBE_SUCCESS) 2131 return IXGBE_ERR_SWFW_SYNC; 2132 2133 do { 2134 ixgbe_i2c_start(hw); 2135 2136 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2137 if (status != IXGBE_SUCCESS) 2138 goto fail; 2139 2140 status = ixgbe_get_i2c_ack(hw); 2141 if (status != IXGBE_SUCCESS) 2142 goto fail; 2143 2144 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2145 if (status != IXGBE_SUCCESS) 2146 goto fail; 2147 2148 status = ixgbe_get_i2c_ack(hw); 2149 if (status != IXGBE_SUCCESS) 2150 goto fail; 2151 2152 status = ixgbe_clock_out_i2c_byte(hw, data); 2153 if (status != IXGBE_SUCCESS) 2154 goto fail; 2155 2156 status = ixgbe_get_i2c_ack(hw); 2157 if (status != IXGBE_SUCCESS) 2158 goto fail; 2159 2160 ixgbe_i2c_stop(hw); 2161 if (lock) 2162 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2163 return IXGBE_SUCCESS; 2164 2165 fail: 2166 ixgbe_i2c_bus_clear(hw); 2167 retry++; 2168 if (retry < max_retry) 2169 DEBUGOUT("I2C byte write error - Retrying.\n"); 2170 else 2171 DEBUGOUT("I2C byte write error.\n"); 2172 } while (retry < max_retry); 2173 2174 if (lock) 2175 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2176 2177 return status; 2178 } 2179 2180 /** 2181 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2182 * @hw: pointer to hardware structure 2183 * @byte_offset: byte offset to write 2184 * @data: value to write 2185 * 2186 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2187 * a specified device address. 2188 **/ 2189 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2190 u8 dev_addr, u8 data) 2191 { 2192 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2193 data, TRUE); 2194 } 2195 2196 /** 2197 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2198 * @hw: pointer to hardware structure 2199 * @byte_offset: byte offset to write 2200 * @data: value to write 2201 * 2202 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2203 * a specified device address. 2204 **/ 2205 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2206 u8 dev_addr, u8 data) 2207 { 2208 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2209 data, FALSE); 2210 } 2211 2212 /** 2213 * ixgbe_i2c_start - Sets I2C start condition 2214 * @hw: pointer to hardware structure 2215 * 2216 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2217 * Set bit-bang mode on X550 hardware. 2218 **/ 2219 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2220 { 2221 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2222 2223 DEBUGFUNC("ixgbe_i2c_start"); 2224 2225 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2226 2227 /* Start condition must begin with data and clock high */ 2228 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2229 ixgbe_raise_i2c_clk(hw, &i2cctl); 2230 2231 /* Setup time for start condition (4.7us) */ 2232 usec_delay(IXGBE_I2C_T_SU_STA); 2233 2234 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2235 2236 /* Hold time for start condition (4us) */ 2237 usec_delay(IXGBE_I2C_T_HD_STA); 2238 2239 ixgbe_lower_i2c_clk(hw, &i2cctl); 2240 2241 /* Minimum low period of clock is 4.7 us */ 2242 usec_delay(IXGBE_I2C_T_LOW); 2243 2244 } 2245 2246 /** 2247 * ixgbe_i2c_stop - Sets I2C stop condition 2248 * @hw: pointer to hardware structure 2249 * 2250 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2251 * Disables bit-bang mode and negates data output enable on X550 2252 * hardware. 2253 **/ 2254 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2255 { 2256 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2257 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2258 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2259 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2260 2261 DEBUGFUNC("ixgbe_i2c_stop"); 2262 2263 /* Stop condition must begin with data low and clock high */ 2264 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2265 ixgbe_raise_i2c_clk(hw, &i2cctl); 2266 2267 /* Setup time for stop condition (4us) */ 2268 usec_delay(IXGBE_I2C_T_SU_STO); 2269 2270 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2271 2272 /* bus free time between stop and start (4.7us)*/ 2273 usec_delay(IXGBE_I2C_T_BUF); 2274 2275 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2276 i2cctl &= ~bb_en_bit; 2277 i2cctl |= data_oe_bit | clk_oe_bit; 2278 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2279 IXGBE_WRITE_FLUSH(hw); 2280 } 2281 } 2282 2283 /** 2284 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2285 * @hw: pointer to hardware structure 2286 * @data: data byte to clock in 2287 * 2288 * Clocks in one byte data via I2C data/clock 2289 **/ 2290 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2291 { 2292 s32 i; 2293 bool bit = 0; 2294 2295 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2296 2297 *data = 0; 2298 for (i = 7; i >= 0; i--) { 2299 ixgbe_clock_in_i2c_bit(hw, &bit); 2300 *data |= bit << i; 2301 } 2302 2303 return IXGBE_SUCCESS; 2304 } 2305 2306 /** 2307 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2308 * @hw: pointer to hardware structure 2309 * @data: data byte clocked out 2310 * 2311 * Clocks out one byte data via I2C data/clock 2312 **/ 2313 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2314 { 2315 s32 status = IXGBE_SUCCESS; 2316 s32 i; 2317 u32 i2cctl; 2318 bool bit; 2319 2320 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2321 2322 for (i = 7; i >= 0; i--) { 2323 bit = (data >> i) & 0x1; 2324 status = ixgbe_clock_out_i2c_bit(hw, bit); 2325 2326 if (status != IXGBE_SUCCESS) 2327 break; 2328 } 2329 2330 /* Release SDA line (set high) */ 2331 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2332 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2333 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2334 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2335 IXGBE_WRITE_FLUSH(hw); 2336 2337 return status; 2338 } 2339 2340 /** 2341 * ixgbe_get_i2c_ack - Polls for I2C ACK 2342 * @hw: pointer to hardware structure 2343 * 2344 * Clocks in/out one bit via I2C data/clock 2345 **/ 2346 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2347 { 2348 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2349 s32 status = IXGBE_SUCCESS; 2350 u32 i = 0; 2351 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2352 u32 timeout = 10; 2353 bool ack = 1; 2354 2355 DEBUGFUNC("ixgbe_get_i2c_ack"); 2356 2357 if (data_oe_bit) { 2358 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2359 i2cctl |= data_oe_bit; 2360 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2361 IXGBE_WRITE_FLUSH(hw); 2362 } 2363 ixgbe_raise_i2c_clk(hw, &i2cctl); 2364 2365 /* Minimum high period of clock is 4us */ 2366 usec_delay(IXGBE_I2C_T_HIGH); 2367 2368 /* Poll for ACK. Note that ACK in I2C spec is 2369 * transition from 1 to 0 */ 2370 for (i = 0; i < timeout; i++) { 2371 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2372 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2373 2374 usec_delay(1); 2375 if (!ack) 2376 break; 2377 } 2378 2379 if (ack) { 2380 DEBUGOUT("I2C ack was not received.\n"); 2381 status = IXGBE_ERR_I2C; 2382 } 2383 2384 ixgbe_lower_i2c_clk(hw, &i2cctl); 2385 2386 /* Minimum low period of clock is 4.7 us */ 2387 usec_delay(IXGBE_I2C_T_LOW); 2388 2389 return status; 2390 } 2391 2392 /** 2393 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2394 * @hw: pointer to hardware structure 2395 * @data: read data value 2396 * 2397 * Clocks in one bit via I2C data/clock 2398 **/ 2399 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2400 { 2401 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2402 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2403 2404 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2405 2406 if (data_oe_bit) { 2407 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2408 i2cctl |= data_oe_bit; 2409 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2410 IXGBE_WRITE_FLUSH(hw); 2411 } 2412 ixgbe_raise_i2c_clk(hw, &i2cctl); 2413 2414 /* Minimum high period of clock is 4us */ 2415 usec_delay(IXGBE_I2C_T_HIGH); 2416 2417 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2418 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2419 2420 ixgbe_lower_i2c_clk(hw, &i2cctl); 2421 2422 /* Minimum low period of clock is 4.7 us */ 2423 usec_delay(IXGBE_I2C_T_LOW); 2424 2425 return IXGBE_SUCCESS; 2426 } 2427 2428 /** 2429 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2430 * @hw: pointer to hardware structure 2431 * @data: data value to write 2432 * 2433 * Clocks out one bit via I2C data/clock 2434 **/ 2435 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2436 { 2437 s32 status; 2438 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2439 2440 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2441 2442 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2443 if (status == IXGBE_SUCCESS) { 2444 ixgbe_raise_i2c_clk(hw, &i2cctl); 2445 2446 /* Minimum high period of clock is 4us */ 2447 usec_delay(IXGBE_I2C_T_HIGH); 2448 2449 ixgbe_lower_i2c_clk(hw, &i2cctl); 2450 2451 /* Minimum low period of clock is 4.7 us. 2452 * This also takes care of the data hold time. 2453 */ 2454 usec_delay(IXGBE_I2C_T_LOW); 2455 } else { 2456 status = IXGBE_ERR_I2C; 2457 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2458 "I2C data was not set to %X\n", data); 2459 } 2460 2461 return status; 2462 } 2463 2464 /** 2465 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2466 * @hw: pointer to hardware structure 2467 * @i2cctl: Current value of I2CCTL register 2468 * 2469 * Raises the I2C clock line '0'->'1' 2470 * Negates the I2C clock output enable on X550 hardware. 2471 **/ 2472 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2473 { 2474 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2475 u32 i = 0; 2476 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2477 u32 i2cctl_r = 0; 2478 2479 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2480 2481 if (clk_oe_bit) { 2482 *i2cctl |= clk_oe_bit; 2483 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2484 } 2485 2486 for (i = 0; i < timeout; i++) { 2487 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2488 2489 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2490 IXGBE_WRITE_FLUSH(hw); 2491 /* SCL rise time (1000ns) */ 2492 usec_delay(IXGBE_I2C_T_RISE); 2493 2494 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2495 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2496 break; 2497 } 2498 } 2499 2500 /** 2501 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2502 * @hw: pointer to hardware structure 2503 * @i2cctl: Current value of I2CCTL register 2504 * 2505 * Lowers the I2C clock line '1'->'0' 2506 * Asserts the I2C clock output enable on X550 hardware. 2507 **/ 2508 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2509 { 2510 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2511 2512 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2513 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2514 2515 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2516 IXGBE_WRITE_FLUSH(hw); 2517 2518 /* SCL fall time (300ns) */ 2519 usec_delay(IXGBE_I2C_T_FALL); 2520 } 2521 2522 /** 2523 * ixgbe_set_i2c_data - Sets the I2C data bit 2524 * @hw: pointer to hardware structure 2525 * @i2cctl: Current value of I2CCTL register 2526 * @data: I2C data value (0 or 1) to set 2527 * 2528 * Sets the I2C data bit 2529 * Asserts the I2C data output enable on X550 hardware. 2530 **/ 2531 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2532 { 2533 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2534 s32 status = IXGBE_SUCCESS; 2535 2536 DEBUGFUNC("ixgbe_set_i2c_data"); 2537 2538 if (data) 2539 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2540 else 2541 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2542 *i2cctl &= ~data_oe_bit; 2543 2544 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2545 IXGBE_WRITE_FLUSH(hw); 2546 2547 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2548 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2549 2550 if (!data) /* Can't verify data in this case */ 2551 return IXGBE_SUCCESS; 2552 if (data_oe_bit) { 2553 *i2cctl |= data_oe_bit; 2554 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2555 IXGBE_WRITE_FLUSH(hw); 2556 } 2557 2558 /* Verify data was set correctly */ 2559 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2560 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2561 status = IXGBE_ERR_I2C; 2562 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2563 "Error - I2C data was not set to %X.\n", 2564 data); 2565 } 2566 2567 return status; 2568 } 2569 2570 /** 2571 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2572 * @hw: pointer to hardware structure 2573 * @i2cctl: Current value of I2CCTL register 2574 * 2575 * Returns the I2C data bit value 2576 * Negates the I2C data output enable on X550 hardware. 2577 **/ 2578 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2579 { 2580 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2581 bool data; 2582 2583 DEBUGFUNC("ixgbe_get_i2c_data"); 2584 2585 if (data_oe_bit) { 2586 *i2cctl |= data_oe_bit; 2587 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2588 IXGBE_WRITE_FLUSH(hw); 2589 usec_delay(IXGBE_I2C_T_FALL); 2590 } 2591 2592 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2593 data = 1; 2594 else 2595 data = 0; 2596 2597 return data; 2598 } 2599 2600 /** 2601 * ixgbe_i2c_bus_clear - Clears the I2C bus 2602 * @hw: pointer to hardware structure 2603 * 2604 * Clears the I2C bus by sending nine clock pulses. 2605 * Used when data line is stuck low. 2606 **/ 2607 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2608 { 2609 u32 i2cctl; 2610 u32 i; 2611 2612 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2613 2614 ixgbe_i2c_start(hw); 2615 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2616 2617 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2618 2619 for (i = 0; i < 9; i++) { 2620 ixgbe_raise_i2c_clk(hw, &i2cctl); 2621 2622 /* Min high period of clock is 4us */ 2623 usec_delay(IXGBE_I2C_T_HIGH); 2624 2625 ixgbe_lower_i2c_clk(hw, &i2cctl); 2626 2627 /* Min low period of clock is 4.7us*/ 2628 usec_delay(IXGBE_I2C_T_LOW); 2629 } 2630 2631 ixgbe_i2c_start(hw); 2632 2633 /* Put the i2c bus back to default state */ 2634 ixgbe_i2c_stop(hw); 2635 } 2636 2637 /** 2638 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2639 * @hw: pointer to hardware structure 2640 * 2641 * Checks if the LASI temp alarm status was triggered due to overtemp 2642 **/ 2643 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2644 { 2645 s32 status = IXGBE_SUCCESS; 2646 u16 phy_data = 0; 2647 2648 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2649 2650 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2651 goto out; 2652 2653 /* Check that the LASI temp alarm status was triggered */ 2654 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2655 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2656 2657 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2658 goto out; 2659 2660 status = IXGBE_ERR_OVERTEMP; 2661 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2662 out: 2663 return status; 2664 } 2665 2666 /** 2667 * ixgbe_set_copper_phy_power - Control power for copper phy 2668 * @hw: pointer to hardware structure 2669 * @on: TRUE for on, FALSE for off 2670 */ 2671 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2672 { 2673 u32 status; 2674 u16 reg; 2675 2676 if (!on && ixgbe_mng_present(hw)) 2677 return 0; 2678 2679 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2680 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2681 ®); 2682 if (status) 2683 return status; 2684 2685 if (on) { 2686 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2687 } else { 2688 if (ixgbe_check_reset_blocked(hw)) 2689 return 0; 2690 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2691 } 2692 2693 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2694 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2695 reg); 2696 return status; 2697 } 2698
Indexes created Sat Sep 27 14:09:57 GMT 2025