ixgbe_phy.c revision 1.13
1 /* $NetBSD: ixgbe_phy.c,v 1.13 2017/11/07 05:41:54 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2017, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 320688 2017-07-05 17:27:03Z erj $*/ 36 37 #include "ixgbe_api.h" 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 41 #include <dev/mii/mdio.h> 42 43 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 44 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 45 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 46 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 47 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 48 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 49 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 50 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 51 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 52 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 53 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 54 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 55 u8 *sff8472_data); 56 57 /** 58 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 59 * @hw: pointer to the hardware structure 60 * @byte: byte to send 61 * 62 * Returns an error code on error. 63 */ 64 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 65 { 66 s32 status; 67 68 status = ixgbe_clock_out_i2c_byte(hw, byte); 69 if (status) 70 return status; 71 return ixgbe_get_i2c_ack(hw); 72 } 73 74 /** 75 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 76 * @hw: pointer to the hardware structure 77 * @byte: pointer to a u8 to receive the byte 78 * 79 * Returns an error code on error. 80 */ 81 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 82 { 83 s32 status; 84 85 status = ixgbe_clock_in_i2c_byte(hw, byte); 86 if (status) 87 return status; 88 /* ACK */ 89 return ixgbe_clock_out_i2c_bit(hw, FALSE); 90 } 91 92 /** 93 * ixgbe_ones_comp_byte_add - Perform one's complement addition 94 * @add1 - addend 1 95 * @add2 - addend 2 96 * 97 * Returns one's complement 8-bit sum. 98 */ 99 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 100 { 101 u16 sum = add1 + add2; 102 103 sum = (sum & 0xFF) + (sum >> 8); 104 return sum & 0xFF; 105 } 106 107 /** 108 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 109 * @hw: pointer to the hardware structure 110 * @addr: I2C bus address to read from 111 * @reg: I2C device register to read from 112 * @val: pointer to location to receive read value 113 * @lock: TRUE if to take and release semaphore 114 * 115 * Returns an error code on error. 116 */ 117 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 118 u16 *val, bool lock) 119 { 120 u32 swfw_mask = hw->phy.phy_semaphore_mask; 121 int max_retry = 3; 122 int retry = 0; 123 u8 csum_byte; 124 u8 high_bits; 125 u8 low_bits; 126 u8 reg_high; 127 u8 csum; 128 129 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 130 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 131 csum = ~csum; 132 do { 133 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 134 return IXGBE_ERR_SWFW_SYNC; 135 ixgbe_i2c_start(hw); 136 /* Device Address and write indication */ 137 if (ixgbe_out_i2c_byte_ack(hw, addr)) 138 goto fail; 139 /* Write bits 14:8 */ 140 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 141 goto fail; 142 /* Write bits 7:0 */ 143 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 144 goto fail; 145 /* Write csum */ 146 if (ixgbe_out_i2c_byte_ack(hw, csum)) 147 goto fail; 148 /* Re-start condition */ 149 ixgbe_i2c_start(hw); 150 /* Device Address and read indication */ 151 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 152 goto fail; 153 /* Get upper bits */ 154 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 155 goto fail; 156 /* Get low bits */ 157 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 158 goto fail; 159 /* Get csum */ 160 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 161 goto fail; 162 /* NACK */ 163 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 164 goto fail; 165 ixgbe_i2c_stop(hw); 166 if (lock) 167 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 168 *val = (high_bits << 8) | low_bits; 169 return 0; 170 171 fail: 172 ixgbe_i2c_bus_clear(hw); 173 if (lock) 174 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 175 retry++; 176 if (retry < max_retry) 177 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 178 else 179 DEBUGOUT("I2C byte read combined error.\n"); 180 } while (retry < max_retry); 181 182 return IXGBE_ERR_I2C; 183 } 184 185 /** 186 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 187 * @hw: pointer to the hardware structure 188 * @addr: I2C bus address to write to 189 * @reg: I2C device register to write to 190 * @val: value to write 191 * @lock: TRUE if to take and release semaphore 192 * 193 * Returns an error code on error. 194 */ 195 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 196 u16 val, bool lock) 197 { 198 u32 swfw_mask = hw->phy.phy_semaphore_mask; 199 int max_retry = 1; 200 int retry = 0; 201 u8 reg_high; 202 u8 csum; 203 204 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 205 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 206 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 207 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 208 csum = ~csum; 209 do { 210 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 211 return IXGBE_ERR_SWFW_SYNC; 212 ixgbe_i2c_start(hw); 213 /* Device Address and write indication */ 214 if (ixgbe_out_i2c_byte_ack(hw, addr)) 215 goto fail; 216 /* Write bits 14:8 */ 217 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 218 goto fail; 219 /* Write bits 7:0 */ 220 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 221 goto fail; 222 /* Write data 15:8 */ 223 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 224 goto fail; 225 /* Write data 7:0 */ 226 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 227 goto fail; 228 /* Write csum */ 229 if (ixgbe_out_i2c_byte_ack(hw, csum)) 230 goto fail; 231 ixgbe_i2c_stop(hw); 232 if (lock) 233 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 234 return 0; 235 236 fail: 237 ixgbe_i2c_bus_clear(hw); 238 if (lock) 239 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 240 retry++; 241 if (retry < max_retry) 242 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 243 else 244 DEBUGOUT("I2C byte write combined error.\n"); 245 } while (retry < max_retry); 246 247 return IXGBE_ERR_I2C; 248 } 249 250 /** 251 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 252 * @hw: pointer to the hardware structure 253 * 254 * Initialize the function pointers. 255 **/ 256 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 257 { 258 struct ixgbe_phy_info *phy = &hw->phy; 259 260 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 261 262 /* PHY */ 263 phy->ops.identify = ixgbe_identify_phy_generic; 264 phy->ops.reset = ixgbe_reset_phy_generic; 265 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 266 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 267 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 268 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 269 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 270 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 271 phy->ops.check_link = NULL; 272 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 273 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 274 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 275 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 276 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 277 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 278 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 279 phy->ops.identify_sfp = ixgbe_identify_module_generic; 280 phy->sfp_type = ixgbe_sfp_type_unknown; 281 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 282 phy->ops.write_i2c_byte_unlocked = 283 ixgbe_write_i2c_byte_generic_unlocked; 284 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 285 return IXGBE_SUCCESS; 286 } 287 288 /** 289 * ixgbe_probe_phy - Probe a single address for a PHY 290 * @hw: pointer to hardware structure 291 * @phy_addr: PHY address to probe 292 * 293 * Returns TRUE if PHY found 294 */ 295 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 296 { 297 u16 ext_ability = 0; 298 299 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 300 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 301 phy_addr); 302 return FALSE; 303 } 304 305 if (ixgbe_get_phy_id(hw)) 306 return FALSE; 307 308 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 309 310 if (hw->phy.type == ixgbe_phy_unknown) { 311 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 312 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 313 if (ext_ability & 314 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 315 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 316 hw->phy.type = ixgbe_phy_cu_unknown; 317 else 318 hw->phy.type = ixgbe_phy_generic; 319 } 320 321 return TRUE; 322 } 323 324 /** 325 * ixgbe_identify_phy_generic - Get physical layer module 326 * @hw: pointer to hardware structure 327 * 328 * Determines the physical layer module found on the current adapter. 329 **/ 330 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 331 { 332 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 333 u16 phy_addr; 334 335 DEBUGFUNC("ixgbe_identify_phy_generic"); 336 337 if (!hw->phy.phy_semaphore_mask) { 338 if (hw->bus.lan_id) 339 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 340 else 341 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 342 } 343 344 if (hw->phy.type != ixgbe_phy_unknown) 345 return IXGBE_SUCCESS; 346 347 if (hw->phy.nw_mng_if_sel) { 348 phy_addr = (hw->phy.nw_mng_if_sel & 349 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 350 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 351 if (ixgbe_probe_phy(hw, phy_addr)) 352 return IXGBE_SUCCESS; 353 else 354 return IXGBE_ERR_PHY_ADDR_INVALID; 355 } 356 357 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 358 if (ixgbe_probe_phy(hw, phy_addr)) { 359 status = IXGBE_SUCCESS; 360 break; 361 } 362 } 363 364 /* Certain media types do not have a phy so an address will not 365 * be found and the code will take this path. Caller has to 366 * decide if it is an error or not. 367 */ 368 if (status != IXGBE_SUCCESS) 369 hw->phy.addr = 0; 370 371 return status; 372 } 373 374 /** 375 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 376 * @hw: pointer to the hardware structure 377 * 378 * This function checks the MMNGC.MNG_VETO bit to see if there are 379 * any constraints on link from manageability. For MAC's that don't 380 * have this bit just return faluse since the link can not be blocked 381 * via this method. 382 **/ 383 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 384 { 385 u32 mmngc; 386 387 DEBUGFUNC("ixgbe_check_reset_blocked"); 388 389 /* If we don't have this bit, it can't be blocking */ 390 if (hw->mac.type == ixgbe_mac_82598EB) 391 return FALSE; 392 393 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 394 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 395 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 396 "MNG_VETO bit detected.\n"); 397 return TRUE; 398 } 399 400 return FALSE; 401 } 402 403 /** 404 * ixgbe_validate_phy_addr - Determines phy address is valid 405 * @hw: pointer to hardware structure 406 * 407 **/ 408 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 409 { 410 u16 phy_id = 0; 411 bool valid = FALSE; 412 413 DEBUGFUNC("ixgbe_validate_phy_addr"); 414 415 hw->phy.addr = phy_addr; 416 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 417 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 418 419 if (phy_id != 0xFFFF && phy_id != 0x0) 420 valid = TRUE; 421 422 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 423 424 return valid; 425 } 426 427 /** 428 * ixgbe_get_phy_id - Get the phy type 429 * @hw: pointer to hardware structure 430 * 431 **/ 432 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 433 { 434 u32 status; 435 u16 phy_id_high = 0; 436 u16 phy_id_low = 0; 437 438 DEBUGFUNC("ixgbe_get_phy_id"); 439 440 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 441 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 442 &phy_id_high); 443 444 if (status == IXGBE_SUCCESS) { 445 hw->phy.id = (u32)(phy_id_high << 16); 446 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 447 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 448 &phy_id_low); 449 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 450 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 451 } 452 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 453 phy_id_high, phy_id_low); 454 455 return status; 456 } 457 458 /** 459 * ixgbe_get_phy_type_from_id - Get the phy type 460 * @phy_id: PHY ID information 461 * 462 **/ 463 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 464 { 465 enum ixgbe_phy_type phy_type; 466 467 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 468 469 switch (phy_id) { 470 case TN1010_PHY_ID: 471 phy_type = ixgbe_phy_tn; 472 break; 473 case X550_PHY_ID2: 474 case X550_PHY_ID3: 475 case X540_PHY_ID: 476 phy_type = ixgbe_phy_aq; 477 break; 478 case QT2022_PHY_ID: 479 phy_type = ixgbe_phy_qt; 480 break; 481 case ATH_PHY_ID: 482 phy_type = ixgbe_phy_nl; 483 break; 484 case X557_PHY_ID: 485 case X557_PHY_ID2: 486 phy_type = ixgbe_phy_x550em_ext_t; 487 break; 488 case IXGBE_M88E1500_E_PHY_ID: 489 case IXGBE_M88E1543_E_PHY_ID: 490 phy_type = ixgbe_phy_ext_1g_t; 491 break; 492 default: 493 phy_type = ixgbe_phy_unknown; 494 break; 495 } 496 return phy_type; 497 } 498 499 /** 500 * ixgbe_reset_phy_generic - Performs a PHY reset 501 * @hw: pointer to hardware structure 502 **/ 503 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 504 { 505 u32 i; 506 u16 ctrl = 0; 507 s32 status = IXGBE_SUCCESS; 508 509 DEBUGFUNC("ixgbe_reset_phy_generic"); 510 511 if (hw->phy.type == ixgbe_phy_unknown) 512 status = ixgbe_identify_phy_generic(hw); 513 514 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 515 goto out; 516 517 /* Don't reset PHY if it's shut down due to overtemp. */ 518 if (!hw->phy.reset_if_overtemp && 519 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 520 goto out; 521 522 /* Blocked by MNG FW so bail */ 523 if (ixgbe_check_reset_blocked(hw)) 524 goto out; 525 526 /* 527 * Perform soft PHY reset to the PHY_XS. 528 * This will cause a soft reset to the PHY 529 */ 530 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 531 IXGBE_MDIO_PHY_XS_DEV_TYPE, 532 IXGBE_MDIO_PHY_XS_RESET); 533 534 /* 535 * Poll for reset bit to self-clear indicating reset is complete. 536 * Some PHYs could take up to 3 seconds to complete and need about 537 * 1.7 usec delay after the reset is complete. 538 */ 539 for (i = 0; i < 30; i++) { 540 msec_delay(100); 541 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 542 status = hw->phy.ops.read_reg(hw, 543 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 544 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 545 &ctrl); 546 if (status != IXGBE_SUCCESS) 547 return status; 548 549 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 550 usec_delay(2); 551 break; 552 } 553 } else { 554 status = hw->phy.ops.read_reg(hw, 555 IXGBE_MDIO_PHY_XS_CONTROL, 556 IXGBE_MDIO_PHY_XS_DEV_TYPE, 557 &ctrl); 558 if (status != IXGBE_SUCCESS) 559 return status; 560 561 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 562 usec_delay(2); 563 break; 564 } 565 } 566 } 567 568 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 569 status = IXGBE_ERR_RESET_FAILED; 570 ERROR_REPORT1(IXGBE_ERROR_POLLING, 571 "PHY reset polling failed to complete.\n"); 572 } 573 574 out: 575 return status; 576 } 577 578 /** 579 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 580 * the SWFW lock 581 * @hw: pointer to hardware structure 582 * @reg_addr: 32 bit address of PHY register to read 583 * @phy_data: Pointer to read data from PHY register 584 **/ 585 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 586 u16 *phy_data) 587 { 588 u32 i, data, command; 589 590 /* Setup and write the address cycle command */ 591 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 592 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 593 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 594 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 595 596 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 597 598 /* 599 * Check every 10 usec to see if the address cycle completed. 600 * The MDI Command bit will clear when the operation is 601 * complete 602 */ 603 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 604 usec_delay(10); 605 606 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 607 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 608 break; 609 } 610 611 612 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 613 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 614 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 615 return IXGBE_ERR_PHY; 616 } 617 618 /* 619 * Address cycle complete, setup and write the read 620 * command 621 */ 622 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 623 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 624 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 625 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 626 627 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 628 629 /* 630 * Check every 10 usec to see if the address cycle 631 * completed. The MDI Command bit will clear when the 632 * operation is complete 633 */ 634 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 635 usec_delay(10); 636 637 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 638 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 639 break; 640 } 641 642 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 643 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 644 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 645 return IXGBE_ERR_PHY; 646 } 647 648 /* 649 * Read operation is complete. Get the data 650 * from MSRWD 651 */ 652 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 653 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 654 *phy_data = (u16)(data); 655 656 return IXGBE_SUCCESS; 657 } 658 659 /** 660 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 661 * using the SWFW lock - this function is needed in most cases 662 * @hw: pointer to hardware structure 663 * @reg_addr: 32 bit address of PHY register to read 664 * @phy_data: Pointer to read data from PHY register 665 **/ 666 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 667 u32 device_type, u16 *phy_data) 668 { 669 s32 status; 670 u32 gssr = hw->phy.phy_semaphore_mask; 671 672 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 673 674 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 675 return IXGBE_ERR_SWFW_SYNC; 676 677 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 678 679 hw->mac.ops.release_swfw_sync(hw, gssr); 680 681 return status; 682 } 683 684 /** 685 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 686 * without SWFW lock 687 * @hw: pointer to hardware structure 688 * @reg_addr: 32 bit PHY register to write 689 * @device_type: 5 bit device type 690 * @phy_data: Data to write to the PHY register 691 **/ 692 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 693 u32 device_type, u16 phy_data) 694 { 695 u32 i, command; 696 697 /* Put the data in the MDI single read and write data register*/ 698 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 699 700 /* Setup and write the address cycle command */ 701 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 702 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 703 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 704 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 705 706 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 707 708 /* 709 * Check every 10 usec to see if the address cycle completed. 710 * The MDI Command bit will clear when the operation is 711 * complete 712 */ 713 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 714 usec_delay(10); 715 716 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 717 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 718 break; 719 } 720 721 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 722 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 723 return IXGBE_ERR_PHY; 724 } 725 726 /* 727 * Address cycle complete, setup and write the write 728 * command 729 */ 730 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 731 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 732 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 733 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 734 735 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 736 737 /* 738 * Check every 10 usec to see if the address cycle 739 * completed. The MDI Command bit will clear when the 740 * operation is complete 741 */ 742 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 743 usec_delay(10); 744 745 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 746 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 747 break; 748 } 749 750 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 751 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 752 return IXGBE_ERR_PHY; 753 } 754 755 return IXGBE_SUCCESS; 756 } 757 758 /** 759 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 760 * using SWFW lock- this function is needed in most cases 761 * @hw: pointer to hardware structure 762 * @reg_addr: 32 bit PHY register to write 763 * @device_type: 5 bit device type 764 * @phy_data: Data to write to the PHY register 765 **/ 766 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 767 u32 device_type, u16 phy_data) 768 { 769 s32 status; 770 u32 gssr = hw->phy.phy_semaphore_mask; 771 772 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 773 774 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 775 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 776 phy_data); 777 hw->mac.ops.release_swfw_sync(hw, gssr); 778 } else { 779 status = IXGBE_ERR_SWFW_SYNC; 780 } 781 782 return status; 783 } 784 785 /** 786 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 787 * @hw: pointer to hardware structure 788 * 789 * Restart auto-negotiation and PHY and waits for completion. 790 **/ 791 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 792 { 793 s32 status = IXGBE_SUCCESS; 794 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 795 bool autoneg = FALSE; 796 ixgbe_link_speed speed; 797 798 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 799 800 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 801 802 /* Set or unset auto-negotiation 10G advertisement */ 803 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 804 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 805 &autoneg_reg); 806 807 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 808 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 809 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 810 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 811 812 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 813 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 814 autoneg_reg); 815 816 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 817 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 818 &autoneg_reg); 819 820 if (hw->mac.type == ixgbe_mac_X550) { 821 /* Set or unset auto-negotiation 5G advertisement */ 822 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 823 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 824 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 825 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 826 827 /* Set or unset auto-negotiation 2.5G advertisement */ 828 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 829 if ((hw->phy.autoneg_advertised & 830 IXGBE_LINK_SPEED_2_5GB_FULL) && 831 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 832 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 833 } 834 835 /* Set or unset auto-negotiation 1G advertisement */ 836 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 837 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 838 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 839 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 840 841 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 842 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 843 autoneg_reg); 844 845 /* Set or unset auto-negotiation 100M advertisement */ 846 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 847 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 848 &autoneg_reg); 849 850 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 851 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 852 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 853 (speed & IXGBE_LINK_SPEED_100_FULL)) 854 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 855 856 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 858 autoneg_reg); 859 860 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) { 861 u16 ctrl; 862 863 /* Force 100Mbps */ 864 hw->phy.ops.read_reg(hw, MDIO_PMAPMD_CTRL1, MDIO_MMD_PMAPMD, 865 &ctrl); 866 ctrl &= ~PMAPMD_CTRL1_SPEED_MASK; 867 ctrl |= PMAPMD_CTRL1_SPEED_100; 868 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD, 869 ctrl); 870 871 /* Don't use auto-nego for 100Mbps */ 872 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 873 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 874 875 autoneg_reg &= ~AN_CTRL1_AUTOEN; 876 877 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 878 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 879 } else { 880 /* Blocked by MNG FW so don't reset PHY */ 881 if (ixgbe_check_reset_blocked(hw)) 882 return status; 883 884 /* Restart PHY auto-negotiation. */ 885 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 886 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 887 888 autoneg_reg |= IXGBE_MII_RESTART | AN_CTRL1_AUTOEN; 889 890 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 892 } 893 894 return status; 895 } 896 897 /** 898 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 899 * @hw: pointer to hardware structure 900 * @speed: new link speed 901 **/ 902 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 903 ixgbe_link_speed speed, 904 bool autoneg_wait_to_complete) 905 { 906 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 907 908 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 909 910 /* 911 * Clear autoneg_advertised and set new values based on input link 912 * speed. 913 */ 914 hw->phy.autoneg_advertised = 0; 915 916 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 917 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 918 919 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 920 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 921 922 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 923 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 924 925 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 926 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 927 928 if (speed & IXGBE_LINK_SPEED_100_FULL) 929 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 930 931 if (speed & IXGBE_LINK_SPEED_10_FULL) 932 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 933 934 /* Setup link based on the new speed settings */ 935 ixgbe_setup_phy_link(hw); 936 937 return IXGBE_SUCCESS; 938 } 939 940 /** 941 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 942 * @hw: pointer to hardware structure 943 * 944 * Determines the supported link capabilities by reading the PHY auto 945 * negotiation register. 946 **/ 947 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 948 { 949 s32 status; 950 u16 speed_ability; 951 952 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 953 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 954 &speed_ability); 955 if (status) 956 return status; 957 958 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 959 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 960 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 961 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 962 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 963 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 964 965 switch (hw->mac.type) { 966 case ixgbe_mac_X550: 967 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 968 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 969 break; 970 case ixgbe_mac_X550EM_x: 971 case ixgbe_mac_X550EM_a: 972 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 973 break; 974 default: 975 break; 976 } 977 978 return status; 979 } 980 981 /** 982 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 983 * @hw: pointer to hardware structure 984 * @speed: pointer to link speed 985 * @autoneg: boolean auto-negotiation value 986 **/ 987 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 988 ixgbe_link_speed *speed, 989 bool *autoneg) 990 { 991 s32 status = IXGBE_SUCCESS; 992 993 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 994 995 *autoneg = TRUE; 996 if (!hw->phy.speeds_supported) 997 status = ixgbe_get_copper_speeds_supported(hw); 998 999 *speed = hw->phy.speeds_supported; 1000 return status; 1001 } 1002 1003 /** 1004 * ixgbe_check_phy_link_tnx - Determine link and speed status 1005 * @hw: pointer to hardware structure 1006 * 1007 * Reads the VS1 register to determine if link is up and the current speed for 1008 * the PHY. 1009 **/ 1010 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1011 bool *link_up) 1012 { 1013 s32 status = IXGBE_SUCCESS; 1014 u32 time_out; 1015 u32 max_time_out = 10; 1016 u16 phy_link = 0; 1017 u16 phy_speed = 0; 1018 u16 phy_data = 0; 1019 1020 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1021 1022 /* Initialize speed and link to default case */ 1023 *link_up = FALSE; 1024 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1025 1026 /* 1027 * Check current speed and link status of the PHY register. 1028 * This is a vendor specific register and may have to 1029 * be changed for other copper PHYs. 1030 */ 1031 for (time_out = 0; time_out < max_time_out; time_out++) { 1032 usec_delay(10); 1033 status = hw->phy.ops.read_reg(hw, 1034 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1035 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1036 &phy_data); 1037 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1038 phy_speed = phy_data & 1039 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1040 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1041 *link_up = TRUE; 1042 if (phy_speed == 1043 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1044 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1045 break; 1046 } 1047 } 1048 1049 return status; 1050 } 1051 1052 /** 1053 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1054 * @hw: pointer to hardware structure 1055 * 1056 * Restart auto-negotiation and PHY and waits for completion. 1057 **/ 1058 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1059 { 1060 s32 status = IXGBE_SUCCESS; 1061 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1062 bool autoneg = FALSE; 1063 ixgbe_link_speed speed; 1064 1065 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1066 1067 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1068 1069 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1070 /* Set or unset auto-negotiation 10G advertisement */ 1071 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1072 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1073 &autoneg_reg); 1074 1075 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1076 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1077 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1078 1079 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1080 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1081 autoneg_reg); 1082 } 1083 1084 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1085 /* Set or unset auto-negotiation 1G advertisement */ 1086 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1088 &autoneg_reg); 1089 1090 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1091 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1092 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1093 1094 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1095 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1096 autoneg_reg); 1097 } 1098 1099 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1100 /* Set or unset auto-negotiation 100M advertisement */ 1101 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1102 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1103 &autoneg_reg); 1104 1105 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1106 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1107 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1108 1109 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1110 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1111 autoneg_reg); 1112 } 1113 1114 /* Blocked by MNG FW so don't reset PHY */ 1115 if (ixgbe_check_reset_blocked(hw)) 1116 return status; 1117 1118 /* Restart PHY auto-negotiation. */ 1119 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1120 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1121 1122 autoneg_reg |= IXGBE_MII_RESTART; 1123 1124 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1125 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1126 1127 return status; 1128 } 1129 1130 /** 1131 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1132 * @hw: pointer to hardware structure 1133 * @firmware_version: pointer to the PHY Firmware Version 1134 **/ 1135 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1136 u16 *firmware_version) 1137 { 1138 s32 status; 1139 1140 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1141 1142 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1143 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1144 firmware_version); 1145 1146 return status; 1147 } 1148 1149 /** 1150 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1151 * @hw: pointer to hardware structure 1152 * @firmware_version: pointer to the PHY Firmware Version 1153 **/ 1154 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1155 u16 *firmware_version) 1156 { 1157 s32 status; 1158 1159 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1160 1161 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1162 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1163 firmware_version); 1164 1165 return status; 1166 } 1167 1168 /** 1169 * ixgbe_reset_phy_nl - Performs a PHY reset 1170 * @hw: pointer to hardware structure 1171 **/ 1172 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1173 { 1174 u16 phy_offset, control, eword, edata, block_crc; 1175 bool end_data = FALSE; 1176 u16 list_offset, data_offset; 1177 u16 phy_data = 0; 1178 s32 ret_val = IXGBE_SUCCESS; 1179 u32 i; 1180 1181 DEBUGFUNC("ixgbe_reset_phy_nl"); 1182 1183 /* Blocked by MNG FW so bail */ 1184 if (ixgbe_check_reset_blocked(hw)) 1185 goto out; 1186 1187 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1188 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1189 1190 /* reset the PHY and poll for completion */ 1191 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1192 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1193 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1194 1195 for (i = 0; i < 100; i++) { 1196 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1197 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1198 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1199 break; 1200 msec_delay(10); 1201 } 1202 1203 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1204 DEBUGOUT("PHY reset did not complete.\n"); 1205 ret_val = IXGBE_ERR_PHY; 1206 goto out; 1207 } 1208 1209 /* Get init offsets */ 1210 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1211 &data_offset); 1212 if (ret_val != IXGBE_SUCCESS) 1213 goto out; 1214 1215 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1216 data_offset++; 1217 while (!end_data) { 1218 /* 1219 * Read control word from PHY init contents offset 1220 */ 1221 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1222 if (ret_val) 1223 goto err_eeprom; 1224 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1225 IXGBE_CONTROL_SHIFT_NL; 1226 edata = eword & IXGBE_DATA_MASK_NL; 1227 switch (control) { 1228 case IXGBE_DELAY_NL: 1229 data_offset++; 1230 DEBUGOUT1("DELAY: %d MS\n", edata); 1231 msec_delay(edata); 1232 break; 1233 case IXGBE_DATA_NL: 1234 DEBUGOUT("DATA:\n"); 1235 data_offset++; 1236 ret_val = hw->eeprom.ops.read(hw, data_offset, 1237 &phy_offset); 1238 if (ret_val) 1239 goto err_eeprom; 1240 data_offset++; 1241 for (i = 0; i < edata; i++) { 1242 ret_val = hw->eeprom.ops.read(hw, data_offset, 1243 &eword); 1244 if (ret_val) 1245 goto err_eeprom; 1246 hw->phy.ops.write_reg(hw, phy_offset, 1247 IXGBE_TWINAX_DEV, eword); 1248 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1249 phy_offset); 1250 data_offset++; 1251 phy_offset++; 1252 } 1253 break; 1254 case IXGBE_CONTROL_NL: 1255 data_offset++; 1256 DEBUGOUT("CONTROL:\n"); 1257 if (edata == IXGBE_CONTROL_EOL_NL) { 1258 DEBUGOUT("EOL\n"); 1259 end_data = TRUE; 1260 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1261 DEBUGOUT("SOL\n"); 1262 } else { 1263 DEBUGOUT("Bad control value\n"); 1264 ret_val = IXGBE_ERR_PHY; 1265 goto out; 1266 } 1267 break; 1268 default: 1269 DEBUGOUT("Bad control type\n"); 1270 ret_val = IXGBE_ERR_PHY; 1271 goto out; 1272 } 1273 } 1274 1275 out: 1276 return ret_val; 1277 1278 err_eeprom: 1279 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1280 "eeprom read at offset %d failed", data_offset); 1281 return IXGBE_ERR_PHY; 1282 } 1283 1284 /** 1285 * ixgbe_identify_module_generic - Identifies module type 1286 * @hw: pointer to hardware structure 1287 * 1288 * Determines HW type and calls appropriate function. 1289 **/ 1290 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1291 { 1292 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1293 1294 DEBUGFUNC("ixgbe_identify_module_generic"); 1295 1296 switch (hw->mac.ops.get_media_type(hw)) { 1297 case ixgbe_media_type_fiber: 1298 status = ixgbe_identify_sfp_module_generic(hw); 1299 break; 1300 1301 case ixgbe_media_type_fiber_qsfp: 1302 status = ixgbe_identify_qsfp_module_generic(hw); 1303 break; 1304 1305 default: 1306 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1307 status = IXGBE_ERR_SFP_NOT_PRESENT; 1308 break; 1309 } 1310 1311 return status; 1312 } 1313 1314 /** 1315 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1316 * @hw: pointer to hardware structure 1317 * 1318 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1319 **/ 1320 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1321 { 1322 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1323 u32 vendor_oui = 0; 1324 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1325 u8 identifier = 0; 1326 u8 comp_codes_1g = 0; 1327 u8 comp_codes_10g = 0; 1328 u8 oui_bytes[3] = {0, 0, 0}; 1329 u8 cable_tech = 0; 1330 u8 cable_spec = 0; 1331 u16 enforce_sfp = 0; 1332 1333 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1334 1335 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1336 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1337 status = IXGBE_ERR_SFP_NOT_PRESENT; 1338 goto out; 1339 } 1340 1341 /* LAN ID is needed for I2C access */ 1342 hw->mac.ops.set_lan_id(hw); 1343 1344 status = hw->phy.ops.read_i2c_eeprom(hw, 1345 IXGBE_SFF_IDENTIFIER, 1346 &identifier); 1347 1348 if (status != IXGBE_SUCCESS) 1349 goto err_read_i2c_eeprom; 1350 1351 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1352 hw->phy.type = ixgbe_phy_sfp_unsupported; 1353 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1354 } else { 1355 status = hw->phy.ops.read_i2c_eeprom(hw, 1356 IXGBE_SFF_1GBE_COMP_CODES, 1357 &comp_codes_1g); 1358 1359 if (status != IXGBE_SUCCESS) 1360 goto err_read_i2c_eeprom; 1361 1362 status = hw->phy.ops.read_i2c_eeprom(hw, 1363 IXGBE_SFF_10GBE_COMP_CODES, 1364 &comp_codes_10g); 1365 1366 if (status != IXGBE_SUCCESS) 1367 goto err_read_i2c_eeprom; 1368 status = hw->phy.ops.read_i2c_eeprom(hw, 1369 IXGBE_SFF_CABLE_TECHNOLOGY, 1370 &cable_tech); 1371 1372 if (status != IXGBE_SUCCESS) 1373 goto err_read_i2c_eeprom; 1374 1375 /* ID Module 1376 * ========= 1377 * 0 SFP_DA_CU 1378 * 1 SFP_SR 1379 * 2 SFP_LR 1380 * 3 SFP_DA_CORE0 - 82599-specific 1381 * 4 SFP_DA_CORE1 - 82599-specific 1382 * 5 SFP_SR/LR_CORE0 - 82599-specific 1383 * 6 SFP_SR/LR_CORE1 - 82599-specific 1384 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1385 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1386 * 9 SFP_1g_cu_CORE0 - 82599-specific 1387 * 10 SFP_1g_cu_CORE1 - 82599-specific 1388 * 11 SFP_1g_sx_CORE0 - 82599-specific 1389 * 12 SFP_1g_sx_CORE1 - 82599-specific 1390 */ 1391 if (hw->mac.type == ixgbe_mac_82598EB) { 1392 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1393 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1394 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1395 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1396 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1397 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1398 else 1399 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1400 } else { 1401 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1402 if (hw->bus.lan_id == 0) 1403 hw->phy.sfp_type = 1404 ixgbe_sfp_type_da_cu_core0; 1405 else 1406 hw->phy.sfp_type = 1407 ixgbe_sfp_type_da_cu_core1; 1408 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1409 hw->phy.ops.read_i2c_eeprom( 1410 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1411 &cable_spec); 1412 if (cable_spec & 1413 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1414 if (hw->bus.lan_id == 0) 1415 hw->phy.sfp_type = 1416 ixgbe_sfp_type_da_act_lmt_core0; 1417 else 1418 hw->phy.sfp_type = 1419 ixgbe_sfp_type_da_act_lmt_core1; 1420 } else { 1421 hw->phy.sfp_type = 1422 ixgbe_sfp_type_unknown; 1423 } 1424 } else if (comp_codes_10g & 1425 (IXGBE_SFF_10GBASESR_CAPABLE | 1426 IXGBE_SFF_10GBASELR_CAPABLE)) { 1427 if (hw->bus.lan_id == 0) 1428 hw->phy.sfp_type = 1429 ixgbe_sfp_type_srlr_core0; 1430 else 1431 hw->phy.sfp_type = 1432 ixgbe_sfp_type_srlr_core1; 1433 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1434 if (hw->bus.lan_id == 0) 1435 hw->phy.sfp_type = 1436 ixgbe_sfp_type_1g_cu_core0; 1437 else 1438 hw->phy.sfp_type = 1439 ixgbe_sfp_type_1g_cu_core1; 1440 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1441 if (hw->bus.lan_id == 0) 1442 hw->phy.sfp_type = 1443 ixgbe_sfp_type_1g_sx_core0; 1444 else 1445 hw->phy.sfp_type = 1446 ixgbe_sfp_type_1g_sx_core1; 1447 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1448 if (hw->bus.lan_id == 0) 1449 hw->phy.sfp_type = 1450 ixgbe_sfp_type_1g_lx_core0; 1451 else 1452 hw->phy.sfp_type = 1453 ixgbe_sfp_type_1g_lx_core1; 1454 } else { 1455 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1456 } 1457 } 1458 1459 if (hw->phy.sfp_type != stored_sfp_type) 1460 hw->phy.sfp_setup_needed = TRUE; 1461 1462 /* Determine if the SFP+ PHY is dual speed or not. */ 1463 hw->phy.multispeed_fiber = FALSE; 1464 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1465 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1466 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1467 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1468 hw->phy.multispeed_fiber = TRUE; 1469 1470 /* Determine PHY vendor */ 1471 if (hw->phy.type != ixgbe_phy_nl) { 1472 hw->phy.id = identifier; 1473 status = hw->phy.ops.read_i2c_eeprom(hw, 1474 IXGBE_SFF_VENDOR_OUI_BYTE0, 1475 &oui_bytes[0]); 1476 1477 if (status != IXGBE_SUCCESS) 1478 goto err_read_i2c_eeprom; 1479 1480 status = hw->phy.ops.read_i2c_eeprom(hw, 1481 IXGBE_SFF_VENDOR_OUI_BYTE1, 1482 &oui_bytes[1]); 1483 1484 if (status != IXGBE_SUCCESS) 1485 goto err_read_i2c_eeprom; 1486 1487 status = hw->phy.ops.read_i2c_eeprom(hw, 1488 IXGBE_SFF_VENDOR_OUI_BYTE2, 1489 &oui_bytes[2]); 1490 1491 if (status != IXGBE_SUCCESS) 1492 goto err_read_i2c_eeprom; 1493 1494 vendor_oui = 1495 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1496 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1497 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1498 1499 switch (vendor_oui) { 1500 case IXGBE_SFF_VENDOR_OUI_TYCO: 1501 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1502 hw->phy.type = 1503 ixgbe_phy_sfp_passive_tyco; 1504 break; 1505 case IXGBE_SFF_VENDOR_OUI_FTL: 1506 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1507 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1508 else 1509 hw->phy.type = ixgbe_phy_sfp_ftl; 1510 break; 1511 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1512 hw->phy.type = ixgbe_phy_sfp_avago; 1513 break; 1514 case IXGBE_SFF_VENDOR_OUI_INTEL: 1515 hw->phy.type = ixgbe_phy_sfp_intel; 1516 break; 1517 default: 1518 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1519 hw->phy.type = 1520 ixgbe_phy_sfp_passive_unknown; 1521 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1522 hw->phy.type = 1523 ixgbe_phy_sfp_active_unknown; 1524 else 1525 hw->phy.type = ixgbe_phy_sfp_unknown; 1526 break; 1527 } 1528 } 1529 1530 /* Allow any DA cable vendor */ 1531 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1532 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1533 status = IXGBE_SUCCESS; 1534 goto out; 1535 } 1536 1537 /* Verify supported 1G SFP modules */ 1538 if (comp_codes_10g == 0 && 1539 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1540 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1541 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1543 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1544 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1545 hw->phy.type = ixgbe_phy_sfp_unsupported; 1546 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1547 goto out; 1548 } 1549 1550 /* Anything else 82598-based is supported */ 1551 if (hw->mac.type == ixgbe_mac_82598EB) { 1552 status = IXGBE_SUCCESS; 1553 goto out; 1554 } 1555 1556 ixgbe_get_device_caps(hw, &enforce_sfp); 1557 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1558 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1559 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1561 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1562 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1563 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1564 /* Make sure we're a supported PHY type */ 1565 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1566 status = IXGBE_SUCCESS; 1567 } else { 1568 if (hw->allow_unsupported_sfp == TRUE) { 1569 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1570 status = IXGBE_SUCCESS; 1571 } else { 1572 DEBUGOUT("SFP+ module not supported\n"); 1573 hw->phy.type = 1574 ixgbe_phy_sfp_unsupported; 1575 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1576 } 1577 } 1578 } else { 1579 status = IXGBE_SUCCESS; 1580 } 1581 } 1582 1583 out: 1584 return status; 1585 1586 err_read_i2c_eeprom: 1587 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1588 if (hw->phy.type != ixgbe_phy_nl) { 1589 hw->phy.id = 0; 1590 hw->phy.type = ixgbe_phy_unknown; 1591 } 1592 return IXGBE_ERR_SFP_NOT_PRESENT; 1593 } 1594 1595 /** 1596 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1597 * @hw: pointer to hardware structure 1598 * 1599 * Determines physical layer capabilities of the current SFP. 1600 */ 1601 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1602 { 1603 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1604 u8 comp_codes_10g = 0; 1605 u8 comp_codes_1g = 0; 1606 1607 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1608 1609 hw->phy.ops.identify_sfp(hw); 1610 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1611 return physical_layer; 1612 1613 switch (hw->phy.type) { 1614 case ixgbe_phy_sfp_passive_tyco: 1615 case ixgbe_phy_sfp_passive_unknown: 1616 case ixgbe_phy_qsfp_passive_unknown: 1617 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1618 break; 1619 case ixgbe_phy_sfp_ftl_active: 1620 case ixgbe_phy_sfp_active_unknown: 1621 case ixgbe_phy_qsfp_active_unknown: 1622 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1623 break; 1624 case ixgbe_phy_sfp_avago: 1625 case ixgbe_phy_sfp_ftl: 1626 case ixgbe_phy_sfp_intel: 1627 case ixgbe_phy_sfp_unknown: 1628 hw->phy.ops.read_i2c_eeprom(hw, 1629 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1630 hw->phy.ops.read_i2c_eeprom(hw, 1631 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1632 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1633 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1634 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1635 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1636 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1637 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1638 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1639 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1640 break; 1641 case ixgbe_phy_qsfp_intel: 1642 case ixgbe_phy_qsfp_unknown: 1643 hw->phy.ops.read_i2c_eeprom(hw, 1644 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1645 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1646 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1647 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1648 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1649 break; 1650 default: 1651 break; 1652 } 1653 1654 return physical_layer; 1655 } 1656 1657 /** 1658 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1659 * @hw: pointer to hardware structure 1660 * 1661 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1662 **/ 1663 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1664 { 1665 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1666 u32 vendor_oui = 0; 1667 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1668 u8 identifier = 0; 1669 u8 comp_codes_1g = 0; 1670 u8 comp_codes_10g = 0; 1671 u8 oui_bytes[3] = {0, 0, 0}; 1672 u16 enforce_sfp = 0; 1673 u8 connector = 0; 1674 u8 cable_length = 0; 1675 u8 device_tech = 0; 1676 bool active_cable = FALSE; 1677 1678 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1679 1680 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1681 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1682 status = IXGBE_ERR_SFP_NOT_PRESENT; 1683 goto out; 1684 } 1685 1686 /* LAN ID is needed for I2C access */ 1687 hw->mac.ops.set_lan_id(hw); 1688 1689 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1690 &identifier); 1691 1692 if (status != IXGBE_SUCCESS) 1693 goto err_read_i2c_eeprom; 1694 1695 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1696 hw->phy.type = ixgbe_phy_sfp_unsupported; 1697 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1698 goto out; 1699 } 1700 1701 hw->phy.id = identifier; 1702 1703 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1704 &comp_codes_10g); 1705 1706 if (status != IXGBE_SUCCESS) 1707 goto err_read_i2c_eeprom; 1708 1709 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1710 &comp_codes_1g); 1711 1712 if (status != IXGBE_SUCCESS) 1713 goto err_read_i2c_eeprom; 1714 1715 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1716 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1717 if (hw->bus.lan_id == 0) 1718 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1719 else 1720 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1721 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1722 IXGBE_SFF_10GBASELR_CAPABLE)) { 1723 if (hw->bus.lan_id == 0) 1724 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1725 else 1726 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1727 } else { 1728 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1729 active_cable = TRUE; 1730 1731 if (!active_cable) { 1732 /* check for active DA cables that pre-date 1733 * SFF-8436 v3.6 */ 1734 hw->phy.ops.read_i2c_eeprom(hw, 1735 IXGBE_SFF_QSFP_CONNECTOR, 1736 &connector); 1737 1738 hw->phy.ops.read_i2c_eeprom(hw, 1739 IXGBE_SFF_QSFP_CABLE_LENGTH, 1740 &cable_length); 1741 1742 hw->phy.ops.read_i2c_eeprom(hw, 1743 IXGBE_SFF_QSFP_DEVICE_TECH, 1744 &device_tech); 1745 1746 if ((connector == 1747 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1748 (cable_length > 0) && 1749 ((device_tech >> 4) == 1750 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1751 active_cable = TRUE; 1752 } 1753 1754 if (active_cable) { 1755 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1756 if (hw->bus.lan_id == 0) 1757 hw->phy.sfp_type = 1758 ixgbe_sfp_type_da_act_lmt_core0; 1759 else 1760 hw->phy.sfp_type = 1761 ixgbe_sfp_type_da_act_lmt_core1; 1762 } else { 1763 /* unsupported module type */ 1764 hw->phy.type = ixgbe_phy_sfp_unsupported; 1765 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1766 goto out; 1767 } 1768 } 1769 1770 if (hw->phy.sfp_type != stored_sfp_type) 1771 hw->phy.sfp_setup_needed = TRUE; 1772 1773 /* Determine if the QSFP+ PHY is dual speed or not. */ 1774 hw->phy.multispeed_fiber = FALSE; 1775 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1776 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1777 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1778 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1779 hw->phy.multispeed_fiber = TRUE; 1780 1781 /* Determine PHY vendor for optical modules */ 1782 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1783 IXGBE_SFF_10GBASELR_CAPABLE)) { 1784 status = hw->phy.ops.read_i2c_eeprom(hw, 1785 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1786 &oui_bytes[0]); 1787 1788 if (status != IXGBE_SUCCESS) 1789 goto err_read_i2c_eeprom; 1790 1791 status = hw->phy.ops.read_i2c_eeprom(hw, 1792 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1793 &oui_bytes[1]); 1794 1795 if (status != IXGBE_SUCCESS) 1796 goto err_read_i2c_eeprom; 1797 1798 status = hw->phy.ops.read_i2c_eeprom(hw, 1799 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1800 &oui_bytes[2]); 1801 1802 if (status != IXGBE_SUCCESS) 1803 goto err_read_i2c_eeprom; 1804 1805 vendor_oui = 1806 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1807 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1808 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1809 1810 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1811 hw->phy.type = ixgbe_phy_qsfp_intel; 1812 else 1813 hw->phy.type = ixgbe_phy_qsfp_unknown; 1814 1815 ixgbe_get_device_caps(hw, &enforce_sfp); 1816 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1817 /* Make sure we're a supported PHY type */ 1818 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1819 status = IXGBE_SUCCESS; 1820 } else { 1821 if (hw->allow_unsupported_sfp == TRUE) { 1822 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1823 status = IXGBE_SUCCESS; 1824 } else { 1825 DEBUGOUT("QSFP module not supported\n"); 1826 hw->phy.type = 1827 ixgbe_phy_sfp_unsupported; 1828 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1829 } 1830 } 1831 } else { 1832 status = IXGBE_SUCCESS; 1833 } 1834 } 1835 1836 out: 1837 return status; 1838 1839 err_read_i2c_eeprom: 1840 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1841 hw->phy.id = 0; 1842 hw->phy.type = ixgbe_phy_unknown; 1843 1844 return IXGBE_ERR_SFP_NOT_PRESENT; 1845 } 1846 1847 /** 1848 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1849 * @hw: pointer to hardware structure 1850 * @list_offset: offset to the SFP ID list 1851 * @data_offset: offset to the SFP data block 1852 * 1853 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1854 * so it returns the offsets to the phy init sequence block. 1855 **/ 1856 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1857 u16 *list_offset, 1858 u16 *data_offset) 1859 { 1860 u16 sfp_id; 1861 u16 sfp_type = hw->phy.sfp_type; 1862 1863 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1864 1865 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1866 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1867 1868 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1869 return IXGBE_ERR_SFP_NOT_PRESENT; 1870 1871 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1872 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1873 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1874 1875 /* 1876 * Limiting active cables and 1G Phys must be initialized as 1877 * SR modules 1878 */ 1879 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1880 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1881 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1882 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1883 sfp_type = ixgbe_sfp_type_srlr_core0; 1884 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1885 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1886 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1887 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1888 sfp_type = ixgbe_sfp_type_srlr_core1; 1889 1890 /* Read offset to PHY init contents */ 1891 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1892 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1893 "eeprom read at offset %d failed", 1894 IXGBE_PHY_INIT_OFFSET_NL); 1895 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1896 } 1897 1898 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1899 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1900 1901 /* Shift offset to first ID word */ 1902 (*list_offset)++; 1903 1904 /* 1905 * Find the matching SFP ID in the EEPROM 1906 * and program the init sequence 1907 */ 1908 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1909 goto err_phy; 1910 1911 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1912 if (sfp_id == sfp_type) { 1913 (*list_offset)++; 1914 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1915 goto err_phy; 1916 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1917 DEBUGOUT("SFP+ module not supported\n"); 1918 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1919 } else { 1920 break; 1921 } 1922 } else { 1923 (*list_offset) += 2; 1924 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1925 goto err_phy; 1926 } 1927 } 1928 1929 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1930 DEBUGOUT("No matching SFP+ module found\n"); 1931 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1932 } 1933 1934 return IXGBE_SUCCESS; 1935 1936 err_phy: 1937 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1938 "eeprom read at offset %d failed", *list_offset); 1939 return IXGBE_ERR_PHY; 1940 } 1941 1942 /** 1943 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1944 * @hw: pointer to hardware structure 1945 * @byte_offset: EEPROM byte offset to read 1946 * @eeprom_data: value read 1947 * 1948 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1949 **/ 1950 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1951 u8 *eeprom_data) 1952 { 1953 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1954 1955 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1956 IXGBE_I2C_EEPROM_DEV_ADDR, 1957 eeprom_data); 1958 } 1959 1960 /** 1961 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1962 * @hw: pointer to hardware structure 1963 * @byte_offset: byte offset at address 0xA2 1964 * @eeprom_data: value read 1965 * 1966 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1967 **/ 1968 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1969 u8 *sff8472_data) 1970 { 1971 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1972 IXGBE_I2C_EEPROM_DEV_ADDR2, 1973 sff8472_data); 1974 } 1975 1976 /** 1977 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1978 * @hw: pointer to hardware structure 1979 * @byte_offset: EEPROM byte offset to write 1980 * @eeprom_data: value to write 1981 * 1982 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1983 **/ 1984 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1985 u8 eeprom_data) 1986 { 1987 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1988 1989 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1990 IXGBE_I2C_EEPROM_DEV_ADDR, 1991 eeprom_data); 1992 } 1993 1994 /** 1995 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1996 * @hw: pointer to hardware structure 1997 * @offset: eeprom offset to be read 1998 * @addr: I2C address to be read 1999 */ 2000 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2001 { 2002 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2003 offset == IXGBE_SFF_IDENTIFIER && 2004 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2005 return TRUE; 2006 return FALSE; 2007 } 2008 2009 /** 2010 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2011 * @hw: pointer to hardware structure 2012 * @byte_offset: byte offset to read 2013 * @data: value read 2014 * @lock: TRUE if to take and release semaphore 2015 * 2016 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2017 * a specified device address. 2018 **/ 2019 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2020 u8 dev_addr, u8 *data, bool lock) 2021 { 2022 s32 status; 2023 u32 max_retry = 10; 2024 u32 retry = 0; 2025 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2026 bool nack = 1; 2027 *data = 0; 2028 2029 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2030 2031 if (hw->mac.type >= ixgbe_mac_X550) 2032 max_retry = 3; 2033 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2034 max_retry = IXGBE_SFP_DETECT_RETRIES; 2035 2036 do { 2037 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2038 return IXGBE_ERR_SWFW_SYNC; 2039 2040 ixgbe_i2c_start(hw); 2041 2042 /* Device Address and write indication */ 2043 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2044 if (status != IXGBE_SUCCESS) 2045 goto fail; 2046 2047 status = ixgbe_get_i2c_ack(hw); 2048 if (status != IXGBE_SUCCESS) 2049 goto fail; 2050 2051 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2052 if (status != IXGBE_SUCCESS) 2053 goto fail; 2054 2055 status = ixgbe_get_i2c_ack(hw); 2056 if (status != IXGBE_SUCCESS) 2057 goto fail; 2058 2059 ixgbe_i2c_start(hw); 2060 2061 /* Device Address and read indication */ 2062 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2063 if (status != IXGBE_SUCCESS) 2064 goto fail; 2065 2066 status = ixgbe_get_i2c_ack(hw); 2067 if (status != IXGBE_SUCCESS) 2068 goto fail; 2069 2070 status = ixgbe_clock_in_i2c_byte(hw, data); 2071 if (status != IXGBE_SUCCESS) 2072 goto fail; 2073 2074 status = ixgbe_clock_out_i2c_bit(hw, nack); 2075 if (status != IXGBE_SUCCESS) 2076 goto fail; 2077 2078 ixgbe_i2c_stop(hw); 2079 if (lock) 2080 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2081 return IXGBE_SUCCESS; 2082 2083 fail: 2084 ixgbe_i2c_bus_clear(hw); 2085 if (lock) { 2086 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2087 msec_delay(100); 2088 } 2089 retry++; 2090 if (retry < max_retry) 2091 DEBUGOUT("I2C byte read error - Retrying.\n"); 2092 else 2093 DEBUGOUT("I2C byte read error.\n"); 2094 2095 } while (retry < max_retry); 2096 2097 return status; 2098 } 2099 2100 /** 2101 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2102 * @hw: pointer to hardware structure 2103 * @byte_offset: byte offset to read 2104 * @data: value read 2105 * 2106 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2107 * a specified device address. 2108 **/ 2109 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2110 u8 dev_addr, u8 *data) 2111 { 2112 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2113 data, TRUE); 2114 } 2115 2116 /** 2117 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2118 * @hw: pointer to hardware structure 2119 * @byte_offset: byte offset to read 2120 * @data: value read 2121 * 2122 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2123 * a specified device address. 2124 **/ 2125 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2126 u8 dev_addr, u8 *data) 2127 { 2128 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2129 data, FALSE); 2130 } 2131 2132 /** 2133 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2134 * @hw: pointer to hardware structure 2135 * @byte_offset: byte offset to write 2136 * @data: value to write 2137 * @lock: TRUE if to take and release semaphore 2138 * 2139 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2140 * a specified device address. 2141 **/ 2142 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2143 u8 dev_addr, u8 data, bool lock) 2144 { 2145 s32 status; 2146 u32 max_retry = 2; 2147 u32 retry = 0; 2148 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2149 2150 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2151 2152 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2153 IXGBE_SUCCESS) 2154 return IXGBE_ERR_SWFW_SYNC; 2155 2156 do { 2157 ixgbe_i2c_start(hw); 2158 2159 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2160 if (status != IXGBE_SUCCESS) 2161 goto fail; 2162 2163 status = ixgbe_get_i2c_ack(hw); 2164 if (status != IXGBE_SUCCESS) 2165 goto fail; 2166 2167 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2168 if (status != IXGBE_SUCCESS) 2169 goto fail; 2170 2171 status = ixgbe_get_i2c_ack(hw); 2172 if (status != IXGBE_SUCCESS) 2173 goto fail; 2174 2175 status = ixgbe_clock_out_i2c_byte(hw, data); 2176 if (status != IXGBE_SUCCESS) 2177 goto fail; 2178 2179 status = ixgbe_get_i2c_ack(hw); 2180 if (status != IXGBE_SUCCESS) 2181 goto fail; 2182 2183 ixgbe_i2c_stop(hw); 2184 if (lock) 2185 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2186 return IXGBE_SUCCESS; 2187 2188 fail: 2189 ixgbe_i2c_bus_clear(hw); 2190 retry++; 2191 if (retry < max_retry) 2192 DEBUGOUT("I2C byte write error - Retrying.\n"); 2193 else 2194 DEBUGOUT("I2C byte write error.\n"); 2195 } while (retry < max_retry); 2196 2197 if (lock) 2198 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2199 2200 return status; 2201 } 2202 2203 /** 2204 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2205 * @hw: pointer to hardware structure 2206 * @byte_offset: byte offset to write 2207 * @data: value to write 2208 * 2209 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2210 * a specified device address. 2211 **/ 2212 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2213 u8 dev_addr, u8 data) 2214 { 2215 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2216 data, TRUE); 2217 } 2218 2219 /** 2220 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2221 * @hw: pointer to hardware structure 2222 * @byte_offset: byte offset to write 2223 * @data: value to write 2224 * 2225 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2226 * a specified device address. 2227 **/ 2228 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2229 u8 dev_addr, u8 data) 2230 { 2231 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2232 data, FALSE); 2233 } 2234 2235 /** 2236 * ixgbe_i2c_start - Sets I2C start condition 2237 * @hw: pointer to hardware structure 2238 * 2239 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2240 * Set bit-bang mode on X550 hardware. 2241 **/ 2242 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2243 { 2244 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2245 2246 DEBUGFUNC("ixgbe_i2c_start"); 2247 2248 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2249 2250 /* Start condition must begin with data and clock high */ 2251 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2252 ixgbe_raise_i2c_clk(hw, &i2cctl); 2253 2254 /* Setup time for start condition (4.7us) */ 2255 usec_delay(IXGBE_I2C_T_SU_STA); 2256 2257 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2258 2259 /* Hold time for start condition (4us) */ 2260 usec_delay(IXGBE_I2C_T_HD_STA); 2261 2262 ixgbe_lower_i2c_clk(hw, &i2cctl); 2263 2264 /* Minimum low period of clock is 4.7 us */ 2265 usec_delay(IXGBE_I2C_T_LOW); 2266 2267 } 2268 2269 /** 2270 * ixgbe_i2c_stop - Sets I2C stop condition 2271 * @hw: pointer to hardware structure 2272 * 2273 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2274 * Disables bit-bang mode and negates data output enable on X550 2275 * hardware. 2276 **/ 2277 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2278 { 2279 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2280 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2281 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2282 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2283 2284 DEBUGFUNC("ixgbe_i2c_stop"); 2285 2286 /* Stop condition must begin with data low and clock high */ 2287 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2288 ixgbe_raise_i2c_clk(hw, &i2cctl); 2289 2290 /* Setup time for stop condition (4us) */ 2291 usec_delay(IXGBE_I2C_T_SU_STO); 2292 2293 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2294 2295 /* bus free time between stop and start (4.7us)*/ 2296 usec_delay(IXGBE_I2C_T_BUF); 2297 2298 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2299 i2cctl &= ~bb_en_bit; 2300 i2cctl |= data_oe_bit | clk_oe_bit; 2301 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2302 IXGBE_WRITE_FLUSH(hw); 2303 } 2304 } 2305 2306 /** 2307 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2308 * @hw: pointer to hardware structure 2309 * @data: data byte to clock in 2310 * 2311 * Clocks in one byte data via I2C data/clock 2312 **/ 2313 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2314 { 2315 s32 i; 2316 bool bit = 0; 2317 2318 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2319 2320 *data = 0; 2321 for (i = 7; i >= 0; i--) { 2322 ixgbe_clock_in_i2c_bit(hw, &bit); 2323 *data |= bit << i; 2324 } 2325 2326 return IXGBE_SUCCESS; 2327 } 2328 2329 /** 2330 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2331 * @hw: pointer to hardware structure 2332 * @data: data byte clocked out 2333 * 2334 * Clocks out one byte data via I2C data/clock 2335 **/ 2336 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2337 { 2338 s32 status = IXGBE_SUCCESS; 2339 s32 i; 2340 u32 i2cctl; 2341 bool bit; 2342 2343 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2344 2345 for (i = 7; i >= 0; i--) { 2346 bit = (data >> i) & 0x1; 2347 status = ixgbe_clock_out_i2c_bit(hw, bit); 2348 2349 if (status != IXGBE_SUCCESS) 2350 break; 2351 } 2352 2353 /* Release SDA line (set high) */ 2354 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2355 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2356 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2357 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2358 IXGBE_WRITE_FLUSH(hw); 2359 2360 return status; 2361 } 2362 2363 /** 2364 * ixgbe_get_i2c_ack - Polls for I2C ACK 2365 * @hw: pointer to hardware structure 2366 * 2367 * Clocks in/out one bit via I2C data/clock 2368 **/ 2369 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2370 { 2371 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2372 s32 status = IXGBE_SUCCESS; 2373 u32 i = 0; 2374 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2375 u32 timeout = 10; 2376 bool ack = 1; 2377 2378 DEBUGFUNC("ixgbe_get_i2c_ack"); 2379 2380 if (data_oe_bit) { 2381 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2382 i2cctl |= data_oe_bit; 2383 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2384 IXGBE_WRITE_FLUSH(hw); 2385 } 2386 ixgbe_raise_i2c_clk(hw, &i2cctl); 2387 2388 /* Minimum high period of clock is 4us */ 2389 usec_delay(IXGBE_I2C_T_HIGH); 2390 2391 /* Poll for ACK. Note that ACK in I2C spec is 2392 * transition from 1 to 0 */ 2393 for (i = 0; i < timeout; i++) { 2394 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2395 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2396 2397 usec_delay(1); 2398 if (!ack) 2399 break; 2400 } 2401 2402 if (ack) { 2403 DEBUGOUT("I2C ack was not received.\n"); 2404 status = IXGBE_ERR_I2C; 2405 } 2406 2407 ixgbe_lower_i2c_clk(hw, &i2cctl); 2408 2409 /* Minimum low period of clock is 4.7 us */ 2410 usec_delay(IXGBE_I2C_T_LOW); 2411 2412 return status; 2413 } 2414 2415 /** 2416 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2417 * @hw: pointer to hardware structure 2418 * @data: read data value 2419 * 2420 * Clocks in one bit via I2C data/clock 2421 **/ 2422 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2423 { 2424 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2425 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2426 2427 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2428 2429 if (data_oe_bit) { 2430 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2431 i2cctl |= data_oe_bit; 2432 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2433 IXGBE_WRITE_FLUSH(hw); 2434 } 2435 ixgbe_raise_i2c_clk(hw, &i2cctl); 2436 2437 /* Minimum high period of clock is 4us */ 2438 usec_delay(IXGBE_I2C_T_HIGH); 2439 2440 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2441 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2442 2443 ixgbe_lower_i2c_clk(hw, &i2cctl); 2444 2445 /* Minimum low period of clock is 4.7 us */ 2446 usec_delay(IXGBE_I2C_T_LOW); 2447 2448 return IXGBE_SUCCESS; 2449 } 2450 2451 /** 2452 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2453 * @hw: pointer to hardware structure 2454 * @data: data value to write 2455 * 2456 * Clocks out one bit via I2C data/clock 2457 **/ 2458 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2459 { 2460 s32 status; 2461 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2462 2463 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2464 2465 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2466 if (status == IXGBE_SUCCESS) { 2467 ixgbe_raise_i2c_clk(hw, &i2cctl); 2468 2469 /* Minimum high period of clock is 4us */ 2470 usec_delay(IXGBE_I2C_T_HIGH); 2471 2472 ixgbe_lower_i2c_clk(hw, &i2cctl); 2473 2474 /* Minimum low period of clock is 4.7 us. 2475 * This also takes care of the data hold time. 2476 */ 2477 usec_delay(IXGBE_I2C_T_LOW); 2478 } else { 2479 status = IXGBE_ERR_I2C; 2480 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2481 "I2C data was not set to %X\n", data); 2482 } 2483 2484 return status; 2485 } 2486 2487 /** 2488 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2489 * @hw: pointer to hardware structure 2490 * @i2cctl: Current value of I2CCTL register 2491 * 2492 * Raises the I2C clock line '0'->'1' 2493 * Negates the I2C clock output enable on X550 hardware. 2494 **/ 2495 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2496 { 2497 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2498 u32 i = 0; 2499 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2500 u32 i2cctl_r = 0; 2501 2502 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2503 2504 if (clk_oe_bit) { 2505 *i2cctl |= clk_oe_bit; 2506 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2507 } 2508 2509 for (i = 0; i < timeout; i++) { 2510 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2511 2512 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2513 IXGBE_WRITE_FLUSH(hw); 2514 /* SCL rise time (1000ns) */ 2515 usec_delay(IXGBE_I2C_T_RISE); 2516 2517 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2518 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2519 break; 2520 } 2521 } 2522 2523 /** 2524 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2525 * @hw: pointer to hardware structure 2526 * @i2cctl: Current value of I2CCTL register 2527 * 2528 * Lowers the I2C clock line '1'->'0' 2529 * Asserts the I2C clock output enable on X550 hardware. 2530 **/ 2531 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2532 { 2533 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2534 2535 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2536 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2537 2538 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2539 IXGBE_WRITE_FLUSH(hw); 2540 2541 /* SCL fall time (300ns) */ 2542 usec_delay(IXGBE_I2C_T_FALL); 2543 } 2544 2545 /** 2546 * ixgbe_set_i2c_data - Sets the I2C data bit 2547 * @hw: pointer to hardware structure 2548 * @i2cctl: Current value of I2CCTL register 2549 * @data: I2C data value (0 or 1) to set 2550 * 2551 * Sets the I2C data bit 2552 * Asserts the I2C data output enable on X550 hardware. 2553 **/ 2554 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2555 { 2556 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2557 s32 status = IXGBE_SUCCESS; 2558 2559 DEBUGFUNC("ixgbe_set_i2c_data"); 2560 2561 if (data) 2562 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2563 else 2564 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2565 *i2cctl &= ~data_oe_bit; 2566 2567 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2568 IXGBE_WRITE_FLUSH(hw); 2569 2570 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2571 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2572 2573 if (!data) /* Can't verify data in this case */ 2574 return IXGBE_SUCCESS; 2575 if (data_oe_bit) { 2576 *i2cctl |= data_oe_bit; 2577 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2578 IXGBE_WRITE_FLUSH(hw); 2579 } 2580 2581 /* Verify data was set correctly */ 2582 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2583 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2584 status = IXGBE_ERR_I2C; 2585 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2586 "Error - I2C data was not set to %X.\n", 2587 data); 2588 } 2589 2590 return status; 2591 } 2592 2593 /** 2594 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2595 * @hw: pointer to hardware structure 2596 * @i2cctl: Current value of I2CCTL register 2597 * 2598 * Returns the I2C data bit value 2599 * Negates the I2C data output enable on X550 hardware. 2600 **/ 2601 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2602 { 2603 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2604 bool data; 2605 2606 DEBUGFUNC("ixgbe_get_i2c_data"); 2607 2608 if (data_oe_bit) { 2609 *i2cctl |= data_oe_bit; 2610 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2611 IXGBE_WRITE_FLUSH(hw); 2612 usec_delay(IXGBE_I2C_T_FALL); 2613 } 2614 2615 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2616 data = 1; 2617 else 2618 data = 0; 2619 2620 return data; 2621 } 2622 2623 /** 2624 * ixgbe_i2c_bus_clear - Clears the I2C bus 2625 * @hw: pointer to hardware structure 2626 * 2627 * Clears the I2C bus by sending nine clock pulses. 2628 * Used when data line is stuck low. 2629 **/ 2630 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2631 { 2632 u32 i2cctl; 2633 u32 i; 2634 2635 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2636 2637 ixgbe_i2c_start(hw); 2638 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2639 2640 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2641 2642 for (i = 0; i < 9; i++) { 2643 ixgbe_raise_i2c_clk(hw, &i2cctl); 2644 2645 /* Min high period of clock is 4us */ 2646 usec_delay(IXGBE_I2C_T_HIGH); 2647 2648 ixgbe_lower_i2c_clk(hw, &i2cctl); 2649 2650 /* Min low period of clock is 4.7us*/ 2651 usec_delay(IXGBE_I2C_T_LOW); 2652 } 2653 2654 ixgbe_i2c_start(hw); 2655 2656 /* Put the i2c bus back to default state */ 2657 ixgbe_i2c_stop(hw); 2658 } 2659 2660 /** 2661 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2662 * @hw: pointer to hardware structure 2663 * 2664 * Checks if the LASI temp alarm status was triggered due to overtemp 2665 **/ 2666 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2667 { 2668 s32 status = IXGBE_SUCCESS; 2669 u16 phy_data = 0; 2670 2671 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2672 2673 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2674 goto out; 2675 2676 /* Check that the LASI temp alarm status was triggered */ 2677 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2678 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2679 2680 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2681 goto out; 2682 2683 status = IXGBE_ERR_OVERTEMP; 2684 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2685 out: 2686 return status; 2687 } 2688 2689 /** 2690 * ixgbe_set_copper_phy_power - Control power for copper phy 2691 * @hw: pointer to hardware structure 2692 * @on: TRUE for on, FALSE for off 2693 */ 2694 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2695 { 2696 u32 status; 2697 u16 reg; 2698 2699 if (!on && ixgbe_mng_present(hw)) 2700 return 0; 2701 2702 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2703 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2704 ®); 2705 if (status) 2706 return status; 2707 2708 if (on) { 2709 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2710 } else { 2711 if (ixgbe_check_reset_blocked(hw)) 2712 return 0; 2713 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2714 } 2715 2716 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2717 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2718 reg); 2719 return status; 2720 } 2721
Indexes created Wed Sep 24 15:09:51 GMT 2025