ixgbe_phy.c revision 1.14.2.1
1 /* $NetBSD: ixgbe_phy.c,v 1.14.2.1 2018/03/15 09:12:06 pgoyette Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 320688 2017-07-05 17:27:03Z erj $*/ 37 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 42 #include <dev/mii/mdio.h> 43 44 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 45 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 46 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 47 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 48 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 49 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 50 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 51 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 52 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 53 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 54 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 55 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 56 u8 *sff8472_data); 57 58 /** 59 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 60 * @hw: pointer to the hardware structure 61 * @byte: byte to send 62 * 63 * Returns an error code on error. 64 */ 65 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 66 { 67 s32 status; 68 69 status = ixgbe_clock_out_i2c_byte(hw, byte); 70 if (status) 71 return status; 72 return ixgbe_get_i2c_ack(hw); 73 } 74 75 /** 76 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 77 * @hw: pointer to the hardware structure 78 * @byte: pointer to a u8 to receive the byte 79 * 80 * Returns an error code on error. 81 */ 82 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 83 { 84 s32 status; 85 86 status = ixgbe_clock_in_i2c_byte(hw, byte); 87 if (status) 88 return status; 89 /* ACK */ 90 return ixgbe_clock_out_i2c_bit(hw, FALSE); 91 } 92 93 /** 94 * ixgbe_ones_comp_byte_add - Perform one's complement addition 95 * @add1 - addend 1 96 * @add2 - addend 2 97 * 98 * Returns one's complement 8-bit sum. 99 */ 100 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 101 { 102 u16 sum = add1 + add2; 103 104 sum = (sum & 0xFF) + (sum >> 8); 105 return sum & 0xFF; 106 } 107 108 /** 109 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 110 * @hw: pointer to the hardware structure 111 * @addr: I2C bus address to read from 112 * @reg: I2C device register to read from 113 * @val: pointer to location to receive read value 114 * @lock: TRUE if to take and release semaphore 115 * 116 * Returns an error code on error. 117 */ 118 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 119 u16 *val, bool lock) 120 { 121 u32 swfw_mask = hw->phy.phy_semaphore_mask; 122 int max_retry = 3; 123 int retry = 0; 124 u8 csum_byte; 125 u8 high_bits; 126 u8 low_bits; 127 u8 reg_high; 128 u8 csum; 129 130 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 131 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 132 csum = ~csum; 133 do { 134 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 135 return IXGBE_ERR_SWFW_SYNC; 136 ixgbe_i2c_start(hw); 137 /* Device Address and write indication */ 138 if (ixgbe_out_i2c_byte_ack(hw, addr)) 139 goto fail; 140 /* Write bits 14:8 */ 141 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 142 goto fail; 143 /* Write bits 7:0 */ 144 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 145 goto fail; 146 /* Write csum */ 147 if (ixgbe_out_i2c_byte_ack(hw, csum)) 148 goto fail; 149 /* Re-start condition */ 150 ixgbe_i2c_start(hw); 151 /* Device Address and read indication */ 152 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 153 goto fail; 154 /* Get upper bits */ 155 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 156 goto fail; 157 /* Get low bits */ 158 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 159 goto fail; 160 /* Get csum */ 161 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 162 goto fail; 163 /* NACK */ 164 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 165 goto fail; 166 ixgbe_i2c_stop(hw); 167 if (lock) 168 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 169 *val = (high_bits << 8) | low_bits; 170 return 0; 171 172 fail: 173 ixgbe_i2c_bus_clear(hw); 174 if (lock) 175 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 176 retry++; 177 if (retry < max_retry) 178 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 179 else 180 DEBUGOUT("I2C byte read combined error.\n"); 181 } while (retry < max_retry); 182 183 return IXGBE_ERR_I2C; 184 } 185 186 /** 187 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 188 * @hw: pointer to the hardware structure 189 * @addr: I2C bus address to write to 190 * @reg: I2C device register to write to 191 * @val: value to write 192 * @lock: TRUE if to take and release semaphore 193 * 194 * Returns an error code on error. 195 */ 196 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 197 u16 val, bool lock) 198 { 199 u32 swfw_mask = hw->phy.phy_semaphore_mask; 200 int max_retry = 1; 201 int retry = 0; 202 u8 reg_high; 203 u8 csum; 204 205 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 206 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 207 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 208 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 209 csum = ~csum; 210 do { 211 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 212 return IXGBE_ERR_SWFW_SYNC; 213 ixgbe_i2c_start(hw); 214 /* Device Address and write indication */ 215 if (ixgbe_out_i2c_byte_ack(hw, addr)) 216 goto fail; 217 /* Write bits 14:8 */ 218 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 219 goto fail; 220 /* Write bits 7:0 */ 221 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 222 goto fail; 223 /* Write data 15:8 */ 224 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 225 goto fail; 226 /* Write data 7:0 */ 227 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 228 goto fail; 229 /* Write csum */ 230 if (ixgbe_out_i2c_byte_ack(hw, csum)) 231 goto fail; 232 ixgbe_i2c_stop(hw); 233 if (lock) 234 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 235 return 0; 236 237 fail: 238 ixgbe_i2c_bus_clear(hw); 239 if (lock) 240 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 241 retry++; 242 if (retry < max_retry) 243 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 244 else 245 DEBUGOUT("I2C byte write combined error.\n"); 246 } while (retry < max_retry); 247 248 return IXGBE_ERR_I2C; 249 } 250 251 /** 252 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 253 * @hw: pointer to the hardware structure 254 * 255 * Initialize the function pointers. 256 **/ 257 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 258 { 259 struct ixgbe_phy_info *phy = &hw->phy; 260 261 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 262 263 /* PHY */ 264 phy->ops.identify = ixgbe_identify_phy_generic; 265 phy->ops.reset = ixgbe_reset_phy_generic; 266 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 267 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 268 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 269 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 270 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 271 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 272 phy->ops.check_link = NULL; 273 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 274 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 275 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 276 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 277 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 278 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 279 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 280 phy->ops.identify_sfp = ixgbe_identify_module_generic; 281 phy->sfp_type = ixgbe_sfp_type_unknown; 282 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 283 phy->ops.write_i2c_byte_unlocked = 284 ixgbe_write_i2c_byte_generic_unlocked; 285 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 286 return IXGBE_SUCCESS; 287 } 288 289 /** 290 * ixgbe_probe_phy - Probe a single address for a PHY 291 * @hw: pointer to hardware structure 292 * @phy_addr: PHY address to probe 293 * 294 * Returns TRUE if PHY found 295 */ 296 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 297 { 298 u16 ext_ability = 0; 299 300 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 301 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 302 phy_addr); 303 return FALSE; 304 } 305 306 if (ixgbe_get_phy_id(hw)) 307 return FALSE; 308 309 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 310 311 if (hw->phy.type == ixgbe_phy_unknown) { 312 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 313 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 314 if (ext_ability & 315 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 316 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 317 hw->phy.type = ixgbe_phy_cu_unknown; 318 else 319 hw->phy.type = ixgbe_phy_generic; 320 } 321 322 return TRUE; 323 } 324 325 /** 326 * ixgbe_identify_phy_generic - Get physical layer module 327 * @hw: pointer to hardware structure 328 * 329 * Determines the physical layer module found on the current adapter. 330 **/ 331 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 332 { 333 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 334 u16 phy_addr; 335 336 DEBUGFUNC("ixgbe_identify_phy_generic"); 337 338 if (!hw->phy.phy_semaphore_mask) { 339 if (hw->bus.lan_id) 340 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 341 else 342 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 343 } 344 345 if (hw->phy.type != ixgbe_phy_unknown) 346 return IXGBE_SUCCESS; 347 348 if (hw->phy.nw_mng_if_sel) { 349 phy_addr = (hw->phy.nw_mng_if_sel & 350 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 351 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 352 if (ixgbe_probe_phy(hw, phy_addr)) 353 return IXGBE_SUCCESS; 354 else 355 return IXGBE_ERR_PHY_ADDR_INVALID; 356 } 357 358 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 359 if (ixgbe_probe_phy(hw, phy_addr)) { 360 status = IXGBE_SUCCESS; 361 break; 362 } 363 } 364 365 /* Certain media types do not have a phy so an address will not 366 * be found and the code will take this path. Caller has to 367 * decide if it is an error or not. 368 */ 369 if (status != IXGBE_SUCCESS) 370 hw->phy.addr = 0; 371 372 return status; 373 } 374 375 /** 376 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 377 * @hw: pointer to the hardware structure 378 * 379 * This function checks the MMNGC.MNG_VETO bit to see if there are 380 * any constraints on link from manageability. For MAC's that don't 381 * have this bit just return faluse since the link can not be blocked 382 * via this method. 383 **/ 384 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 385 { 386 u32 mmngc; 387 388 DEBUGFUNC("ixgbe_check_reset_blocked"); 389 390 /* If we don't have this bit, it can't be blocking */ 391 if (hw->mac.type == ixgbe_mac_82598EB) 392 return FALSE; 393 394 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 395 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 396 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 397 "MNG_VETO bit detected.\n"); 398 return TRUE; 399 } 400 401 return FALSE; 402 } 403 404 /** 405 * ixgbe_validate_phy_addr - Determines phy address is valid 406 * @hw: pointer to hardware structure 407 * 408 **/ 409 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 410 { 411 u16 phy_id = 0; 412 bool valid = FALSE; 413 414 DEBUGFUNC("ixgbe_validate_phy_addr"); 415 416 hw->phy.addr = phy_addr; 417 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 418 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 419 420 if (phy_id != 0xFFFF && phy_id != 0x0) 421 valid = TRUE; 422 423 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 424 425 return valid; 426 } 427 428 /** 429 * ixgbe_get_phy_id - Get the phy type 430 * @hw: pointer to hardware structure 431 * 432 **/ 433 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 434 { 435 u32 status; 436 u16 phy_id_high = 0; 437 u16 phy_id_low = 0; 438 439 DEBUGFUNC("ixgbe_get_phy_id"); 440 441 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 442 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 443 &phy_id_high); 444 445 if (status == IXGBE_SUCCESS) { 446 hw->phy.id = (u32)(phy_id_high << 16); 447 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 448 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 449 &phy_id_low); 450 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 451 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 452 } 453 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 454 phy_id_high, phy_id_low); 455 456 return status; 457 } 458 459 /** 460 * ixgbe_get_phy_type_from_id - Get the phy type 461 * @phy_id: PHY ID information 462 * 463 **/ 464 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 465 { 466 enum ixgbe_phy_type phy_type; 467 468 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 469 470 switch (phy_id) { 471 case TN1010_PHY_ID: 472 phy_type = ixgbe_phy_tn; 473 break; 474 case X550_PHY_ID2: 475 case X550_PHY_ID3: 476 case X540_PHY_ID: 477 phy_type = ixgbe_phy_aq; 478 break; 479 case QT2022_PHY_ID: 480 phy_type = ixgbe_phy_qt; 481 break; 482 case ATH_PHY_ID: 483 phy_type = ixgbe_phy_nl; 484 break; 485 case X557_PHY_ID: 486 case X557_PHY_ID2: 487 phy_type = ixgbe_phy_x550em_ext_t; 488 break; 489 case IXGBE_M88E1500_E_PHY_ID: 490 case IXGBE_M88E1543_E_PHY_ID: 491 phy_type = ixgbe_phy_ext_1g_t; 492 break; 493 default: 494 phy_type = ixgbe_phy_unknown; 495 break; 496 } 497 return phy_type; 498 } 499 500 /** 501 * ixgbe_reset_phy_generic - Performs a PHY reset 502 * @hw: pointer to hardware structure 503 **/ 504 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 505 { 506 u32 i; 507 u16 ctrl = 0; 508 s32 status = IXGBE_SUCCESS; 509 510 DEBUGFUNC("ixgbe_reset_phy_generic"); 511 512 if (hw->phy.type == ixgbe_phy_unknown) 513 status = ixgbe_identify_phy_generic(hw); 514 515 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 516 goto out; 517 518 /* Don't reset PHY if it's shut down due to overtemp. */ 519 if (!hw->phy.reset_if_overtemp && 520 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 521 goto out; 522 523 /* Blocked by MNG FW so bail */ 524 if (ixgbe_check_reset_blocked(hw)) 525 goto out; 526 527 /* 528 * Perform soft PHY reset to the PHY_XS. 529 * This will cause a soft reset to the PHY 530 */ 531 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 532 IXGBE_MDIO_PHY_XS_DEV_TYPE, 533 IXGBE_MDIO_PHY_XS_RESET); 534 535 /* 536 * Poll for reset bit to self-clear indicating reset is complete. 537 * Some PHYs could take up to 3 seconds to complete and need about 538 * 1.7 usec delay after the reset is complete. 539 */ 540 for (i = 0; i < 30; i++) { 541 msec_delay(100); 542 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 543 status = hw->phy.ops.read_reg(hw, 544 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 545 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 546 &ctrl); 547 if (status != IXGBE_SUCCESS) 548 return status; 549 550 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 551 usec_delay(2); 552 break; 553 } 554 } else { 555 status = hw->phy.ops.read_reg(hw, 556 IXGBE_MDIO_PHY_XS_CONTROL, 557 IXGBE_MDIO_PHY_XS_DEV_TYPE, 558 &ctrl); 559 if (status != IXGBE_SUCCESS) 560 return status; 561 562 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 563 usec_delay(2); 564 break; 565 } 566 } 567 } 568 569 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 570 status = IXGBE_ERR_RESET_FAILED; 571 ERROR_REPORT1(IXGBE_ERROR_POLLING, 572 "PHY reset polling failed to complete.\n"); 573 } 574 575 out: 576 return status; 577 } 578 579 /** 580 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 581 * the SWFW lock 582 * @hw: pointer to hardware structure 583 * @reg_addr: 32 bit address of PHY register to read 584 * @phy_data: Pointer to read data from PHY register 585 **/ 586 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 587 u16 *phy_data) 588 { 589 u32 i, data, command; 590 591 /* Setup and write the address cycle command */ 592 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 593 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 594 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 595 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 596 597 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 598 599 /* 600 * Check every 10 usec to see if the address cycle completed. 601 * The MDI Command bit will clear when the operation is 602 * complete 603 */ 604 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 605 usec_delay(10); 606 607 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 608 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 609 break; 610 } 611 612 613 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 614 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 615 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 616 return IXGBE_ERR_PHY; 617 } 618 619 /* 620 * Address cycle complete, setup and write the read 621 * command 622 */ 623 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 624 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 625 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 626 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 627 628 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 629 630 /* 631 * Check every 10 usec to see if the address cycle 632 * completed. The MDI Command bit will clear when the 633 * operation is complete 634 */ 635 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 636 usec_delay(10); 637 638 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 639 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 640 break; 641 } 642 643 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 644 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 645 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 646 return IXGBE_ERR_PHY; 647 } 648 649 /* 650 * Read operation is complete. Get the data 651 * from MSRWD 652 */ 653 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 654 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 655 *phy_data = (u16)(data); 656 657 return IXGBE_SUCCESS; 658 } 659 660 /** 661 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 662 * using the SWFW lock - this function is needed in most cases 663 * @hw: pointer to hardware structure 664 * @reg_addr: 32 bit address of PHY register to read 665 * @phy_data: Pointer to read data from PHY register 666 **/ 667 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 668 u32 device_type, u16 *phy_data) 669 { 670 s32 status; 671 u32 gssr = hw->phy.phy_semaphore_mask; 672 673 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 674 675 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 676 return IXGBE_ERR_SWFW_SYNC; 677 678 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 679 680 hw->mac.ops.release_swfw_sync(hw, gssr); 681 682 return status; 683 } 684 685 /** 686 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 687 * without SWFW lock 688 * @hw: pointer to hardware structure 689 * @reg_addr: 32 bit PHY register to write 690 * @device_type: 5 bit device type 691 * @phy_data: Data to write to the PHY register 692 **/ 693 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 694 u32 device_type, u16 phy_data) 695 { 696 u32 i, command; 697 698 /* Put the data in the MDI single read and write data register*/ 699 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 700 701 /* Setup and write the address cycle command */ 702 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 703 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 704 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 705 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 706 707 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 708 709 /* 710 * Check every 10 usec to see if the address cycle completed. 711 * The MDI Command bit will clear when the operation is 712 * complete 713 */ 714 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 715 usec_delay(10); 716 717 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 718 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 719 break; 720 } 721 722 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 723 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 724 return IXGBE_ERR_PHY; 725 } 726 727 /* 728 * Address cycle complete, setup and write the write 729 * command 730 */ 731 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 732 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 733 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 734 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 735 736 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 737 738 /* 739 * Check every 10 usec to see if the address cycle 740 * completed. The MDI Command bit will clear when the 741 * operation is complete 742 */ 743 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 744 usec_delay(10); 745 746 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 747 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 748 break; 749 } 750 751 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 752 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 753 return IXGBE_ERR_PHY; 754 } 755 756 return IXGBE_SUCCESS; 757 } 758 759 /** 760 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 761 * using SWFW lock- this function is needed in most cases 762 * @hw: pointer to hardware structure 763 * @reg_addr: 32 bit PHY register to write 764 * @device_type: 5 bit device type 765 * @phy_data: Data to write to the PHY register 766 **/ 767 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 768 u32 device_type, u16 phy_data) 769 { 770 s32 status; 771 u32 gssr = hw->phy.phy_semaphore_mask; 772 773 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 774 775 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 776 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 777 phy_data); 778 hw->mac.ops.release_swfw_sync(hw, gssr); 779 } else { 780 status = IXGBE_ERR_SWFW_SYNC; 781 } 782 783 return status; 784 } 785 786 /** 787 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 788 * @hw: pointer to hardware structure 789 * 790 * Restart auto-negotiation and PHY and waits for completion. 791 **/ 792 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 793 { 794 s32 status = IXGBE_SUCCESS; 795 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 796 bool autoneg = FALSE; 797 ixgbe_link_speed speed; 798 799 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 800 801 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 802 803 /* Set or unset auto-negotiation 10G advertisement */ 804 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 805 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 806 &autoneg_reg); 807 808 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 809 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 810 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 811 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 812 813 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 814 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 815 autoneg_reg); 816 817 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 818 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 819 &autoneg_reg); 820 821 if (hw->mac.type == ixgbe_mac_X550) { 822 /* Set or unset auto-negotiation 5G advertisement */ 823 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 824 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 825 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 826 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 827 828 /* Set or unset auto-negotiation 2.5G advertisement */ 829 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 830 if ((hw->phy.autoneg_advertised & 831 IXGBE_LINK_SPEED_2_5GB_FULL) && 832 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 833 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 834 } 835 836 /* Set or unset auto-negotiation 1G advertisement */ 837 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 839 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 840 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 841 842 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 843 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 844 autoneg_reg); 845 846 /* Set or unset auto-negotiation 100M advertisement */ 847 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 848 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 849 &autoneg_reg); 850 851 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 852 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 853 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 854 (speed & IXGBE_LINK_SPEED_100_FULL)) 855 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 856 857 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 858 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 859 autoneg_reg); 860 861 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) { 862 u16 ctrl; 863 864 /* Force 100Mbps */ 865 hw->phy.ops.read_reg(hw, MDIO_PMAPMD_CTRL1, MDIO_MMD_PMAPMD, 866 &ctrl); 867 ctrl &= ~PMAPMD_CTRL1_SPEED_MASK; 868 ctrl |= PMAPMD_CTRL1_SPEED_100; 869 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD, 870 ctrl); 871 872 /* Don't use auto-nego for 100Mbps */ 873 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 874 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 875 876 autoneg_reg &= ~AN_CTRL1_AUTOEN; 877 878 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 879 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 880 } else { 881 /* Blocked by MNG FW so don't reset PHY */ 882 if (ixgbe_check_reset_blocked(hw)) 883 return status; 884 885 /* Restart PHY auto-negotiation. */ 886 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 887 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 888 889 autoneg_reg |= IXGBE_MII_RESTART | AN_CTRL1_AUTOEN; 890 891 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 892 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 893 } 894 895 return status; 896 } 897 898 /** 899 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 900 * @hw: pointer to hardware structure 901 * @speed: new link speed 902 **/ 903 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 904 ixgbe_link_speed speed, 905 bool autoneg_wait_to_complete) 906 { 907 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 908 909 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 910 911 /* 912 * Clear autoneg_advertised and set new values based on input link 913 * speed. 914 */ 915 hw->phy.autoneg_advertised = 0; 916 917 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 918 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 919 920 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 921 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 922 923 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 924 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 925 926 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 927 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 928 929 if (speed & IXGBE_LINK_SPEED_100_FULL) 930 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 931 932 if (speed & IXGBE_LINK_SPEED_10_FULL) 933 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 934 935 /* Setup link based on the new speed settings */ 936 ixgbe_setup_phy_link(hw); 937 938 return IXGBE_SUCCESS; 939 } 940 941 /** 942 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 943 * @hw: pointer to hardware structure 944 * 945 * Determines the supported link capabilities by reading the PHY auto 946 * negotiation register. 947 **/ 948 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 949 { 950 s32 status; 951 u16 speed_ability; 952 953 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 954 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 955 &speed_ability); 956 if (status) 957 return status; 958 959 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 960 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 961 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 962 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 963 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 964 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 965 966 switch (hw->mac.type) { 967 case ixgbe_mac_X550: 968 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 969 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 970 break; 971 case ixgbe_mac_X550EM_x: 972 case ixgbe_mac_X550EM_a: 973 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 974 break; 975 default: 976 break; 977 } 978 979 return status; 980 } 981 982 /** 983 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 984 * @hw: pointer to hardware structure 985 * @speed: pointer to link speed 986 * @autoneg: boolean auto-negotiation value 987 **/ 988 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 989 ixgbe_link_speed *speed, 990 bool *autoneg) 991 { 992 s32 status = IXGBE_SUCCESS; 993 994 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 995 996 *autoneg = TRUE; 997 if (!hw->phy.speeds_supported) 998 status = ixgbe_get_copper_speeds_supported(hw); 999 1000 *speed = hw->phy.speeds_supported; 1001 return status; 1002 } 1003 1004 /** 1005 * ixgbe_check_phy_link_tnx - Determine link and speed status 1006 * @hw: pointer to hardware structure 1007 * 1008 * Reads the VS1 register to determine if link is up and the current speed for 1009 * the PHY. 1010 **/ 1011 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1012 bool *link_up) 1013 { 1014 s32 status = IXGBE_SUCCESS; 1015 u32 time_out; 1016 u32 max_time_out = 10; 1017 u16 phy_link = 0; 1018 u16 phy_speed = 0; 1019 u16 phy_data = 0; 1020 1021 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1022 1023 /* Initialize speed and link to default case */ 1024 *link_up = FALSE; 1025 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1026 1027 /* 1028 * Check current speed and link status of the PHY register. 1029 * This is a vendor specific register and may have to 1030 * be changed for other copper PHYs. 1031 */ 1032 for (time_out = 0; time_out < max_time_out; time_out++) { 1033 usec_delay(10); 1034 status = hw->phy.ops.read_reg(hw, 1035 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1036 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1037 &phy_data); 1038 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1039 phy_speed = phy_data & 1040 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1041 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1042 *link_up = TRUE; 1043 if (phy_speed == 1044 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1045 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1046 break; 1047 } 1048 } 1049 1050 return status; 1051 } 1052 1053 /** 1054 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1055 * @hw: pointer to hardware structure 1056 * 1057 * Restart auto-negotiation and PHY and waits for completion. 1058 **/ 1059 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1060 { 1061 s32 status = IXGBE_SUCCESS; 1062 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1063 bool autoneg = FALSE; 1064 ixgbe_link_speed speed; 1065 1066 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1067 1068 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1069 1070 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1071 /* Set or unset auto-negotiation 10G advertisement */ 1072 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1073 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1074 &autoneg_reg); 1075 1076 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1077 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1078 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1079 1080 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1081 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1082 autoneg_reg); 1083 } 1084 1085 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1086 /* Set or unset auto-negotiation 1G advertisement */ 1087 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1088 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1089 &autoneg_reg); 1090 1091 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1092 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1093 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1094 1095 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1096 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1097 autoneg_reg); 1098 } 1099 1100 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1101 /* Set or unset auto-negotiation 100M advertisement */ 1102 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1103 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1104 &autoneg_reg); 1105 1106 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1107 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1108 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1109 1110 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1111 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1112 autoneg_reg); 1113 } 1114 1115 /* Blocked by MNG FW so don't reset PHY */ 1116 if (ixgbe_check_reset_blocked(hw)) 1117 return status; 1118 1119 /* Restart PHY auto-negotiation. */ 1120 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1121 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1122 1123 autoneg_reg |= IXGBE_MII_RESTART; 1124 1125 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1126 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1127 1128 return status; 1129 } 1130 1131 /** 1132 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1133 * @hw: pointer to hardware structure 1134 * @firmware_version: pointer to the PHY Firmware Version 1135 **/ 1136 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1137 u16 *firmware_version) 1138 { 1139 s32 status; 1140 1141 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1142 1143 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1144 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1145 firmware_version); 1146 1147 return status; 1148 } 1149 1150 /** 1151 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1152 * @hw: pointer to hardware structure 1153 * @firmware_version: pointer to the PHY Firmware Version 1154 **/ 1155 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1156 u16 *firmware_version) 1157 { 1158 s32 status; 1159 1160 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1161 1162 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1163 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1164 firmware_version); 1165 1166 return status; 1167 } 1168 1169 /** 1170 * ixgbe_reset_phy_nl - Performs a PHY reset 1171 * @hw: pointer to hardware structure 1172 **/ 1173 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1174 { 1175 u16 phy_offset, control, eword, edata, block_crc; 1176 bool end_data = FALSE; 1177 u16 list_offset, data_offset; 1178 u16 phy_data = 0; 1179 s32 ret_val = IXGBE_SUCCESS; 1180 u32 i; 1181 1182 DEBUGFUNC("ixgbe_reset_phy_nl"); 1183 1184 /* Blocked by MNG FW so bail */ 1185 if (ixgbe_check_reset_blocked(hw)) 1186 goto out; 1187 1188 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1189 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1190 1191 /* reset the PHY and poll for completion */ 1192 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1193 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1194 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1195 1196 for (i = 0; i < 100; i++) { 1197 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1198 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1199 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1200 break; 1201 msec_delay(10); 1202 } 1203 1204 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1205 DEBUGOUT("PHY reset did not complete.\n"); 1206 ret_val = IXGBE_ERR_PHY; 1207 goto out; 1208 } 1209 1210 /* Get init offsets */ 1211 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1212 &data_offset); 1213 if (ret_val != IXGBE_SUCCESS) 1214 goto out; 1215 1216 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1217 data_offset++; 1218 while (!end_data) { 1219 /* 1220 * Read control word from PHY init contents offset 1221 */ 1222 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1223 if (ret_val) 1224 goto err_eeprom; 1225 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1226 IXGBE_CONTROL_SHIFT_NL; 1227 edata = eword & IXGBE_DATA_MASK_NL; 1228 switch (control) { 1229 case IXGBE_DELAY_NL: 1230 data_offset++; 1231 DEBUGOUT1("DELAY: %d MS\n", edata); 1232 msec_delay(edata); 1233 break; 1234 case IXGBE_DATA_NL: 1235 DEBUGOUT("DATA:\n"); 1236 data_offset++; 1237 ret_val = hw->eeprom.ops.read(hw, data_offset, 1238 &phy_offset); 1239 if (ret_val) 1240 goto err_eeprom; 1241 data_offset++; 1242 for (i = 0; i < edata; i++) { 1243 ret_val = hw->eeprom.ops.read(hw, data_offset, 1244 &eword); 1245 if (ret_val) 1246 goto err_eeprom; 1247 hw->phy.ops.write_reg(hw, phy_offset, 1248 IXGBE_TWINAX_DEV, eword); 1249 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1250 phy_offset); 1251 data_offset++; 1252 phy_offset++; 1253 } 1254 break; 1255 case IXGBE_CONTROL_NL: 1256 data_offset++; 1257 DEBUGOUT("CONTROL:\n"); 1258 if (edata == IXGBE_CONTROL_EOL_NL) { 1259 DEBUGOUT("EOL\n"); 1260 end_data = TRUE; 1261 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1262 DEBUGOUT("SOL\n"); 1263 } else { 1264 DEBUGOUT("Bad control value\n"); 1265 ret_val = IXGBE_ERR_PHY; 1266 goto out; 1267 } 1268 break; 1269 default: 1270 DEBUGOUT("Bad control type\n"); 1271 ret_val = IXGBE_ERR_PHY; 1272 goto out; 1273 } 1274 } 1275 1276 out: 1277 return ret_val; 1278 1279 err_eeprom: 1280 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1281 "eeprom read at offset %d failed", data_offset); 1282 return IXGBE_ERR_PHY; 1283 } 1284 1285 /** 1286 * ixgbe_identify_module_generic - Identifies module type 1287 * @hw: pointer to hardware structure 1288 * 1289 * Determines HW type and calls appropriate function. 1290 **/ 1291 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1292 { 1293 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1294 1295 DEBUGFUNC("ixgbe_identify_module_generic"); 1296 1297 switch (hw->mac.ops.get_media_type(hw)) { 1298 case ixgbe_media_type_fiber: 1299 status = ixgbe_identify_sfp_module_generic(hw); 1300 break; 1301 1302 case ixgbe_media_type_fiber_qsfp: 1303 status = ixgbe_identify_qsfp_module_generic(hw); 1304 break; 1305 1306 default: 1307 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1308 status = IXGBE_ERR_SFP_NOT_PRESENT; 1309 break; 1310 } 1311 1312 return status; 1313 } 1314 1315 /** 1316 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1317 * @hw: pointer to hardware structure 1318 * 1319 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1320 **/ 1321 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1322 { 1323 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1324 u32 vendor_oui = 0; 1325 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1326 u8 identifier = 0; 1327 u8 comp_codes_1g = 0; 1328 u8 comp_codes_10g = 0; 1329 u8 oui_bytes[3] = {0, 0, 0}; 1330 u8 cable_tech = 0; 1331 u8 cable_spec = 0; 1332 u16 enforce_sfp = 0; 1333 1334 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1335 1336 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1337 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1338 status = IXGBE_ERR_SFP_NOT_PRESENT; 1339 goto out; 1340 } 1341 1342 /* LAN ID is needed for I2C access */ 1343 hw->mac.ops.set_lan_id(hw); 1344 1345 status = hw->phy.ops.read_i2c_eeprom(hw, 1346 IXGBE_SFF_IDENTIFIER, 1347 &identifier); 1348 1349 if (status != IXGBE_SUCCESS) 1350 goto err_read_i2c_eeprom; 1351 1352 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1353 hw->phy.type = ixgbe_phy_sfp_unsupported; 1354 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1355 } else { 1356 status = hw->phy.ops.read_i2c_eeprom(hw, 1357 IXGBE_SFF_1GBE_COMP_CODES, 1358 &comp_codes_1g); 1359 1360 if (status != IXGBE_SUCCESS) 1361 goto err_read_i2c_eeprom; 1362 1363 status = hw->phy.ops.read_i2c_eeprom(hw, 1364 IXGBE_SFF_10GBE_COMP_CODES, 1365 &comp_codes_10g); 1366 1367 if (status != IXGBE_SUCCESS) 1368 goto err_read_i2c_eeprom; 1369 status = hw->phy.ops.read_i2c_eeprom(hw, 1370 IXGBE_SFF_CABLE_TECHNOLOGY, 1371 &cable_tech); 1372 1373 if (status != IXGBE_SUCCESS) 1374 goto err_read_i2c_eeprom; 1375 1376 /* ID Module 1377 * ========= 1378 * 0 SFP_DA_CU 1379 * 1 SFP_SR 1380 * 2 SFP_LR 1381 * 3 SFP_DA_CORE0 - 82599-specific 1382 * 4 SFP_DA_CORE1 - 82599-specific 1383 * 5 SFP_SR/LR_CORE0 - 82599-specific 1384 * 6 SFP_SR/LR_CORE1 - 82599-specific 1385 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1386 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1387 * 9 SFP_1g_cu_CORE0 - 82599-specific 1388 * 10 SFP_1g_cu_CORE1 - 82599-specific 1389 * 11 SFP_1g_sx_CORE0 - 82599-specific 1390 * 12 SFP_1g_sx_CORE1 - 82599-specific 1391 */ 1392 if (hw->mac.type == ixgbe_mac_82598EB) { 1393 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1394 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1395 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1396 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1397 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1398 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1399 else 1400 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1401 } else { 1402 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1403 if (hw->bus.lan_id == 0) 1404 hw->phy.sfp_type = 1405 ixgbe_sfp_type_da_cu_core0; 1406 else 1407 hw->phy.sfp_type = 1408 ixgbe_sfp_type_da_cu_core1; 1409 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1410 hw->phy.ops.read_i2c_eeprom( 1411 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1412 &cable_spec); 1413 if (cable_spec & 1414 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1415 if (hw->bus.lan_id == 0) 1416 hw->phy.sfp_type = 1417 ixgbe_sfp_type_da_act_lmt_core0; 1418 else 1419 hw->phy.sfp_type = 1420 ixgbe_sfp_type_da_act_lmt_core1; 1421 } else { 1422 hw->phy.sfp_type = 1423 ixgbe_sfp_type_unknown; 1424 } 1425 } else if (comp_codes_10g & 1426 (IXGBE_SFF_10GBASESR_CAPABLE | 1427 IXGBE_SFF_10GBASELR_CAPABLE)) { 1428 if (hw->bus.lan_id == 0) 1429 hw->phy.sfp_type = 1430 ixgbe_sfp_type_srlr_core0; 1431 else 1432 hw->phy.sfp_type = 1433 ixgbe_sfp_type_srlr_core1; 1434 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1435 if (hw->bus.lan_id == 0) 1436 hw->phy.sfp_type = 1437 ixgbe_sfp_type_1g_cu_core0; 1438 else 1439 hw->phy.sfp_type = 1440 ixgbe_sfp_type_1g_cu_core1; 1441 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1442 if (hw->bus.lan_id == 0) 1443 hw->phy.sfp_type = 1444 ixgbe_sfp_type_1g_sx_core0; 1445 else 1446 hw->phy.sfp_type = 1447 ixgbe_sfp_type_1g_sx_core1; 1448 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1449 if (hw->bus.lan_id == 0) 1450 hw->phy.sfp_type = 1451 ixgbe_sfp_type_1g_lx_core0; 1452 else 1453 hw->phy.sfp_type = 1454 ixgbe_sfp_type_1g_lx_core1; 1455 } else { 1456 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1457 } 1458 } 1459 1460 if (hw->phy.sfp_type != stored_sfp_type) 1461 hw->phy.sfp_setup_needed = TRUE; 1462 1463 /* Determine if the SFP+ PHY is dual speed or not. */ 1464 hw->phy.multispeed_fiber = FALSE; 1465 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1466 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1467 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1468 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1469 hw->phy.multispeed_fiber = TRUE; 1470 1471 /* Determine PHY vendor */ 1472 if (hw->phy.type != ixgbe_phy_nl) { 1473 hw->phy.id = identifier; 1474 status = hw->phy.ops.read_i2c_eeprom(hw, 1475 IXGBE_SFF_VENDOR_OUI_BYTE0, 1476 &oui_bytes[0]); 1477 1478 if (status != IXGBE_SUCCESS) 1479 goto err_read_i2c_eeprom; 1480 1481 status = hw->phy.ops.read_i2c_eeprom(hw, 1482 IXGBE_SFF_VENDOR_OUI_BYTE1, 1483 &oui_bytes[1]); 1484 1485 if (status != IXGBE_SUCCESS) 1486 goto err_read_i2c_eeprom; 1487 1488 status = hw->phy.ops.read_i2c_eeprom(hw, 1489 IXGBE_SFF_VENDOR_OUI_BYTE2, 1490 &oui_bytes[2]); 1491 1492 if (status != IXGBE_SUCCESS) 1493 goto err_read_i2c_eeprom; 1494 1495 vendor_oui = 1496 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1497 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1498 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1499 1500 switch (vendor_oui) { 1501 case IXGBE_SFF_VENDOR_OUI_TYCO: 1502 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1503 hw->phy.type = 1504 ixgbe_phy_sfp_passive_tyco; 1505 break; 1506 case IXGBE_SFF_VENDOR_OUI_FTL: 1507 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1508 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1509 else 1510 hw->phy.type = ixgbe_phy_sfp_ftl; 1511 break; 1512 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1513 hw->phy.type = ixgbe_phy_sfp_avago; 1514 break; 1515 case IXGBE_SFF_VENDOR_OUI_INTEL: 1516 hw->phy.type = ixgbe_phy_sfp_intel; 1517 break; 1518 default: 1519 hw->phy.type = ixgbe_phy_sfp_unknown; 1520 break; 1521 } 1522 } 1523 1524 /* Allow any DA cable vendor */ 1525 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1526 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1527 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1528 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1529 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1530 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1531 status = IXGBE_SUCCESS; 1532 goto out; 1533 } 1534 1535 /* Verify supported 1G SFP modules */ 1536 if (comp_codes_10g == 0 && 1537 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1539 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1540 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1541 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1543 hw->phy.type = ixgbe_phy_sfp_unsupported; 1544 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1545 goto out; 1546 } 1547 1548 /* Anything else 82598-based is supported */ 1549 if (hw->mac.type == ixgbe_mac_82598EB) { 1550 status = IXGBE_SUCCESS; 1551 goto out; 1552 } 1553 1554 ixgbe_get_device_caps(hw, &enforce_sfp); 1555 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1556 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1557 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1558 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1559 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1561 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1562 /* Make sure we're a supported PHY type */ 1563 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1564 status = IXGBE_SUCCESS; 1565 } else { 1566 if (hw->allow_unsupported_sfp == TRUE) { 1567 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1568 status = IXGBE_SUCCESS; 1569 } else { 1570 DEBUGOUT("SFP+ module not supported\n"); 1571 hw->phy.type = 1572 ixgbe_phy_sfp_unsupported; 1573 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1574 } 1575 } 1576 } else { 1577 status = IXGBE_SUCCESS; 1578 } 1579 } 1580 1581 out: 1582 return status; 1583 1584 err_read_i2c_eeprom: 1585 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1586 if (hw->phy.type != ixgbe_phy_nl) { 1587 hw->phy.id = 0; 1588 hw->phy.type = ixgbe_phy_unknown; 1589 } 1590 return IXGBE_ERR_SFP_NOT_PRESENT; 1591 } 1592 1593 /** 1594 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1595 * @hw: pointer to hardware structure 1596 * 1597 * Determines physical layer capabilities of the current SFP. 1598 */ 1599 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1600 { 1601 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1602 u8 comp_codes_10g = 0; 1603 u8 comp_codes_1g = 0; 1604 1605 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1606 1607 hw->phy.ops.identify_sfp(hw); 1608 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1609 return physical_layer; 1610 1611 switch (hw->phy.type) { 1612 case ixgbe_phy_sfp_passive_tyco: 1613 case ixgbe_phy_sfp_passive_unknown: 1614 case ixgbe_phy_qsfp_passive_unknown: 1615 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1616 break; 1617 case ixgbe_phy_sfp_ftl_active: 1618 case ixgbe_phy_sfp_active_unknown: 1619 case ixgbe_phy_qsfp_active_unknown: 1620 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1621 break; 1622 case ixgbe_phy_sfp_avago: 1623 case ixgbe_phy_sfp_ftl: 1624 case ixgbe_phy_sfp_intel: 1625 case ixgbe_phy_sfp_unknown: 1626 hw->phy.ops.read_i2c_eeprom(hw, 1627 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1628 hw->phy.ops.read_i2c_eeprom(hw, 1629 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1630 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1631 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1632 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1633 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1634 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1635 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1636 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1637 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1638 break; 1639 case ixgbe_phy_qsfp_intel: 1640 case ixgbe_phy_qsfp_unknown: 1641 hw->phy.ops.read_i2c_eeprom(hw, 1642 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1643 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1644 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1645 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1646 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1647 break; 1648 default: 1649 break; 1650 } 1651 1652 return physical_layer; 1653 } 1654 1655 /** 1656 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1657 * @hw: pointer to hardware structure 1658 * 1659 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1660 **/ 1661 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1662 { 1663 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1664 u32 vendor_oui = 0; 1665 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1666 u8 identifier = 0; 1667 u8 comp_codes_1g = 0; 1668 u8 comp_codes_10g = 0; 1669 u8 oui_bytes[3] = {0, 0, 0}; 1670 u16 enforce_sfp = 0; 1671 u8 connector = 0; 1672 u8 cable_length = 0; 1673 u8 device_tech = 0; 1674 bool active_cable = FALSE; 1675 1676 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1677 1678 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1679 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1680 status = IXGBE_ERR_SFP_NOT_PRESENT; 1681 goto out; 1682 } 1683 1684 /* LAN ID is needed for I2C access */ 1685 hw->mac.ops.set_lan_id(hw); 1686 1687 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1688 &identifier); 1689 1690 if (status != IXGBE_SUCCESS) 1691 goto err_read_i2c_eeprom; 1692 1693 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1694 hw->phy.type = ixgbe_phy_sfp_unsupported; 1695 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1696 goto out; 1697 } 1698 1699 hw->phy.id = identifier; 1700 1701 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1702 &comp_codes_10g); 1703 1704 if (status != IXGBE_SUCCESS) 1705 goto err_read_i2c_eeprom; 1706 1707 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1708 &comp_codes_1g); 1709 1710 if (status != IXGBE_SUCCESS) 1711 goto err_read_i2c_eeprom; 1712 1713 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1714 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1715 if (hw->bus.lan_id == 0) 1716 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1717 else 1718 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1719 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1720 IXGBE_SFF_10GBASELR_CAPABLE)) { 1721 if (hw->bus.lan_id == 0) 1722 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1723 else 1724 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1725 } else { 1726 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1727 active_cable = TRUE; 1728 1729 if (!active_cable) { 1730 /* check for active DA cables that pre-date 1731 * SFF-8436 v3.6 */ 1732 hw->phy.ops.read_i2c_eeprom(hw, 1733 IXGBE_SFF_QSFP_CONNECTOR, 1734 &connector); 1735 1736 hw->phy.ops.read_i2c_eeprom(hw, 1737 IXGBE_SFF_QSFP_CABLE_LENGTH, 1738 &cable_length); 1739 1740 hw->phy.ops.read_i2c_eeprom(hw, 1741 IXGBE_SFF_QSFP_DEVICE_TECH, 1742 &device_tech); 1743 1744 if ((connector == 1745 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1746 (cable_length > 0) && 1747 ((device_tech >> 4) == 1748 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1749 active_cable = TRUE; 1750 } 1751 1752 if (active_cable) { 1753 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1754 if (hw->bus.lan_id == 0) 1755 hw->phy.sfp_type = 1756 ixgbe_sfp_type_da_act_lmt_core0; 1757 else 1758 hw->phy.sfp_type = 1759 ixgbe_sfp_type_da_act_lmt_core1; 1760 } else { 1761 /* unsupported module type */ 1762 hw->phy.type = ixgbe_phy_sfp_unsupported; 1763 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1764 goto out; 1765 } 1766 } 1767 1768 if (hw->phy.sfp_type != stored_sfp_type) 1769 hw->phy.sfp_setup_needed = TRUE; 1770 1771 /* Determine if the QSFP+ PHY is dual speed or not. */ 1772 hw->phy.multispeed_fiber = FALSE; 1773 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1774 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1775 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1776 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1777 hw->phy.multispeed_fiber = TRUE; 1778 1779 /* Determine PHY vendor for optical modules */ 1780 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1781 IXGBE_SFF_10GBASELR_CAPABLE)) { 1782 status = hw->phy.ops.read_i2c_eeprom(hw, 1783 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1784 &oui_bytes[0]); 1785 1786 if (status != IXGBE_SUCCESS) 1787 goto err_read_i2c_eeprom; 1788 1789 status = hw->phy.ops.read_i2c_eeprom(hw, 1790 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1791 &oui_bytes[1]); 1792 1793 if (status != IXGBE_SUCCESS) 1794 goto err_read_i2c_eeprom; 1795 1796 status = hw->phy.ops.read_i2c_eeprom(hw, 1797 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1798 &oui_bytes[2]); 1799 1800 if (status != IXGBE_SUCCESS) 1801 goto err_read_i2c_eeprom; 1802 1803 vendor_oui = 1804 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1805 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1806 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1807 1808 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1809 hw->phy.type = ixgbe_phy_qsfp_intel; 1810 else 1811 hw->phy.type = ixgbe_phy_qsfp_unknown; 1812 1813 ixgbe_get_device_caps(hw, &enforce_sfp); 1814 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1815 /* Make sure we're a supported PHY type */ 1816 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1817 status = IXGBE_SUCCESS; 1818 } else { 1819 if (hw->allow_unsupported_sfp == TRUE) { 1820 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1821 status = IXGBE_SUCCESS; 1822 } else { 1823 DEBUGOUT("QSFP module not supported\n"); 1824 hw->phy.type = 1825 ixgbe_phy_sfp_unsupported; 1826 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1827 } 1828 } 1829 } else { 1830 status = IXGBE_SUCCESS; 1831 } 1832 } 1833 1834 out: 1835 return status; 1836 1837 err_read_i2c_eeprom: 1838 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1839 hw->phy.id = 0; 1840 hw->phy.type = ixgbe_phy_unknown; 1841 1842 return IXGBE_ERR_SFP_NOT_PRESENT; 1843 } 1844 1845 /** 1846 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1847 * @hw: pointer to hardware structure 1848 * @list_offset: offset to the SFP ID list 1849 * @data_offset: offset to the SFP data block 1850 * 1851 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1852 * so it returns the offsets to the phy init sequence block. 1853 **/ 1854 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1855 u16 *list_offset, 1856 u16 *data_offset) 1857 { 1858 u16 sfp_id; 1859 u16 sfp_type = hw->phy.sfp_type; 1860 1861 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1862 1863 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1864 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1865 1866 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1867 return IXGBE_ERR_SFP_NOT_PRESENT; 1868 1869 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1870 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1871 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1872 1873 /* 1874 * Limiting active cables and 1G Phys must be initialized as 1875 * SR modules 1876 */ 1877 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1878 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1879 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1880 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1881 sfp_type = ixgbe_sfp_type_srlr_core0; 1882 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1883 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1884 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1885 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1886 sfp_type = ixgbe_sfp_type_srlr_core1; 1887 1888 /* Read offset to PHY init contents */ 1889 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1890 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1891 "eeprom read at offset %d failed", 1892 IXGBE_PHY_INIT_OFFSET_NL); 1893 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1894 } 1895 1896 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1897 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1898 1899 /* Shift offset to first ID word */ 1900 (*list_offset)++; 1901 1902 /* 1903 * Find the matching SFP ID in the EEPROM 1904 * and program the init sequence 1905 */ 1906 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1907 goto err_phy; 1908 1909 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1910 if (sfp_id == sfp_type) { 1911 (*list_offset)++; 1912 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1913 goto err_phy; 1914 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1915 DEBUGOUT("SFP+ module not supported\n"); 1916 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1917 } else { 1918 break; 1919 } 1920 } else { 1921 (*list_offset) += 2; 1922 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1923 goto err_phy; 1924 } 1925 } 1926 1927 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1928 DEBUGOUT("No matching SFP+ module found\n"); 1929 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1930 } 1931 1932 return IXGBE_SUCCESS; 1933 1934 err_phy: 1935 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1936 "eeprom read at offset %d failed", *list_offset); 1937 return IXGBE_ERR_PHY; 1938 } 1939 1940 /** 1941 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1942 * @hw: pointer to hardware structure 1943 * @byte_offset: EEPROM byte offset to read 1944 * @eeprom_data: value read 1945 * 1946 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1947 **/ 1948 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1949 u8 *eeprom_data) 1950 { 1951 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1952 1953 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1954 IXGBE_I2C_EEPROM_DEV_ADDR, 1955 eeprom_data); 1956 } 1957 1958 /** 1959 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1960 * @hw: pointer to hardware structure 1961 * @byte_offset: byte offset at address 0xA2 1962 * @eeprom_data: value read 1963 * 1964 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1965 **/ 1966 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1967 u8 *sff8472_data) 1968 { 1969 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1970 IXGBE_I2C_EEPROM_DEV_ADDR2, 1971 sff8472_data); 1972 } 1973 1974 /** 1975 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1976 * @hw: pointer to hardware structure 1977 * @byte_offset: EEPROM byte offset to write 1978 * @eeprom_data: value to write 1979 * 1980 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1981 **/ 1982 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1983 u8 eeprom_data) 1984 { 1985 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1986 1987 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1988 IXGBE_I2C_EEPROM_DEV_ADDR, 1989 eeprom_data); 1990 } 1991 1992 /** 1993 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1994 * @hw: pointer to hardware structure 1995 * @offset: eeprom offset to be read 1996 * @addr: I2C address to be read 1997 */ 1998 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1999 { 2000 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2001 offset == IXGBE_SFF_IDENTIFIER && 2002 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2003 return TRUE; 2004 return FALSE; 2005 } 2006 2007 /** 2008 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2009 * @hw: pointer to hardware structure 2010 * @byte_offset: byte offset to read 2011 * @data: value read 2012 * @lock: TRUE if to take and release semaphore 2013 * 2014 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2015 * a specified device address. 2016 **/ 2017 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2018 u8 dev_addr, u8 *data, bool lock) 2019 { 2020 s32 status; 2021 u32 max_retry = 10; 2022 u32 retry = 0; 2023 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2024 bool nack = 1; 2025 *data = 0; 2026 2027 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2028 2029 if (hw->mac.type >= ixgbe_mac_X550) 2030 max_retry = 3; 2031 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2032 max_retry = IXGBE_SFP_DETECT_RETRIES; 2033 2034 do { 2035 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2036 return IXGBE_ERR_SWFW_SYNC; 2037 2038 ixgbe_i2c_start(hw); 2039 2040 /* Device Address and write indication */ 2041 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2042 if (status != IXGBE_SUCCESS) 2043 goto fail; 2044 2045 status = ixgbe_get_i2c_ack(hw); 2046 if (status != IXGBE_SUCCESS) 2047 goto fail; 2048 2049 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2050 if (status != IXGBE_SUCCESS) 2051 goto fail; 2052 2053 status = ixgbe_get_i2c_ack(hw); 2054 if (status != IXGBE_SUCCESS) 2055 goto fail; 2056 2057 ixgbe_i2c_start(hw); 2058 2059 /* Device Address and read indication */ 2060 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2061 if (status != IXGBE_SUCCESS) 2062 goto fail; 2063 2064 status = ixgbe_get_i2c_ack(hw); 2065 if (status != IXGBE_SUCCESS) 2066 goto fail; 2067 2068 status = ixgbe_clock_in_i2c_byte(hw, data); 2069 if (status != IXGBE_SUCCESS) 2070 goto fail; 2071 2072 status = ixgbe_clock_out_i2c_bit(hw, nack); 2073 if (status != IXGBE_SUCCESS) 2074 goto fail; 2075 2076 ixgbe_i2c_stop(hw); 2077 if (lock) 2078 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2079 return IXGBE_SUCCESS; 2080 2081 fail: 2082 ixgbe_i2c_bus_clear(hw); 2083 if (lock) { 2084 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2085 msec_delay(100); 2086 } 2087 retry++; 2088 if (retry < max_retry) 2089 DEBUGOUT("I2C byte read error - Retrying.\n"); 2090 else 2091 DEBUGOUT("I2C byte read error.\n"); 2092 2093 } while (retry < max_retry); 2094 2095 return status; 2096 } 2097 2098 /** 2099 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2100 * @hw: pointer to hardware structure 2101 * @byte_offset: byte offset to read 2102 * @data: value read 2103 * 2104 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2105 * a specified device address. 2106 **/ 2107 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2108 u8 dev_addr, u8 *data) 2109 { 2110 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2111 data, TRUE); 2112 } 2113 2114 /** 2115 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2116 * @hw: pointer to hardware structure 2117 * @byte_offset: byte offset to read 2118 * @data: value read 2119 * 2120 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2121 * a specified device address. 2122 **/ 2123 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2124 u8 dev_addr, u8 *data) 2125 { 2126 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2127 data, FALSE); 2128 } 2129 2130 /** 2131 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2132 * @hw: pointer to hardware structure 2133 * @byte_offset: byte offset to write 2134 * @data: value to write 2135 * @lock: TRUE if to take and release semaphore 2136 * 2137 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2138 * a specified device address. 2139 **/ 2140 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2141 u8 dev_addr, u8 data, bool lock) 2142 { 2143 s32 status; 2144 u32 max_retry = 2; 2145 u32 retry = 0; 2146 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2147 2148 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2149 2150 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2151 IXGBE_SUCCESS) 2152 return IXGBE_ERR_SWFW_SYNC; 2153 2154 do { 2155 ixgbe_i2c_start(hw); 2156 2157 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2158 if (status != IXGBE_SUCCESS) 2159 goto fail; 2160 2161 status = ixgbe_get_i2c_ack(hw); 2162 if (status != IXGBE_SUCCESS) 2163 goto fail; 2164 2165 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2166 if (status != IXGBE_SUCCESS) 2167 goto fail; 2168 2169 status = ixgbe_get_i2c_ack(hw); 2170 if (status != IXGBE_SUCCESS) 2171 goto fail; 2172 2173 status = ixgbe_clock_out_i2c_byte(hw, data); 2174 if (status != IXGBE_SUCCESS) 2175 goto fail; 2176 2177 status = ixgbe_get_i2c_ack(hw); 2178 if (status != IXGBE_SUCCESS) 2179 goto fail; 2180 2181 ixgbe_i2c_stop(hw); 2182 if (lock) 2183 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2184 return IXGBE_SUCCESS; 2185 2186 fail: 2187 ixgbe_i2c_bus_clear(hw); 2188 retry++; 2189 if (retry < max_retry) 2190 DEBUGOUT("I2C byte write error - Retrying.\n"); 2191 else 2192 DEBUGOUT("I2C byte write error.\n"); 2193 } while (retry < max_retry); 2194 2195 if (lock) 2196 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2197 2198 return status; 2199 } 2200 2201 /** 2202 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2203 * @hw: pointer to hardware structure 2204 * @byte_offset: byte offset to write 2205 * @data: value to write 2206 * 2207 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2208 * a specified device address. 2209 **/ 2210 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2211 u8 dev_addr, u8 data) 2212 { 2213 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2214 data, TRUE); 2215 } 2216 2217 /** 2218 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2219 * @hw: pointer to hardware structure 2220 * @byte_offset: byte offset to write 2221 * @data: value to write 2222 * 2223 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2224 * a specified device address. 2225 **/ 2226 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2227 u8 dev_addr, u8 data) 2228 { 2229 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2230 data, FALSE); 2231 } 2232 2233 /** 2234 * ixgbe_i2c_start - Sets I2C start condition 2235 * @hw: pointer to hardware structure 2236 * 2237 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2238 * Set bit-bang mode on X550 hardware. 2239 **/ 2240 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2241 { 2242 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2243 2244 DEBUGFUNC("ixgbe_i2c_start"); 2245 2246 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2247 2248 /* Start condition must begin with data and clock high */ 2249 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2250 ixgbe_raise_i2c_clk(hw, &i2cctl); 2251 2252 /* Setup time for start condition (4.7us) */ 2253 usec_delay(IXGBE_I2C_T_SU_STA); 2254 2255 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2256 2257 /* Hold time for start condition (4us) */ 2258 usec_delay(IXGBE_I2C_T_HD_STA); 2259 2260 ixgbe_lower_i2c_clk(hw, &i2cctl); 2261 2262 /* Minimum low period of clock is 4.7 us */ 2263 usec_delay(IXGBE_I2C_T_LOW); 2264 2265 } 2266 2267 /** 2268 * ixgbe_i2c_stop - Sets I2C stop condition 2269 * @hw: pointer to hardware structure 2270 * 2271 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2272 * Disables bit-bang mode and negates data output enable on X550 2273 * hardware. 2274 **/ 2275 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2276 { 2277 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2278 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2279 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2280 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2281 2282 DEBUGFUNC("ixgbe_i2c_stop"); 2283 2284 /* Stop condition must begin with data low and clock high */ 2285 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2286 ixgbe_raise_i2c_clk(hw, &i2cctl); 2287 2288 /* Setup time for stop condition (4us) */ 2289 usec_delay(IXGBE_I2C_T_SU_STO); 2290 2291 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2292 2293 /* bus free time between stop and start (4.7us)*/ 2294 usec_delay(IXGBE_I2C_T_BUF); 2295 2296 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2297 i2cctl &= ~bb_en_bit; 2298 i2cctl |= data_oe_bit | clk_oe_bit; 2299 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2300 IXGBE_WRITE_FLUSH(hw); 2301 } 2302 } 2303 2304 /** 2305 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2306 * @hw: pointer to hardware structure 2307 * @data: data byte to clock in 2308 * 2309 * Clocks in one byte data via I2C data/clock 2310 **/ 2311 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2312 { 2313 s32 i; 2314 bool bit = 0; 2315 2316 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2317 2318 *data = 0; 2319 for (i = 7; i >= 0; i--) { 2320 ixgbe_clock_in_i2c_bit(hw, &bit); 2321 *data |= bit << i; 2322 } 2323 2324 return IXGBE_SUCCESS; 2325 } 2326 2327 /** 2328 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2329 * @hw: pointer to hardware structure 2330 * @data: data byte clocked out 2331 * 2332 * Clocks out one byte data via I2C data/clock 2333 **/ 2334 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2335 { 2336 s32 status = IXGBE_SUCCESS; 2337 s32 i; 2338 u32 i2cctl; 2339 bool bit; 2340 2341 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2342 2343 for (i = 7; i >= 0; i--) { 2344 bit = (data >> i) & 0x1; 2345 status = ixgbe_clock_out_i2c_bit(hw, bit); 2346 2347 if (status != IXGBE_SUCCESS) 2348 break; 2349 } 2350 2351 /* Release SDA line (set high) */ 2352 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2353 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2354 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2355 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2356 IXGBE_WRITE_FLUSH(hw); 2357 2358 return status; 2359 } 2360 2361 /** 2362 * ixgbe_get_i2c_ack - Polls for I2C ACK 2363 * @hw: pointer to hardware structure 2364 * 2365 * Clocks in/out one bit via I2C data/clock 2366 **/ 2367 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2368 { 2369 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2370 s32 status = IXGBE_SUCCESS; 2371 u32 i = 0; 2372 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2373 u32 timeout = 10; 2374 bool ack = 1; 2375 2376 DEBUGFUNC("ixgbe_get_i2c_ack"); 2377 2378 if (data_oe_bit) { 2379 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2380 i2cctl |= data_oe_bit; 2381 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2382 IXGBE_WRITE_FLUSH(hw); 2383 } 2384 ixgbe_raise_i2c_clk(hw, &i2cctl); 2385 2386 /* Minimum high period of clock is 4us */ 2387 usec_delay(IXGBE_I2C_T_HIGH); 2388 2389 /* Poll for ACK. Note that ACK in I2C spec is 2390 * transition from 1 to 0 */ 2391 for (i = 0; i < timeout; i++) { 2392 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2393 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2394 2395 usec_delay(1); 2396 if (!ack) 2397 break; 2398 } 2399 2400 if (ack) { 2401 DEBUGOUT("I2C ack was not received.\n"); 2402 status = IXGBE_ERR_I2C; 2403 } 2404 2405 ixgbe_lower_i2c_clk(hw, &i2cctl); 2406 2407 /* Minimum low period of clock is 4.7 us */ 2408 usec_delay(IXGBE_I2C_T_LOW); 2409 2410 return status; 2411 } 2412 2413 /** 2414 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2415 * @hw: pointer to hardware structure 2416 * @data: read data value 2417 * 2418 * Clocks in one bit via I2C data/clock 2419 **/ 2420 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2421 { 2422 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2423 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2424 2425 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2426 2427 if (data_oe_bit) { 2428 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2429 i2cctl |= data_oe_bit; 2430 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2431 IXGBE_WRITE_FLUSH(hw); 2432 } 2433 ixgbe_raise_i2c_clk(hw, &i2cctl); 2434 2435 /* Minimum high period of clock is 4us */ 2436 usec_delay(IXGBE_I2C_T_HIGH); 2437 2438 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2439 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2440 2441 ixgbe_lower_i2c_clk(hw, &i2cctl); 2442 2443 /* Minimum low period of clock is 4.7 us */ 2444 usec_delay(IXGBE_I2C_T_LOW); 2445 2446 return IXGBE_SUCCESS; 2447 } 2448 2449 /** 2450 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2451 * @hw: pointer to hardware structure 2452 * @data: data value to write 2453 * 2454 * Clocks out one bit via I2C data/clock 2455 **/ 2456 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2457 { 2458 s32 status; 2459 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2460 2461 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2462 2463 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2464 if (status == IXGBE_SUCCESS) { 2465 ixgbe_raise_i2c_clk(hw, &i2cctl); 2466 2467 /* Minimum high period of clock is 4us */ 2468 usec_delay(IXGBE_I2C_T_HIGH); 2469 2470 ixgbe_lower_i2c_clk(hw, &i2cctl); 2471 2472 /* Minimum low period of clock is 4.7 us. 2473 * This also takes care of the data hold time. 2474 */ 2475 usec_delay(IXGBE_I2C_T_LOW); 2476 } else { 2477 status = IXGBE_ERR_I2C; 2478 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2479 "I2C data was not set to %X\n", data); 2480 } 2481 2482 return status; 2483 } 2484 2485 /** 2486 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2487 * @hw: pointer to hardware structure 2488 * @i2cctl: Current value of I2CCTL register 2489 * 2490 * Raises the I2C clock line '0'->'1' 2491 * Negates the I2C clock output enable on X550 hardware. 2492 **/ 2493 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2494 { 2495 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2496 u32 i = 0; 2497 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2498 u32 i2cctl_r = 0; 2499 2500 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2501 2502 if (clk_oe_bit) { 2503 *i2cctl |= clk_oe_bit; 2504 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2505 } 2506 2507 for (i = 0; i < timeout; i++) { 2508 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2509 2510 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2511 IXGBE_WRITE_FLUSH(hw); 2512 /* SCL rise time (1000ns) */ 2513 usec_delay(IXGBE_I2C_T_RISE); 2514 2515 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2516 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2517 break; 2518 } 2519 } 2520 2521 /** 2522 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2523 * @hw: pointer to hardware structure 2524 * @i2cctl: Current value of I2CCTL register 2525 * 2526 * Lowers the I2C clock line '1'->'0' 2527 * Asserts the I2C clock output enable on X550 hardware. 2528 **/ 2529 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2530 { 2531 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2532 2533 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2534 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2535 2536 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2537 IXGBE_WRITE_FLUSH(hw); 2538 2539 /* SCL fall time (300ns) */ 2540 usec_delay(IXGBE_I2C_T_FALL); 2541 } 2542 2543 /** 2544 * ixgbe_set_i2c_data - Sets the I2C data bit 2545 * @hw: pointer to hardware structure 2546 * @i2cctl: Current value of I2CCTL register 2547 * @data: I2C data value (0 or 1) to set 2548 * 2549 * Sets the I2C data bit 2550 * Asserts the I2C data output enable on X550 hardware. 2551 **/ 2552 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2553 { 2554 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2555 s32 status = IXGBE_SUCCESS; 2556 2557 DEBUGFUNC("ixgbe_set_i2c_data"); 2558 2559 if (data) 2560 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2561 else 2562 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2563 *i2cctl &= ~data_oe_bit; 2564 2565 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2566 IXGBE_WRITE_FLUSH(hw); 2567 2568 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2569 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2570 2571 if (!data) /* Can't verify data in this case */ 2572 return IXGBE_SUCCESS; 2573 if (data_oe_bit) { 2574 *i2cctl |= data_oe_bit; 2575 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2576 IXGBE_WRITE_FLUSH(hw); 2577 } 2578 2579 /* Verify data was set correctly */ 2580 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2581 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2582 status = IXGBE_ERR_I2C; 2583 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2584 "Error - I2C data was not set to %X.\n", 2585 data); 2586 } 2587 2588 return status; 2589 } 2590 2591 /** 2592 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2593 * @hw: pointer to hardware structure 2594 * @i2cctl: Current value of I2CCTL register 2595 * 2596 * Returns the I2C data bit value 2597 * Negates the I2C data output enable on X550 hardware. 2598 **/ 2599 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2600 { 2601 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2602 bool data; 2603 2604 DEBUGFUNC("ixgbe_get_i2c_data"); 2605 2606 if (data_oe_bit) { 2607 *i2cctl |= data_oe_bit; 2608 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2609 IXGBE_WRITE_FLUSH(hw); 2610 usec_delay(IXGBE_I2C_T_FALL); 2611 } 2612 2613 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2614 data = 1; 2615 else 2616 data = 0; 2617 2618 return data; 2619 } 2620 2621 /** 2622 * ixgbe_i2c_bus_clear - Clears the I2C bus 2623 * @hw: pointer to hardware structure 2624 * 2625 * Clears the I2C bus by sending nine clock pulses. 2626 * Used when data line is stuck low. 2627 **/ 2628 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2629 { 2630 u32 i2cctl; 2631 u32 i; 2632 2633 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2634 2635 ixgbe_i2c_start(hw); 2636 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2637 2638 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2639 2640 for (i = 0; i < 9; i++) { 2641 ixgbe_raise_i2c_clk(hw, &i2cctl); 2642 2643 /* Min high period of clock is 4us */ 2644 usec_delay(IXGBE_I2C_T_HIGH); 2645 2646 ixgbe_lower_i2c_clk(hw, &i2cctl); 2647 2648 /* Min low period of clock is 4.7us*/ 2649 usec_delay(IXGBE_I2C_T_LOW); 2650 } 2651 2652 ixgbe_i2c_start(hw); 2653 2654 /* Put the i2c bus back to default state */ 2655 ixgbe_i2c_stop(hw); 2656 } 2657 2658 /** 2659 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2660 * @hw: pointer to hardware structure 2661 * 2662 * Checks if the LASI temp alarm status was triggered due to overtemp 2663 **/ 2664 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2665 { 2666 s32 status = IXGBE_SUCCESS; 2667 u16 phy_data = 0; 2668 2669 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2670 2671 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2672 goto out; 2673 2674 /* Check that the LASI temp alarm status was triggered */ 2675 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2676 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2677 2678 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2679 goto out; 2680 2681 status = IXGBE_ERR_OVERTEMP; 2682 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2683 out: 2684 return status; 2685 } 2686 2687 /** 2688 * ixgbe_set_copper_phy_power - Control power for copper phy 2689 * @hw: pointer to hardware structure 2690 * @on: TRUE for on, FALSE for off 2691 */ 2692 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2693 { 2694 u32 status; 2695 u16 reg; 2696 2697 if (!on && ixgbe_mng_present(hw)) 2698 return 0; 2699 2700 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2701 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2702 ®); 2703 if (status) 2704 return status; 2705 2706 if (on) { 2707 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2708 } else { 2709 if (ixgbe_check_reset_blocked(hw)) 2710 return 0; 2711 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2712 } 2713 2714 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2715 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2716 reg); 2717 return status; 2718 } 2719
Indexes created Sun Oct 19 02:09:48 GMT 2025