ixgbe_phy.c revision 1.17
1 /* $NetBSD: ixgbe_phy.c,v 1.17 2018/04/04 08:59:22 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 42 #include <dev/mii/mdio.h> 43 44 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 45 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 46 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 47 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 48 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 49 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 50 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 51 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 52 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 53 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 54 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 55 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 56 u8 *sff8472_data); 57 58 /** 59 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 60 * @hw: pointer to the hardware structure 61 * @byte: byte to send 62 * 63 * Returns an error code on error. 64 */ 65 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 66 { 67 s32 status; 68 69 status = ixgbe_clock_out_i2c_byte(hw, byte); 70 if (status) 71 return status; 72 return ixgbe_get_i2c_ack(hw); 73 } 74 75 /** 76 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 77 * @hw: pointer to the hardware structure 78 * @byte: pointer to a u8 to receive the byte 79 * 80 * Returns an error code on error. 81 */ 82 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 83 { 84 s32 status; 85 86 status = ixgbe_clock_in_i2c_byte(hw, byte); 87 if (status) 88 return status; 89 /* ACK */ 90 return ixgbe_clock_out_i2c_bit(hw, FALSE); 91 } 92 93 /** 94 * ixgbe_ones_comp_byte_add - Perform one's complement addition 95 * @add1: addend 1 96 * @add2: addend 2 97 * 98 * Returns one's complement 8-bit sum. 99 */ 100 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 101 { 102 u16 sum = add1 + add2; 103 104 sum = (sum & 0xFF) + (sum >> 8); 105 return sum & 0xFF; 106 } 107 108 /** 109 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 110 * @hw: pointer to the hardware structure 111 * @addr: I2C bus address to read from 112 * @reg: I2C device register to read from 113 * @val: pointer to location to receive read value 114 * @lock: TRUE if to take and release semaphore 115 * 116 * Returns an error code on error. 117 */ 118 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 119 u16 *val, bool lock) 120 { 121 u32 swfw_mask = hw->phy.phy_semaphore_mask; 122 int max_retry = 3; 123 int retry = 0; 124 u8 csum_byte; 125 u8 high_bits; 126 u8 low_bits; 127 u8 reg_high; 128 u8 csum; 129 130 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 131 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 132 csum = ~csum; 133 do { 134 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 135 return IXGBE_ERR_SWFW_SYNC; 136 ixgbe_i2c_start(hw); 137 /* Device Address and write indication */ 138 if (ixgbe_out_i2c_byte_ack(hw, addr)) 139 goto fail; 140 /* Write bits 14:8 */ 141 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 142 goto fail; 143 /* Write bits 7:0 */ 144 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 145 goto fail; 146 /* Write csum */ 147 if (ixgbe_out_i2c_byte_ack(hw, csum)) 148 goto fail; 149 /* Re-start condition */ 150 ixgbe_i2c_start(hw); 151 /* Device Address and read indication */ 152 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 153 goto fail; 154 /* Get upper bits */ 155 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 156 goto fail; 157 /* Get low bits */ 158 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 159 goto fail; 160 /* Get csum */ 161 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 162 goto fail; 163 /* NACK */ 164 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 165 goto fail; 166 ixgbe_i2c_stop(hw); 167 if (lock) 168 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 169 *val = (high_bits << 8) | low_bits; 170 return 0; 171 172 fail: 173 ixgbe_i2c_bus_clear(hw); 174 if (lock) 175 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 176 retry++; 177 if (retry < max_retry) 178 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 179 else 180 DEBUGOUT("I2C byte read combined error.\n"); 181 } while (retry < max_retry); 182 183 return IXGBE_ERR_I2C; 184 } 185 186 /** 187 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 188 * @hw: pointer to the hardware structure 189 * @addr: I2C bus address to write to 190 * @reg: I2C device register to write to 191 * @val: value to write 192 * @lock: TRUE if to take and release semaphore 193 * 194 * Returns an error code on error. 195 */ 196 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 197 u16 val, bool lock) 198 { 199 u32 swfw_mask = hw->phy.phy_semaphore_mask; 200 int max_retry = 1; 201 int retry = 0; 202 u8 reg_high; 203 u8 csum; 204 205 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 206 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 207 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 208 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 209 csum = ~csum; 210 do { 211 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 212 return IXGBE_ERR_SWFW_SYNC; 213 ixgbe_i2c_start(hw); 214 /* Device Address and write indication */ 215 if (ixgbe_out_i2c_byte_ack(hw, addr)) 216 goto fail; 217 /* Write bits 14:8 */ 218 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 219 goto fail; 220 /* Write bits 7:0 */ 221 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 222 goto fail; 223 /* Write data 15:8 */ 224 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 225 goto fail; 226 /* Write data 7:0 */ 227 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 228 goto fail; 229 /* Write csum */ 230 if (ixgbe_out_i2c_byte_ack(hw, csum)) 231 goto fail; 232 ixgbe_i2c_stop(hw); 233 if (lock) 234 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 235 return 0; 236 237 fail: 238 ixgbe_i2c_bus_clear(hw); 239 if (lock) 240 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 241 retry++; 242 if (retry < max_retry) 243 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 244 else 245 DEBUGOUT("I2C byte write combined error.\n"); 246 } while (retry < max_retry); 247 248 return IXGBE_ERR_I2C; 249 } 250 251 /** 252 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 253 * @hw: pointer to the hardware structure 254 * 255 * Initialize the function pointers. 256 **/ 257 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 258 { 259 struct ixgbe_phy_info *phy = &hw->phy; 260 261 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 262 263 /* PHY */ 264 phy->ops.identify = ixgbe_identify_phy_generic; 265 phy->ops.reset = ixgbe_reset_phy_generic; 266 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 267 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 268 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 269 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 270 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 271 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 272 phy->ops.check_link = NULL; 273 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 274 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 275 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 276 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 277 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 278 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 279 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 280 phy->ops.identify_sfp = ixgbe_identify_module_generic; 281 phy->sfp_type = ixgbe_sfp_type_unknown; 282 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 283 phy->ops.write_i2c_byte_unlocked = 284 ixgbe_write_i2c_byte_generic_unlocked; 285 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 286 return IXGBE_SUCCESS; 287 } 288 289 /** 290 * ixgbe_probe_phy - Probe a single address for a PHY 291 * @hw: pointer to hardware structure 292 * @phy_addr: PHY address to probe 293 * 294 * Returns TRUE if PHY found 295 */ 296 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 297 { 298 u16 ext_ability = 0; 299 300 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 301 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 302 phy_addr); 303 return FALSE; 304 } 305 306 if (ixgbe_get_phy_id(hw)) 307 return FALSE; 308 309 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 310 311 if (hw->phy.type == ixgbe_phy_unknown) { 312 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 313 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 314 if (ext_ability & 315 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 316 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 317 hw->phy.type = ixgbe_phy_cu_unknown; 318 else 319 hw->phy.type = ixgbe_phy_generic; 320 } 321 322 return TRUE; 323 } 324 325 /** 326 * ixgbe_identify_phy_generic - Get physical layer module 327 * @hw: pointer to hardware structure 328 * 329 * Determines the physical layer module found on the current adapter. 330 **/ 331 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 332 { 333 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 334 u16 phy_addr; 335 336 DEBUGFUNC("ixgbe_identify_phy_generic"); 337 338 if (!hw->phy.phy_semaphore_mask) { 339 if (hw->bus.lan_id) 340 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 341 else 342 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 343 } 344 345 if (hw->phy.type != ixgbe_phy_unknown) 346 return IXGBE_SUCCESS; 347 348 if (hw->phy.nw_mng_if_sel) { 349 phy_addr = (hw->phy.nw_mng_if_sel & 350 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 351 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 352 if (ixgbe_probe_phy(hw, phy_addr)) 353 return IXGBE_SUCCESS; 354 else 355 return IXGBE_ERR_PHY_ADDR_INVALID; 356 } 357 358 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 359 if (ixgbe_probe_phy(hw, phy_addr)) { 360 status = IXGBE_SUCCESS; 361 break; 362 } 363 } 364 365 /* Certain media types do not have a phy so an address will not 366 * be found and the code will take this path. Caller has to 367 * decide if it is an error or not. 368 */ 369 if (status != IXGBE_SUCCESS) 370 hw->phy.addr = 0; 371 372 return status; 373 } 374 375 /** 376 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 377 * @hw: pointer to the hardware structure 378 * 379 * This function checks the MMNGC.MNG_VETO bit to see if there are 380 * any constraints on link from manageability. For MAC's that don't 381 * have this bit just return faluse since the link can not be blocked 382 * via this method. 383 **/ 384 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 385 { 386 u32 mmngc; 387 388 DEBUGFUNC("ixgbe_check_reset_blocked"); 389 390 /* If we don't have this bit, it can't be blocking */ 391 if (hw->mac.type == ixgbe_mac_82598EB) 392 return FALSE; 393 394 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 395 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 396 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 397 "MNG_VETO bit detected.\n"); 398 return TRUE; 399 } 400 401 return FALSE; 402 } 403 404 /** 405 * ixgbe_validate_phy_addr - Determines phy address is valid 406 * @hw: pointer to hardware structure 407 * @phy_addr: PHY address 408 * 409 **/ 410 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 411 { 412 u16 phy_id = 0; 413 bool valid = FALSE; 414 415 DEBUGFUNC("ixgbe_validate_phy_addr"); 416 417 hw->phy.addr = phy_addr; 418 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 419 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 420 421 if (phy_id != 0xFFFF && phy_id != 0x0) 422 valid = TRUE; 423 424 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 425 426 return valid; 427 } 428 429 /** 430 * ixgbe_get_phy_id - Get the phy type 431 * @hw: pointer to hardware structure 432 * 433 **/ 434 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 435 { 436 u32 status; 437 u16 phy_id_high = 0; 438 u16 phy_id_low = 0; 439 440 DEBUGFUNC("ixgbe_get_phy_id"); 441 442 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 443 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 444 &phy_id_high); 445 446 if (status == IXGBE_SUCCESS) { 447 hw->phy.id = (u32)(phy_id_high << 16); 448 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 449 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 450 &phy_id_low); 451 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 452 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 453 } 454 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 455 phy_id_high, phy_id_low); 456 457 return status; 458 } 459 460 /** 461 * ixgbe_get_phy_type_from_id - Get the phy type 462 * @phy_id: PHY ID information 463 * 464 **/ 465 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 466 { 467 enum ixgbe_phy_type phy_type; 468 469 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 470 471 switch (phy_id) { 472 case TN1010_PHY_ID: 473 phy_type = ixgbe_phy_tn; 474 break; 475 case X550_PHY_ID2: 476 case X550_PHY_ID3: 477 case X540_PHY_ID: 478 phy_type = ixgbe_phy_aq; 479 break; 480 case QT2022_PHY_ID: 481 phy_type = ixgbe_phy_qt; 482 break; 483 case ATH_PHY_ID: 484 phy_type = ixgbe_phy_nl; 485 break; 486 case X557_PHY_ID: 487 case X557_PHY_ID2: 488 phy_type = ixgbe_phy_x550em_ext_t; 489 break; 490 case IXGBE_M88E1500_E_PHY_ID: 491 case IXGBE_M88E1543_E_PHY_ID: 492 phy_type = ixgbe_phy_ext_1g_t; 493 break; 494 default: 495 phy_type = ixgbe_phy_unknown; 496 break; 497 } 498 return phy_type; 499 } 500 501 /** 502 * ixgbe_reset_phy_generic - Performs a PHY reset 503 * @hw: pointer to hardware structure 504 **/ 505 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 506 { 507 u32 i; 508 u16 ctrl = 0; 509 s32 status = IXGBE_SUCCESS; 510 511 DEBUGFUNC("ixgbe_reset_phy_generic"); 512 513 if (hw->phy.type == ixgbe_phy_unknown) 514 status = ixgbe_identify_phy_generic(hw); 515 516 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 517 goto out; 518 519 /* Don't reset PHY if it's shut down due to overtemp. */ 520 if (!hw->phy.reset_if_overtemp && 521 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 522 goto out; 523 524 /* Blocked by MNG FW so bail */ 525 if (ixgbe_check_reset_blocked(hw)) 526 goto out; 527 528 /* 529 * Perform soft PHY reset to the PHY_XS. 530 * This will cause a soft reset to the PHY 531 */ 532 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 533 IXGBE_MDIO_PHY_XS_DEV_TYPE, 534 IXGBE_MDIO_PHY_XS_RESET); 535 536 /* 537 * Poll for reset bit to self-clear indicating reset is complete. 538 * Some PHYs could take up to 3 seconds to complete and need about 539 * 1.7 usec delay after the reset is complete. 540 */ 541 for (i = 0; i < 30; i++) { 542 msec_delay(100); 543 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 544 status = hw->phy.ops.read_reg(hw, 545 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 546 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 547 &ctrl); 548 if (status != IXGBE_SUCCESS) 549 return status; 550 551 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 552 usec_delay(2); 553 break; 554 } 555 } else { 556 status = hw->phy.ops.read_reg(hw, 557 IXGBE_MDIO_PHY_XS_CONTROL, 558 IXGBE_MDIO_PHY_XS_DEV_TYPE, 559 &ctrl); 560 if (status != IXGBE_SUCCESS) 561 return status; 562 563 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 564 usec_delay(2); 565 break; 566 } 567 } 568 } 569 570 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 571 status = IXGBE_ERR_RESET_FAILED; 572 ERROR_REPORT1(IXGBE_ERROR_POLLING, 573 "PHY reset polling failed to complete.\n"); 574 } 575 576 out: 577 return status; 578 } 579 580 /** 581 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 582 * the SWFW lock 583 * @hw: pointer to hardware structure 584 * @reg_addr: 32 bit address of PHY register to read 585 * @device_type: 5 bit device type 586 * @phy_data: Pointer to read data from PHY register 587 **/ 588 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 589 u16 *phy_data) 590 { 591 u32 i, data, command; 592 593 /* Setup and write the address cycle command */ 594 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 595 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 596 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 597 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 598 599 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 600 601 /* 602 * Check every 10 usec to see if the address cycle completed. 603 * The MDI Command bit will clear when the operation is 604 * complete 605 */ 606 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 607 usec_delay(10); 608 609 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 610 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 611 break; 612 } 613 614 615 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 616 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 617 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 618 return IXGBE_ERR_PHY; 619 } 620 621 /* 622 * Address cycle complete, setup and write the read 623 * command 624 */ 625 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 626 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 627 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 628 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 629 630 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 631 632 /* 633 * Check every 10 usec to see if the address cycle 634 * completed. The MDI Command bit will clear when the 635 * operation is complete 636 */ 637 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 638 usec_delay(10); 639 640 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 641 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 642 break; 643 } 644 645 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 646 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 647 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 648 return IXGBE_ERR_PHY; 649 } 650 651 /* 652 * Read operation is complete. Get the data 653 * from MSRWD 654 */ 655 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 656 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 657 *phy_data = (u16)(data); 658 659 return IXGBE_SUCCESS; 660 } 661 662 /** 663 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 664 * using the SWFW lock - this function is needed in most cases 665 * @hw: pointer to hardware structure 666 * @reg_addr: 32 bit address of PHY register to read 667 * @device_type: 5 bit device type 668 * @phy_data: Pointer to read data from PHY register 669 **/ 670 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 671 u32 device_type, u16 *phy_data) 672 { 673 s32 status; 674 u32 gssr = hw->phy.phy_semaphore_mask; 675 676 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 677 678 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 679 return IXGBE_ERR_SWFW_SYNC; 680 681 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 682 683 hw->mac.ops.release_swfw_sync(hw, gssr); 684 685 return status; 686 } 687 688 /** 689 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 690 * without SWFW lock 691 * @hw: pointer to hardware structure 692 * @reg_addr: 32 bit PHY register to write 693 * @device_type: 5 bit device type 694 * @phy_data: Data to write to the PHY register 695 **/ 696 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 697 u32 device_type, u16 phy_data) 698 { 699 u32 i, command; 700 701 /* Put the data in the MDI single read and write data register*/ 702 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 703 704 /* Setup and write the address cycle command */ 705 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 706 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 707 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 708 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 709 710 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 711 712 /* 713 * Check every 10 usec to see if the address cycle completed. 714 * The MDI Command bit will clear when the operation is 715 * complete 716 */ 717 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 718 usec_delay(10); 719 720 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 721 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 722 break; 723 } 724 725 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 726 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 727 return IXGBE_ERR_PHY; 728 } 729 730 /* 731 * Address cycle complete, setup and write the write 732 * command 733 */ 734 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 735 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 736 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 737 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 738 739 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 740 741 /* 742 * Check every 10 usec to see if the address cycle 743 * completed. The MDI Command bit will clear when the 744 * operation is complete 745 */ 746 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 747 usec_delay(10); 748 749 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 750 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 751 break; 752 } 753 754 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 755 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 756 return IXGBE_ERR_PHY; 757 } 758 759 return IXGBE_SUCCESS; 760 } 761 762 /** 763 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 764 * using SWFW lock- this function is needed in most cases 765 * @hw: pointer to hardware structure 766 * @reg_addr: 32 bit PHY register to write 767 * @device_type: 5 bit device type 768 * @phy_data: Data to write to the PHY register 769 **/ 770 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 771 u32 device_type, u16 phy_data) 772 { 773 s32 status; 774 u32 gssr = hw->phy.phy_semaphore_mask; 775 776 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 777 778 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 779 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 780 phy_data); 781 hw->mac.ops.release_swfw_sync(hw, gssr); 782 } else { 783 status = IXGBE_ERR_SWFW_SYNC; 784 } 785 786 return status; 787 } 788 789 /** 790 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 791 * @hw: pointer to hardware structure 792 * 793 * Restart auto-negotiation and PHY and waits for completion. 794 **/ 795 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 796 { 797 s32 status = IXGBE_SUCCESS; 798 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 799 bool autoneg = FALSE; 800 ixgbe_link_speed speed; 801 802 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 803 804 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 805 806 /* Set or unset auto-negotiation 10G advertisement */ 807 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 808 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 809 &autoneg_reg); 810 811 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 812 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 813 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 814 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 815 816 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 817 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 818 autoneg_reg); 819 820 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 821 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 822 &autoneg_reg); 823 824 if (hw->mac.type == ixgbe_mac_X550) { 825 /* Set or unset auto-negotiation 5G advertisement */ 826 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 827 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 828 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 829 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 830 831 /* Set or unset auto-negotiation 2.5G advertisement */ 832 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 833 if ((hw->phy.autoneg_advertised & 834 IXGBE_LINK_SPEED_2_5GB_FULL) && 835 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 836 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 837 } 838 839 /* Set or unset auto-negotiation 1G advertisement */ 840 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 841 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 842 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 843 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 844 845 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 846 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 847 autoneg_reg); 848 849 /* Set or unset auto-negotiation 100M advertisement */ 850 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 851 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 852 &autoneg_reg); 853 854 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 855 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 856 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 857 (speed & IXGBE_LINK_SPEED_100_FULL)) 858 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 859 860 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 861 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 862 autoneg_reg); 863 864 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) { 865 u16 ctrl; 866 867 /* Force 100Mbps */ 868 hw->phy.ops.read_reg(hw, MDIO_PMAPMD_CTRL1, MDIO_MMD_PMAPMD, 869 &ctrl); 870 ctrl &= ~PMAPMD_CTRL1_SPEED_MASK; 871 ctrl |= PMAPMD_CTRL1_SPEED_100; 872 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD, 873 ctrl); 874 875 /* Don't use auto-nego for 100Mbps */ 876 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 877 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 878 879 autoneg_reg &= ~AN_CTRL1_AUTOEN; 880 881 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 882 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 883 } else { 884 /* Blocked by MNG FW so don't reset PHY */ 885 if (ixgbe_check_reset_blocked(hw)) 886 return status; 887 888 /* Restart PHY auto-negotiation. */ 889 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 890 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 891 892 autoneg_reg |= IXGBE_MII_RESTART | AN_CTRL1_AUTOEN; 893 894 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 895 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 896 } 897 898 return status; 899 } 900 901 /** 902 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 903 * @hw: pointer to hardware structure 904 * @speed: new link speed 905 * @autoneg_wait_to_complete: unused 906 **/ 907 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 908 ixgbe_link_speed speed, 909 bool autoneg_wait_to_complete) 910 { 911 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 912 913 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 914 915 /* 916 * Clear autoneg_advertised and set new values based on input link 917 * speed. 918 */ 919 hw->phy.autoneg_advertised = 0; 920 921 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 922 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 923 924 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 925 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 926 927 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 928 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 929 930 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 931 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 932 933 if (speed & IXGBE_LINK_SPEED_100_FULL) 934 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 935 936 if (speed & IXGBE_LINK_SPEED_10_FULL) 937 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 938 939 /* Setup link based on the new speed settings */ 940 ixgbe_setup_phy_link(hw); 941 942 return IXGBE_SUCCESS; 943 } 944 945 /** 946 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 947 * @hw: pointer to hardware structure 948 * 949 * Determines the supported link capabilities by reading the PHY auto 950 * negotiation register. 951 **/ 952 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 953 { 954 s32 status; 955 u16 speed_ability; 956 957 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 958 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 959 &speed_ability); 960 if (status) 961 return status; 962 963 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 964 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 965 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 966 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 967 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 968 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 969 970 switch (hw->mac.type) { 971 case ixgbe_mac_X550: 972 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 973 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 974 break; 975 case ixgbe_mac_X550EM_x: 976 case ixgbe_mac_X550EM_a: 977 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 978 break; 979 default: 980 break; 981 } 982 983 return status; 984 } 985 986 /** 987 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 988 * @hw: pointer to hardware structure 989 * @speed: pointer to link speed 990 * @autoneg: boolean auto-negotiation value 991 **/ 992 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 993 ixgbe_link_speed *speed, 994 bool *autoneg) 995 { 996 s32 status = IXGBE_SUCCESS; 997 998 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 999 1000 *autoneg = TRUE; 1001 if (!hw->phy.speeds_supported) 1002 status = ixgbe_get_copper_speeds_supported(hw); 1003 1004 *speed = hw->phy.speeds_supported; 1005 return status; 1006 } 1007 1008 /** 1009 * ixgbe_check_phy_link_tnx - Determine link and speed status 1010 * @hw: pointer to hardware structure 1011 * @speed: current link speed 1012 * @link_up: TRUE is link is up, FALSE otherwise 1013 * 1014 * Reads the VS1 register to determine if link is up and the current speed for 1015 * the PHY. 1016 **/ 1017 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1018 bool *link_up) 1019 { 1020 s32 status = IXGBE_SUCCESS; 1021 u32 time_out; 1022 u32 max_time_out = 10; 1023 u16 phy_link = 0; 1024 u16 phy_speed = 0; 1025 u16 phy_data = 0; 1026 1027 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1028 1029 /* Initialize speed and link to default case */ 1030 *link_up = FALSE; 1031 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1032 1033 /* 1034 * Check current speed and link status of the PHY register. 1035 * This is a vendor specific register and may have to 1036 * be changed for other copper PHYs. 1037 */ 1038 for (time_out = 0; time_out < max_time_out; time_out++) { 1039 usec_delay(10); 1040 status = hw->phy.ops.read_reg(hw, 1041 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1042 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1043 &phy_data); 1044 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1045 phy_speed = phy_data & 1046 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1047 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1048 *link_up = TRUE; 1049 if (phy_speed == 1050 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1051 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1052 break; 1053 } 1054 } 1055 1056 return status; 1057 } 1058 1059 /** 1060 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1061 * @hw: pointer to hardware structure 1062 * 1063 * Restart auto-negotiation and PHY and waits for completion. 1064 **/ 1065 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1066 { 1067 s32 status = IXGBE_SUCCESS; 1068 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1069 bool autoneg = FALSE; 1070 ixgbe_link_speed speed; 1071 1072 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1073 1074 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1075 1076 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1077 /* Set or unset auto-negotiation 10G advertisement */ 1078 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1079 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1080 &autoneg_reg); 1081 1082 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1083 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1084 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1085 1086 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1088 autoneg_reg); 1089 } 1090 1091 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1092 /* Set or unset auto-negotiation 1G advertisement */ 1093 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1094 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1095 &autoneg_reg); 1096 1097 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1098 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1099 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1100 1101 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1102 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1103 autoneg_reg); 1104 } 1105 1106 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1107 /* Set or unset auto-negotiation 100M advertisement */ 1108 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1109 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1110 &autoneg_reg); 1111 1112 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1113 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1114 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1115 1116 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1117 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1118 autoneg_reg); 1119 } 1120 1121 /* Blocked by MNG FW so don't reset PHY */ 1122 if (ixgbe_check_reset_blocked(hw)) 1123 return status; 1124 1125 /* Restart PHY auto-negotiation. */ 1126 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1127 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1128 1129 autoneg_reg |= IXGBE_MII_RESTART; 1130 1131 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1132 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1133 1134 return status; 1135 } 1136 1137 /** 1138 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1139 * @hw: pointer to hardware structure 1140 * @firmware_version: pointer to the PHY Firmware Version 1141 **/ 1142 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1143 u16 *firmware_version) 1144 { 1145 s32 status; 1146 1147 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1148 1149 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1150 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1151 firmware_version); 1152 1153 return status; 1154 } 1155 1156 /** 1157 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1158 * @hw: pointer to hardware structure 1159 * @firmware_version: pointer to the PHY Firmware Version 1160 **/ 1161 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1162 u16 *firmware_version) 1163 { 1164 s32 status; 1165 1166 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1167 1168 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1169 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1170 firmware_version); 1171 1172 return status; 1173 } 1174 1175 /** 1176 * ixgbe_reset_phy_nl - Performs a PHY reset 1177 * @hw: pointer to hardware structure 1178 **/ 1179 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1180 { 1181 u16 phy_offset, control, eword, edata, block_crc; 1182 bool end_data = FALSE; 1183 u16 list_offset, data_offset; 1184 u16 phy_data = 0; 1185 s32 ret_val = IXGBE_SUCCESS; 1186 u32 i; 1187 1188 DEBUGFUNC("ixgbe_reset_phy_nl"); 1189 1190 /* Blocked by MNG FW so bail */ 1191 if (ixgbe_check_reset_blocked(hw)) 1192 goto out; 1193 1194 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1195 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1196 1197 /* reset the PHY and poll for completion */ 1198 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1199 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1200 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1201 1202 for (i = 0; i < 100; i++) { 1203 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1204 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1205 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1206 break; 1207 msec_delay(10); 1208 } 1209 1210 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1211 DEBUGOUT("PHY reset did not complete.\n"); 1212 ret_val = IXGBE_ERR_PHY; 1213 goto out; 1214 } 1215 1216 /* Get init offsets */ 1217 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1218 &data_offset); 1219 if (ret_val != IXGBE_SUCCESS) 1220 goto out; 1221 1222 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1223 data_offset++; 1224 while (!end_data) { 1225 /* 1226 * Read control word from PHY init contents offset 1227 */ 1228 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1229 if (ret_val) 1230 goto err_eeprom; 1231 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1232 IXGBE_CONTROL_SHIFT_NL; 1233 edata = eword & IXGBE_DATA_MASK_NL; 1234 switch (control) { 1235 case IXGBE_DELAY_NL: 1236 data_offset++; 1237 DEBUGOUT1("DELAY: %d MS\n", edata); 1238 msec_delay(edata); 1239 break; 1240 case IXGBE_DATA_NL: 1241 DEBUGOUT("DATA:\n"); 1242 data_offset++; 1243 ret_val = hw->eeprom.ops.read(hw, data_offset, 1244 &phy_offset); 1245 if (ret_val) 1246 goto err_eeprom; 1247 data_offset++; 1248 for (i = 0; i < edata; i++) { 1249 ret_val = hw->eeprom.ops.read(hw, data_offset, 1250 &eword); 1251 if (ret_val) 1252 goto err_eeprom; 1253 hw->phy.ops.write_reg(hw, phy_offset, 1254 IXGBE_TWINAX_DEV, eword); 1255 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1256 phy_offset); 1257 data_offset++; 1258 phy_offset++; 1259 } 1260 break; 1261 case IXGBE_CONTROL_NL: 1262 data_offset++; 1263 DEBUGOUT("CONTROL:\n"); 1264 if (edata == IXGBE_CONTROL_EOL_NL) { 1265 DEBUGOUT("EOL\n"); 1266 end_data = TRUE; 1267 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1268 DEBUGOUT("SOL\n"); 1269 } else { 1270 DEBUGOUT("Bad control value\n"); 1271 ret_val = IXGBE_ERR_PHY; 1272 goto out; 1273 } 1274 break; 1275 default: 1276 DEBUGOUT("Bad control type\n"); 1277 ret_val = IXGBE_ERR_PHY; 1278 goto out; 1279 } 1280 } 1281 1282 out: 1283 return ret_val; 1284 1285 err_eeprom: 1286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1287 "eeprom read at offset %d failed", data_offset); 1288 return IXGBE_ERR_PHY; 1289 } 1290 1291 /** 1292 * ixgbe_identify_module_generic - Identifies module type 1293 * @hw: pointer to hardware structure 1294 * 1295 * Determines HW type and calls appropriate function. 1296 **/ 1297 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1298 { 1299 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1300 1301 DEBUGFUNC("ixgbe_identify_module_generic"); 1302 1303 switch (hw->mac.ops.get_media_type(hw)) { 1304 case ixgbe_media_type_fiber: 1305 status = ixgbe_identify_sfp_module_generic(hw); 1306 break; 1307 1308 case ixgbe_media_type_fiber_qsfp: 1309 status = ixgbe_identify_qsfp_module_generic(hw); 1310 break; 1311 1312 default: 1313 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1314 status = IXGBE_ERR_SFP_NOT_PRESENT; 1315 break; 1316 } 1317 1318 return status; 1319 } 1320 1321 /** 1322 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1323 * @hw: pointer to hardware structure 1324 * 1325 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1326 **/ 1327 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1328 { 1329 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1330 u32 vendor_oui = 0; 1331 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1332 u8 identifier = 0; 1333 u8 comp_codes_1g = 0; 1334 u8 comp_codes_10g = 0; 1335 u8 oui_bytes[3] = {0, 0, 0}; 1336 u8 cable_tech = 0; 1337 u8 cable_spec = 0; 1338 u16 enforce_sfp = 0; 1339 1340 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1341 1342 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1343 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1344 status = IXGBE_ERR_SFP_NOT_PRESENT; 1345 goto out; 1346 } 1347 1348 /* LAN ID is needed for I2C access */ 1349 hw->mac.ops.set_lan_id(hw); 1350 1351 status = hw->phy.ops.read_i2c_eeprom(hw, 1352 IXGBE_SFF_IDENTIFIER, 1353 &identifier); 1354 1355 if (status != IXGBE_SUCCESS) 1356 goto err_read_i2c_eeprom; 1357 1358 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1359 hw->phy.type = ixgbe_phy_sfp_unsupported; 1360 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1361 } else { 1362 status = hw->phy.ops.read_i2c_eeprom(hw, 1363 IXGBE_SFF_1GBE_COMP_CODES, 1364 &comp_codes_1g); 1365 1366 if (status != IXGBE_SUCCESS) 1367 goto err_read_i2c_eeprom; 1368 1369 status = hw->phy.ops.read_i2c_eeprom(hw, 1370 IXGBE_SFF_10GBE_COMP_CODES, 1371 &comp_codes_10g); 1372 1373 if (status != IXGBE_SUCCESS) 1374 goto err_read_i2c_eeprom; 1375 status = hw->phy.ops.read_i2c_eeprom(hw, 1376 IXGBE_SFF_CABLE_TECHNOLOGY, 1377 &cable_tech); 1378 1379 if (status != IXGBE_SUCCESS) 1380 goto err_read_i2c_eeprom; 1381 1382 /* ID Module 1383 * ========= 1384 * 0 SFP_DA_CU 1385 * 1 SFP_SR 1386 * 2 SFP_LR 1387 * 3 SFP_DA_CORE0 - 82599-specific 1388 * 4 SFP_DA_CORE1 - 82599-specific 1389 * 5 SFP_SR/LR_CORE0 - 82599-specific 1390 * 6 SFP_SR/LR_CORE1 - 82599-specific 1391 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1392 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1393 * 9 SFP_1g_cu_CORE0 - 82599-specific 1394 * 10 SFP_1g_cu_CORE1 - 82599-specific 1395 * 11 SFP_1g_sx_CORE0 - 82599-specific 1396 * 12 SFP_1g_sx_CORE1 - 82599-specific 1397 */ 1398 if (hw->mac.type == ixgbe_mac_82598EB) { 1399 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1400 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1401 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1402 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1403 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1404 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1405 else 1406 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1407 } else { 1408 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1409 if (hw->bus.lan_id == 0) 1410 hw->phy.sfp_type = 1411 ixgbe_sfp_type_da_cu_core0; 1412 else 1413 hw->phy.sfp_type = 1414 ixgbe_sfp_type_da_cu_core1; 1415 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1416 hw->phy.ops.read_i2c_eeprom( 1417 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1418 &cable_spec); 1419 if (cable_spec & 1420 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1421 if (hw->bus.lan_id == 0) 1422 hw->phy.sfp_type = 1423 ixgbe_sfp_type_da_act_lmt_core0; 1424 else 1425 hw->phy.sfp_type = 1426 ixgbe_sfp_type_da_act_lmt_core1; 1427 } else { 1428 hw->phy.sfp_type = 1429 ixgbe_sfp_type_unknown; 1430 } 1431 } else if (comp_codes_10g & 1432 (IXGBE_SFF_10GBASESR_CAPABLE | 1433 IXGBE_SFF_10GBASELR_CAPABLE)) { 1434 if (hw->bus.lan_id == 0) 1435 hw->phy.sfp_type = 1436 ixgbe_sfp_type_srlr_core0; 1437 else 1438 hw->phy.sfp_type = 1439 ixgbe_sfp_type_srlr_core1; 1440 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1441 if (hw->bus.lan_id == 0) 1442 hw->phy.sfp_type = 1443 ixgbe_sfp_type_1g_cu_core0; 1444 else 1445 hw->phy.sfp_type = 1446 ixgbe_sfp_type_1g_cu_core1; 1447 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1448 if (hw->bus.lan_id == 0) 1449 hw->phy.sfp_type = 1450 ixgbe_sfp_type_1g_sx_core0; 1451 else 1452 hw->phy.sfp_type = 1453 ixgbe_sfp_type_1g_sx_core1; 1454 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1455 if (hw->bus.lan_id == 0) 1456 hw->phy.sfp_type = 1457 ixgbe_sfp_type_1g_lx_core0; 1458 else 1459 hw->phy.sfp_type = 1460 ixgbe_sfp_type_1g_lx_core1; 1461 } else { 1462 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1463 } 1464 } 1465 1466 if (hw->phy.sfp_type != stored_sfp_type) 1467 hw->phy.sfp_setup_needed = TRUE; 1468 1469 /* Determine if the SFP+ PHY is dual speed or not. */ 1470 hw->phy.multispeed_fiber = FALSE; 1471 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1472 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1473 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1474 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1475 hw->phy.multispeed_fiber = TRUE; 1476 1477 /* Determine PHY vendor */ 1478 if (hw->phy.type != ixgbe_phy_nl) { 1479 hw->phy.id = identifier; 1480 status = hw->phy.ops.read_i2c_eeprom(hw, 1481 IXGBE_SFF_VENDOR_OUI_BYTE0, 1482 &oui_bytes[0]); 1483 1484 if (status != IXGBE_SUCCESS) 1485 goto err_read_i2c_eeprom; 1486 1487 status = hw->phy.ops.read_i2c_eeprom(hw, 1488 IXGBE_SFF_VENDOR_OUI_BYTE1, 1489 &oui_bytes[1]); 1490 1491 if (status != IXGBE_SUCCESS) 1492 goto err_read_i2c_eeprom; 1493 1494 status = hw->phy.ops.read_i2c_eeprom(hw, 1495 IXGBE_SFF_VENDOR_OUI_BYTE2, 1496 &oui_bytes[2]); 1497 1498 if (status != IXGBE_SUCCESS) 1499 goto err_read_i2c_eeprom; 1500 1501 vendor_oui = 1502 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1503 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1504 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1505 1506 switch (vendor_oui) { 1507 case IXGBE_SFF_VENDOR_OUI_TYCO: 1508 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1509 hw->phy.type = 1510 ixgbe_phy_sfp_passive_tyco; 1511 break; 1512 case IXGBE_SFF_VENDOR_OUI_FTL: 1513 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1514 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1515 else 1516 hw->phy.type = ixgbe_phy_sfp_ftl; 1517 break; 1518 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1519 hw->phy.type = ixgbe_phy_sfp_avago; 1520 break; 1521 case IXGBE_SFF_VENDOR_OUI_INTEL: 1522 hw->phy.type = ixgbe_phy_sfp_intel; 1523 break; 1524 default: 1525 hw->phy.type = ixgbe_phy_sfp_unknown; 1526 break; 1527 } 1528 } 1529 1530 /* Allow any DA cable vendor */ 1531 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1532 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1533 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1534 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1535 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1536 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1537 status = IXGBE_SUCCESS; 1538 goto out; 1539 } 1540 1541 /* Verify supported 1G SFP modules */ 1542 if (comp_codes_10g == 0 && 1543 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1544 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1545 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1546 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1547 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1548 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1549 hw->phy.type = ixgbe_phy_sfp_unsupported; 1550 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1551 goto out; 1552 } 1553 1554 /* Anything else 82598-based is supported */ 1555 if (hw->mac.type == ixgbe_mac_82598EB) { 1556 status = IXGBE_SUCCESS; 1557 goto out; 1558 } 1559 1560 ixgbe_get_device_caps(hw, &enforce_sfp); 1561 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1562 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1563 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1564 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1565 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1566 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1567 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1568 /* Make sure we're a supported PHY type */ 1569 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1570 status = IXGBE_SUCCESS; 1571 } else { 1572 if (hw->allow_unsupported_sfp == TRUE) { 1573 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1574 status = IXGBE_SUCCESS; 1575 } else { 1576 DEBUGOUT("SFP+ module not supported\n"); 1577 hw->phy.type = 1578 ixgbe_phy_sfp_unsupported; 1579 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1580 } 1581 } 1582 } else { 1583 status = IXGBE_SUCCESS; 1584 } 1585 } 1586 1587 out: 1588 return status; 1589 1590 err_read_i2c_eeprom: 1591 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1592 if (hw->phy.type != ixgbe_phy_nl) { 1593 hw->phy.id = 0; 1594 hw->phy.type = ixgbe_phy_unknown; 1595 } 1596 return IXGBE_ERR_SFP_NOT_PRESENT; 1597 } 1598 1599 /** 1600 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1601 * @hw: pointer to hardware structure 1602 * 1603 * Determines physical layer capabilities of the current SFP. 1604 */ 1605 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1606 { 1607 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1608 u8 comp_codes_10g = 0; 1609 u8 comp_codes_1g = 0; 1610 1611 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1612 1613 hw->phy.ops.identify_sfp(hw); 1614 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1615 return physical_layer; 1616 1617 switch (hw->phy.type) { 1618 case ixgbe_phy_sfp_passive_tyco: 1619 case ixgbe_phy_sfp_passive_unknown: 1620 case ixgbe_phy_qsfp_passive_unknown: 1621 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1622 break; 1623 case ixgbe_phy_sfp_ftl_active: 1624 case ixgbe_phy_sfp_active_unknown: 1625 case ixgbe_phy_qsfp_active_unknown: 1626 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1627 break; 1628 case ixgbe_phy_sfp_avago: 1629 case ixgbe_phy_sfp_ftl: 1630 case ixgbe_phy_sfp_intel: 1631 case ixgbe_phy_sfp_unknown: 1632 hw->phy.ops.read_i2c_eeprom(hw, 1633 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1634 hw->phy.ops.read_i2c_eeprom(hw, 1635 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1636 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1637 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1638 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1639 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1640 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1641 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1642 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1643 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1644 break; 1645 case ixgbe_phy_qsfp_intel: 1646 case ixgbe_phy_qsfp_unknown: 1647 hw->phy.ops.read_i2c_eeprom(hw, 1648 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1649 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1650 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1651 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1652 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1653 break; 1654 default: 1655 break; 1656 } 1657 1658 return physical_layer; 1659 } 1660 1661 /** 1662 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1663 * @hw: pointer to hardware structure 1664 * 1665 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1666 **/ 1667 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1668 { 1669 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1670 u32 vendor_oui = 0; 1671 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1672 u8 identifier = 0; 1673 u8 comp_codes_1g = 0; 1674 u8 comp_codes_10g = 0; 1675 u8 oui_bytes[3] = {0, 0, 0}; 1676 u16 enforce_sfp = 0; 1677 u8 connector = 0; 1678 u8 cable_length = 0; 1679 u8 device_tech = 0; 1680 bool active_cable = FALSE; 1681 1682 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1683 1684 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1685 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1686 status = IXGBE_ERR_SFP_NOT_PRESENT; 1687 goto out; 1688 } 1689 1690 /* LAN ID is needed for I2C access */ 1691 hw->mac.ops.set_lan_id(hw); 1692 1693 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1694 &identifier); 1695 1696 if (status != IXGBE_SUCCESS) 1697 goto err_read_i2c_eeprom; 1698 1699 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1700 hw->phy.type = ixgbe_phy_sfp_unsupported; 1701 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1702 goto out; 1703 } 1704 1705 hw->phy.id = identifier; 1706 1707 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1708 &comp_codes_10g); 1709 1710 if (status != IXGBE_SUCCESS) 1711 goto err_read_i2c_eeprom; 1712 1713 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1714 &comp_codes_1g); 1715 1716 if (status != IXGBE_SUCCESS) 1717 goto err_read_i2c_eeprom; 1718 1719 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1720 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1721 if (hw->bus.lan_id == 0) 1722 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1723 else 1724 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1725 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1726 IXGBE_SFF_10GBASELR_CAPABLE)) { 1727 if (hw->bus.lan_id == 0) 1728 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1729 else 1730 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1731 } else { 1732 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1733 active_cable = TRUE; 1734 1735 if (!active_cable) { 1736 /* check for active DA cables that pre-date 1737 * SFF-8436 v3.6 */ 1738 hw->phy.ops.read_i2c_eeprom(hw, 1739 IXGBE_SFF_QSFP_CONNECTOR, 1740 &connector); 1741 1742 hw->phy.ops.read_i2c_eeprom(hw, 1743 IXGBE_SFF_QSFP_CABLE_LENGTH, 1744 &cable_length); 1745 1746 hw->phy.ops.read_i2c_eeprom(hw, 1747 IXGBE_SFF_QSFP_DEVICE_TECH, 1748 &device_tech); 1749 1750 if ((connector == 1751 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1752 (cable_length > 0) && 1753 ((device_tech >> 4) == 1754 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1755 active_cable = TRUE; 1756 } 1757 1758 if (active_cable) { 1759 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1760 if (hw->bus.lan_id == 0) 1761 hw->phy.sfp_type = 1762 ixgbe_sfp_type_da_act_lmt_core0; 1763 else 1764 hw->phy.sfp_type = 1765 ixgbe_sfp_type_da_act_lmt_core1; 1766 } else { 1767 /* unsupported module type */ 1768 hw->phy.type = ixgbe_phy_sfp_unsupported; 1769 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1770 goto out; 1771 } 1772 } 1773 1774 if (hw->phy.sfp_type != stored_sfp_type) 1775 hw->phy.sfp_setup_needed = TRUE; 1776 1777 /* Determine if the QSFP+ PHY is dual speed or not. */ 1778 hw->phy.multispeed_fiber = FALSE; 1779 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1780 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1781 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1782 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1783 hw->phy.multispeed_fiber = TRUE; 1784 1785 /* Determine PHY vendor for optical modules */ 1786 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1787 IXGBE_SFF_10GBASELR_CAPABLE)) { 1788 status = hw->phy.ops.read_i2c_eeprom(hw, 1789 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1790 &oui_bytes[0]); 1791 1792 if (status != IXGBE_SUCCESS) 1793 goto err_read_i2c_eeprom; 1794 1795 status = hw->phy.ops.read_i2c_eeprom(hw, 1796 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1797 &oui_bytes[1]); 1798 1799 if (status != IXGBE_SUCCESS) 1800 goto err_read_i2c_eeprom; 1801 1802 status = hw->phy.ops.read_i2c_eeprom(hw, 1803 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1804 &oui_bytes[2]); 1805 1806 if (status != IXGBE_SUCCESS) 1807 goto err_read_i2c_eeprom; 1808 1809 vendor_oui = 1810 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1811 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1812 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1813 1814 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1815 hw->phy.type = ixgbe_phy_qsfp_intel; 1816 else 1817 hw->phy.type = ixgbe_phy_qsfp_unknown; 1818 1819 ixgbe_get_device_caps(hw, &enforce_sfp); 1820 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1821 /* Make sure we're a supported PHY type */ 1822 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1823 status = IXGBE_SUCCESS; 1824 } else { 1825 if (hw->allow_unsupported_sfp == TRUE) { 1826 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1827 status = IXGBE_SUCCESS; 1828 } else { 1829 DEBUGOUT("QSFP module not supported\n"); 1830 hw->phy.type = 1831 ixgbe_phy_sfp_unsupported; 1832 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1833 } 1834 } 1835 } else { 1836 status = IXGBE_SUCCESS; 1837 } 1838 } 1839 1840 out: 1841 return status; 1842 1843 err_read_i2c_eeprom: 1844 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1845 hw->phy.id = 0; 1846 hw->phy.type = ixgbe_phy_unknown; 1847 1848 return IXGBE_ERR_SFP_NOT_PRESENT; 1849 } 1850 1851 /** 1852 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1853 * @hw: pointer to hardware structure 1854 * @list_offset: offset to the SFP ID list 1855 * @data_offset: offset to the SFP data block 1856 * 1857 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1858 * so it returns the offsets to the phy init sequence block. 1859 **/ 1860 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1861 u16 *list_offset, 1862 u16 *data_offset) 1863 { 1864 u16 sfp_id; 1865 u16 sfp_type = hw->phy.sfp_type; 1866 1867 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1868 1869 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1870 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1871 1872 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1873 return IXGBE_ERR_SFP_NOT_PRESENT; 1874 1875 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1876 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1877 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1878 1879 /* 1880 * Limiting active cables and 1G Phys must be initialized as 1881 * SR modules 1882 */ 1883 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1884 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1885 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1886 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1887 sfp_type = ixgbe_sfp_type_srlr_core0; 1888 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1889 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1890 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1891 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1892 sfp_type = ixgbe_sfp_type_srlr_core1; 1893 1894 /* Read offset to PHY init contents */ 1895 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1896 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1897 "eeprom read at offset %d failed", 1898 IXGBE_PHY_INIT_OFFSET_NL); 1899 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1900 } 1901 1902 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1903 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1904 1905 /* Shift offset to first ID word */ 1906 (*list_offset)++; 1907 1908 /* 1909 * Find the matching SFP ID in the EEPROM 1910 * and program the init sequence 1911 */ 1912 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1913 goto err_phy; 1914 1915 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1916 if (sfp_id == sfp_type) { 1917 (*list_offset)++; 1918 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1919 goto err_phy; 1920 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1921 DEBUGOUT("SFP+ module not supported\n"); 1922 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1923 } else { 1924 break; 1925 } 1926 } else { 1927 (*list_offset) += 2; 1928 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1929 goto err_phy; 1930 } 1931 } 1932 1933 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1934 DEBUGOUT("No matching SFP+ module found\n"); 1935 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1936 } 1937 1938 return IXGBE_SUCCESS; 1939 1940 err_phy: 1941 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1942 "eeprom read at offset %d failed", *list_offset); 1943 return IXGBE_ERR_PHY; 1944 } 1945 1946 /** 1947 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1948 * @hw: pointer to hardware structure 1949 * @byte_offset: EEPROM byte offset to read 1950 * @eeprom_data: value read 1951 * 1952 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1953 **/ 1954 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1955 u8 *eeprom_data) 1956 { 1957 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1958 1959 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1960 IXGBE_I2C_EEPROM_DEV_ADDR, 1961 eeprom_data); 1962 } 1963 1964 /** 1965 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1966 * @hw: pointer to hardware structure 1967 * @byte_offset: byte offset at address 0xA2 1968 * @sff8472_data: value read 1969 * 1970 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1971 **/ 1972 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1973 u8 *sff8472_data) 1974 { 1975 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1976 IXGBE_I2C_EEPROM_DEV_ADDR2, 1977 sff8472_data); 1978 } 1979 1980 /** 1981 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1982 * @hw: pointer to hardware structure 1983 * @byte_offset: EEPROM byte offset to write 1984 * @eeprom_data: value to write 1985 * 1986 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1987 **/ 1988 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1989 u8 eeprom_data) 1990 { 1991 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1992 1993 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1994 IXGBE_I2C_EEPROM_DEV_ADDR, 1995 eeprom_data); 1996 } 1997 1998 /** 1999 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2000 * @hw: pointer to hardware structure 2001 * @offset: eeprom offset to be read 2002 * @addr: I2C address to be read 2003 */ 2004 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2005 { 2006 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2007 offset == IXGBE_SFF_IDENTIFIER && 2008 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2009 return TRUE; 2010 return FALSE; 2011 } 2012 2013 /** 2014 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2015 * @hw: pointer to hardware structure 2016 * @byte_offset: byte offset to read 2017 * @dev_addr: address to read from 2018 * @data: value read 2019 * @lock: TRUE if to take and release semaphore 2020 * 2021 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2022 * a specified device address. 2023 **/ 2024 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2025 u8 dev_addr, u8 *data, bool lock) 2026 { 2027 s32 status; 2028 u32 max_retry = 10; 2029 u32 retry = 0; 2030 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2031 bool nack = 1; 2032 *data = 0; 2033 2034 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2035 2036 if (hw->mac.type >= ixgbe_mac_X550) 2037 max_retry = 3; 2038 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2039 max_retry = IXGBE_SFP_DETECT_RETRIES; 2040 2041 do { 2042 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2043 return IXGBE_ERR_SWFW_SYNC; 2044 2045 ixgbe_i2c_start(hw); 2046 2047 /* Device Address and write indication */ 2048 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2049 if (status != IXGBE_SUCCESS) 2050 goto fail; 2051 2052 status = ixgbe_get_i2c_ack(hw); 2053 if (status != IXGBE_SUCCESS) 2054 goto fail; 2055 2056 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2057 if (status != IXGBE_SUCCESS) 2058 goto fail; 2059 2060 status = ixgbe_get_i2c_ack(hw); 2061 if (status != IXGBE_SUCCESS) 2062 goto fail; 2063 2064 ixgbe_i2c_start(hw); 2065 2066 /* Device Address and read indication */ 2067 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2068 if (status != IXGBE_SUCCESS) 2069 goto fail; 2070 2071 status = ixgbe_get_i2c_ack(hw); 2072 if (status != IXGBE_SUCCESS) 2073 goto fail; 2074 2075 status = ixgbe_clock_in_i2c_byte(hw, data); 2076 if (status != IXGBE_SUCCESS) 2077 goto fail; 2078 2079 status = ixgbe_clock_out_i2c_bit(hw, nack); 2080 if (status != IXGBE_SUCCESS) 2081 goto fail; 2082 2083 ixgbe_i2c_stop(hw); 2084 if (lock) 2085 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2086 return IXGBE_SUCCESS; 2087 2088 fail: 2089 ixgbe_i2c_bus_clear(hw); 2090 if (lock) { 2091 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2092 msec_delay(100); 2093 } 2094 retry++; 2095 if (retry < max_retry) 2096 DEBUGOUT("I2C byte read error - Retrying.\n"); 2097 else 2098 DEBUGOUT("I2C byte read error.\n"); 2099 2100 } while (retry < max_retry); 2101 2102 return status; 2103 } 2104 2105 /** 2106 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2107 * @hw: pointer to hardware structure 2108 * @byte_offset: byte offset to read 2109 * @dev_addr: address to read from 2110 * @data: value read 2111 * 2112 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2113 * a specified device address. 2114 **/ 2115 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2116 u8 dev_addr, u8 *data) 2117 { 2118 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2119 data, TRUE); 2120 } 2121 2122 /** 2123 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2124 * @hw: pointer to hardware structure 2125 * @byte_offset: byte offset to read 2126 * @dev_addr: address to read from 2127 * @data: value read 2128 * 2129 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2130 * a specified device address. 2131 **/ 2132 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2133 u8 dev_addr, u8 *data) 2134 { 2135 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2136 data, FALSE); 2137 } 2138 2139 /** 2140 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2141 * @hw: pointer to hardware structure 2142 * @byte_offset: byte offset to write 2143 * @dev_addr: address to write to 2144 * @data: value to write 2145 * @lock: TRUE if to take and release semaphore 2146 * 2147 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2148 * a specified device address. 2149 **/ 2150 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2151 u8 dev_addr, u8 data, bool lock) 2152 { 2153 s32 status; 2154 u32 max_retry = 2; 2155 u32 retry = 0; 2156 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2157 2158 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2159 2160 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2161 IXGBE_SUCCESS) 2162 return IXGBE_ERR_SWFW_SYNC; 2163 2164 do { 2165 ixgbe_i2c_start(hw); 2166 2167 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2168 if (status != IXGBE_SUCCESS) 2169 goto fail; 2170 2171 status = ixgbe_get_i2c_ack(hw); 2172 if (status != IXGBE_SUCCESS) 2173 goto fail; 2174 2175 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2176 if (status != IXGBE_SUCCESS) 2177 goto fail; 2178 2179 status = ixgbe_get_i2c_ack(hw); 2180 if (status != IXGBE_SUCCESS) 2181 goto fail; 2182 2183 status = ixgbe_clock_out_i2c_byte(hw, data); 2184 if (status != IXGBE_SUCCESS) 2185 goto fail; 2186 2187 status = ixgbe_get_i2c_ack(hw); 2188 if (status != IXGBE_SUCCESS) 2189 goto fail; 2190 2191 ixgbe_i2c_stop(hw); 2192 if (lock) 2193 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2194 return IXGBE_SUCCESS; 2195 2196 fail: 2197 ixgbe_i2c_bus_clear(hw); 2198 retry++; 2199 if (retry < max_retry) 2200 DEBUGOUT("I2C byte write error - Retrying.\n"); 2201 else 2202 DEBUGOUT("I2C byte write error.\n"); 2203 } while (retry < max_retry); 2204 2205 if (lock) 2206 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2207 2208 return status; 2209 } 2210 2211 /** 2212 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2213 * @hw: pointer to hardware structure 2214 * @byte_offset: byte offset to write 2215 * @dev_addr: address to write to 2216 * @data: value to write 2217 * 2218 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2219 * a specified device address. 2220 **/ 2221 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2222 u8 dev_addr, u8 data) 2223 { 2224 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2225 data, TRUE); 2226 } 2227 2228 /** 2229 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2230 * @hw: pointer to hardware structure 2231 * @byte_offset: byte offset to write 2232 * @dev_addr: address to write to 2233 * @data: value to write 2234 * 2235 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2236 * a specified device address. 2237 **/ 2238 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2239 u8 dev_addr, u8 data) 2240 { 2241 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2242 data, FALSE); 2243 } 2244 2245 /** 2246 * ixgbe_i2c_start - Sets I2C start condition 2247 * @hw: pointer to hardware structure 2248 * 2249 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2250 * Set bit-bang mode on X550 hardware. 2251 **/ 2252 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2253 { 2254 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2255 2256 DEBUGFUNC("ixgbe_i2c_start"); 2257 2258 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2259 2260 /* Start condition must begin with data and clock high */ 2261 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2262 ixgbe_raise_i2c_clk(hw, &i2cctl); 2263 2264 /* Setup time for start condition (4.7us) */ 2265 usec_delay(IXGBE_I2C_T_SU_STA); 2266 2267 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2268 2269 /* Hold time for start condition (4us) */ 2270 usec_delay(IXGBE_I2C_T_HD_STA); 2271 2272 ixgbe_lower_i2c_clk(hw, &i2cctl); 2273 2274 /* Minimum low period of clock is 4.7 us */ 2275 usec_delay(IXGBE_I2C_T_LOW); 2276 2277 } 2278 2279 /** 2280 * ixgbe_i2c_stop - Sets I2C stop condition 2281 * @hw: pointer to hardware structure 2282 * 2283 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2284 * Disables bit-bang mode and negates data output enable on X550 2285 * hardware. 2286 **/ 2287 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2288 { 2289 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2290 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2291 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2292 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2293 2294 DEBUGFUNC("ixgbe_i2c_stop"); 2295 2296 /* Stop condition must begin with data low and clock high */ 2297 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2298 ixgbe_raise_i2c_clk(hw, &i2cctl); 2299 2300 /* Setup time for stop condition (4us) */ 2301 usec_delay(IXGBE_I2C_T_SU_STO); 2302 2303 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2304 2305 /* bus free time between stop and start (4.7us)*/ 2306 usec_delay(IXGBE_I2C_T_BUF); 2307 2308 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2309 i2cctl &= ~bb_en_bit; 2310 i2cctl |= data_oe_bit | clk_oe_bit; 2311 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2312 IXGBE_WRITE_FLUSH(hw); 2313 } 2314 } 2315 2316 /** 2317 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2318 * @hw: pointer to hardware structure 2319 * @data: data byte to clock in 2320 * 2321 * Clocks in one byte data via I2C data/clock 2322 **/ 2323 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2324 { 2325 s32 i; 2326 bool bit = 0; 2327 2328 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2329 2330 *data = 0; 2331 for (i = 7; i >= 0; i--) { 2332 ixgbe_clock_in_i2c_bit(hw, &bit); 2333 *data |= bit << i; 2334 } 2335 2336 return IXGBE_SUCCESS; 2337 } 2338 2339 /** 2340 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2341 * @hw: pointer to hardware structure 2342 * @data: data byte clocked out 2343 * 2344 * Clocks out one byte data via I2C data/clock 2345 **/ 2346 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2347 { 2348 s32 status = IXGBE_SUCCESS; 2349 s32 i; 2350 u32 i2cctl; 2351 bool bit; 2352 2353 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2354 2355 for (i = 7; i >= 0; i--) { 2356 bit = (data >> i) & 0x1; 2357 status = ixgbe_clock_out_i2c_bit(hw, bit); 2358 2359 if (status != IXGBE_SUCCESS) 2360 break; 2361 } 2362 2363 /* Release SDA line (set high) */ 2364 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2365 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2366 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2367 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2368 IXGBE_WRITE_FLUSH(hw); 2369 2370 return status; 2371 } 2372 2373 /** 2374 * ixgbe_get_i2c_ack - Polls for I2C ACK 2375 * @hw: pointer to hardware structure 2376 * 2377 * Clocks in/out one bit via I2C data/clock 2378 **/ 2379 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2380 { 2381 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2382 s32 status = IXGBE_SUCCESS; 2383 u32 i = 0; 2384 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2385 u32 timeout = 10; 2386 bool ack = 1; 2387 2388 DEBUGFUNC("ixgbe_get_i2c_ack"); 2389 2390 if (data_oe_bit) { 2391 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2392 i2cctl |= data_oe_bit; 2393 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2394 IXGBE_WRITE_FLUSH(hw); 2395 } 2396 ixgbe_raise_i2c_clk(hw, &i2cctl); 2397 2398 /* Minimum high period of clock is 4us */ 2399 usec_delay(IXGBE_I2C_T_HIGH); 2400 2401 /* Poll for ACK. Note that ACK in I2C spec is 2402 * transition from 1 to 0 */ 2403 for (i = 0; i < timeout; i++) { 2404 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2405 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2406 2407 usec_delay(1); 2408 if (!ack) 2409 break; 2410 } 2411 2412 if (ack) { 2413 DEBUGOUT("I2C ack was not received.\n"); 2414 status = IXGBE_ERR_I2C; 2415 } 2416 2417 ixgbe_lower_i2c_clk(hw, &i2cctl); 2418 2419 /* Minimum low period of clock is 4.7 us */ 2420 usec_delay(IXGBE_I2C_T_LOW); 2421 2422 return status; 2423 } 2424 2425 /** 2426 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2427 * @hw: pointer to hardware structure 2428 * @data: read data value 2429 * 2430 * Clocks in one bit via I2C data/clock 2431 **/ 2432 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2433 { 2434 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2435 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2436 2437 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2438 2439 if (data_oe_bit) { 2440 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2441 i2cctl |= data_oe_bit; 2442 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2443 IXGBE_WRITE_FLUSH(hw); 2444 } 2445 ixgbe_raise_i2c_clk(hw, &i2cctl); 2446 2447 /* Minimum high period of clock is 4us */ 2448 usec_delay(IXGBE_I2C_T_HIGH); 2449 2450 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2451 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2452 2453 ixgbe_lower_i2c_clk(hw, &i2cctl); 2454 2455 /* Minimum low period of clock is 4.7 us */ 2456 usec_delay(IXGBE_I2C_T_LOW); 2457 2458 return IXGBE_SUCCESS; 2459 } 2460 2461 /** 2462 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2463 * @hw: pointer to hardware structure 2464 * @data: data value to write 2465 * 2466 * Clocks out one bit via I2C data/clock 2467 **/ 2468 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2469 { 2470 s32 status; 2471 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2472 2473 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2474 2475 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2476 if (status == IXGBE_SUCCESS) { 2477 ixgbe_raise_i2c_clk(hw, &i2cctl); 2478 2479 /* Minimum high period of clock is 4us */ 2480 usec_delay(IXGBE_I2C_T_HIGH); 2481 2482 ixgbe_lower_i2c_clk(hw, &i2cctl); 2483 2484 /* Minimum low period of clock is 4.7 us. 2485 * This also takes care of the data hold time. 2486 */ 2487 usec_delay(IXGBE_I2C_T_LOW); 2488 } else { 2489 status = IXGBE_ERR_I2C; 2490 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2491 "I2C data was not set to %X\n", data); 2492 } 2493 2494 return status; 2495 } 2496 2497 /** 2498 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2499 * @hw: pointer to hardware structure 2500 * @i2cctl: Current value of I2CCTL register 2501 * 2502 * Raises the I2C clock line '0'->'1' 2503 * Negates the I2C clock output enable on X550 hardware. 2504 **/ 2505 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2506 { 2507 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2508 u32 i = 0; 2509 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2510 u32 i2cctl_r = 0; 2511 2512 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2513 2514 if (clk_oe_bit) { 2515 *i2cctl |= clk_oe_bit; 2516 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2517 } 2518 2519 for (i = 0; i < timeout; i++) { 2520 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2521 2522 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2523 IXGBE_WRITE_FLUSH(hw); 2524 /* SCL rise time (1000ns) */ 2525 usec_delay(IXGBE_I2C_T_RISE); 2526 2527 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2528 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2529 break; 2530 } 2531 } 2532 2533 /** 2534 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2535 * @hw: pointer to hardware structure 2536 * @i2cctl: Current value of I2CCTL register 2537 * 2538 * Lowers the I2C clock line '1'->'0' 2539 * Asserts the I2C clock output enable on X550 hardware. 2540 **/ 2541 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2542 { 2543 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2544 2545 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2546 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2547 2548 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2549 IXGBE_WRITE_FLUSH(hw); 2550 2551 /* SCL fall time (300ns) */ 2552 usec_delay(IXGBE_I2C_T_FALL); 2553 } 2554 2555 /** 2556 * ixgbe_set_i2c_data - Sets the I2C data bit 2557 * @hw: pointer to hardware structure 2558 * @i2cctl: Current value of I2CCTL register 2559 * @data: I2C data value (0 or 1) to set 2560 * 2561 * Sets the I2C data bit 2562 * Asserts the I2C data output enable on X550 hardware. 2563 **/ 2564 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2565 { 2566 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2567 s32 status = IXGBE_SUCCESS; 2568 2569 DEBUGFUNC("ixgbe_set_i2c_data"); 2570 2571 if (data) 2572 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2573 else 2574 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2575 *i2cctl &= ~data_oe_bit; 2576 2577 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2578 IXGBE_WRITE_FLUSH(hw); 2579 2580 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2581 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2582 2583 if (!data) /* Can't verify data in this case */ 2584 return IXGBE_SUCCESS; 2585 if (data_oe_bit) { 2586 *i2cctl |= data_oe_bit; 2587 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2588 IXGBE_WRITE_FLUSH(hw); 2589 } 2590 2591 /* Verify data was set correctly */ 2592 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2593 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2594 status = IXGBE_ERR_I2C; 2595 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2596 "Error - I2C data was not set to %X.\n", 2597 data); 2598 } 2599 2600 return status; 2601 } 2602 2603 /** 2604 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2605 * @hw: pointer to hardware structure 2606 * @i2cctl: Current value of I2CCTL register 2607 * 2608 * Returns the I2C data bit value 2609 * Negates the I2C data output enable on X550 hardware. 2610 **/ 2611 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2612 { 2613 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2614 bool data; 2615 UNREFERENCED_1PARAMETER(hw); 2616 2617 DEBUGFUNC("ixgbe_get_i2c_data"); 2618 2619 if (data_oe_bit) { 2620 *i2cctl |= data_oe_bit; 2621 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2622 IXGBE_WRITE_FLUSH(hw); 2623 usec_delay(IXGBE_I2C_T_FALL); 2624 } 2625 2626 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2627 data = 1; 2628 else 2629 data = 0; 2630 2631 return data; 2632 } 2633 2634 /** 2635 * ixgbe_i2c_bus_clear - Clears the I2C bus 2636 * @hw: pointer to hardware structure 2637 * 2638 * Clears the I2C bus by sending nine clock pulses. 2639 * Used when data line is stuck low. 2640 **/ 2641 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2642 { 2643 u32 i2cctl; 2644 u32 i; 2645 2646 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2647 2648 ixgbe_i2c_start(hw); 2649 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2650 2651 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2652 2653 for (i = 0; i < 9; i++) { 2654 ixgbe_raise_i2c_clk(hw, &i2cctl); 2655 2656 /* Min high period of clock is 4us */ 2657 usec_delay(IXGBE_I2C_T_HIGH); 2658 2659 ixgbe_lower_i2c_clk(hw, &i2cctl); 2660 2661 /* Min low period of clock is 4.7us*/ 2662 usec_delay(IXGBE_I2C_T_LOW); 2663 } 2664 2665 ixgbe_i2c_start(hw); 2666 2667 /* Put the i2c bus back to default state */ 2668 ixgbe_i2c_stop(hw); 2669 } 2670 2671 /** 2672 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2673 * @hw: pointer to hardware structure 2674 * 2675 * Checks if the LASI temp alarm status was triggered due to overtemp 2676 **/ 2677 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2678 { 2679 s32 status = IXGBE_SUCCESS; 2680 u16 phy_data = 0; 2681 2682 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2683 2684 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2685 goto out; 2686 2687 /* Check that the LASI temp alarm status was triggered */ 2688 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2689 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2690 2691 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2692 goto out; 2693 2694 status = IXGBE_ERR_OVERTEMP; 2695 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2696 out: 2697 return status; 2698 } 2699 2700 /** 2701 * ixgbe_set_copper_phy_power - Control power for copper phy 2702 * @hw: pointer to hardware structure 2703 * @on: TRUE for on, FALSE for off 2704 */ 2705 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2706 { 2707 u32 status; 2708 u16 reg; 2709 2710 if (!on && ixgbe_mng_present(hw)) 2711 return 0; 2712 2713 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2714 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2715 ®); 2716 if (status) 2717 return status; 2718 2719 if (on) { 2720 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2721 } else { 2722 if (ixgbe_check_reset_blocked(hw)) 2723 return 0; 2724 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2725 } 2726 2727 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2728 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2729 reg); 2730 return status; 2731 } 2732
Indexes created Fri Sep 26 20:09:58 GMT 2025