ixgbe_phy.c revision 1.2
1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.11 2010/11/26 22:46:32 jfv Exp $*/ 34 /*$NetBSD: ixgbe_phy.c,v 1.2 2014/04/17 15:35:49 christos Exp $*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 47 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 50 static bool ixgbe_get_i2c_data(u32 *i2cctl); 51 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 52 53 /** 54 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 55 * @hw: pointer to the hardware structure 56 * 57 * Initialize the function pointers. 58 **/ 59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 60 { 61 struct ixgbe_phy_info *phy = &hw->phy; 62 63 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 64 65 /* PHY */ 66 phy->ops.identify = &ixgbe_identify_phy_generic; 67 phy->ops.reset = &ixgbe_reset_phy_generic; 68 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 69 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 70 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 71 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 72 phy->ops.check_link = NULL; 73 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 74 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 75 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 76 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 77 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 78 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 79 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 80 phy->sfp_type = ixgbe_sfp_type_unknown; 81 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 82 return IXGBE_SUCCESS; 83 } 84 85 /** 86 * ixgbe_identify_phy_generic - Get physical layer module 87 * @hw: pointer to hardware structure 88 * 89 * Determines the physical layer module found on the current adapter. 90 **/ 91 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 92 { 93 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 94 u32 phy_addr; 95 u16 ext_ability = 0; 96 97 DEBUGFUNC("ixgbe_identify_phy_generic"); 98 99 if (hw->phy.type == ixgbe_phy_unknown) { 100 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 101 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 102 hw->phy.addr = phy_addr; 103 ixgbe_get_phy_id(hw); 104 hw->phy.type = 105 ixgbe_get_phy_type_from_id(hw->phy.id); 106 107 if (hw->phy.type == ixgbe_phy_unknown) { 108 hw->phy.ops.read_reg(hw, 109 IXGBE_MDIO_PHY_EXT_ABILITY, 110 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 111 &ext_ability); 112 if (ext_ability & 113 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 114 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 115 hw->phy.type = 116 ixgbe_phy_cu_unknown; 117 else 118 hw->phy.type = 119 ixgbe_phy_generic; 120 } 121 122 status = IXGBE_SUCCESS; 123 break; 124 } 125 } 126 /* clear value if nothing found */ 127 if (status != IXGBE_SUCCESS) 128 hw->phy.addr = 0; 129 } else { 130 status = IXGBE_SUCCESS; 131 } 132 133 return status; 134 } 135 136 /** 137 * ixgbe_validate_phy_addr - Determines phy address is valid 138 * @hw: pointer to hardware structure 139 * 140 **/ 141 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 142 { 143 u16 phy_id = 0; 144 bool valid = FALSE; 145 146 DEBUGFUNC("ixgbe_validate_phy_addr"); 147 148 hw->phy.addr = phy_addr; 149 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 150 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 151 152 if (phy_id != 0xFFFF && phy_id != 0x0) 153 valid = TRUE; 154 155 return valid; 156 } 157 158 /** 159 * ixgbe_get_phy_id - Get the phy type 160 * @hw: pointer to hardware structure 161 * 162 **/ 163 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 164 { 165 u32 status; 166 u16 phy_id_high = 0; 167 u16 phy_id_low = 0; 168 169 DEBUGFUNC("ixgbe_get_phy_id"); 170 171 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 172 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 173 &phy_id_high); 174 175 if (status == IXGBE_SUCCESS) { 176 hw->phy.id = (u32)(phy_id_high << 16); 177 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 178 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 179 &phy_id_low); 180 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 181 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 182 } 183 return status; 184 } 185 186 /** 187 * ixgbe_get_phy_type_from_id - Get the phy type 188 * @hw: pointer to hardware structure 189 * 190 **/ 191 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 192 { 193 enum ixgbe_phy_type phy_type; 194 195 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 196 197 switch (phy_id) { 198 case TN1010_PHY_ID: 199 phy_type = ixgbe_phy_tn; 200 break; 201 case AQ1002_PHY_ID: 202 phy_type = ixgbe_phy_aq; 203 break; 204 case QT2022_PHY_ID: 205 phy_type = ixgbe_phy_qt; 206 break; 207 case ATH_PHY_ID: 208 phy_type = ixgbe_phy_nl; 209 break; 210 default: 211 phy_type = ixgbe_phy_unknown; 212 break; 213 } 214 215 DEBUGOUT1("phy type found is %d\n", phy_type); 216 return phy_type; 217 } 218 219 /** 220 * ixgbe_reset_phy_generic - Performs a PHY reset 221 * @hw: pointer to hardware structure 222 **/ 223 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 224 { 225 u32 i; 226 u16 ctrl = 0; 227 s32 status = IXGBE_SUCCESS; 228 229 DEBUGFUNC("ixgbe_reset_phy_generic"); 230 231 if (hw->phy.type == ixgbe_phy_unknown) 232 status = ixgbe_identify_phy_generic(hw); 233 234 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 235 goto out; 236 237 /* Don't reset PHY if it's shut down due to overtemp. */ 238 if (!hw->phy.reset_if_overtemp && 239 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 240 goto out; 241 242 /* 243 * Perform soft PHY reset to the PHY_XS. 244 * This will cause a soft reset to the PHY 245 */ 246 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 247 IXGBE_MDIO_PHY_XS_DEV_TYPE, 248 IXGBE_MDIO_PHY_XS_RESET); 249 250 /* 251 * Poll for reset bit to self-clear indicating reset is complete. 252 * Some PHYs could take up to 3 seconds to complete and need about 253 * 1.7 usec delay after the reset is complete. 254 */ 255 for (i = 0; i < 30; i++) { 256 msec_delay(100); 257 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 258 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 259 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 260 usec_delay(2); 261 break; 262 } 263 } 264 265 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 266 status = IXGBE_ERR_RESET_FAILED; 267 DEBUGOUT("PHY reset polling failed to complete.\n"); 268 } 269 270 out: 271 return status; 272 } 273 274 /** 275 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 276 * @hw: pointer to hardware structure 277 * @reg_addr: 32 bit address of PHY register to read 278 * @phy_data: Pointer to read data from PHY register 279 **/ 280 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 281 u32 device_type, u16 *phy_data) 282 { 283 u32 command; 284 u32 i; 285 u32 data; 286 s32 status = IXGBE_SUCCESS; 287 u16 gssr; 288 289 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 290 291 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 292 gssr = IXGBE_GSSR_PHY1_SM; 293 else 294 gssr = IXGBE_GSSR_PHY0_SM; 295 296 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 297 status = IXGBE_ERR_SWFW_SYNC; 298 299 if (status == IXGBE_SUCCESS) { 300 /* Setup and write the address cycle command */ 301 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 302 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 303 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 304 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 305 306 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 307 308 /* 309 * Check every 10 usec to see if the address cycle completed. 310 * The MDI Command bit will clear when the operation is 311 * complete 312 */ 313 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 314 usec_delay(10); 315 316 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 317 318 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 319 break; 320 } 321 322 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 323 DEBUGOUT("PHY address command did not complete.\n"); 324 status = IXGBE_ERR_PHY; 325 } 326 327 if (status == IXGBE_SUCCESS) { 328 /* 329 * Address cycle complete, setup and write the read 330 * command 331 */ 332 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 333 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 334 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 335 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 336 337 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 338 339 /* 340 * Check every 10 usec to see if the address cycle 341 * completed. The MDI Command bit will clear when the 342 * operation is complete 343 */ 344 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 345 usec_delay(10); 346 347 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 348 349 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 350 break; 351 } 352 353 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 354 DEBUGOUT("PHY read command didn't complete\n"); 355 status = IXGBE_ERR_PHY; 356 } else { 357 /* 358 * Read operation is complete. Get the data 359 * from MSRWD 360 */ 361 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 362 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 363 *phy_data = (u16)(data); 364 } 365 } 366 367 ixgbe_release_swfw_sync(hw, gssr); 368 } 369 370 return status; 371 } 372 373 /** 374 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 375 * @hw: pointer to hardware structure 376 * @reg_addr: 32 bit PHY register to write 377 * @device_type: 5 bit device type 378 * @phy_data: Data to write to the PHY register 379 **/ 380 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 381 u32 device_type, u16 phy_data) 382 { 383 u32 command; 384 u32 i; 385 s32 status = IXGBE_SUCCESS; 386 u16 gssr; 387 388 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 389 390 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 391 gssr = IXGBE_GSSR_PHY1_SM; 392 else 393 gssr = IXGBE_GSSR_PHY0_SM; 394 395 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 396 status = IXGBE_ERR_SWFW_SYNC; 397 398 if (status == IXGBE_SUCCESS) { 399 /* Put the data in the MDI single read and write data register*/ 400 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 401 402 /* Setup and write the address cycle command */ 403 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 404 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 405 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 406 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 407 408 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 409 410 /* 411 * Check every 10 usec to see if the address cycle completed. 412 * The MDI Command bit will clear when the operation is 413 * complete 414 */ 415 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 416 usec_delay(10); 417 418 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 419 420 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 421 break; 422 } 423 424 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 425 DEBUGOUT("PHY address cmd didn't complete\n"); 426 status = IXGBE_ERR_PHY; 427 } 428 429 if (status == IXGBE_SUCCESS) { 430 /* 431 * Address cycle complete, setup and write the write 432 * command 433 */ 434 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 435 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 436 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 437 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 438 439 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 440 441 /* 442 * Check every 10 usec to see if the address cycle 443 * completed. The MDI Command bit will clear when the 444 * operation is complete 445 */ 446 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 447 usec_delay(10); 448 449 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 450 451 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 452 break; 453 } 454 455 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 456 DEBUGOUT("PHY address cmd didn't complete\n"); 457 status = IXGBE_ERR_PHY; 458 } 459 } 460 461 ixgbe_release_swfw_sync(hw, gssr); 462 } 463 464 return status; 465 } 466 467 /** 468 * ixgbe_setup_phy_link_generic - Set and restart autoneg 469 * @hw: pointer to hardware structure 470 * 471 * Restart autonegotiation and PHY and waits for completion. 472 **/ 473 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 474 { 475 s32 status = IXGBE_SUCCESS; 476 u32 time_out; 477 u32 max_time_out = 10; 478 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 479 bool autoneg = FALSE; 480 ixgbe_link_speed speed; 481 482 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 483 484 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 485 486 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 487 /* Set or unset auto-negotiation 10G advertisement */ 488 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 489 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 490 &autoneg_reg); 491 492 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 493 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 494 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 495 496 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 497 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 498 autoneg_reg); 499 } 500 501 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 502 /* Set or unset auto-negotiation 1G advertisement */ 503 hw->phy.ops.read_reg(hw, 504 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 505 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 506 &autoneg_reg); 507 508 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 509 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 510 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 511 512 hw->phy.ops.write_reg(hw, 513 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 514 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 515 autoneg_reg); 516 } 517 518 if (speed & IXGBE_LINK_SPEED_100_FULL) { 519 /* Set or unset auto-negotiation 100M advertisement */ 520 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 521 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 522 &autoneg_reg); 523 524 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 525 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 526 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 527 528 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 529 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 530 autoneg_reg); 531 } 532 533 /* Restart PHY autonegotiation and wait for completion */ 534 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 535 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 536 537 autoneg_reg |= IXGBE_MII_RESTART; 538 539 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 540 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 541 542 /* Wait for autonegotiation to finish */ 543 for (time_out = 0; time_out < max_time_out; time_out++) { 544 usec_delay(10); 545 /* Restart PHY autonegotiation and wait for completion */ 546 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 547 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 548 &autoneg_reg); 549 550 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 551 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 552 break; 553 } 554 } 555 556 if (time_out == max_time_out) { 557 status = IXGBE_ERR_LINK_SETUP; 558 DEBUGOUT("ixgbe_setup_phy_link_generic: time out"); 559 } 560 561 return status; 562 } 563 564 /** 565 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 566 * @hw: pointer to hardware structure 567 * @speed: new link speed 568 * @autoneg: TRUE if autonegotiation enabled 569 **/ 570 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 571 ixgbe_link_speed speed, 572 bool autoneg, 573 bool autoneg_wait_to_complete) 574 { 575 UNREFERENCED_PARAMETER(autoneg); 576 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 577 578 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 579 580 /* 581 * Clear autoneg_advertised and set new values based on input link 582 * speed. 583 */ 584 hw->phy.autoneg_advertised = 0; 585 586 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 587 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 588 589 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 590 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 591 592 if (speed & IXGBE_LINK_SPEED_100_FULL) 593 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 594 595 /* Setup link based on the new speed settings */ 596 hw->phy.ops.setup_link(hw); 597 598 return IXGBE_SUCCESS; 599 } 600 601 /** 602 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 603 * @hw: pointer to hardware structure 604 * @speed: pointer to link speed 605 * @autoneg: boolean auto-negotiation value 606 * 607 * Determines the link capabilities by reading the AUTOC register. 608 **/ 609 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 610 ixgbe_link_speed *speed, 611 bool *autoneg) 612 { 613 s32 status = IXGBE_ERR_LINK_SETUP; 614 u16 speed_ability; 615 616 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 617 618 *speed = 0; 619 *autoneg = TRUE; 620 621 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 622 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 623 &speed_ability); 624 625 if (status == IXGBE_SUCCESS) { 626 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 627 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 628 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 629 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 630 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 631 *speed |= IXGBE_LINK_SPEED_100_FULL; 632 } 633 634 return status; 635 } 636 637 /** 638 * ixgbe_check_phy_link_tnx - Determine link and speed status 639 * @hw: pointer to hardware structure 640 * 641 * Reads the VS1 register to determine if link is up and the current speed for 642 * the PHY. 643 **/ 644 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 645 bool *link_up) 646 { 647 s32 status = IXGBE_SUCCESS; 648 u32 time_out; 649 u32 max_time_out = 10; 650 u16 phy_link = 0; 651 u16 phy_speed = 0; 652 u16 phy_data = 0; 653 654 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 655 656 /* Initialize speed and link to default case */ 657 *link_up = FALSE; 658 *speed = IXGBE_LINK_SPEED_10GB_FULL; 659 660 /* 661 * Check current speed and link status of the PHY register. 662 * This is a vendor specific register and may have to 663 * be changed for other copper PHYs. 664 */ 665 for (time_out = 0; time_out < max_time_out; time_out++) { 666 usec_delay(10); 667 status = hw->phy.ops.read_reg(hw, 668 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 669 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 670 &phy_data); 671 phy_link = phy_data & 672 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 673 phy_speed = phy_data & 674 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 675 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 676 *link_up = TRUE; 677 if (phy_speed == 678 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 679 *speed = IXGBE_LINK_SPEED_1GB_FULL; 680 break; 681 } 682 } 683 684 return status; 685 } 686 687 /** 688 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 689 * @hw: pointer to hardware structure 690 * 691 * Restart autonegotiation and PHY and waits for completion. 692 **/ 693 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 694 { 695 s32 status = IXGBE_SUCCESS; 696 u32 time_out; 697 u32 max_time_out = 10; 698 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 699 bool autoneg = FALSE; 700 ixgbe_link_speed speed; 701 702 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 703 704 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 705 706 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 707 /* Set or unset auto-negotiation 10G advertisement */ 708 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 709 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 710 &autoneg_reg); 711 712 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 713 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 714 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 715 716 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 717 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 718 autoneg_reg); 719 } 720 721 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 722 /* Set or unset auto-negotiation 1G advertisement */ 723 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 724 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 725 &autoneg_reg); 726 727 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 728 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 729 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 730 731 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 732 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 733 autoneg_reg); 734 } 735 736 if (speed & IXGBE_LINK_SPEED_100_FULL) { 737 /* Set or unset auto-negotiation 100M advertisement */ 738 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 739 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 740 &autoneg_reg); 741 742 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 743 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 744 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 745 746 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 747 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 748 autoneg_reg); 749 } 750 751 /* Restart PHY autonegotiation and wait for completion */ 752 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 753 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 754 755 autoneg_reg |= IXGBE_MII_RESTART; 756 757 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 758 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 759 760 /* Wait for autonegotiation to finish */ 761 for (time_out = 0; time_out < max_time_out; time_out++) { 762 usec_delay(10); 763 /* Restart PHY autonegotiation and wait for completion */ 764 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 765 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 766 &autoneg_reg); 767 768 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 769 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 770 break; 771 } 772 } 773 774 if (time_out == max_time_out) { 775 status = IXGBE_ERR_LINK_SETUP; 776 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 777 } 778 779 return status; 780 } 781 782 /** 783 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 784 * @hw: pointer to hardware structure 785 * @firmware_version: pointer to the PHY Firmware Version 786 **/ 787 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 788 u16 *firmware_version) 789 { 790 s32 status = IXGBE_SUCCESS; 791 792 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 793 794 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 795 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 796 firmware_version); 797 798 return status; 799 } 800 801 /** 802 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 803 * @hw: pointer to hardware structure 804 * @firmware_version: pointer to the PHY Firmware Version 805 **/ 806 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 807 u16 *firmware_version) 808 { 809 s32 status = IXGBE_SUCCESS; 810 811 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 812 813 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 814 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 815 firmware_version); 816 817 return status; 818 } 819 820 /** 821 * ixgbe_reset_phy_nl - Performs a PHY reset 822 * @hw: pointer to hardware structure 823 **/ 824 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 825 { 826 u16 phy_offset, control, eword, edata, block_crc; 827 bool end_data = FALSE; 828 u16 list_offset, data_offset; 829 u16 phy_data = 0; 830 s32 ret_val = IXGBE_SUCCESS; 831 u32 i; 832 833 DEBUGFUNC("ixgbe_reset_phy_nl"); 834 835 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 836 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 837 838 /* reset the PHY and poll for completion */ 839 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 840 IXGBE_MDIO_PHY_XS_DEV_TYPE, 841 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 842 843 for (i = 0; i < 100; i++) { 844 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 845 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 846 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 847 break; 848 msec_delay(10); 849 } 850 851 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 852 DEBUGOUT("PHY reset did not complete.\n"); 853 ret_val = IXGBE_ERR_PHY; 854 goto out; 855 } 856 857 /* Get init offsets */ 858 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 859 &data_offset); 860 if (ret_val != IXGBE_SUCCESS) 861 goto out; 862 863 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 864 data_offset++; 865 while (!end_data) { 866 /* 867 * Read control word from PHY init contents offset 868 */ 869 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 870 control = (eword & IXGBE_CONTROL_MASK_NL) >> 871 IXGBE_CONTROL_SHIFT_NL; 872 edata = eword & IXGBE_DATA_MASK_NL; 873 switch (control) { 874 case IXGBE_DELAY_NL: 875 data_offset++; 876 DEBUGOUT1("DELAY: %d MS\n", edata); 877 msec_delay(edata); 878 break; 879 case IXGBE_DATA_NL: 880 DEBUGOUT("DATA: \n"); 881 data_offset++; 882 hw->eeprom.ops.read(hw, data_offset++, 883 &phy_offset); 884 for (i = 0; i < edata; i++) { 885 hw->eeprom.ops.read(hw, data_offset, &eword); 886 hw->phy.ops.write_reg(hw, phy_offset, 887 IXGBE_TWINAX_DEV, eword); 888 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 889 phy_offset); 890 data_offset++; 891 phy_offset++; 892 } 893 break; 894 case IXGBE_CONTROL_NL: 895 data_offset++; 896 DEBUGOUT("CONTROL: \n"); 897 if (edata == IXGBE_CONTROL_EOL_NL) { 898 DEBUGOUT("EOL\n"); 899 end_data = TRUE; 900 } else if (edata == IXGBE_CONTROL_SOL_NL) { 901 DEBUGOUT("SOL\n"); 902 } else { 903 DEBUGOUT("Bad control value\n"); 904 ret_val = IXGBE_ERR_PHY; 905 goto out; 906 } 907 break; 908 default: 909 DEBUGOUT("Bad control type\n"); 910 ret_val = IXGBE_ERR_PHY; 911 goto out; 912 } 913 } 914 915 out: 916 return ret_val; 917 } 918 919 /** 920 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 921 * @hw: pointer to hardware structure 922 * 923 * Searches for and identifies the SFP module and assigns appropriate PHY type. 924 **/ 925 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 926 { 927 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 928 u32 vendor_oui = 0; 929 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 930 u8 identifier = 0; 931 u8 comp_codes_1g = 0; 932 u8 comp_codes_10g = 0; 933 u8 oui_bytes[3] = {0, 0, 0}; 934 u8 cable_tech = 0; 935 u8 cable_spec = 0; 936 u16 enforce_sfp = 0; 937 938 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 939 940 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 941 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 942 status = IXGBE_ERR_SFP_NOT_PRESENT; 943 goto out; 944 } 945 946 status = hw->phy.ops.read_i2c_eeprom(hw, 947 IXGBE_SFF_IDENTIFIER, 948 &identifier); 949 950 if (status == IXGBE_ERR_SWFW_SYNC || 951 status == IXGBE_ERR_I2C || 952 status == IXGBE_ERR_SFP_NOT_PRESENT) 953 goto err_read_i2c_eeprom; 954 955 /* LAN ID is needed for sfp_type determination */ 956 hw->mac.ops.set_lan_id(hw); 957 958 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 959 hw->phy.type = ixgbe_phy_sfp_unsupported; 960 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 961 } else { 962 status = hw->phy.ops.read_i2c_eeprom(hw, 963 IXGBE_SFF_1GBE_COMP_CODES, 964 &comp_codes_1g); 965 966 if (status == IXGBE_ERR_SWFW_SYNC || 967 status == IXGBE_ERR_I2C || 968 status == IXGBE_ERR_SFP_NOT_PRESENT) 969 goto err_read_i2c_eeprom; 970 971 status = hw->phy.ops.read_i2c_eeprom(hw, 972 IXGBE_SFF_10GBE_COMP_CODES, 973 &comp_codes_10g); 974 975 if (status == IXGBE_ERR_SWFW_SYNC || 976 status == IXGBE_ERR_I2C || 977 status == IXGBE_ERR_SFP_NOT_PRESENT) 978 goto err_read_i2c_eeprom; 979 status = hw->phy.ops.read_i2c_eeprom(hw, 980 IXGBE_SFF_CABLE_TECHNOLOGY, 981 &cable_tech); 982 983 if (status == IXGBE_ERR_SWFW_SYNC || 984 status == IXGBE_ERR_I2C || 985 status == IXGBE_ERR_SFP_NOT_PRESENT) 986 goto err_read_i2c_eeprom; 987 988 /* ID Module 989 * ========= 990 * 0 SFP_DA_CU 991 * 1 SFP_SR 992 * 2 SFP_LR 993 * 3 SFP_DA_CORE0 - 82599-specific 994 * 4 SFP_DA_CORE1 - 82599-specific 995 * 5 SFP_SR/LR_CORE0 - 82599-specific 996 * 6 SFP_SR/LR_CORE1 - 82599-specific 997 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 998 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 999 * 9 SFP_1g_cu_CORE0 - 82599-specific 1000 * 10 SFP_1g_cu_CORE1 - 82599-specific 1001 */ 1002 if (hw->mac.type == ixgbe_mac_82598EB) { 1003 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1004 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1005 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1006 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1007 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1008 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1009 else 1010 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1011 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1012 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1013 if (hw->bus.lan_id == 0) 1014 hw->phy.sfp_type = 1015 ixgbe_sfp_type_da_cu_core0; 1016 else 1017 hw->phy.sfp_type = 1018 ixgbe_sfp_type_da_cu_core1; 1019 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1020 hw->phy.ops.read_i2c_eeprom( 1021 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1022 &cable_spec); 1023 if (cable_spec & 1024 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1025 if (hw->bus.lan_id == 0) 1026 hw->phy.sfp_type = 1027 ixgbe_sfp_type_da_act_lmt_core0; 1028 else 1029 hw->phy.sfp_type = 1030 ixgbe_sfp_type_da_act_lmt_core1; 1031 } else { 1032 hw->phy.sfp_type = 1033 ixgbe_sfp_type_unknown; 1034 } 1035 } else if (comp_codes_10g & 1036 (IXGBE_SFF_10GBASESR_CAPABLE | 1037 IXGBE_SFF_10GBASELR_CAPABLE)) { 1038 if (hw->bus.lan_id == 0) 1039 hw->phy.sfp_type = 1040 ixgbe_sfp_type_srlr_core0; 1041 else 1042 hw->phy.sfp_type = 1043 ixgbe_sfp_type_srlr_core1; 1044 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1045 if (hw->bus.lan_id == 0) 1046 hw->phy.sfp_type = 1047 ixgbe_sfp_type_1g_cu_core0; 1048 else 1049 hw->phy.sfp_type = 1050 ixgbe_sfp_type_1g_cu_core1; 1051 } else { 1052 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1053 } 1054 } 1055 1056 if (hw->phy.sfp_type != stored_sfp_type) 1057 hw->phy.sfp_setup_needed = TRUE; 1058 1059 /* Determine if the SFP+ PHY is dual speed or not. */ 1060 hw->phy.multispeed_fiber = FALSE; 1061 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1062 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1063 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1064 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1065 hw->phy.multispeed_fiber = TRUE; 1066 1067 /* Determine PHY vendor */ 1068 if (hw->phy.type != ixgbe_phy_nl) { 1069 hw->phy.id = identifier; 1070 status = hw->phy.ops.read_i2c_eeprom(hw, 1071 IXGBE_SFF_VENDOR_OUI_BYTE0, 1072 &oui_bytes[0]); 1073 1074 if (status == IXGBE_ERR_SWFW_SYNC || 1075 status == IXGBE_ERR_I2C || 1076 status == IXGBE_ERR_SFP_NOT_PRESENT) 1077 goto err_read_i2c_eeprom; 1078 1079 status = hw->phy.ops.read_i2c_eeprom(hw, 1080 IXGBE_SFF_VENDOR_OUI_BYTE1, 1081 &oui_bytes[1]); 1082 1083 if (status == IXGBE_ERR_SWFW_SYNC || 1084 status == IXGBE_ERR_I2C || 1085 status == IXGBE_ERR_SFP_NOT_PRESENT) 1086 goto err_read_i2c_eeprom; 1087 1088 status = hw->phy.ops.read_i2c_eeprom(hw, 1089 IXGBE_SFF_VENDOR_OUI_BYTE2, 1090 &oui_bytes[2]); 1091 1092 if (status == IXGBE_ERR_SWFW_SYNC || 1093 status == IXGBE_ERR_I2C || 1094 status == IXGBE_ERR_SFP_NOT_PRESENT) 1095 goto err_read_i2c_eeprom; 1096 1097 vendor_oui = 1098 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1099 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1100 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1101 1102 switch (vendor_oui) { 1103 case IXGBE_SFF_VENDOR_OUI_TYCO: 1104 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1105 hw->phy.type = 1106 ixgbe_phy_sfp_passive_tyco; 1107 break; 1108 case IXGBE_SFF_VENDOR_OUI_FTL: 1109 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1110 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1111 else 1112 hw->phy.type = ixgbe_phy_sfp_ftl; 1113 break; 1114 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1115 hw->phy.type = ixgbe_phy_sfp_avago; 1116 break; 1117 case IXGBE_SFF_VENDOR_OUI_INTEL: 1118 hw->phy.type = ixgbe_phy_sfp_intel; 1119 break; 1120 default: 1121 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1122 hw->phy.type = 1123 ixgbe_phy_sfp_passive_unknown; 1124 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1125 hw->phy.type = 1126 ixgbe_phy_sfp_active_unknown; 1127 else 1128 hw->phy.type = ixgbe_phy_sfp_unknown; 1129 break; 1130 } 1131 } 1132 1133 /* Allow any DA cable vendor */ 1134 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1135 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1136 status = IXGBE_SUCCESS; 1137 goto out; 1138 } 1139 1140 /* Verify supported 1G SFP modules */ 1141 if (comp_codes_10g == 0 && 1142 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1143 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) { 1144 hw->phy.type = ixgbe_phy_sfp_unsupported; 1145 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1146 goto out; 1147 } 1148 1149 /* Anything else 82598-based is supported */ 1150 if (hw->mac.type == ixgbe_mac_82598EB) { 1151 status = IXGBE_SUCCESS; 1152 goto out; 1153 } 1154 1155 ixgbe_get_device_caps(hw, &enforce_sfp); 1156 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1157 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || 1158 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) { 1159 /* Make sure we're a supported PHY type */ 1160 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1161 status = IXGBE_SUCCESS; 1162 } else { 1163 DEBUGOUT("SFP+ module not supported\n"); 1164 hw->phy.type = ixgbe_phy_sfp_unsupported; 1165 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1166 } 1167 } else { 1168 status = IXGBE_SUCCESS; 1169 } 1170 } 1171 1172 out: 1173 return status; 1174 1175 err_read_i2c_eeprom: 1176 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1177 if (hw->phy.type != ixgbe_phy_nl) { 1178 hw->phy.id = 0; 1179 hw->phy.type = ixgbe_phy_unknown; 1180 } 1181 return IXGBE_ERR_SFP_NOT_PRESENT; 1182 } 1183 1184 /** 1185 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1186 * @hw: pointer to hardware structure 1187 * @list_offset: offset to the SFP ID list 1188 * @data_offset: offset to the SFP data block 1189 * 1190 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1191 * so it returns the offsets to the phy init sequence block. 1192 **/ 1193 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1194 u16 *list_offset, 1195 u16 *data_offset) 1196 { 1197 u16 sfp_id; 1198 u16 sfp_type = hw->phy.sfp_type; 1199 1200 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1201 1202 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1203 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1204 1205 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1206 return IXGBE_ERR_SFP_NOT_PRESENT; 1207 1208 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1209 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1210 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1211 1212 /* 1213 * Limiting active cables and 1G Phys must be initialized as 1214 * SR modules 1215 */ 1216 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1217 sfp_type == ixgbe_sfp_type_1g_cu_core0) 1218 sfp_type = ixgbe_sfp_type_srlr_core0; 1219 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1220 sfp_type == ixgbe_sfp_type_1g_cu_core1) 1221 sfp_type = ixgbe_sfp_type_srlr_core1; 1222 1223 /* Read offset to PHY init contents */ 1224 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1225 1226 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1227 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1228 1229 /* Shift offset to first ID word */ 1230 (*list_offset)++; 1231 1232 /* 1233 * Find the matching SFP ID in the EEPROM 1234 * and program the init sequence 1235 */ 1236 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1237 1238 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1239 if (sfp_id == sfp_type) { 1240 (*list_offset)++; 1241 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1242 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1243 DEBUGOUT("SFP+ module not supported\n"); 1244 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1245 } else { 1246 break; 1247 } 1248 } else { 1249 (*list_offset) += 2; 1250 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1251 return IXGBE_ERR_PHY; 1252 } 1253 } 1254 1255 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1256 DEBUGOUT("No matching SFP+ module found\n"); 1257 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1258 } 1259 1260 return IXGBE_SUCCESS; 1261 } 1262 1263 /** 1264 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1265 * @hw: pointer to hardware structure 1266 * @byte_offset: EEPROM byte offset to read 1267 * @eeprom_data: value read 1268 * 1269 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1270 **/ 1271 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1272 u8 *eeprom_data) 1273 { 1274 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1275 1276 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1277 IXGBE_I2C_EEPROM_DEV_ADDR, 1278 eeprom_data); 1279 } 1280 1281 /** 1282 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1283 * @hw: pointer to hardware structure 1284 * @byte_offset: EEPROM byte offset to write 1285 * @eeprom_data: value to write 1286 * 1287 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1288 **/ 1289 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1290 u8 eeprom_data) 1291 { 1292 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1293 1294 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1295 IXGBE_I2C_EEPROM_DEV_ADDR, 1296 eeprom_data); 1297 } 1298 1299 /** 1300 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1301 * @hw: pointer to hardware structure 1302 * @byte_offset: byte offset to read 1303 * @data: value read 1304 * 1305 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1306 * a specified deivce address. 1307 **/ 1308 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1309 u8 dev_addr, u8 *data) 1310 { 1311 s32 status = IXGBE_SUCCESS; 1312 u32 max_retry = 10; 1313 u32 retry = 0; 1314 u16 swfw_mask = 0; 1315 bool nack = 1; 1316 1317 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1318 1319 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1320 swfw_mask = IXGBE_GSSR_PHY1_SM; 1321 else 1322 swfw_mask = IXGBE_GSSR_PHY0_SM; 1323 1324 do { 1325 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1326 status = IXGBE_ERR_SWFW_SYNC; 1327 goto read_byte_out; 1328 } 1329 1330 ixgbe_i2c_start(hw); 1331 1332 /* Device Address and write indication */ 1333 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1334 if (status != IXGBE_SUCCESS) 1335 goto fail; 1336 1337 status = ixgbe_get_i2c_ack(hw); 1338 if (status != IXGBE_SUCCESS) 1339 goto fail; 1340 1341 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1342 if (status != IXGBE_SUCCESS) 1343 goto fail; 1344 1345 status = ixgbe_get_i2c_ack(hw); 1346 if (status != IXGBE_SUCCESS) 1347 goto fail; 1348 1349 ixgbe_i2c_start(hw); 1350 1351 /* Device Address and read indication */ 1352 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1353 if (status != IXGBE_SUCCESS) 1354 goto fail; 1355 1356 status = ixgbe_get_i2c_ack(hw); 1357 if (status != IXGBE_SUCCESS) 1358 goto fail; 1359 1360 status = ixgbe_clock_in_i2c_byte(hw, data); 1361 if (status != IXGBE_SUCCESS) 1362 goto fail; 1363 1364 status = ixgbe_clock_out_i2c_bit(hw, nack); 1365 if (status != IXGBE_SUCCESS) 1366 goto fail; 1367 1368 ixgbe_i2c_stop(hw); 1369 break; 1370 1371 fail: 1372 ixgbe_release_swfw_sync(hw, swfw_mask); 1373 msec_delay(100); 1374 ixgbe_i2c_bus_clear(hw); 1375 retry++; 1376 if (retry < max_retry) 1377 DEBUGOUT("I2C byte read error - Retrying.\n"); 1378 else 1379 DEBUGOUT("I2C byte read error.\n"); 1380 1381 } while (retry < max_retry); 1382 1383 ixgbe_release_swfw_sync(hw, swfw_mask); 1384 1385 read_byte_out: 1386 return status; 1387 } 1388 1389 /** 1390 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1391 * @hw: pointer to hardware structure 1392 * @byte_offset: byte offset to write 1393 * @data: value to write 1394 * 1395 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1396 * a specified device address. 1397 **/ 1398 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1399 u8 dev_addr, u8 data) 1400 { 1401 s32 status = IXGBE_SUCCESS; 1402 u32 max_retry = 2; 1403 u32 retry = 0; 1404 u16 swfw_mask = 0; 1405 1406 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1407 1408 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1409 swfw_mask = IXGBE_GSSR_PHY1_SM; 1410 else 1411 swfw_mask = IXGBE_GSSR_PHY0_SM; 1412 1413 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1414 status = IXGBE_ERR_SWFW_SYNC; 1415 goto write_byte_out; 1416 } 1417 1418 do { 1419 ixgbe_i2c_start(hw); 1420 1421 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1422 if (status != IXGBE_SUCCESS) 1423 goto fail; 1424 1425 status = ixgbe_get_i2c_ack(hw); 1426 if (status != IXGBE_SUCCESS) 1427 goto fail; 1428 1429 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1430 if (status != IXGBE_SUCCESS) 1431 goto fail; 1432 1433 status = ixgbe_get_i2c_ack(hw); 1434 if (status != IXGBE_SUCCESS) 1435 goto fail; 1436 1437 status = ixgbe_clock_out_i2c_byte(hw, data); 1438 if (status != IXGBE_SUCCESS) 1439 goto fail; 1440 1441 status = ixgbe_get_i2c_ack(hw); 1442 if (status != IXGBE_SUCCESS) 1443 goto fail; 1444 1445 ixgbe_i2c_stop(hw); 1446 break; 1447 1448 fail: 1449 ixgbe_i2c_bus_clear(hw); 1450 retry++; 1451 if (retry < max_retry) 1452 DEBUGOUT("I2C byte write error - Retrying.\n"); 1453 else 1454 DEBUGOUT("I2C byte write error.\n"); 1455 } while (retry < max_retry); 1456 1457 ixgbe_release_swfw_sync(hw, swfw_mask); 1458 1459 write_byte_out: 1460 return status; 1461 } 1462 1463 /** 1464 * ixgbe_i2c_start - Sets I2C start condition 1465 * @hw: pointer to hardware structure 1466 * 1467 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1468 **/ 1469 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1470 { 1471 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1472 1473 DEBUGFUNC("ixgbe_i2c_start"); 1474 1475 /* Start condition must begin with data and clock high */ 1476 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1477 ixgbe_raise_i2c_clk(hw, &i2cctl); 1478 1479 /* Setup time for start condition (4.7us) */ 1480 usec_delay(IXGBE_I2C_T_SU_STA); 1481 1482 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1483 1484 /* Hold time for start condition (4us) */ 1485 usec_delay(IXGBE_I2C_T_HD_STA); 1486 1487 ixgbe_lower_i2c_clk(hw, &i2cctl); 1488 1489 /* Minimum low period of clock is 4.7 us */ 1490 usec_delay(IXGBE_I2C_T_LOW); 1491 1492 } 1493 1494 /** 1495 * ixgbe_i2c_stop - Sets I2C stop condition 1496 * @hw: pointer to hardware structure 1497 * 1498 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1499 **/ 1500 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1501 { 1502 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1503 1504 DEBUGFUNC("ixgbe_i2c_stop"); 1505 1506 /* Stop condition must begin with data low and clock high */ 1507 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1508 ixgbe_raise_i2c_clk(hw, &i2cctl); 1509 1510 /* Setup time for stop condition (4us) */ 1511 usec_delay(IXGBE_I2C_T_SU_STO); 1512 1513 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1514 1515 /* bus free time between stop and start (4.7us)*/ 1516 usec_delay(IXGBE_I2C_T_BUF); 1517 } 1518 1519 /** 1520 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1521 * @hw: pointer to hardware structure 1522 * @data: data byte to clock in 1523 * 1524 * Clocks in one byte data via I2C data/clock 1525 **/ 1526 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1527 { 1528 s32 status = IXGBE_SUCCESS; 1529 s32 i; 1530 bool bit = 0; 1531 1532 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1533 1534 for (i = 7; i >= 0; i--) { 1535 status = ixgbe_clock_in_i2c_bit(hw, &bit); 1536 *data |= bit << i; 1537 1538 if (status != IXGBE_SUCCESS) 1539 break; 1540 } 1541 1542 return status; 1543 } 1544 1545 /** 1546 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1547 * @hw: pointer to hardware structure 1548 * @data: data byte clocked out 1549 * 1550 * Clocks out one byte data via I2C data/clock 1551 **/ 1552 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1553 { 1554 s32 status = IXGBE_SUCCESS; 1555 s32 i; 1556 u32 i2cctl; 1557 bool bit = 0; 1558 1559 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1560 1561 for (i = 7; i >= 0; i--) { 1562 bit = (data >> i) & 0x1; 1563 status = ixgbe_clock_out_i2c_bit(hw, bit); 1564 1565 if (status != IXGBE_SUCCESS) 1566 break; 1567 } 1568 1569 /* Release SDA line (set high) */ 1570 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1571 i2cctl |= IXGBE_I2C_DATA_OUT; 1572 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1573 1574 return status; 1575 } 1576 1577 /** 1578 * ixgbe_get_i2c_ack - Polls for I2C ACK 1579 * @hw: pointer to hardware structure 1580 * 1581 * Clocks in/out one bit via I2C data/clock 1582 **/ 1583 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1584 { 1585 s32 status; 1586 u32 i = 0; 1587 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1588 u32 timeout = 10; 1589 bool ack = 1; 1590 1591 DEBUGFUNC("ixgbe_get_i2c_ack"); 1592 1593 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1594 1595 if (status != IXGBE_SUCCESS) 1596 goto out; 1597 1598 /* Minimum high period of clock is 4us */ 1599 usec_delay(IXGBE_I2C_T_HIGH); 1600 1601 /* Poll for ACK. Note that ACK in I2C spec is 1602 * transition from 1 to 0 */ 1603 for (i = 0; i < timeout; i++) { 1604 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1605 ack = ixgbe_get_i2c_data(&i2cctl); 1606 1607 usec_delay(1); 1608 if (ack == 0) 1609 break; 1610 } 1611 1612 if (ack == 1) { 1613 DEBUGOUT("I2C ack was not received.\n"); 1614 status = IXGBE_ERR_I2C; 1615 } 1616 1617 ixgbe_lower_i2c_clk(hw, &i2cctl); 1618 1619 /* Minimum low period of clock is 4.7 us */ 1620 usec_delay(IXGBE_I2C_T_LOW); 1621 1622 out: 1623 return status; 1624 } 1625 1626 /** 1627 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1628 * @hw: pointer to hardware structure 1629 * @data: read data value 1630 * 1631 * Clocks in one bit via I2C data/clock 1632 **/ 1633 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1634 { 1635 s32 status; 1636 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1637 1638 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1639 1640 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1641 1642 /* Minimum high period of clock is 4us */ 1643 usec_delay(IXGBE_I2C_T_HIGH); 1644 1645 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1646 *data = ixgbe_get_i2c_data(&i2cctl); 1647 1648 ixgbe_lower_i2c_clk(hw, &i2cctl); 1649 1650 /* Minimum low period of clock is 4.7 us */ 1651 usec_delay(IXGBE_I2C_T_LOW); 1652 1653 return status; 1654 } 1655 1656 /** 1657 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1658 * @hw: pointer to hardware structure 1659 * @data: data value to write 1660 * 1661 * Clocks out one bit via I2C data/clock 1662 **/ 1663 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1664 { 1665 s32 status; 1666 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1667 1668 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1669 1670 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1671 if (status == IXGBE_SUCCESS) { 1672 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1673 1674 /* Minimum high period of clock is 4us */ 1675 usec_delay(IXGBE_I2C_T_HIGH); 1676 1677 ixgbe_lower_i2c_clk(hw, &i2cctl); 1678 1679 /* Minimum low period of clock is 4.7 us. 1680 * This also takes care of the data hold time. 1681 */ 1682 usec_delay(IXGBE_I2C_T_LOW); 1683 } else { 1684 status = IXGBE_ERR_I2C; 1685 DEBUGOUT1("I2C data was not set to %X\n", data); 1686 } 1687 1688 return status; 1689 } 1690 /** 1691 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1692 * @hw: pointer to hardware structure 1693 * @i2cctl: Current value of I2CCTL register 1694 * 1695 * Raises the I2C clock line '0'->'1' 1696 **/ 1697 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1698 { 1699 s32 status = IXGBE_SUCCESS; 1700 1701 DEBUGFUNC("ixgbe_raise_i2c_clk"); 1702 1703 *i2cctl |= IXGBE_I2C_CLK_OUT; 1704 1705 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1706 1707 /* SCL rise time (1000ns) */ 1708 usec_delay(IXGBE_I2C_T_RISE); 1709 1710 return status; 1711 } 1712 1713 /** 1714 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1715 * @hw: pointer to hardware structure 1716 * @i2cctl: Current value of I2CCTL register 1717 * 1718 * Lowers the I2C clock line '1'->'0' 1719 **/ 1720 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1721 { 1722 1723 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1724 1725 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1726 1727 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1728 1729 /* SCL fall time (300ns) */ 1730 usec_delay(IXGBE_I2C_T_FALL); 1731 } 1732 1733 /** 1734 * ixgbe_set_i2c_data - Sets the I2C data bit 1735 * @hw: pointer to hardware structure 1736 * @i2cctl: Current value of I2CCTL register 1737 * @data: I2C data value (0 or 1) to set 1738 * 1739 * Sets the I2C data bit 1740 **/ 1741 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1742 { 1743 s32 status = IXGBE_SUCCESS; 1744 1745 DEBUGFUNC("ixgbe_set_i2c_data"); 1746 1747 if (data) 1748 *i2cctl |= IXGBE_I2C_DATA_OUT; 1749 else 1750 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1751 1752 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1753 1754 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1755 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1756 1757 /* Verify data was set correctly */ 1758 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1759 if (data != ixgbe_get_i2c_data(i2cctl)) { 1760 status = IXGBE_ERR_I2C; 1761 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1762 } 1763 1764 return status; 1765 } 1766 1767 /** 1768 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1769 * @hw: pointer to hardware structure 1770 * @i2cctl: Current value of I2CCTL register 1771 * 1772 * Returns the I2C data bit value 1773 **/ 1774 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1775 { 1776 bool data; 1777 1778 DEBUGFUNC("ixgbe_get_i2c_data"); 1779 1780 if (*i2cctl & IXGBE_I2C_DATA_IN) 1781 data = 1; 1782 else 1783 data = 0; 1784 1785 return data; 1786 } 1787 1788 /** 1789 * ixgbe_i2c_bus_clear - Clears the I2C bus 1790 * @hw: pointer to hardware structure 1791 * 1792 * Clears the I2C bus by sending nine clock pulses. 1793 * Used when data line is stuck low. 1794 **/ 1795 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1796 { 1797 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1798 u32 i; 1799 1800 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1801 1802 ixgbe_i2c_start(hw); 1803 1804 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1805 1806 for (i = 0; i < 9; i++) { 1807 ixgbe_raise_i2c_clk(hw, &i2cctl); 1808 1809 /* Min high period of clock is 4us */ 1810 usec_delay(IXGBE_I2C_T_HIGH); 1811 1812 ixgbe_lower_i2c_clk(hw, &i2cctl); 1813 1814 /* Min low period of clock is 4.7us*/ 1815 usec_delay(IXGBE_I2C_T_LOW); 1816 } 1817 1818 ixgbe_i2c_start(hw); 1819 1820 /* Put the i2c bus back to default state */ 1821 ixgbe_i2c_stop(hw); 1822 } 1823 1824 /** 1825 * ixgbe_tn_check_overtemp - Checks if an overtemp occured. 1826 * @hw: pointer to hardware structure 1827 * 1828 * Checks if the LASI temp alarm status was triggered due to overtemp 1829 **/ 1830 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1831 { 1832 s32 status = IXGBE_SUCCESS; 1833 u16 phy_data = 0; 1834 1835 DEBUGFUNC("ixgbe_tn_check_overtemp"); 1836 1837 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1838 goto out; 1839 1840 /* Check that the LASI temp alarm status was triggered */ 1841 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1842 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1843 1844 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1845 goto out; 1846 1847 status = IXGBE_ERR_OVERTEMP; 1848 out: 1849 return status; 1850 } 1851
Indexes created Thu Sep 25 16:09:42 GMT 2025