ixgbe_phy.c revision 1.2.4.4
1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 292674 2015-12-23 22:45:17Z sbruno $*/ 34 /*$NetBSD: ixgbe_phy.c,v 1.2.4.4 2016/12/05 10:55:17 skrll Exp $*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 52 u8 *sff8472_data); 53 54 /** 55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 56 * @hw: pointer to the hardware structure 57 * @byte: byte to send 58 * 59 * Returns an error code on error. 60 */ 61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 62 { 63 s32 status; 64 65 status = ixgbe_clock_out_i2c_byte(hw, byte); 66 if (status) 67 return status; 68 return ixgbe_get_i2c_ack(hw); 69 } 70 71 /** 72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 73 * @hw: pointer to the hardware structure 74 * @byte: pointer to a u8 to receive the byte 75 * 76 * Returns an error code on error. 77 */ 78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 79 { 80 s32 status; 81 82 status = ixgbe_clock_in_i2c_byte(hw, byte); 83 if (status) 84 return status; 85 /* ACK */ 86 return ixgbe_clock_out_i2c_bit(hw, FALSE); 87 } 88 89 /** 90 * ixgbe_ones_comp_byte_add - Perform one's complement addition 91 * @add1 - addend 1 92 * @add2 - addend 2 93 * 94 * Returns one's complement 8-bit sum. 95 */ 96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 97 { 98 u16 sum = add1 + add2; 99 100 sum = (sum & 0xFF) + (sum >> 8); 101 return sum & 0xFF; 102 } 103 104 /** 105 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 106 * @hw: pointer to the hardware structure 107 * @addr: I2C bus address to read from 108 * @reg: I2C device register to read from 109 * @val: pointer to location to receive read value 110 * @lock: TRUE if to take and release semaphore 111 * 112 * Returns an error code on error. 113 */ 114 static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 115 u16 reg, u16 *val, bool lock) 116 { 117 u32 swfw_mask = hw->phy.phy_semaphore_mask; 118 int max_retry = 10; 119 int retry = 0; 120 u8 csum_byte; 121 u8 high_bits; 122 u8 low_bits; 123 u8 reg_high; 124 u8 csum; 125 126 if (hw->mac.type >= ixgbe_mac_X550) 127 max_retry = 3; 128 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 129 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 130 csum = ~csum; 131 do { 132 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 133 return IXGBE_ERR_SWFW_SYNC; 134 ixgbe_i2c_start(hw); 135 /* Device Address and write indication */ 136 if (ixgbe_out_i2c_byte_ack(hw, addr)) 137 goto fail; 138 /* Write bits 14:8 */ 139 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 140 goto fail; 141 /* Write bits 7:0 */ 142 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 143 goto fail; 144 /* Write csum */ 145 if (ixgbe_out_i2c_byte_ack(hw, csum)) 146 goto fail; 147 /* Re-start condition */ 148 ixgbe_i2c_start(hw); 149 /* Device Address and read indication */ 150 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 151 goto fail; 152 /* Get upper bits */ 153 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 154 goto fail; 155 /* Get low bits */ 156 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 157 goto fail; 158 /* Get csum */ 159 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 160 goto fail; 161 /* NACK */ 162 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 163 goto fail; 164 ixgbe_i2c_stop(hw); 165 if (lock) 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 *val = (high_bits << 8) | low_bits; 168 return 0; 169 170 fail: 171 ixgbe_i2c_bus_clear(hw); 172 if (lock) 173 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 174 retry++; 175 if (retry < max_retry) 176 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 177 else 178 DEBUGOUT("I2C byte read combined error.\n"); 179 } while (retry < max_retry); 180 181 return IXGBE_ERR_I2C; 182 } 183 184 /** 185 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 186 * @hw: pointer to the hardware structure 187 * @addr: I2C bus address to read from 188 * @reg: I2C device register to read from 189 * @val: pointer to location to receive read value 190 * 191 * Returns an error code on error. 192 **/ 193 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 194 u16 reg, u16 *val) 195 { 196 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 197 } 198 199 /** 200 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 201 * @hw: pointer to the hardware structure 202 * @addr: I2C bus address to read from 203 * @reg: I2C device register to read from 204 * @val: pointer to location to receive read value 205 * 206 * Returns an error code on error. 207 **/ 208 static s32 209 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 210 u16 reg, u16 *val) 211 { 212 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 213 } 214 215 /** 216 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 217 * @hw: pointer to the hardware structure 218 * @addr: I2C bus address to write to 219 * @reg: I2C device register to write to 220 * @val: value to write 221 * @lock: TRUE if to take and release semaphore 222 * 223 * Returns an error code on error. 224 */ 225 static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 226 u16 reg, u16 val, bool lock) 227 { 228 u32 swfw_mask = hw->phy.phy_semaphore_mask; 229 int max_retry = 1; 230 int retry = 0; 231 u8 reg_high; 232 u8 csum; 233 234 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 235 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 236 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 237 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 238 csum = ~csum; 239 do { 240 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 241 return IXGBE_ERR_SWFW_SYNC; 242 ixgbe_i2c_start(hw); 243 /* Device Address and write indication */ 244 if (ixgbe_out_i2c_byte_ack(hw, addr)) 245 goto fail; 246 /* Write bits 14:8 */ 247 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 248 goto fail; 249 /* Write bits 7:0 */ 250 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 251 goto fail; 252 /* Write data 15:8 */ 253 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 254 goto fail; 255 /* Write data 7:0 */ 256 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 257 goto fail; 258 /* Write csum */ 259 if (ixgbe_out_i2c_byte_ack(hw, csum)) 260 goto fail; 261 ixgbe_i2c_stop(hw); 262 if (lock) 263 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 264 return 0; 265 266 fail: 267 ixgbe_i2c_bus_clear(hw); 268 if (lock) 269 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 270 retry++; 271 if (retry < max_retry) 272 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 273 else 274 DEBUGOUT("I2C byte write combined error.\n"); 275 } while (retry < max_retry); 276 277 return IXGBE_ERR_I2C; 278 } 279 280 /** 281 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 282 * @hw: pointer to the hardware structure 283 * @addr: I2C bus address to write to 284 * @reg: I2C device register to write to 285 * @val: value to write 286 * 287 * Returns an error code on error. 288 **/ 289 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 290 u8 addr, u16 reg, u16 val) 291 { 292 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 293 } 294 295 /** 296 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 297 * @hw: pointer to the hardware structure 298 * @addr: I2C bus address to write to 299 * @reg: I2C device register to write to 300 * @val: value to write 301 * 302 * Returns an error code on error. 303 **/ 304 static s32 305 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 306 u8 addr, u16 reg, u16 val) 307 { 308 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 309 } 310 311 /** 312 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 313 * @hw: pointer to the hardware structure 314 * 315 * Initialize the function pointers. 316 **/ 317 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 318 { 319 struct ixgbe_phy_info *phy = &hw->phy; 320 321 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 322 323 /* PHY */ 324 phy->ops.identify = ixgbe_identify_phy_generic; 325 phy->ops.reset = ixgbe_reset_phy_generic; 326 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 327 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 328 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 329 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 330 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 331 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 332 phy->ops.check_link = NULL; 333 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 334 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 335 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 336 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 337 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 338 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 339 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 340 phy->ops.identify_sfp = ixgbe_identify_module_generic; 341 phy->sfp_type = ixgbe_sfp_type_unknown; 342 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic; 343 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic; 344 phy->ops.read_i2c_combined_unlocked = 345 ixgbe_read_i2c_combined_generic_unlocked; 346 phy->ops.write_i2c_combined_unlocked = 347 ixgbe_write_i2c_combined_generic_unlocked; 348 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 349 phy->ops.write_i2c_byte_unlocked = 350 ixgbe_write_i2c_byte_generic_unlocked; 351 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 352 return IXGBE_SUCCESS; 353 } 354 355 /** 356 * ixgbe_identify_phy_generic - Get physical layer module 357 * @hw: pointer to hardware structure 358 * 359 * Determines the physical layer module found on the current adapter. 360 **/ 361 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 362 { 363 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 364 u32 phy_addr; 365 u16 ext_ability = 0; 366 367 DEBUGFUNC("ixgbe_identify_phy_generic"); 368 369 if (!hw->phy.phy_semaphore_mask) { 370 if (hw->bus.lan_id) 371 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 372 else 373 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 374 } 375 376 if (hw->phy.type == ixgbe_phy_unknown) { 377 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 378 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 379 hw->phy.addr = phy_addr; 380 ixgbe_get_phy_id(hw); 381 hw->phy.type = 382 ixgbe_get_phy_type_from_id(hw->phy.id); 383 384 if (hw->phy.type == ixgbe_phy_unknown) { 385 hw->phy.ops.read_reg(hw, 386 IXGBE_MDIO_PHY_EXT_ABILITY, 387 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 388 &ext_ability); 389 if (ext_ability & 390 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 391 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 392 hw->phy.type = 393 ixgbe_phy_cu_unknown; 394 else 395 hw->phy.type = 396 ixgbe_phy_generic; 397 } 398 399 status = IXGBE_SUCCESS; 400 break; 401 } 402 } 403 404 /* Certain media types do not have a phy so an address will not 405 * be found and the code will take this path. Caller has to 406 * decide if it is an error or not. 407 */ 408 if (status != IXGBE_SUCCESS) { 409 hw->phy.addr = 0; 410 } 411 } else { 412 status = IXGBE_SUCCESS; 413 } 414 415 return status; 416 } 417 418 /** 419 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 420 * @hw: pointer to the hardware structure 421 * 422 * This function checks the MMNGC.MNG_VETO bit to see if there are 423 * any constraints on link from manageability. For MAC's that don't 424 * have this bit just return faluse since the link can not be blocked 425 * via this method. 426 **/ 427 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 428 { 429 u32 mmngc; 430 431 DEBUGFUNC("ixgbe_check_reset_blocked"); 432 433 /* If we don't have this bit, it can't be blocking */ 434 if (hw->mac.type == ixgbe_mac_82598EB) 435 return FALSE; 436 437 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 438 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 439 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 440 "MNG_VETO bit detected.\n"); 441 return TRUE; 442 } 443 444 return FALSE; 445 } 446 447 /** 448 * ixgbe_validate_phy_addr - Determines phy address is valid 449 * @hw: pointer to hardware structure 450 * 451 **/ 452 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 453 { 454 u16 phy_id = 0; 455 bool valid = FALSE; 456 457 DEBUGFUNC("ixgbe_validate_phy_addr"); 458 459 hw->phy.addr = phy_addr; 460 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 461 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 462 463 if (phy_id != 0xFFFF && phy_id != 0x0) 464 valid = TRUE; 465 466 return valid; 467 } 468 469 /** 470 * ixgbe_get_phy_id - Get the phy type 471 * @hw: pointer to hardware structure 472 * 473 **/ 474 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 475 { 476 u32 status; 477 u16 phy_id_high = 0; 478 u16 phy_id_low = 0; 479 480 DEBUGFUNC("ixgbe_get_phy_id"); 481 482 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 483 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 484 &phy_id_high); 485 486 if (status == IXGBE_SUCCESS) { 487 hw->phy.id = (u32)(phy_id_high << 16); 488 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 489 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 490 &phy_id_low); 491 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 492 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 493 } 494 return status; 495 } 496 497 /** 498 * ixgbe_get_phy_type_from_id - Get the phy type 499 * @hw: pointer to hardware structure 500 * 501 **/ 502 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 503 { 504 enum ixgbe_phy_type phy_type; 505 506 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 507 508 switch (phy_id) { 509 case TN1010_PHY_ID: 510 phy_type = ixgbe_phy_tn; 511 break; 512 case X550_PHY_ID1: 513 case X550_PHY_ID2: 514 case X550_PHY_ID3: 515 case X540_PHY_ID: 516 phy_type = ixgbe_phy_aq; 517 break; 518 case QT2022_PHY_ID: 519 phy_type = ixgbe_phy_qt; 520 break; 521 case ATH_PHY_ID: 522 phy_type = ixgbe_phy_nl; 523 break; 524 case X557_PHY_ID: 525 phy_type = ixgbe_phy_x550em_ext_t; 526 break; 527 default: 528 phy_type = ixgbe_phy_unknown; 529 break; 530 } 531 532 DEBUGOUT1("phy type found is %d\n", phy_type); 533 return phy_type; 534 } 535 536 /** 537 * ixgbe_reset_phy_generic - Performs a PHY reset 538 * @hw: pointer to hardware structure 539 **/ 540 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 541 { 542 u32 i; 543 u16 ctrl = 0; 544 s32 status = IXGBE_SUCCESS; 545 546 DEBUGFUNC("ixgbe_reset_phy_generic"); 547 548 if (hw->phy.type == ixgbe_phy_unknown) 549 status = ixgbe_identify_phy_generic(hw); 550 551 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 552 goto out; 553 554 /* Don't reset PHY if it's shut down due to overtemp. */ 555 if (!hw->phy.reset_if_overtemp && 556 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 557 goto out; 558 559 /* Blocked by MNG FW so bail */ 560 if (ixgbe_check_reset_blocked(hw)) 561 goto out; 562 563 /* 564 * Perform soft PHY reset to the PHY_XS. 565 * This will cause a soft reset to the PHY 566 */ 567 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 568 IXGBE_MDIO_PHY_XS_DEV_TYPE, 569 IXGBE_MDIO_PHY_XS_RESET); 570 571 /* 572 * Poll for reset bit to self-clear indicating reset is complete. 573 * Some PHYs could take up to 3 seconds to complete and need about 574 * 1.7 usec delay after the reset is complete. 575 */ 576 for (i = 0; i < 30; i++) { 577 msec_delay(100); 578 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 579 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 580 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 581 usec_delay(2); 582 break; 583 } 584 } 585 586 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 587 status = IXGBE_ERR_RESET_FAILED; 588 ERROR_REPORT1(IXGBE_ERROR_POLLING, 589 "PHY reset polling failed to complete.\n"); 590 } 591 592 out: 593 return status; 594 } 595 596 /** 597 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 598 * the SWFW lock 599 * @hw: pointer to hardware structure 600 * @reg_addr: 32 bit address of PHY register to read 601 * @phy_data: Pointer to read data from PHY register 602 **/ 603 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 604 u16 *phy_data) 605 { 606 u32 i, data, command; 607 608 /* Setup and write the address cycle command */ 609 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 610 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 611 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 612 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 613 614 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 615 616 /* 617 * Check every 10 usec to see if the address cycle completed. 618 * The MDI Command bit will clear when the operation is 619 * complete 620 */ 621 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 622 usec_delay(10); 623 624 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 625 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 626 break; 627 } 628 629 630 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 631 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 632 return IXGBE_ERR_PHY; 633 } 634 635 /* 636 * Address cycle complete, setup and write the read 637 * command 638 */ 639 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 640 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 641 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 642 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 643 644 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 645 646 /* 647 * Check every 10 usec to see if the address cycle 648 * completed. The MDI Command bit will clear when the 649 * operation is complete 650 */ 651 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 652 usec_delay(10); 653 654 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 655 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 656 break; 657 } 658 659 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 660 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 661 return IXGBE_ERR_PHY; 662 } 663 664 /* 665 * Read operation is complete. Get the data 666 * from MSRWD 667 */ 668 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 669 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 670 *phy_data = (u16)(data); 671 672 return IXGBE_SUCCESS; 673 } 674 675 /** 676 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 677 * using the SWFW lock - this function is needed in most cases 678 * @hw: pointer to hardware structure 679 * @reg_addr: 32 bit address of PHY register to read 680 * @phy_data: Pointer to read data from PHY register 681 **/ 682 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 683 u32 device_type, u16 *phy_data) 684 { 685 s32 status; 686 u32 gssr = hw->phy.phy_semaphore_mask; 687 688 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 689 690 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 691 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 692 phy_data); 693 hw->mac.ops.release_swfw_sync(hw, gssr); 694 } else { 695 status = IXGBE_ERR_SWFW_SYNC; 696 } 697 698 return status; 699 } 700 701 /** 702 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 703 * without SWFW lock 704 * @hw: pointer to hardware structure 705 * @reg_addr: 32 bit PHY register to write 706 * @device_type: 5 bit device type 707 * @phy_data: Data to write to the PHY register 708 **/ 709 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 710 u32 device_type, u16 phy_data) 711 { 712 u32 i, command; 713 714 /* Put the data in the MDI single read and write data register*/ 715 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 716 717 /* Setup and write the address cycle command */ 718 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 719 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 720 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 721 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 722 723 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 724 725 /* 726 * Check every 10 usec to see if the address cycle completed. 727 * The MDI Command bit will clear when the operation is 728 * complete 729 */ 730 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 731 usec_delay(10); 732 733 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 734 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 735 break; 736 } 737 738 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 739 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 740 return IXGBE_ERR_PHY; 741 } 742 743 /* 744 * Address cycle complete, setup and write the write 745 * command 746 */ 747 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 748 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 749 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 750 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 751 752 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 753 754 /* 755 * Check every 10 usec to see if the address cycle 756 * completed. The MDI Command bit will clear when the 757 * operation is complete 758 */ 759 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 760 usec_delay(10); 761 762 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 763 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 764 break; 765 } 766 767 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 768 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 769 return IXGBE_ERR_PHY; 770 } 771 772 return IXGBE_SUCCESS; 773 } 774 775 /** 776 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 777 * using SWFW lock- this function is needed in most cases 778 * @hw: pointer to hardware structure 779 * @reg_addr: 32 bit PHY register to write 780 * @device_type: 5 bit device type 781 * @phy_data: Data to write to the PHY register 782 **/ 783 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 784 u32 device_type, u16 phy_data) 785 { 786 s32 status; 787 u32 gssr = hw->phy.phy_semaphore_mask; 788 789 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 790 791 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 792 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 793 phy_data); 794 hw->mac.ops.release_swfw_sync(hw, gssr); 795 } else { 796 status = IXGBE_ERR_SWFW_SYNC; 797 } 798 799 return status; 800 } 801 802 /** 803 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 804 * @hw: pointer to hardware structure 805 * 806 * Restart auto-negotiation and PHY and waits for completion. 807 **/ 808 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 809 { 810 s32 status = IXGBE_SUCCESS; 811 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 812 bool autoneg = FALSE; 813 ixgbe_link_speed speed; 814 815 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 816 817 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 818 819 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 820 /* Set or unset auto-negotiation 10G advertisement */ 821 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 822 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 823 &autoneg_reg); 824 825 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 826 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 827 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 828 829 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 830 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 831 autoneg_reg); 832 } 833 834 if (hw->mac.type == ixgbe_mac_X550) { 835 if (speed & IXGBE_LINK_SPEED_5GB_FULL) { 836 /* Set or unset auto-negotiation 5G advertisement */ 837 hw->phy.ops.read_reg(hw, 838 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 839 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 840 &autoneg_reg); 841 842 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 843 if (hw->phy.autoneg_advertised & 844 IXGBE_LINK_SPEED_5GB_FULL) 845 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 846 847 hw->phy.ops.write_reg(hw, 848 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 849 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 850 autoneg_reg); 851 } 852 853 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) { 854 /* Set or unset auto-negotiation 2.5G advertisement */ 855 hw->phy.ops.read_reg(hw, 856 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 858 &autoneg_reg); 859 860 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 861 if (hw->phy.autoneg_advertised & 862 IXGBE_LINK_SPEED_2_5GB_FULL) 863 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 864 865 hw->phy.ops.write_reg(hw, 866 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 867 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 868 autoneg_reg); 869 } 870 } 871 872 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 873 /* Set or unset auto-negotiation 1G advertisement */ 874 hw->phy.ops.read_reg(hw, 875 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 876 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 877 &autoneg_reg); 878 879 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 880 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 881 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 882 883 hw->phy.ops.write_reg(hw, 884 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 885 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 886 autoneg_reg); 887 } 888 889 if (speed & IXGBE_LINK_SPEED_100_FULL) { 890 /* Set or unset auto-negotiation 100M advertisement */ 891 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 892 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 893 &autoneg_reg); 894 895 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 896 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 897 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 898 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 899 900 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 901 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 902 autoneg_reg); 903 } 904 905 /* Blocked by MNG FW so don't reset PHY */ 906 if (ixgbe_check_reset_blocked(hw)) 907 return status; 908 909 /* Restart PHY auto-negotiation. */ 910 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 911 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 912 913 autoneg_reg |= IXGBE_MII_RESTART; 914 915 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 916 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 917 918 return status; 919 } 920 921 /** 922 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 923 * @hw: pointer to hardware structure 924 * @speed: new link speed 925 **/ 926 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 927 ixgbe_link_speed speed, 928 bool autoneg_wait_to_complete) 929 { 930 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 931 932 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 933 934 /* 935 * Clear autoneg_advertised and set new values based on input link 936 * speed. 937 */ 938 hw->phy.autoneg_advertised = 0; 939 940 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 941 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 942 943 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 944 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 945 946 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 947 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 948 949 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 950 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 951 952 if (speed & IXGBE_LINK_SPEED_100_FULL) 953 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 954 955 /* Setup link based on the new speed settings */ 956 ixgbe_setup_phy_link(hw); 957 958 return IXGBE_SUCCESS; 959 } 960 961 /** 962 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 963 * @hw: pointer to hardware structure 964 * 965 * Determines the supported link capabilities by reading the PHY auto 966 * negotiation register. 967 **/ 968 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 969 { 970 s32 status; 971 u16 speed_ability; 972 973 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 974 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 975 &speed_ability); 976 if (status) 977 return status; 978 979 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 980 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 981 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 982 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 983 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 984 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 985 986 switch (hw->mac.type) { 987 case ixgbe_mac_X550: 988 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 989 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 990 break; 991 case ixgbe_mac_X550EM_x: 992 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 993 break; 994 default: 995 break; 996 } 997 998 return status; 999 } 1000 1001 /** 1002 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 1003 * @hw: pointer to hardware structure 1004 * @speed: pointer to link speed 1005 * @autoneg: boolean auto-negotiation value 1006 **/ 1007 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 1008 ixgbe_link_speed *speed, 1009 bool *autoneg) 1010 { 1011 s32 status = IXGBE_SUCCESS; 1012 1013 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 1014 1015 *autoneg = TRUE; 1016 if (!hw->phy.speeds_supported) 1017 status = ixgbe_get_copper_speeds_supported(hw); 1018 1019 *speed = hw->phy.speeds_supported; 1020 return status; 1021 } 1022 1023 /** 1024 * ixgbe_check_phy_link_tnx - Determine link and speed status 1025 * @hw: pointer to hardware structure 1026 * 1027 * Reads the VS1 register to determine if link is up and the current speed for 1028 * the PHY. 1029 **/ 1030 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1031 bool *link_up) 1032 { 1033 s32 status = IXGBE_SUCCESS; 1034 u32 time_out; 1035 u32 max_time_out = 10; 1036 u16 phy_link = 0; 1037 u16 phy_speed = 0; 1038 u16 phy_data = 0; 1039 1040 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1041 1042 /* Initialize speed and link to default case */ 1043 *link_up = FALSE; 1044 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1045 1046 /* 1047 * Check current speed and link status of the PHY register. 1048 * This is a vendor specific register and may have to 1049 * be changed for other copper PHYs. 1050 */ 1051 for (time_out = 0; time_out < max_time_out; time_out++) { 1052 usec_delay(10); 1053 status = hw->phy.ops.read_reg(hw, 1054 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1055 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1056 &phy_data); 1057 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1058 phy_speed = phy_data & 1059 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1060 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1061 *link_up = TRUE; 1062 if (phy_speed == 1063 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1064 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1065 break; 1066 } 1067 } 1068 1069 return status; 1070 } 1071 1072 /** 1073 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1074 * @hw: pointer to hardware structure 1075 * 1076 * Restart auto-negotiation and PHY and waits for completion. 1077 **/ 1078 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1079 { 1080 s32 status = IXGBE_SUCCESS; 1081 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1082 bool autoneg = FALSE; 1083 ixgbe_link_speed speed; 1084 1085 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1086 1087 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1088 1089 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1090 /* Set or unset auto-negotiation 10G advertisement */ 1091 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1092 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1093 &autoneg_reg); 1094 1095 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1096 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1097 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1098 1099 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1100 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1101 autoneg_reg); 1102 } 1103 1104 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1105 /* Set or unset auto-negotiation 1G advertisement */ 1106 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1107 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1108 &autoneg_reg); 1109 1110 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1111 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1112 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1113 1114 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1115 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1116 autoneg_reg); 1117 } 1118 1119 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1120 /* Set or unset auto-negotiation 100M advertisement */ 1121 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1122 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1123 &autoneg_reg); 1124 1125 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1126 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1127 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1128 1129 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1130 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1131 autoneg_reg); 1132 } 1133 1134 /* Blocked by MNG FW so don't reset PHY */ 1135 if (ixgbe_check_reset_blocked(hw)) 1136 return status; 1137 1138 /* Restart PHY auto-negotiation. */ 1139 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1140 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1141 1142 autoneg_reg |= IXGBE_MII_RESTART; 1143 1144 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1145 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1146 1147 return status; 1148 } 1149 1150 /** 1151 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1152 * @hw: pointer to hardware structure 1153 * @firmware_version: pointer to the PHY Firmware Version 1154 **/ 1155 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1156 u16 *firmware_version) 1157 { 1158 s32 status; 1159 1160 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1161 1162 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1163 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1164 firmware_version); 1165 1166 return status; 1167 } 1168 1169 /** 1170 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1171 * @hw: pointer to hardware structure 1172 * @firmware_version: pointer to the PHY Firmware Version 1173 **/ 1174 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1175 u16 *firmware_version) 1176 { 1177 s32 status; 1178 1179 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1180 1181 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1182 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1183 firmware_version); 1184 1185 return status; 1186 } 1187 1188 /** 1189 * ixgbe_reset_phy_nl - Performs a PHY reset 1190 * @hw: pointer to hardware structure 1191 **/ 1192 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1193 { 1194 u16 phy_offset, control, eword, edata, block_crc; 1195 bool end_data = FALSE; 1196 u16 list_offset, data_offset; 1197 u16 phy_data = 0; 1198 s32 ret_val = IXGBE_SUCCESS; 1199 u32 i; 1200 1201 DEBUGFUNC("ixgbe_reset_phy_nl"); 1202 1203 /* Blocked by MNG FW so bail */ 1204 if (ixgbe_check_reset_blocked(hw)) 1205 goto out; 1206 1207 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1208 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1209 1210 /* reset the PHY and poll for completion */ 1211 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1212 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1213 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1214 1215 for (i = 0; i < 100; i++) { 1216 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1217 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1218 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1219 break; 1220 msec_delay(10); 1221 } 1222 1223 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1224 DEBUGOUT("PHY reset did not complete.\n"); 1225 ret_val = IXGBE_ERR_PHY; 1226 goto out; 1227 } 1228 1229 /* Get init offsets */ 1230 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1231 &data_offset); 1232 if (ret_val != IXGBE_SUCCESS) 1233 goto out; 1234 1235 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1236 data_offset++; 1237 while (!end_data) { 1238 /* 1239 * Read control word from PHY init contents offset 1240 */ 1241 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1242 if (ret_val) 1243 goto err_eeprom; 1244 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1245 IXGBE_CONTROL_SHIFT_NL; 1246 edata = eword & IXGBE_DATA_MASK_NL; 1247 switch (control) { 1248 case IXGBE_DELAY_NL: 1249 data_offset++; 1250 DEBUGOUT1("DELAY: %d MS\n", edata); 1251 msec_delay(edata); 1252 break; 1253 case IXGBE_DATA_NL: 1254 DEBUGOUT("DATA:\n"); 1255 data_offset++; 1256 ret_val = hw->eeprom.ops.read(hw, data_offset, 1257 &phy_offset); 1258 if (ret_val) 1259 goto err_eeprom; 1260 data_offset++; 1261 for (i = 0; i < edata; i++) { 1262 ret_val = hw->eeprom.ops.read(hw, data_offset, 1263 &eword); 1264 if (ret_val) 1265 goto err_eeprom; 1266 hw->phy.ops.write_reg(hw, phy_offset, 1267 IXGBE_TWINAX_DEV, eword); 1268 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1269 phy_offset); 1270 data_offset++; 1271 phy_offset++; 1272 } 1273 break; 1274 case IXGBE_CONTROL_NL: 1275 data_offset++; 1276 DEBUGOUT("CONTROL:\n"); 1277 if (edata == IXGBE_CONTROL_EOL_NL) { 1278 DEBUGOUT("EOL\n"); 1279 end_data = TRUE; 1280 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1281 DEBUGOUT("SOL\n"); 1282 } else { 1283 DEBUGOUT("Bad control value\n"); 1284 ret_val = IXGBE_ERR_PHY; 1285 goto out; 1286 } 1287 break; 1288 default: 1289 DEBUGOUT("Bad control type\n"); 1290 ret_val = IXGBE_ERR_PHY; 1291 goto out; 1292 } 1293 } 1294 1295 out: 1296 return ret_val; 1297 1298 err_eeprom: 1299 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1300 "eeprom read at offset %d failed", data_offset); 1301 return IXGBE_ERR_PHY; 1302 } 1303 1304 /** 1305 * ixgbe_identify_module_generic - Identifies module type 1306 * @hw: pointer to hardware structure 1307 * 1308 * Determines HW type and calls appropriate function. 1309 **/ 1310 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1311 { 1312 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1313 1314 DEBUGFUNC("ixgbe_identify_module_generic"); 1315 1316 switch (hw->mac.ops.get_media_type(hw)) { 1317 case ixgbe_media_type_fiber: 1318 status = ixgbe_identify_sfp_module_generic(hw); 1319 break; 1320 1321 case ixgbe_media_type_fiber_qsfp: 1322 status = ixgbe_identify_qsfp_module_generic(hw); 1323 break; 1324 1325 default: 1326 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1327 status = IXGBE_ERR_SFP_NOT_PRESENT; 1328 break; 1329 } 1330 1331 return status; 1332 } 1333 1334 /** 1335 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1336 * @hw: pointer to hardware structure 1337 * 1338 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1339 **/ 1340 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1341 { 1342 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1343 u32 vendor_oui = 0; 1344 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1345 u8 identifier = 0; 1346 u8 comp_codes_1g = 0; 1347 u8 comp_codes_10g = 0; 1348 u8 oui_bytes[3] = {0, 0, 0}; 1349 u8 cable_tech = 0; 1350 u8 cable_spec = 0; 1351 u16 enforce_sfp = 0; 1352 1353 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1354 1355 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1356 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1357 status = IXGBE_ERR_SFP_NOT_PRESENT; 1358 goto out; 1359 } 1360 1361 /* LAN ID is needed for I2C access */ 1362 hw->mac.ops.set_lan_id(hw); 1363 1364 status = hw->phy.ops.read_i2c_eeprom(hw, 1365 IXGBE_SFF_IDENTIFIER, 1366 &identifier); 1367 1368 if (status != IXGBE_SUCCESS) 1369 goto err_read_i2c_eeprom; 1370 1371 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1372 hw->phy.type = ixgbe_phy_sfp_unsupported; 1373 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1374 } else { 1375 status = hw->phy.ops.read_i2c_eeprom(hw, 1376 IXGBE_SFF_1GBE_COMP_CODES, 1377 &comp_codes_1g); 1378 1379 if (status != IXGBE_SUCCESS) 1380 goto err_read_i2c_eeprom; 1381 1382 status = hw->phy.ops.read_i2c_eeprom(hw, 1383 IXGBE_SFF_10GBE_COMP_CODES, 1384 &comp_codes_10g); 1385 1386 if (status != IXGBE_SUCCESS) 1387 goto err_read_i2c_eeprom; 1388 status = hw->phy.ops.read_i2c_eeprom(hw, 1389 IXGBE_SFF_CABLE_TECHNOLOGY, 1390 &cable_tech); 1391 1392 if (status != IXGBE_SUCCESS) 1393 goto err_read_i2c_eeprom; 1394 1395 /* ID Module 1396 * ========= 1397 * 0 SFP_DA_CU 1398 * 1 SFP_SR 1399 * 2 SFP_LR 1400 * 3 SFP_DA_CORE0 - 82599-specific 1401 * 4 SFP_DA_CORE1 - 82599-specific 1402 * 5 SFP_SR/LR_CORE0 - 82599-specific 1403 * 6 SFP_SR/LR_CORE1 - 82599-specific 1404 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1405 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1406 * 9 SFP_1g_cu_CORE0 - 82599-specific 1407 * 10 SFP_1g_cu_CORE1 - 82599-specific 1408 * 11 SFP_1g_sx_CORE0 - 82599-specific 1409 * 12 SFP_1g_sx_CORE1 - 82599-specific 1410 */ 1411 if (hw->mac.type == ixgbe_mac_82598EB) { 1412 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1413 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1414 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1415 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1416 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1417 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1418 else 1419 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1420 } else { 1421 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1422 if (hw->bus.lan_id == 0) 1423 hw->phy.sfp_type = 1424 ixgbe_sfp_type_da_cu_core0; 1425 else 1426 hw->phy.sfp_type = 1427 ixgbe_sfp_type_da_cu_core1; 1428 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1429 hw->phy.ops.read_i2c_eeprom( 1430 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1431 &cable_spec); 1432 if (cable_spec & 1433 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1434 if (hw->bus.lan_id == 0) 1435 hw->phy.sfp_type = 1436 ixgbe_sfp_type_da_act_lmt_core0; 1437 else 1438 hw->phy.sfp_type = 1439 ixgbe_sfp_type_da_act_lmt_core1; 1440 } else { 1441 hw->phy.sfp_type = 1442 ixgbe_sfp_type_unknown; 1443 } 1444 } else if (comp_codes_10g & 1445 (IXGBE_SFF_10GBASESR_CAPABLE | 1446 IXGBE_SFF_10GBASELR_CAPABLE)) { 1447 if (hw->bus.lan_id == 0) 1448 hw->phy.sfp_type = 1449 ixgbe_sfp_type_srlr_core0; 1450 else 1451 hw->phy.sfp_type = 1452 ixgbe_sfp_type_srlr_core1; 1453 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1454 if (hw->bus.lan_id == 0) 1455 hw->phy.sfp_type = 1456 ixgbe_sfp_type_1g_cu_core0; 1457 else 1458 hw->phy.sfp_type = 1459 ixgbe_sfp_type_1g_cu_core1; 1460 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1461 if (hw->bus.lan_id == 0) 1462 hw->phy.sfp_type = 1463 ixgbe_sfp_type_1g_sx_core0; 1464 else 1465 hw->phy.sfp_type = 1466 ixgbe_sfp_type_1g_sx_core1; 1467 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1468 if (hw->bus.lan_id == 0) 1469 hw->phy.sfp_type = 1470 ixgbe_sfp_type_1g_lx_core0; 1471 else 1472 hw->phy.sfp_type = 1473 ixgbe_sfp_type_1g_lx_core1; 1474 } else { 1475 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1476 } 1477 } 1478 1479 if (hw->phy.sfp_type != stored_sfp_type) 1480 hw->phy.sfp_setup_needed = TRUE; 1481 1482 /* Determine if the SFP+ PHY is dual speed or not. */ 1483 hw->phy.multispeed_fiber = FALSE; 1484 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1485 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1486 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1487 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1488 hw->phy.multispeed_fiber = TRUE; 1489 1490 /* Determine PHY vendor */ 1491 if (hw->phy.type != ixgbe_phy_nl) { 1492 hw->phy.id = identifier; 1493 status = hw->phy.ops.read_i2c_eeprom(hw, 1494 IXGBE_SFF_VENDOR_OUI_BYTE0, 1495 &oui_bytes[0]); 1496 1497 if (status != IXGBE_SUCCESS) 1498 goto err_read_i2c_eeprom; 1499 1500 status = hw->phy.ops.read_i2c_eeprom(hw, 1501 IXGBE_SFF_VENDOR_OUI_BYTE1, 1502 &oui_bytes[1]); 1503 1504 if (status != IXGBE_SUCCESS) 1505 goto err_read_i2c_eeprom; 1506 1507 status = hw->phy.ops.read_i2c_eeprom(hw, 1508 IXGBE_SFF_VENDOR_OUI_BYTE2, 1509 &oui_bytes[2]); 1510 1511 if (status != IXGBE_SUCCESS) 1512 goto err_read_i2c_eeprom; 1513 1514 vendor_oui = 1515 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1516 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1517 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1518 1519 switch (vendor_oui) { 1520 case IXGBE_SFF_VENDOR_OUI_TYCO: 1521 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1522 hw->phy.type = 1523 ixgbe_phy_sfp_passive_tyco; 1524 break; 1525 case IXGBE_SFF_VENDOR_OUI_FTL: 1526 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1527 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1528 else 1529 hw->phy.type = ixgbe_phy_sfp_ftl; 1530 break; 1531 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1532 hw->phy.type = ixgbe_phy_sfp_avago; 1533 break; 1534 case IXGBE_SFF_VENDOR_OUI_INTEL: 1535 hw->phy.type = ixgbe_phy_sfp_intel; 1536 break; 1537 default: 1538 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1539 hw->phy.type = 1540 ixgbe_phy_sfp_passive_unknown; 1541 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1542 hw->phy.type = 1543 ixgbe_phy_sfp_active_unknown; 1544 else 1545 hw->phy.type = ixgbe_phy_sfp_unknown; 1546 break; 1547 } 1548 } 1549 1550 /* Allow any DA cable vendor */ 1551 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1552 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1553 status = IXGBE_SUCCESS; 1554 goto out; 1555 } 1556 1557 /* Verify supported 1G SFP modules */ 1558 if (comp_codes_10g == 0 && 1559 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1561 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1562 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1563 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1564 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1565 hw->phy.type = ixgbe_phy_sfp_unsupported; 1566 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1567 goto out; 1568 } 1569 1570 /* Anything else 82598-based is supported */ 1571 if (hw->mac.type == ixgbe_mac_82598EB) { 1572 status = IXGBE_SUCCESS; 1573 goto out; 1574 } 1575 1576 ixgbe_get_device_caps(hw, &enforce_sfp); 1577 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1578 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1579 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1580 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1581 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1582 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1583 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1584 /* Make sure we're a supported PHY type */ 1585 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1586 status = IXGBE_SUCCESS; 1587 } else { 1588 if (hw->allow_unsupported_sfp == TRUE) { 1589 EWARN(hw, "WARNING: Intel (R) Network " 1590 "Connections are quality tested " 1591 "using Intel (R) Ethernet Optics." 1592 " Using untested modules is not " 1593 "supported and may cause unstable" 1594 " operation or damage to the " 1595 "module or the adapter. Intel " 1596 "Corporation is not responsible " 1597 "for any harm caused by using " 1598 "untested modules.\n", status); 1599 status = IXGBE_SUCCESS; 1600 } else { 1601 DEBUGOUT("SFP+ module not supported\n"); 1602 hw->phy.type = 1603 ixgbe_phy_sfp_unsupported; 1604 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1605 } 1606 } 1607 } else { 1608 status = IXGBE_SUCCESS; 1609 } 1610 } 1611 1612 out: 1613 return status; 1614 1615 err_read_i2c_eeprom: 1616 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1617 if (hw->phy.type != ixgbe_phy_nl) { 1618 hw->phy.id = 0; 1619 hw->phy.type = ixgbe_phy_unknown; 1620 } 1621 return IXGBE_ERR_SFP_NOT_PRESENT; 1622 } 1623 1624 /** 1625 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1626 * @hw: pointer to hardware structure 1627 * 1628 * Determines physical layer capabilities of the current SFP. 1629 */ 1630 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1631 { 1632 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1633 u8 comp_codes_10g = 0; 1634 u8 comp_codes_1g = 0; 1635 1636 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1637 1638 hw->phy.ops.identify_sfp(hw); 1639 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1640 return physical_layer; 1641 1642 switch (hw->phy.type) { 1643 case ixgbe_phy_sfp_passive_tyco: 1644 case ixgbe_phy_sfp_passive_unknown: 1645 case ixgbe_phy_qsfp_passive_unknown: 1646 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1647 break; 1648 case ixgbe_phy_sfp_ftl_active: 1649 case ixgbe_phy_sfp_active_unknown: 1650 case ixgbe_phy_qsfp_active_unknown: 1651 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1652 break; 1653 case ixgbe_phy_sfp_avago: 1654 case ixgbe_phy_sfp_ftl: 1655 case ixgbe_phy_sfp_intel: 1656 case ixgbe_phy_sfp_unknown: 1657 hw->phy.ops.read_i2c_eeprom(hw, 1658 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1659 hw->phy.ops.read_i2c_eeprom(hw, 1660 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1661 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1662 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1663 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1664 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1665 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1666 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1667 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1668 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1669 break; 1670 case ixgbe_phy_qsfp_intel: 1671 case ixgbe_phy_qsfp_unknown: 1672 hw->phy.ops.read_i2c_eeprom(hw, 1673 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1674 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1675 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1676 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1677 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1678 break; 1679 default: 1680 break; 1681 } 1682 1683 return physical_layer; 1684 } 1685 1686 /** 1687 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1688 * @hw: pointer to hardware structure 1689 * 1690 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1691 **/ 1692 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1693 { 1694 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1695 u32 vendor_oui = 0; 1696 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1697 u8 identifier = 0; 1698 u8 comp_codes_1g = 0; 1699 u8 comp_codes_10g = 0; 1700 u8 oui_bytes[3] = {0, 0, 0}; 1701 u16 enforce_sfp = 0; 1702 u8 connector = 0; 1703 u8 cable_length = 0; 1704 u8 device_tech = 0; 1705 bool active_cable = FALSE; 1706 1707 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1708 1709 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1710 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1711 status = IXGBE_ERR_SFP_NOT_PRESENT; 1712 goto out; 1713 } 1714 1715 /* LAN ID is needed for I2C access */ 1716 hw->mac.ops.set_lan_id(hw); 1717 1718 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1719 &identifier); 1720 1721 if (status != IXGBE_SUCCESS) 1722 goto err_read_i2c_eeprom; 1723 1724 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1725 hw->phy.type = ixgbe_phy_sfp_unsupported; 1726 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1727 goto out; 1728 } 1729 1730 hw->phy.id = identifier; 1731 1732 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1733 &comp_codes_10g); 1734 1735 if (status != IXGBE_SUCCESS) 1736 goto err_read_i2c_eeprom; 1737 1738 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1739 &comp_codes_1g); 1740 1741 if (status != IXGBE_SUCCESS) 1742 goto err_read_i2c_eeprom; 1743 1744 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1745 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1746 if (hw->bus.lan_id == 0) 1747 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1748 else 1749 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1750 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1751 IXGBE_SFF_10GBASELR_CAPABLE)) { 1752 if (hw->bus.lan_id == 0) 1753 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1754 else 1755 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1756 } else { 1757 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1758 active_cable = TRUE; 1759 1760 if (!active_cable) { 1761 /* check for active DA cables that pre-date 1762 * SFF-8436 v3.6 */ 1763 hw->phy.ops.read_i2c_eeprom(hw, 1764 IXGBE_SFF_QSFP_CONNECTOR, 1765 &connector); 1766 1767 hw->phy.ops.read_i2c_eeprom(hw, 1768 IXGBE_SFF_QSFP_CABLE_LENGTH, 1769 &cable_length); 1770 1771 hw->phy.ops.read_i2c_eeprom(hw, 1772 IXGBE_SFF_QSFP_DEVICE_TECH, 1773 &device_tech); 1774 1775 if ((connector == 1776 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1777 (cable_length > 0) && 1778 ((device_tech >> 4) == 1779 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1780 active_cable = TRUE; 1781 } 1782 1783 if (active_cable) { 1784 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1785 if (hw->bus.lan_id == 0) 1786 hw->phy.sfp_type = 1787 ixgbe_sfp_type_da_act_lmt_core0; 1788 else 1789 hw->phy.sfp_type = 1790 ixgbe_sfp_type_da_act_lmt_core1; 1791 } else { 1792 /* unsupported module type */ 1793 hw->phy.type = ixgbe_phy_sfp_unsupported; 1794 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1795 goto out; 1796 } 1797 } 1798 1799 if (hw->phy.sfp_type != stored_sfp_type) 1800 hw->phy.sfp_setup_needed = TRUE; 1801 1802 /* Determine if the QSFP+ PHY is dual speed or not. */ 1803 hw->phy.multispeed_fiber = FALSE; 1804 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1805 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1806 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1807 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1808 hw->phy.multispeed_fiber = TRUE; 1809 1810 /* Determine PHY vendor for optical modules */ 1811 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1812 IXGBE_SFF_10GBASELR_CAPABLE)) { 1813 status = hw->phy.ops.read_i2c_eeprom(hw, 1814 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1815 &oui_bytes[0]); 1816 1817 if (status != IXGBE_SUCCESS) 1818 goto err_read_i2c_eeprom; 1819 1820 status = hw->phy.ops.read_i2c_eeprom(hw, 1821 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1822 &oui_bytes[1]); 1823 1824 if (status != IXGBE_SUCCESS) 1825 goto err_read_i2c_eeprom; 1826 1827 status = hw->phy.ops.read_i2c_eeprom(hw, 1828 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1829 &oui_bytes[2]); 1830 1831 if (status != IXGBE_SUCCESS) 1832 goto err_read_i2c_eeprom; 1833 1834 vendor_oui = 1835 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1836 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1837 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1838 1839 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1840 hw->phy.type = ixgbe_phy_qsfp_intel; 1841 else 1842 hw->phy.type = ixgbe_phy_qsfp_unknown; 1843 1844 ixgbe_get_device_caps(hw, &enforce_sfp); 1845 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1846 /* Make sure we're a supported PHY type */ 1847 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1848 status = IXGBE_SUCCESS; 1849 } else { 1850 if (hw->allow_unsupported_sfp == TRUE) { 1851 EWARN(hw, "WARNING: Intel (R) Network " 1852 "Connections are quality tested " 1853 "using Intel (R) Ethernet Optics." 1854 " Using untested modules is not " 1855 "supported and may cause unstable" 1856 " operation or damage to the " 1857 "module or the adapter. Intel " 1858 "Corporation is not responsible " 1859 "for any harm caused by using " 1860 "untested modules.\n", status); 1861 status = IXGBE_SUCCESS; 1862 } else { 1863 DEBUGOUT("QSFP module not supported\n"); 1864 hw->phy.type = 1865 ixgbe_phy_sfp_unsupported; 1866 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1867 } 1868 } 1869 } else { 1870 status = IXGBE_SUCCESS; 1871 } 1872 } 1873 1874 out: 1875 return status; 1876 1877 err_read_i2c_eeprom: 1878 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1879 hw->phy.id = 0; 1880 hw->phy.type = ixgbe_phy_unknown; 1881 1882 return IXGBE_ERR_SFP_NOT_PRESENT; 1883 } 1884 1885 1886 /** 1887 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1888 * @hw: pointer to hardware structure 1889 * @list_offset: offset to the SFP ID list 1890 * @data_offset: offset to the SFP data block 1891 * 1892 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1893 * so it returns the offsets to the phy init sequence block. 1894 **/ 1895 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1896 u16 *list_offset, 1897 u16 *data_offset) 1898 { 1899 u16 sfp_id; 1900 u16 sfp_type = hw->phy.sfp_type; 1901 1902 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1903 1904 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1905 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1906 1907 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1908 return IXGBE_ERR_SFP_NOT_PRESENT; 1909 1910 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1911 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1912 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1913 1914 /* 1915 * Limiting active cables and 1G Phys must be initialized as 1916 * SR modules 1917 */ 1918 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1919 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1920 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1921 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1922 sfp_type = ixgbe_sfp_type_srlr_core0; 1923 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1924 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1925 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1926 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1927 sfp_type = ixgbe_sfp_type_srlr_core1; 1928 1929 /* Read offset to PHY init contents */ 1930 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1931 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1932 "eeprom read at offset %d failed", 1933 IXGBE_PHY_INIT_OFFSET_NL); 1934 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1935 } 1936 1937 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1938 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1939 1940 /* Shift offset to first ID word */ 1941 (*list_offset)++; 1942 1943 /* 1944 * Find the matching SFP ID in the EEPROM 1945 * and program the init sequence 1946 */ 1947 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1948 goto err_phy; 1949 1950 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1951 if (sfp_id == sfp_type) { 1952 (*list_offset)++; 1953 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1954 goto err_phy; 1955 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1956 DEBUGOUT("SFP+ module not supported\n"); 1957 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1958 } else { 1959 break; 1960 } 1961 } else { 1962 (*list_offset) += 2; 1963 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1964 goto err_phy; 1965 } 1966 } 1967 1968 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1969 DEBUGOUT("No matching SFP+ module found\n"); 1970 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1971 } 1972 1973 return IXGBE_SUCCESS; 1974 1975 err_phy: 1976 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1977 "eeprom read at offset %d failed", *list_offset); 1978 return IXGBE_ERR_PHY; 1979 } 1980 1981 /** 1982 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1983 * @hw: pointer to hardware structure 1984 * @byte_offset: EEPROM byte offset to read 1985 * @eeprom_data: value read 1986 * 1987 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1988 **/ 1989 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1990 u8 *eeprom_data) 1991 { 1992 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1993 1994 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1995 IXGBE_I2C_EEPROM_DEV_ADDR, 1996 eeprom_data); 1997 } 1998 1999 /** 2000 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 2001 * @hw: pointer to hardware structure 2002 * @byte_offset: byte offset at address 0xA2 2003 * @eeprom_data: value read 2004 * 2005 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2006 **/ 2007 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2008 u8 *sff8472_data) 2009 { 2010 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2011 IXGBE_I2C_EEPROM_DEV_ADDR2, 2012 sff8472_data); 2013 } 2014 2015 /** 2016 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2017 * @hw: pointer to hardware structure 2018 * @byte_offset: EEPROM byte offset to write 2019 * @eeprom_data: value to write 2020 * 2021 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2022 **/ 2023 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2024 u8 eeprom_data) 2025 { 2026 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2027 2028 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2029 IXGBE_I2C_EEPROM_DEV_ADDR, 2030 eeprom_data); 2031 } 2032 2033 /** 2034 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2035 * @hw: pointer to hardware structure 2036 * @offset: eeprom offset to be read 2037 * @addr: I2C address to be read 2038 */ 2039 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2040 { 2041 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2042 offset == IXGBE_SFF_IDENTIFIER && 2043 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2044 return TRUE; 2045 return FALSE; 2046 } 2047 2048 /** 2049 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2050 * @hw: pointer to hardware structure 2051 * @byte_offset: byte offset to read 2052 * @data: value read 2053 * @lock: TRUE if to take and release semaphore 2054 * 2055 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2056 * a specified device address. 2057 **/ 2058 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2059 u8 dev_addr, u8 *data, bool lock) 2060 { 2061 s32 status; 2062 u32 max_retry = 10; 2063 u32 retry = 0; 2064 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2065 bool nack = 1; 2066 *data = 0; 2067 2068 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2069 2070 if (hw->mac.type >= ixgbe_mac_X550) 2071 max_retry = 3; 2072 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2073 max_retry = IXGBE_SFP_DETECT_RETRIES; 2074 2075 do { 2076 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2077 return IXGBE_ERR_SWFW_SYNC; 2078 2079 ixgbe_i2c_start(hw); 2080 2081 /* Device Address and write indication */ 2082 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2083 if (status != IXGBE_SUCCESS) 2084 goto fail; 2085 2086 status = ixgbe_get_i2c_ack(hw); 2087 if (status != IXGBE_SUCCESS) 2088 goto fail; 2089 2090 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2091 if (status != IXGBE_SUCCESS) 2092 goto fail; 2093 2094 status = ixgbe_get_i2c_ack(hw); 2095 if (status != IXGBE_SUCCESS) 2096 goto fail; 2097 2098 ixgbe_i2c_start(hw); 2099 2100 /* Device Address and read indication */ 2101 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2102 if (status != IXGBE_SUCCESS) 2103 goto fail; 2104 2105 status = ixgbe_get_i2c_ack(hw); 2106 if (status != IXGBE_SUCCESS) 2107 goto fail; 2108 2109 status = ixgbe_clock_in_i2c_byte(hw, data); 2110 if (status != IXGBE_SUCCESS) 2111 goto fail; 2112 2113 status = ixgbe_clock_out_i2c_bit(hw, nack); 2114 if (status != IXGBE_SUCCESS) 2115 goto fail; 2116 2117 ixgbe_i2c_stop(hw); 2118 if (lock) 2119 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2120 return IXGBE_SUCCESS; 2121 2122 fail: 2123 ixgbe_i2c_bus_clear(hw); 2124 if (lock) { 2125 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2126 msec_delay(100); 2127 } 2128 retry++; 2129 if (retry < max_retry) 2130 DEBUGOUT("I2C byte read error - Retrying.\n"); 2131 else 2132 DEBUGOUT("I2C byte read error.\n"); 2133 2134 } while (retry < max_retry); 2135 2136 return status; 2137 } 2138 2139 /** 2140 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2141 * @hw: pointer to hardware structure 2142 * @byte_offset: byte offset to read 2143 * @data: value read 2144 * 2145 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2146 * a specified device address. 2147 **/ 2148 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2149 u8 dev_addr, u8 *data) 2150 { 2151 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2152 data, TRUE); 2153 } 2154 2155 /** 2156 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2157 * @hw: pointer to hardware structure 2158 * @byte_offset: byte offset to read 2159 * @data: value read 2160 * 2161 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2162 * a specified device address. 2163 **/ 2164 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2165 u8 dev_addr, u8 *data) 2166 { 2167 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2168 data, FALSE); 2169 } 2170 2171 /** 2172 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2173 * @hw: pointer to hardware structure 2174 * @byte_offset: byte offset to write 2175 * @data: value to write 2176 * @lock: TRUE if to take and release semaphore 2177 * 2178 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2179 * a specified device address. 2180 **/ 2181 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2182 u8 dev_addr, u8 data, bool lock) 2183 { 2184 s32 status; 2185 u32 max_retry = 2; 2186 u32 retry = 0; 2187 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2188 2189 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2190 2191 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2192 IXGBE_SUCCESS) 2193 return IXGBE_ERR_SWFW_SYNC; 2194 2195 do { 2196 ixgbe_i2c_start(hw); 2197 2198 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2199 if (status != IXGBE_SUCCESS) 2200 goto fail; 2201 2202 status = ixgbe_get_i2c_ack(hw); 2203 if (status != IXGBE_SUCCESS) 2204 goto fail; 2205 2206 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2207 if (status != IXGBE_SUCCESS) 2208 goto fail; 2209 2210 status = ixgbe_get_i2c_ack(hw); 2211 if (status != IXGBE_SUCCESS) 2212 goto fail; 2213 2214 status = ixgbe_clock_out_i2c_byte(hw, data); 2215 if (status != IXGBE_SUCCESS) 2216 goto fail; 2217 2218 status = ixgbe_get_i2c_ack(hw); 2219 if (status != IXGBE_SUCCESS) 2220 goto fail; 2221 2222 ixgbe_i2c_stop(hw); 2223 if (lock) 2224 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2225 return IXGBE_SUCCESS; 2226 2227 fail: 2228 ixgbe_i2c_bus_clear(hw); 2229 retry++; 2230 if (retry < max_retry) 2231 DEBUGOUT("I2C byte write error - Retrying.\n"); 2232 else 2233 DEBUGOUT("I2C byte write error.\n"); 2234 } while (retry < max_retry); 2235 2236 if (lock) 2237 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2238 2239 return status; 2240 } 2241 2242 /** 2243 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2244 * @hw: pointer to hardware structure 2245 * @byte_offset: byte offset to write 2246 * @data: value to write 2247 * 2248 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2249 * a specified device address. 2250 **/ 2251 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2252 u8 dev_addr, u8 data) 2253 { 2254 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2255 data, TRUE); 2256 } 2257 2258 /** 2259 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2260 * @hw: pointer to hardware structure 2261 * @byte_offset: byte offset to write 2262 * @data: value to write 2263 * 2264 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2265 * a specified device address. 2266 **/ 2267 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2268 u8 dev_addr, u8 data) 2269 { 2270 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2271 data, FALSE); 2272 } 2273 2274 /** 2275 * ixgbe_i2c_start - Sets I2C start condition 2276 * @hw: pointer to hardware structure 2277 * 2278 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2279 * Set bit-bang mode on X550 hardware. 2280 **/ 2281 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2282 { 2283 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2284 2285 DEBUGFUNC("ixgbe_i2c_start"); 2286 2287 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2288 2289 /* Start condition must begin with data and clock high */ 2290 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2291 ixgbe_raise_i2c_clk(hw, &i2cctl); 2292 2293 /* Setup time for start condition (4.7us) */ 2294 usec_delay(IXGBE_I2C_T_SU_STA); 2295 2296 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2297 2298 /* Hold time for start condition (4us) */ 2299 usec_delay(IXGBE_I2C_T_HD_STA); 2300 2301 ixgbe_lower_i2c_clk(hw, &i2cctl); 2302 2303 /* Minimum low period of clock is 4.7 us */ 2304 usec_delay(IXGBE_I2C_T_LOW); 2305 2306 } 2307 2308 /** 2309 * ixgbe_i2c_stop - Sets I2C stop condition 2310 * @hw: pointer to hardware structure 2311 * 2312 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2313 * Disables bit-bang mode and negates data output enable on X550 2314 * hardware. 2315 **/ 2316 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2317 { 2318 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2319 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2320 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2321 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2322 2323 DEBUGFUNC("ixgbe_i2c_stop"); 2324 2325 /* Stop condition must begin with data low and clock high */ 2326 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2327 ixgbe_raise_i2c_clk(hw, &i2cctl); 2328 2329 /* Setup time for stop condition (4us) */ 2330 usec_delay(IXGBE_I2C_T_SU_STO); 2331 2332 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2333 2334 /* bus free time between stop and start (4.7us)*/ 2335 usec_delay(IXGBE_I2C_T_BUF); 2336 2337 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2338 i2cctl &= ~bb_en_bit; 2339 i2cctl |= data_oe_bit | clk_oe_bit; 2340 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2341 IXGBE_WRITE_FLUSH(hw); 2342 } 2343 } 2344 2345 /** 2346 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2347 * @hw: pointer to hardware structure 2348 * @data: data byte to clock in 2349 * 2350 * Clocks in one byte data via I2C data/clock 2351 **/ 2352 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2353 { 2354 s32 i; 2355 bool bit = 0; 2356 2357 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2358 2359 *data = 0; 2360 for (i = 7; i >= 0; i--) { 2361 ixgbe_clock_in_i2c_bit(hw, &bit); 2362 *data |= bit << i; 2363 } 2364 2365 return IXGBE_SUCCESS; 2366 } 2367 2368 /** 2369 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2370 * @hw: pointer to hardware structure 2371 * @data: data byte clocked out 2372 * 2373 * Clocks out one byte data via I2C data/clock 2374 **/ 2375 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2376 { 2377 s32 status = IXGBE_SUCCESS; 2378 s32 i; 2379 u32 i2cctl; 2380 bool bit; 2381 2382 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2383 2384 for (i = 7; i >= 0; i--) { 2385 bit = (data >> i) & 0x1; 2386 status = ixgbe_clock_out_i2c_bit(hw, bit); 2387 2388 if (status != IXGBE_SUCCESS) 2389 break; 2390 } 2391 2392 /* Release SDA line (set high) */ 2393 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2394 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2395 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2396 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2397 IXGBE_WRITE_FLUSH(hw); 2398 2399 return status; 2400 } 2401 2402 /** 2403 * ixgbe_get_i2c_ack - Polls for I2C ACK 2404 * @hw: pointer to hardware structure 2405 * 2406 * Clocks in/out one bit via I2C data/clock 2407 **/ 2408 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2409 { 2410 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2411 s32 status = IXGBE_SUCCESS; 2412 u32 i = 0; 2413 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2414 u32 timeout = 10; 2415 bool ack = 1; 2416 2417 DEBUGFUNC("ixgbe_get_i2c_ack"); 2418 2419 if (data_oe_bit) { 2420 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2421 i2cctl |= data_oe_bit; 2422 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2423 IXGBE_WRITE_FLUSH(hw); 2424 } 2425 ixgbe_raise_i2c_clk(hw, &i2cctl); 2426 2427 /* Minimum high period of clock is 4us */ 2428 usec_delay(IXGBE_I2C_T_HIGH); 2429 2430 /* Poll for ACK. Note that ACK in I2C spec is 2431 * transition from 1 to 0 */ 2432 for (i = 0; i < timeout; i++) { 2433 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2434 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2435 2436 usec_delay(1); 2437 if (!ack) 2438 break; 2439 } 2440 2441 if (ack) { 2442 DEBUGOUT("I2C ack was not received.\n"); 2443 status = IXGBE_ERR_I2C; 2444 } 2445 2446 ixgbe_lower_i2c_clk(hw, &i2cctl); 2447 2448 /* Minimum low period of clock is 4.7 us */ 2449 usec_delay(IXGBE_I2C_T_LOW); 2450 2451 return status; 2452 } 2453 2454 /** 2455 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2456 * @hw: pointer to hardware structure 2457 * @data: read data value 2458 * 2459 * Clocks in one bit via I2C data/clock 2460 **/ 2461 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2462 { 2463 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2464 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2465 2466 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2467 2468 if (data_oe_bit) { 2469 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2470 i2cctl |= data_oe_bit; 2471 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2472 IXGBE_WRITE_FLUSH(hw); 2473 } 2474 ixgbe_raise_i2c_clk(hw, &i2cctl); 2475 2476 /* Minimum high period of clock is 4us */ 2477 usec_delay(IXGBE_I2C_T_HIGH); 2478 2479 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2480 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2481 2482 ixgbe_lower_i2c_clk(hw, &i2cctl); 2483 2484 /* Minimum low period of clock is 4.7 us */ 2485 usec_delay(IXGBE_I2C_T_LOW); 2486 2487 return IXGBE_SUCCESS; 2488 } 2489 2490 /** 2491 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2492 * @hw: pointer to hardware structure 2493 * @data: data value to write 2494 * 2495 * Clocks out one bit via I2C data/clock 2496 **/ 2497 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2498 { 2499 s32 status; 2500 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2501 2502 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2503 2504 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2505 if (status == IXGBE_SUCCESS) { 2506 ixgbe_raise_i2c_clk(hw, &i2cctl); 2507 2508 /* Minimum high period of clock is 4us */ 2509 usec_delay(IXGBE_I2C_T_HIGH); 2510 2511 ixgbe_lower_i2c_clk(hw, &i2cctl); 2512 2513 /* Minimum low period of clock is 4.7 us. 2514 * This also takes care of the data hold time. 2515 */ 2516 usec_delay(IXGBE_I2C_T_LOW); 2517 } else { 2518 status = IXGBE_ERR_I2C; 2519 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2520 "I2C data was not set to %X\n", data); 2521 } 2522 2523 return status; 2524 } 2525 2526 /** 2527 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2528 * @hw: pointer to hardware structure 2529 * @i2cctl: Current value of I2CCTL register 2530 * 2531 * Raises the I2C clock line '0'->'1' 2532 * Negates the I2C clock output enable on X550 hardware. 2533 **/ 2534 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2535 { 2536 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2537 u32 i = 0; 2538 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2539 u32 i2cctl_r = 0; 2540 2541 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2542 2543 if (clk_oe_bit) { 2544 *i2cctl |= clk_oe_bit; 2545 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2546 } 2547 2548 for (i = 0; i < timeout; i++) { 2549 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2550 2551 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2552 IXGBE_WRITE_FLUSH(hw); 2553 /* SCL rise time (1000ns) */ 2554 usec_delay(IXGBE_I2C_T_RISE); 2555 2556 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2557 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2558 break; 2559 } 2560 } 2561 2562 /** 2563 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2564 * @hw: pointer to hardware structure 2565 * @i2cctl: Current value of I2CCTL register 2566 * 2567 * Lowers the I2C clock line '1'->'0' 2568 * Asserts the I2C clock output enable on X550 hardware. 2569 **/ 2570 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2571 { 2572 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2573 2574 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2575 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2576 2577 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2578 IXGBE_WRITE_FLUSH(hw); 2579 2580 /* SCL fall time (300ns) */ 2581 usec_delay(IXGBE_I2C_T_FALL); 2582 } 2583 2584 /** 2585 * ixgbe_set_i2c_data - Sets the I2C data bit 2586 * @hw: pointer to hardware structure 2587 * @i2cctl: Current value of I2CCTL register 2588 * @data: I2C data value (0 or 1) to set 2589 * 2590 * Sets the I2C data bit 2591 * Asserts the I2C data output enable on X550 hardware. 2592 **/ 2593 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2594 { 2595 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2596 s32 status = IXGBE_SUCCESS; 2597 2598 DEBUGFUNC("ixgbe_set_i2c_data"); 2599 2600 if (data) 2601 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2602 else 2603 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2604 *i2cctl &= ~data_oe_bit; 2605 2606 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2607 IXGBE_WRITE_FLUSH(hw); 2608 2609 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2610 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2611 2612 if (!data) /* Can't verify data in this case */ 2613 return IXGBE_SUCCESS; 2614 if (data_oe_bit) { 2615 *i2cctl |= data_oe_bit; 2616 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2617 IXGBE_WRITE_FLUSH(hw); 2618 } 2619 2620 /* Verify data was set correctly */ 2621 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2622 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2623 status = IXGBE_ERR_I2C; 2624 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2625 "Error - I2C data was not set to %X.\n", 2626 data); 2627 } 2628 2629 return status; 2630 } 2631 2632 /** 2633 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2634 * @hw: pointer to hardware structure 2635 * @i2cctl: Current value of I2CCTL register 2636 * 2637 * Returns the I2C data bit value 2638 * Negates the I2C data output enable on X550 hardware. 2639 **/ 2640 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2641 { 2642 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2643 bool data; 2644 2645 DEBUGFUNC("ixgbe_get_i2c_data"); 2646 2647 if (data_oe_bit) { 2648 *i2cctl |= data_oe_bit; 2649 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2650 IXGBE_WRITE_FLUSH(hw); 2651 usec_delay(IXGBE_I2C_T_FALL); 2652 } 2653 2654 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2655 data = 1; 2656 else 2657 data = 0; 2658 2659 return data; 2660 } 2661 2662 /** 2663 * ixgbe_i2c_bus_clear - Clears the I2C bus 2664 * @hw: pointer to hardware structure 2665 * 2666 * Clears the I2C bus by sending nine clock pulses. 2667 * Used when data line is stuck low. 2668 **/ 2669 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2670 { 2671 u32 i2cctl; 2672 u32 i; 2673 2674 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2675 2676 ixgbe_i2c_start(hw); 2677 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2678 2679 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2680 2681 for (i = 0; i < 9; i++) { 2682 ixgbe_raise_i2c_clk(hw, &i2cctl); 2683 2684 /* Min high period of clock is 4us */ 2685 usec_delay(IXGBE_I2C_T_HIGH); 2686 2687 ixgbe_lower_i2c_clk(hw, &i2cctl); 2688 2689 /* Min low period of clock is 4.7us*/ 2690 usec_delay(IXGBE_I2C_T_LOW); 2691 } 2692 2693 ixgbe_i2c_start(hw); 2694 2695 /* Put the i2c bus back to default state */ 2696 ixgbe_i2c_stop(hw); 2697 } 2698 2699 /** 2700 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2701 * @hw: pointer to hardware structure 2702 * 2703 * Checks if the LASI temp alarm status was triggered due to overtemp 2704 **/ 2705 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2706 { 2707 s32 status = IXGBE_SUCCESS; 2708 u16 phy_data = 0; 2709 2710 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2711 2712 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2713 goto out; 2714 2715 /* Check that the LASI temp alarm status was triggered */ 2716 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2717 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2718 2719 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2720 goto out; 2721 2722 status = IXGBE_ERR_OVERTEMP; 2723 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2724 out: 2725 return status; 2726 } 2727 2728 /** 2729 * ixgbe_set_copper_phy_power - Control power for copper phy 2730 * @hw: pointer to hardware structure 2731 * @on: TRUE for on, FALSE for off 2732 */ 2733 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2734 { 2735 u32 status; 2736 u16 reg; 2737 2738 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2739 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2740 ®); 2741 if (status) 2742 return status; 2743 2744 if (on) { 2745 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2746 } else { 2747 if (ixgbe_check_reset_blocked(hw)) 2748 return 0; 2749 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2750 } 2751 2752 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2753 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2754 reg); 2755 return status; 2756 } 2757
Indexes created Fri Oct 17 09:09:57 GMT 2025