ixgbe_phy.c revision 1.24
1 /* $NetBSD: ixgbe_phy.c,v 1.24 2021/04/30 06:55:32 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ixgbe_phy.c,v 1.24 2021/04/30 06:55:32 msaitoh Exp $"); 40 41 #include "ixgbe_api.h" 42 #include "ixgbe_common.h" 43 #include "ixgbe_phy.h" 44 45 #include <dev/mii/mdio.h> 46 47 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 48 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 49 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 50 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 51 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 52 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 53 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 54 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 55 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 56 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 57 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 58 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 59 u8 *sff8472_data); 60 61 /** 62 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 63 * @hw: pointer to the hardware structure 64 * @byte: byte to send 65 * 66 * Returns an error code on error. 67 */ 68 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 69 { 70 s32 status; 71 72 status = ixgbe_clock_out_i2c_byte(hw, byte); 73 if (status) 74 return status; 75 return ixgbe_get_i2c_ack(hw); 76 } 77 78 /** 79 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 80 * @hw: pointer to the hardware structure 81 * @byte: pointer to a u8 to receive the byte 82 * 83 * Returns an error code on error. 84 */ 85 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 86 { 87 s32 status; 88 89 status = ixgbe_clock_in_i2c_byte(hw, byte); 90 if (status) 91 return status; 92 /* ACK */ 93 return ixgbe_clock_out_i2c_bit(hw, FALSE); 94 } 95 96 /** 97 * ixgbe_ones_comp_byte_add - Perform one's complement addition 98 * @add1: addend 1 99 * @add2: addend 2 100 * 101 * Returns one's complement 8-bit sum. 102 */ 103 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 104 { 105 u16 sum = add1 + add2; 106 107 sum = (sum & 0xFF) + (sum >> 8); 108 return sum & 0xFF; 109 } 110 111 /** 112 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 113 * @hw: pointer to the hardware structure 114 * @addr: I2C bus address to read from 115 * @reg: I2C device register to read from 116 * @val: pointer to location to receive read value 117 * @lock: TRUE if to take and release semaphore 118 * 119 * Returns an error code on error. 120 */ 121 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 122 u16 *val, bool lock) 123 { 124 u32 swfw_mask = hw->phy.phy_semaphore_mask; 125 int max_retry = 3; 126 int retry = 0; 127 u8 csum_byte; 128 u8 high_bits; 129 u8 low_bits; 130 u8 reg_high; 131 u8 csum; 132 133 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 134 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 135 csum = ~csum; 136 do { 137 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 138 return IXGBE_ERR_SWFW_SYNC; 139 ixgbe_i2c_start(hw); 140 /* Device Address and write indication */ 141 if (ixgbe_out_i2c_byte_ack(hw, addr)) 142 goto fail; 143 /* Write bits 14:8 */ 144 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 145 goto fail; 146 /* Write bits 7:0 */ 147 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 148 goto fail; 149 /* Write csum */ 150 if (ixgbe_out_i2c_byte_ack(hw, csum)) 151 goto fail; 152 /* Re-start condition */ 153 ixgbe_i2c_start(hw); 154 /* Device Address and read indication */ 155 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 156 goto fail; 157 /* Get upper bits */ 158 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 159 goto fail; 160 /* Get low bits */ 161 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 162 goto fail; 163 /* Get csum */ 164 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 165 goto fail; 166 /* NACK */ 167 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 168 goto fail; 169 ixgbe_i2c_stop(hw); 170 if (lock) 171 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 172 *val = (high_bits << 8) | low_bits; 173 return 0; 174 175 fail: 176 ixgbe_i2c_bus_clear(hw); 177 if (lock) 178 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 179 retry++; 180 if (retry < max_retry) 181 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 182 else 183 DEBUGOUT("I2C byte read combined error.\n"); 184 } while (retry < max_retry); 185 186 return IXGBE_ERR_I2C; 187 } 188 189 /** 190 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 191 * @hw: pointer to the hardware structure 192 * @addr: I2C bus address to write to 193 * @reg: I2C device register to write to 194 * @val: value to write 195 * @lock: TRUE if to take and release semaphore 196 * 197 * Returns an error code on error. 198 */ 199 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 200 u16 val, bool lock) 201 { 202 u32 swfw_mask = hw->phy.phy_semaphore_mask; 203 int max_retry = 1; 204 int retry = 0; 205 u8 reg_high; 206 u8 csum; 207 208 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 209 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 210 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 211 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 212 csum = ~csum; 213 do { 214 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 215 return IXGBE_ERR_SWFW_SYNC; 216 ixgbe_i2c_start(hw); 217 /* Device Address and write indication */ 218 if (ixgbe_out_i2c_byte_ack(hw, addr)) 219 goto fail; 220 /* Write bits 14:8 */ 221 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 222 goto fail; 223 /* Write bits 7:0 */ 224 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 225 goto fail; 226 /* Write data 15:8 */ 227 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 228 goto fail; 229 /* Write data 7:0 */ 230 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 231 goto fail; 232 /* Write csum */ 233 if (ixgbe_out_i2c_byte_ack(hw, csum)) 234 goto fail; 235 ixgbe_i2c_stop(hw); 236 if (lock) 237 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 238 return 0; 239 240 fail: 241 ixgbe_i2c_bus_clear(hw); 242 if (lock) 243 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 244 retry++; 245 if (retry < max_retry) 246 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 247 else 248 DEBUGOUT("I2C byte write combined error.\n"); 249 } while (retry < max_retry); 250 251 return IXGBE_ERR_I2C; 252 } 253 254 /** 255 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 256 * @hw: pointer to the hardware structure 257 * 258 * Initialize the function pointers. 259 **/ 260 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 261 { 262 struct ixgbe_phy_info *phy = &hw->phy; 263 264 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 265 266 /* PHY */ 267 phy->ops.identify = ixgbe_identify_phy_generic; 268 phy->ops.reset = ixgbe_reset_phy_generic; 269 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 270 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 271 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 272 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 273 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 274 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 275 phy->ops.check_link = NULL; 276 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 277 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 278 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 279 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 280 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 281 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 282 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 283 phy->ops.identify_sfp = ixgbe_identify_module_generic; 284 phy->sfp_type = ixgbe_sfp_type_unknown; 285 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 286 phy->ops.write_i2c_byte_unlocked = 287 ixgbe_write_i2c_byte_generic_unlocked; 288 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 289 return IXGBE_SUCCESS; 290 } 291 292 /** 293 * ixgbe_probe_phy - Probe a single address for a PHY 294 * @hw: pointer to hardware structure 295 * @phy_addr: PHY address to probe 296 * 297 * Returns TRUE if PHY found 298 */ 299 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 300 { 301 u16 ext_ability = 0; 302 303 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 304 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 305 phy_addr); 306 return FALSE; 307 } 308 309 if (ixgbe_get_phy_id(hw)) 310 return FALSE; 311 312 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 313 314 if (hw->phy.type == ixgbe_phy_unknown) { 315 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 316 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 317 if (ext_ability & 318 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 319 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 320 hw->phy.type = ixgbe_phy_cu_unknown; 321 else 322 hw->phy.type = ixgbe_phy_generic; 323 } 324 325 return TRUE; 326 } 327 328 /** 329 * ixgbe_identify_phy_generic - Get physical layer module 330 * @hw: pointer to hardware structure 331 * 332 * Determines the physical layer module found on the current adapter. 333 **/ 334 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 335 { 336 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 337 u16 phy_addr; 338 339 DEBUGFUNC("ixgbe_identify_phy_generic"); 340 341 if (!hw->phy.phy_semaphore_mask) { 342 if (hw->bus.lan_id) 343 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 344 else 345 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 346 } 347 348 if (hw->phy.type != ixgbe_phy_unknown) 349 return IXGBE_SUCCESS; 350 351 if (hw->phy.nw_mng_if_sel) { 352 phy_addr = (hw->phy.nw_mng_if_sel & 353 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 354 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 355 if (ixgbe_probe_phy(hw, phy_addr)) 356 return IXGBE_SUCCESS; 357 else 358 return IXGBE_ERR_PHY_ADDR_INVALID; 359 } 360 361 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 362 if (ixgbe_probe_phy(hw, phy_addr)) { 363 status = IXGBE_SUCCESS; 364 break; 365 } 366 } 367 368 /* Certain media types do not have a phy so an address will not 369 * be found and the code will take this path. Caller has to 370 * decide if it is an error or not. 371 */ 372 if (status != IXGBE_SUCCESS) 373 hw->phy.addr = 0; 374 375 return status; 376 } 377 378 /** 379 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 380 * @hw: pointer to the hardware structure 381 * 382 * This function checks the MMNGC.MNG_VETO bit to see if there are 383 * any constraints on link from manageability. For MAC's that don't 384 * have this bit just return faluse since the link can not be blocked 385 * via this method. 386 **/ 387 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 388 { 389 u32 mmngc; 390 391 DEBUGFUNC("ixgbe_check_reset_blocked"); 392 393 /* If we don't have this bit, it can't be blocking */ 394 if (hw->mac.type == ixgbe_mac_82598EB) 395 return FALSE; 396 397 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 398 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 399 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 400 "MNG_VETO bit detected.\n"); 401 return TRUE; 402 } 403 404 return FALSE; 405 } 406 407 /** 408 * ixgbe_validate_phy_addr - Determines phy address is valid 409 * @hw: pointer to hardware structure 410 * @phy_addr: PHY address 411 * 412 **/ 413 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 414 { 415 u16 phy_id = 0; 416 bool valid = FALSE; 417 418 DEBUGFUNC("ixgbe_validate_phy_addr"); 419 420 hw->phy.addr = phy_addr; 421 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 422 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 423 424 if (phy_id != 0xFFFF && phy_id != 0x0) 425 valid = TRUE; 426 427 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 428 429 return valid; 430 } 431 432 /** 433 * ixgbe_get_phy_id - Get the phy type 434 * @hw: pointer to hardware structure 435 * 436 **/ 437 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 438 { 439 u32 status; 440 u16 phy_id_high = 0; 441 u16 phy_id_low = 0; 442 443 DEBUGFUNC("ixgbe_get_phy_id"); 444 445 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 446 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 447 &phy_id_high); 448 449 if (status == IXGBE_SUCCESS) { 450 hw->phy.id = (u32)(phy_id_high << 16); 451 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 452 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 453 &phy_id_low); 454 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 455 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 456 } 457 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 458 phy_id_high, phy_id_low); 459 460 return status; 461 } 462 463 /** 464 * ixgbe_get_phy_type_from_id - Get the phy type 465 * @phy_id: PHY ID information 466 * 467 **/ 468 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 469 { 470 enum ixgbe_phy_type phy_type; 471 472 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 473 474 switch (phy_id) { 475 case TN1010_PHY_ID: 476 phy_type = ixgbe_phy_tn; 477 break; 478 case X550_PHY_ID2: 479 case X550_PHY_ID3: 480 case X540_PHY_ID: 481 phy_type = ixgbe_phy_aq; 482 break; 483 case QT2022_PHY_ID: 484 phy_type = ixgbe_phy_qt; 485 break; 486 case ATH_PHY_ID: 487 phy_type = ixgbe_phy_nl; 488 break; 489 case X557_PHY_ID: 490 case X557_PHY_ID2: 491 phy_type = ixgbe_phy_x550em_ext_t; 492 break; 493 case IXGBE_M88E1500_E_PHY_ID: 494 case IXGBE_M88E1543_E_PHY_ID: 495 phy_type = ixgbe_phy_ext_1g_t; 496 break; 497 default: 498 phy_type = ixgbe_phy_unknown; 499 break; 500 } 501 return phy_type; 502 } 503 504 /** 505 * ixgbe_reset_phy_generic - Performs a PHY reset 506 * @hw: pointer to hardware structure 507 **/ 508 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 509 { 510 u32 i; 511 u16 ctrl = 0; 512 s32 status = IXGBE_SUCCESS; 513 514 DEBUGFUNC("ixgbe_reset_phy_generic"); 515 516 if (hw->phy.type == ixgbe_phy_unknown) 517 status = ixgbe_identify_phy_generic(hw); 518 519 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 520 goto out; 521 522 /* Don't reset PHY if it's shut down due to overtemp. */ 523 if (!hw->phy.reset_if_overtemp && 524 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 525 goto out; 526 527 /* Blocked by MNG FW so bail */ 528 if (ixgbe_check_reset_blocked(hw)) 529 goto out; 530 531 /* 532 * Perform soft PHY reset to the PHY_XS. 533 * This will cause a soft reset to the PHY 534 */ 535 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 536 IXGBE_MDIO_PHY_XS_DEV_TYPE, 537 IXGBE_MDIO_PHY_XS_RESET); 538 539 /* 540 * Poll for reset bit to self-clear indicating reset is complete. 541 * Some PHYs could take up to 3 seconds to complete and need about 542 * 1.7 usec delay after the reset is complete. 543 */ 544 for (i = 0; i < 30; i++) { 545 msec_delay(100); 546 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 547 status = hw->phy.ops.read_reg(hw, 548 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 549 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 550 &ctrl); 551 if (status != IXGBE_SUCCESS) 552 return status; 553 554 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 555 usec_delay(2); 556 break; 557 } 558 } else { 559 status = hw->phy.ops.read_reg(hw, 560 IXGBE_MDIO_PHY_XS_CONTROL, 561 IXGBE_MDIO_PHY_XS_DEV_TYPE, 562 &ctrl); 563 if (status != IXGBE_SUCCESS) 564 return status; 565 566 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 567 usec_delay(2); 568 break; 569 } 570 } 571 } 572 573 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 574 status = IXGBE_ERR_RESET_FAILED; 575 ERROR_REPORT1(IXGBE_ERROR_POLLING, 576 "PHY reset polling failed to complete.\n"); 577 } 578 579 out: 580 return status; 581 } 582 583 /** 584 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 585 * the SWFW lock 586 * @hw: pointer to hardware structure 587 * @reg_addr: 32 bit address of PHY register to read 588 * @device_type: 5 bit device type 589 * @phy_data: Pointer to read data from PHY register 590 **/ 591 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 592 u16 *phy_data) 593 { 594 u32 i, data, command; 595 596 /* Setup and write the address cycle command */ 597 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 598 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 599 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 600 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 601 602 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 603 604 /* 605 * Check every 10 usec to see if the address cycle completed. 606 * The MDI Command bit will clear when the operation is 607 * complete 608 */ 609 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 610 usec_delay(10); 611 612 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 613 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 614 break; 615 } 616 617 618 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 619 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 620 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 621 return IXGBE_ERR_PHY; 622 } 623 624 /* 625 * Address cycle complete, setup and write the read 626 * command 627 */ 628 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 629 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 630 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 631 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 632 633 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 634 635 /* 636 * Check every 10 usec to see if the address cycle 637 * completed. The MDI Command bit will clear when the 638 * operation is complete 639 */ 640 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 641 usec_delay(10); 642 643 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 644 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 645 break; 646 } 647 648 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 649 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 650 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 651 return IXGBE_ERR_PHY; 652 } 653 654 /* 655 * Read operation is complete. Get the data 656 * from MSRWD 657 */ 658 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 659 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 660 *phy_data = (u16)(data); 661 662 return IXGBE_SUCCESS; 663 } 664 665 /** 666 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 667 * using the SWFW lock - this function is needed in most cases 668 * @hw: pointer to hardware structure 669 * @reg_addr: 32 bit address of PHY register to read 670 * @device_type: 5 bit device type 671 * @phy_data: Pointer to read data from PHY register 672 **/ 673 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 674 u32 device_type, u16 *phy_data) 675 { 676 s32 status; 677 u32 gssr = hw->phy.phy_semaphore_mask; 678 679 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 680 681 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 682 return IXGBE_ERR_SWFW_SYNC; 683 684 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 685 686 hw->mac.ops.release_swfw_sync(hw, gssr); 687 688 return status; 689 } 690 691 /** 692 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 693 * without SWFW lock 694 * @hw: pointer to hardware structure 695 * @reg_addr: 32 bit PHY register to write 696 * @device_type: 5 bit device type 697 * @phy_data: Data to write to the PHY register 698 **/ 699 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 700 u32 device_type, u16 phy_data) 701 { 702 u32 i, command; 703 704 /* Put the data in the MDI single read and write data register*/ 705 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 706 707 /* Setup and write the address cycle command */ 708 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 709 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 710 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 711 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 712 713 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 714 715 /* 716 * Check every 10 usec to see if the address cycle completed. 717 * The MDI Command bit will clear when the operation is 718 * complete 719 */ 720 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 721 usec_delay(10); 722 723 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 724 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 725 break; 726 } 727 728 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 729 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 730 return IXGBE_ERR_PHY; 731 } 732 733 /* 734 * Address cycle complete, setup and write the write 735 * command 736 */ 737 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 738 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 739 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 740 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 741 742 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 743 744 /* 745 * Check every 10 usec to see if the address cycle 746 * completed. The MDI Command bit will clear when the 747 * operation is complete 748 */ 749 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 750 usec_delay(10); 751 752 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 753 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 754 break; 755 } 756 757 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 758 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 759 return IXGBE_ERR_PHY; 760 } 761 762 return IXGBE_SUCCESS; 763 } 764 765 /** 766 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 767 * using SWFW lock- this function is needed in most cases 768 * @hw: pointer to hardware structure 769 * @reg_addr: 32 bit PHY register to write 770 * @device_type: 5 bit device type 771 * @phy_data: Data to write to the PHY register 772 **/ 773 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 774 u32 device_type, u16 phy_data) 775 { 776 s32 status; 777 u32 gssr = hw->phy.phy_semaphore_mask; 778 779 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 780 781 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 782 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 783 phy_data); 784 hw->mac.ops.release_swfw_sync(hw, gssr); 785 } else { 786 status = IXGBE_ERR_SWFW_SYNC; 787 } 788 789 return status; 790 } 791 792 /** 793 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 794 * @hw: pointer to hardware structure 795 * 796 * Restart auto-negotiation and PHY and waits for completion. 797 **/ 798 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 799 { 800 s32 status = IXGBE_SUCCESS; 801 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 802 bool autoneg = FALSE; 803 ixgbe_link_speed speed; 804 805 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 806 807 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 808 809 /* Set or unset auto-negotiation 10G advertisement */ 810 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 811 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 812 &autoneg_reg); 813 814 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 815 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 816 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 817 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 818 819 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 820 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 821 autoneg_reg); 822 823 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 824 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 825 &autoneg_reg); 826 827 if (hw->mac.type == ixgbe_mac_X550) { 828 /* Set or unset auto-negotiation 5G advertisement */ 829 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 830 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 831 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 832 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 833 834 /* Set or unset auto-negotiation 2.5G advertisement */ 835 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 836 if ((hw->phy.autoneg_advertised & 837 IXGBE_LINK_SPEED_2_5GB_FULL) && 838 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 839 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 840 } 841 842 /* Set or unset auto-negotiation 1G advertisement */ 843 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 844 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 845 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 846 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 847 848 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 849 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 850 autoneg_reg); 851 852 /* Set or unset auto-negotiation 100M advertisement */ 853 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 854 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 855 &autoneg_reg); 856 857 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 858 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 859 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 860 (speed & IXGBE_LINK_SPEED_100_FULL)) 861 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 862 863 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 864 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 865 autoneg_reg); 866 867 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) { 868 u16 ctrl; 869 870 /* Force 100Mbps */ 871 hw->phy.ops.read_reg(hw, MDIO_PMAPMD_CTRL1, MDIO_MMD_PMAPMD, 872 &ctrl); 873 ctrl &= ~PMAPMD_CTRL1_SPEED_MASK; 874 ctrl |= PMAPMD_CTRL1_SPEED_100; 875 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD, 876 ctrl); 877 878 /* Don't use auto-nego for 100Mbps */ 879 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 880 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 881 882 autoneg_reg &= ~AN_CTRL1_AUTOEN; 883 884 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 885 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 886 } else { 887 /* Blocked by MNG FW so don't reset PHY */ 888 if (ixgbe_check_reset_blocked(hw)) 889 return status; 890 891 /* Restart PHY auto-negotiation. */ 892 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 893 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 894 895 autoneg_reg |= IXGBE_MII_RESTART | AN_CTRL1_AUTOEN; 896 897 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 898 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 899 } 900 901 return status; 902 } 903 904 /** 905 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 906 * @hw: pointer to hardware structure 907 * @speed: new link speed 908 * @autoneg_wait_to_complete: unused 909 **/ 910 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 911 ixgbe_link_speed speed, 912 bool autoneg_wait_to_complete) 913 { 914 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 915 916 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 917 918 /* 919 * Clear autoneg_advertised and set new values based on input link 920 * speed. 921 */ 922 hw->phy.autoneg_advertised = 0; 923 924 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 925 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 926 927 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 928 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 929 930 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 931 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 932 933 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 934 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 935 936 if (speed & IXGBE_LINK_SPEED_100_FULL) 937 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 938 939 if (speed & IXGBE_LINK_SPEED_10_FULL) 940 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 941 942 /* Setup link based on the new speed settings */ 943 ixgbe_setup_phy_link(hw); 944 945 return IXGBE_SUCCESS; 946 } 947 948 /** 949 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 950 * @hw: pointer to hardware structure 951 * 952 * Determines the supported link capabilities by reading the PHY auto 953 * negotiation register. 954 **/ 955 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 956 { 957 s32 status; 958 u16 speed_ability; 959 960 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 961 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 962 &speed_ability); 963 if (status) 964 return status; 965 966 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 967 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 968 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 969 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 970 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 971 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 972 973 switch (hw->mac.type) { 974 case ixgbe_mac_X550: 975 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 976 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 977 break; 978 case ixgbe_mac_X550EM_x: 979 case ixgbe_mac_X550EM_a: 980 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 981 break; 982 default: 983 break; 984 } 985 986 return status; 987 } 988 989 /** 990 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 991 * @hw: pointer to hardware structure 992 * @speed: pointer to link speed 993 * @autoneg: boolean auto-negotiation value 994 **/ 995 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 996 ixgbe_link_speed *speed, 997 bool *autoneg) 998 { 999 s32 status = IXGBE_SUCCESS; 1000 1001 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 1002 1003 *autoneg = TRUE; 1004 if (!hw->phy.speeds_supported) 1005 status = ixgbe_get_copper_speeds_supported(hw); 1006 1007 *speed = hw->phy.speeds_supported; 1008 return status; 1009 } 1010 1011 /** 1012 * ixgbe_check_phy_link_tnx - Determine link and speed status 1013 * @hw: pointer to hardware structure 1014 * @speed: current link speed 1015 * @link_up: TRUE is link is up, FALSE otherwise 1016 * 1017 * Reads the VS1 register to determine if link is up and the current speed for 1018 * the PHY. 1019 **/ 1020 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1021 bool *link_up) 1022 { 1023 s32 status = IXGBE_SUCCESS; 1024 u32 time_out; 1025 u32 max_time_out = 10; 1026 u16 phy_link = 0; 1027 u16 phy_speed = 0; 1028 u16 phy_data = 0; 1029 1030 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1031 1032 /* Initialize speed and link to default case */ 1033 *link_up = FALSE; 1034 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1035 1036 /* 1037 * Check current speed and link status of the PHY register. 1038 * This is a vendor specific register and may have to 1039 * be changed for other copper PHYs. 1040 */ 1041 for (time_out = 0; time_out < max_time_out; time_out++) { 1042 usec_delay(10); 1043 status = hw->phy.ops.read_reg(hw, 1044 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1045 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1046 &phy_data); 1047 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1048 phy_speed = phy_data & 1049 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1050 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1051 *link_up = TRUE; 1052 if (phy_speed == 1053 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1054 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1055 break; 1056 } 1057 } 1058 1059 return status; 1060 } 1061 1062 /** 1063 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1064 * @hw: pointer to hardware structure 1065 * 1066 * Restart auto-negotiation and PHY and waits for completion. 1067 **/ 1068 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1069 { 1070 s32 status = IXGBE_SUCCESS; 1071 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1072 bool autoneg = FALSE; 1073 ixgbe_link_speed speed; 1074 1075 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1076 1077 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1078 1079 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1080 /* Set or unset auto-negotiation 10G advertisement */ 1081 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1082 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1083 &autoneg_reg); 1084 1085 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1086 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1087 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1088 1089 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1090 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1091 autoneg_reg); 1092 } 1093 1094 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1095 /* Set or unset auto-negotiation 1G advertisement */ 1096 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1097 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1098 &autoneg_reg); 1099 1100 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1101 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1102 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1103 1104 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1105 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1106 autoneg_reg); 1107 } 1108 1109 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1110 /* Set or unset auto-negotiation 100M advertisement */ 1111 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1112 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1113 &autoneg_reg); 1114 1115 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1116 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1117 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1118 1119 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1120 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1121 autoneg_reg); 1122 } 1123 1124 /* Blocked by MNG FW so don't reset PHY */ 1125 if (ixgbe_check_reset_blocked(hw)) 1126 return status; 1127 1128 /* Restart PHY auto-negotiation. */ 1129 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1130 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1131 1132 autoneg_reg |= IXGBE_MII_RESTART; 1133 1134 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1135 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1136 1137 return status; 1138 } 1139 1140 /** 1141 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1142 * @hw: pointer to hardware structure 1143 * @firmware_version: pointer to the PHY Firmware Version 1144 **/ 1145 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1146 u16 *firmware_version) 1147 { 1148 s32 status; 1149 1150 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1151 1152 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1153 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1154 firmware_version); 1155 1156 return status; 1157 } 1158 1159 /** 1160 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1161 * @hw: pointer to hardware structure 1162 * @firmware_version: pointer to the PHY Firmware Version 1163 **/ 1164 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1165 u16 *firmware_version) 1166 { 1167 s32 status; 1168 1169 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1170 1171 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1172 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1173 firmware_version); 1174 1175 return status; 1176 } 1177 1178 /** 1179 * ixgbe_reset_phy_nl - Performs a PHY reset 1180 * @hw: pointer to hardware structure 1181 **/ 1182 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1183 { 1184 u16 phy_offset, control, eword, edata, block_crc; 1185 bool end_data = FALSE; 1186 u16 list_offset, data_offset; 1187 u16 phy_data = 0; 1188 s32 ret_val = IXGBE_SUCCESS; 1189 u32 i; 1190 1191 DEBUGFUNC("ixgbe_reset_phy_nl"); 1192 1193 /* Blocked by MNG FW so bail */ 1194 if (ixgbe_check_reset_blocked(hw)) 1195 goto out; 1196 1197 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1198 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1199 1200 /* reset the PHY and poll for completion */ 1201 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1202 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1203 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1204 1205 for (i = 0; i < 100; i++) { 1206 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1207 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1208 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1209 break; 1210 msec_delay(10); 1211 } 1212 1213 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1214 DEBUGOUT("PHY reset did not complete.\n"); 1215 ret_val = IXGBE_ERR_PHY; 1216 goto out; 1217 } 1218 1219 /* Get init offsets */ 1220 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1221 &data_offset); 1222 if (ret_val != IXGBE_SUCCESS) 1223 goto out; 1224 1225 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1226 data_offset++; 1227 while (!end_data) { 1228 /* 1229 * Read control word from PHY init contents offset 1230 */ 1231 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1232 if (ret_val) 1233 goto err_eeprom; 1234 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1235 IXGBE_CONTROL_SHIFT_NL; 1236 edata = eword & IXGBE_DATA_MASK_NL; 1237 switch (control) { 1238 case IXGBE_DELAY_NL: 1239 data_offset++; 1240 DEBUGOUT1("DELAY: %d MS\n", edata); 1241 msec_delay(edata); 1242 break; 1243 case IXGBE_DATA_NL: 1244 DEBUGOUT("DATA:\n"); 1245 data_offset++; 1246 ret_val = hw->eeprom.ops.read(hw, data_offset, 1247 &phy_offset); 1248 if (ret_val) 1249 goto err_eeprom; 1250 data_offset++; 1251 for (i = 0; i < edata; i++) { 1252 ret_val = hw->eeprom.ops.read(hw, data_offset, 1253 &eword); 1254 if (ret_val) 1255 goto err_eeprom; 1256 hw->phy.ops.write_reg(hw, phy_offset, 1257 IXGBE_TWINAX_DEV, eword); 1258 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1259 phy_offset); 1260 data_offset++; 1261 phy_offset++; 1262 } 1263 break; 1264 case IXGBE_CONTROL_NL: 1265 data_offset++; 1266 DEBUGOUT("CONTROL:\n"); 1267 if (edata == IXGBE_CONTROL_EOL_NL) { 1268 DEBUGOUT("EOL\n"); 1269 end_data = TRUE; 1270 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1271 DEBUGOUT("SOL\n"); 1272 } else { 1273 DEBUGOUT("Bad control value\n"); 1274 ret_val = IXGBE_ERR_PHY; 1275 goto out; 1276 } 1277 break; 1278 default: 1279 DEBUGOUT("Bad control type\n"); 1280 ret_val = IXGBE_ERR_PHY; 1281 goto out; 1282 } 1283 } 1284 1285 out: 1286 return ret_val; 1287 1288 err_eeprom: 1289 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1290 "eeprom read at offset %d failed", data_offset); 1291 return IXGBE_ERR_PHY; 1292 } 1293 1294 /************************************************************************ 1295 * ixgbe_sfp_cage_full 1296 * 1297 * Determine if an SFP+ module is inserted to the cage. 1298 ************************************************************************/ 1299 bool 1300 ixgbe_sfp_cage_full(struct ixgbe_hw *hw) 1301 { 1302 uint32_t mask; 1303 int rv; 1304 1305 KASSERT(hw->mac.type != ixgbe_mac_82598EB); 1306 1307 if (hw->mac.type >= ixgbe_mac_X540) 1308 mask = IXGBE_ESDP_SDP0; 1309 else 1310 mask = IXGBE_ESDP_SDP2; 1311 1312 rv = IXGBE_READ_REG(hw, IXGBE_ESDP) & mask; 1313 if ((hw->quirks & IXGBE_QUIRK_MOD_ABS_INVERT) != 0) 1314 rv = !rv; 1315 1316 if (hw->mac.type == ixgbe_mac_X550EM_a) { 1317 /* X550EM_a's SDP0 is inverted than others. */ 1318 return !rv; 1319 } 1320 1321 return rv; 1322 } /* ixgbe_sfp_cage_full */ 1323 1324 /** 1325 * ixgbe_identify_module_generic - Identifies module type 1326 * @hw: pointer to hardware structure 1327 * 1328 * Determines HW type and calls appropriate function. 1329 **/ 1330 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1331 { 1332 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1333 1334 DEBUGFUNC("ixgbe_identify_module_generic"); 1335 1336 /* Lightweight way to check if the cage is not full. */ 1337 if (hw->mac.type != ixgbe_mac_82598EB) { 1338 if (!ixgbe_sfp_cage_full(hw)) { 1339 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1340 return IXGBE_ERR_SFP_NOT_PRESENT; 1341 } 1342 } 1343 1344 switch (hw->mac.ops.get_media_type(hw)) { 1345 case ixgbe_media_type_fiber: 1346 status = ixgbe_identify_sfp_module_generic(hw); 1347 break; 1348 1349 case ixgbe_media_type_fiber_qsfp: 1350 status = ixgbe_identify_qsfp_module_generic(hw); 1351 break; 1352 1353 default: 1354 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1355 status = IXGBE_ERR_SFP_NOT_PRESENT; 1356 break; 1357 } 1358 1359 return status; 1360 } 1361 1362 /** 1363 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1364 * @hw: pointer to hardware structure 1365 * 1366 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1367 **/ 1368 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1369 { 1370 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1371 u32 vendor_oui = 0; 1372 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1373 u8 identifier = 0; 1374 u8 comp_codes_1g = 0; 1375 u8 comp_codes_10g = 0; 1376 u8 oui_bytes[3] = {0, 0, 0}; 1377 u8 cable_tech = 0; 1378 u8 cable_spec = 0; 1379 u16 enforce_sfp = 0; 1380 1381 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1382 1383 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1384 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1385 status = IXGBE_ERR_SFP_NOT_PRESENT; 1386 goto out; 1387 } 1388 1389 /* LAN ID is needed for I2C access */ 1390 hw->mac.ops.set_lan_id(hw); 1391 1392 status = hw->phy.ops.read_i2c_eeprom(hw, 1393 IXGBE_SFF_IDENTIFIER, 1394 &identifier); 1395 1396 if (status != IXGBE_SUCCESS) 1397 goto err_read_i2c_eeprom; 1398 1399 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1400 if (hw->phy.type != ixgbe_phy_nl) 1401 hw->phy.type = ixgbe_phy_sfp_unsupported; 1402 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1403 } else { 1404 status = hw->phy.ops.read_i2c_eeprom(hw, 1405 IXGBE_SFF_1GBE_COMP_CODES, 1406 &comp_codes_1g); 1407 1408 if (status != IXGBE_SUCCESS) 1409 goto err_read_i2c_eeprom; 1410 1411 status = hw->phy.ops.read_i2c_eeprom(hw, 1412 IXGBE_SFF_10GBE_COMP_CODES, 1413 &comp_codes_10g); 1414 1415 if (status != IXGBE_SUCCESS) 1416 goto err_read_i2c_eeprom; 1417 status = hw->phy.ops.read_i2c_eeprom(hw, 1418 IXGBE_SFF_CABLE_TECHNOLOGY, 1419 &cable_tech); 1420 1421 if (status != IXGBE_SUCCESS) 1422 goto err_read_i2c_eeprom; 1423 1424 /* ID Module 1425 * ========= 1426 * 0 SFP_DA_CU 1427 * 1 SFP_SR 1428 * 2 SFP_LR 1429 * 3 SFP_DA_CORE0 - 82599-specific 1430 * 4 SFP_DA_CORE1 - 82599-specific 1431 * 5 SFP_SR/LR_CORE0 - 82599-specific 1432 * 6 SFP_SR/LR_CORE1 - 82599-specific 1433 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1434 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1435 * 9 SFP_1g_cu_CORE0 - 82599-specific 1436 * 10 SFP_1g_cu_CORE1 - 82599-specific 1437 * 11 SFP_1g_sx_CORE0 - 82599-specific 1438 * 12 SFP_1g_sx_CORE1 - 82599-specific 1439 */ 1440 if (hw->mac.type == ixgbe_mac_82598EB) { 1441 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1442 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1443 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1444 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1445 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1446 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1447 else 1448 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1449 } else { 1450 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1451 if (hw->bus.lan_id == 0) 1452 hw->phy.sfp_type = 1453 ixgbe_sfp_type_da_cu_core0; 1454 else 1455 hw->phy.sfp_type = 1456 ixgbe_sfp_type_da_cu_core1; 1457 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1458 hw->phy.ops.read_i2c_eeprom( 1459 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1460 &cable_spec); 1461 if (cable_spec & 1462 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1463 if (hw->bus.lan_id == 0) 1464 hw->phy.sfp_type = 1465 ixgbe_sfp_type_da_act_lmt_core0; 1466 else 1467 hw->phy.sfp_type = 1468 ixgbe_sfp_type_da_act_lmt_core1; 1469 } else { 1470 hw->phy.sfp_type = 1471 ixgbe_sfp_type_unknown; 1472 } 1473 } else if (comp_codes_10g & 1474 (IXGBE_SFF_10GBASESR_CAPABLE | 1475 IXGBE_SFF_10GBASELR_CAPABLE)) { 1476 if (hw->bus.lan_id == 0) 1477 hw->phy.sfp_type = 1478 ixgbe_sfp_type_srlr_core0; 1479 else 1480 hw->phy.sfp_type = 1481 ixgbe_sfp_type_srlr_core1; 1482 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1483 if (hw->bus.lan_id == 0) 1484 hw->phy.sfp_type = 1485 ixgbe_sfp_type_1g_cu_core0; 1486 else 1487 hw->phy.sfp_type = 1488 ixgbe_sfp_type_1g_cu_core1; 1489 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1490 if (hw->bus.lan_id == 0) 1491 hw->phy.sfp_type = 1492 ixgbe_sfp_type_1g_sx_core0; 1493 else 1494 hw->phy.sfp_type = 1495 ixgbe_sfp_type_1g_sx_core1; 1496 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1497 if (hw->bus.lan_id == 0) 1498 hw->phy.sfp_type = 1499 ixgbe_sfp_type_1g_lx_core0; 1500 else 1501 hw->phy.sfp_type = 1502 ixgbe_sfp_type_1g_lx_core1; 1503 } else { 1504 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1505 } 1506 } 1507 1508 if (hw->phy.sfp_type != stored_sfp_type) 1509 hw->phy.sfp_setup_needed = TRUE; 1510 1511 /* Determine if the SFP+ PHY is dual speed or not. */ 1512 hw->phy.multispeed_fiber = FALSE; 1513 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1514 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1515 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1516 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1517 hw->phy.multispeed_fiber = TRUE; 1518 1519 /* Determine PHY vendor */ 1520 if (hw->phy.type != ixgbe_phy_nl) { 1521 hw->phy.id = identifier; 1522 status = hw->phy.ops.read_i2c_eeprom(hw, 1523 IXGBE_SFF_VENDOR_OUI_BYTE0, 1524 &oui_bytes[0]); 1525 1526 if (status != IXGBE_SUCCESS) 1527 goto err_read_i2c_eeprom; 1528 1529 status = hw->phy.ops.read_i2c_eeprom(hw, 1530 IXGBE_SFF_VENDOR_OUI_BYTE1, 1531 &oui_bytes[1]); 1532 1533 if (status != IXGBE_SUCCESS) 1534 goto err_read_i2c_eeprom; 1535 1536 status = hw->phy.ops.read_i2c_eeprom(hw, 1537 IXGBE_SFF_VENDOR_OUI_BYTE2, 1538 &oui_bytes[2]); 1539 1540 if (status != IXGBE_SUCCESS) 1541 goto err_read_i2c_eeprom; 1542 1543 vendor_oui = 1544 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1545 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1546 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1547 1548 switch (vendor_oui) { 1549 case IXGBE_SFF_VENDOR_OUI_TYCO: 1550 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1551 hw->phy.type = 1552 ixgbe_phy_sfp_passive_tyco; 1553 break; 1554 case IXGBE_SFF_VENDOR_OUI_FTL: 1555 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1556 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1557 else 1558 hw->phy.type = ixgbe_phy_sfp_ftl; 1559 break; 1560 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1561 hw->phy.type = ixgbe_phy_sfp_avago; 1562 break; 1563 case IXGBE_SFF_VENDOR_OUI_INTEL: 1564 hw->phy.type = ixgbe_phy_sfp_intel; 1565 break; 1566 default: 1567 hw->phy.type = ixgbe_phy_sfp_unknown; 1568 break; 1569 } 1570 } 1571 1572 /* Allow any DA cable vendor */ 1573 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1574 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1575 status = IXGBE_SUCCESS; 1576 1577 /* Keep phy.type for ixgbe_phy_nl */ 1578 if (hw->phy.type == ixgbe_phy_nl) 1579 goto out; 1580 1581 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1582 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1583 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1584 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1585 goto out; 1586 } 1587 1588 /* Verify supported 1G SFP modules */ 1589 if (comp_codes_10g == 0 && 1590 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1591 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1592 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1593 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1594 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1595 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1596 if (hw->phy.type != ixgbe_phy_nl) 1597 hw->phy.type = ixgbe_phy_sfp_unsupported; 1598 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1599 goto out; 1600 } 1601 1602 /* Anything else 82598-based is supported */ 1603 if (hw->mac.type == ixgbe_mac_82598EB) { 1604 status = IXGBE_SUCCESS; 1605 goto out; 1606 } 1607 1608 ixgbe_get_device_caps(hw, &enforce_sfp); 1609 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1610 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1611 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1612 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1613 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1614 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1615 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1616 /* Make sure we're a supported PHY type */ 1617 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1618 status = IXGBE_SUCCESS; 1619 } else { 1620 if (hw->allow_unsupported_sfp == TRUE) { 1621 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1622 status = IXGBE_SUCCESS; 1623 } else { 1624 DEBUGOUT("SFP+ module not supported\n"); 1625 if (hw->phy.type != ixgbe_phy_nl) 1626 hw->phy.type = 1627 ixgbe_phy_sfp_unsupported; 1628 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1629 } 1630 } 1631 } else { 1632 status = IXGBE_SUCCESS; 1633 } 1634 } 1635 1636 out: 1637 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1638 hw->need_unsupported_sfp_recovery = true; 1639 return status; 1640 1641 err_read_i2c_eeprom: 1642 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1643 if (hw->phy.type != ixgbe_phy_nl) { 1644 hw->phy.id = 0; 1645 hw->phy.type = ixgbe_phy_unknown; 1646 } 1647 return IXGBE_ERR_SFP_NOT_PRESENT; 1648 } 1649 1650 /** 1651 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1652 * @hw: pointer to hardware structure 1653 * 1654 * Determines physical layer capabilities of the current SFP. 1655 */ 1656 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1657 { 1658 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1659 u8 comp_codes_10g = 0; 1660 u8 comp_codes_1g = 0; 1661 1662 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1663 1664 hw->phy.ops.identify_sfp(hw); 1665 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1666 return physical_layer; 1667 1668 switch (hw->phy.type) { 1669 case ixgbe_phy_sfp_passive_tyco: 1670 case ixgbe_phy_sfp_passive_unknown: 1671 case ixgbe_phy_qsfp_passive_unknown: 1672 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1673 break; 1674 case ixgbe_phy_sfp_ftl_active: 1675 case ixgbe_phy_sfp_active_unknown: 1676 case ixgbe_phy_qsfp_active_unknown: 1677 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1678 break; 1679 case ixgbe_phy_sfp_avago: 1680 case ixgbe_phy_sfp_ftl: 1681 case ixgbe_phy_sfp_intel: 1682 case ixgbe_phy_sfp_unknown: 1683 hw->phy.ops.read_i2c_eeprom(hw, 1684 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1685 hw->phy.ops.read_i2c_eeprom(hw, 1686 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1687 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1688 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1689 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1690 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1691 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1692 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1693 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1694 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1695 break; 1696 case ixgbe_phy_qsfp_intel: 1697 case ixgbe_phy_qsfp_unknown: 1698 hw->phy.ops.read_i2c_eeprom(hw, 1699 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1700 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1701 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1702 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1703 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1704 break; 1705 default: 1706 break; 1707 } 1708 1709 return physical_layer; 1710 } 1711 1712 /** 1713 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1714 * @hw: pointer to hardware structure 1715 * 1716 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1717 **/ 1718 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1719 { 1720 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1721 u32 vendor_oui = 0; 1722 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1723 u8 identifier = 0; 1724 u8 comp_codes_1g = 0; 1725 u8 comp_codes_10g = 0; 1726 u8 oui_bytes[3] = {0, 0, 0}; 1727 u16 enforce_sfp = 0; 1728 u8 connector = 0; 1729 u8 cable_length = 0; 1730 u8 device_tech = 0; 1731 bool active_cable = FALSE; 1732 1733 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1734 1735 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1736 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1737 status = IXGBE_ERR_SFP_NOT_PRESENT; 1738 goto out; 1739 } 1740 1741 /* LAN ID is needed for I2C access */ 1742 hw->mac.ops.set_lan_id(hw); 1743 1744 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1745 &identifier); 1746 1747 if (status != IXGBE_SUCCESS) 1748 goto err_read_i2c_eeprom; 1749 1750 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1751 hw->phy.type = ixgbe_phy_sfp_unsupported; 1752 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1753 goto out; 1754 } 1755 1756 hw->phy.id = identifier; 1757 1758 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1759 &comp_codes_10g); 1760 1761 if (status != IXGBE_SUCCESS) 1762 goto err_read_i2c_eeprom; 1763 1764 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1765 &comp_codes_1g); 1766 1767 if (status != IXGBE_SUCCESS) 1768 goto err_read_i2c_eeprom; 1769 1770 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1771 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1772 if (hw->bus.lan_id == 0) 1773 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1774 else 1775 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1776 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1777 IXGBE_SFF_10GBASELR_CAPABLE)) { 1778 if (hw->bus.lan_id == 0) 1779 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1780 else 1781 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1782 } else { 1783 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1784 active_cable = TRUE; 1785 1786 if (!active_cable) { 1787 /* check for active DA cables that pre-date 1788 * SFF-8436 v3.6 */ 1789 hw->phy.ops.read_i2c_eeprom(hw, 1790 IXGBE_SFF_QSFP_CONNECTOR, 1791 &connector); 1792 1793 hw->phy.ops.read_i2c_eeprom(hw, 1794 IXGBE_SFF_QSFP_CABLE_LENGTH, 1795 &cable_length); 1796 1797 hw->phy.ops.read_i2c_eeprom(hw, 1798 IXGBE_SFF_QSFP_DEVICE_TECH, 1799 &device_tech); 1800 1801 if ((connector == 1802 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1803 (cable_length > 0) && 1804 ((device_tech >> 4) == 1805 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1806 active_cable = TRUE; 1807 } 1808 1809 if (active_cable) { 1810 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1811 if (hw->bus.lan_id == 0) 1812 hw->phy.sfp_type = 1813 ixgbe_sfp_type_da_act_lmt_core0; 1814 else 1815 hw->phy.sfp_type = 1816 ixgbe_sfp_type_da_act_lmt_core1; 1817 } else { 1818 /* unsupported module type */ 1819 hw->phy.type = ixgbe_phy_sfp_unsupported; 1820 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1821 goto out; 1822 } 1823 } 1824 1825 if (hw->phy.sfp_type != stored_sfp_type) 1826 hw->phy.sfp_setup_needed = TRUE; 1827 1828 /* Determine if the QSFP+ PHY is dual speed or not. */ 1829 hw->phy.multispeed_fiber = FALSE; 1830 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1831 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1832 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1833 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1834 hw->phy.multispeed_fiber = TRUE; 1835 1836 /* Determine PHY vendor for optical modules */ 1837 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1838 IXGBE_SFF_10GBASELR_CAPABLE)) { 1839 status = hw->phy.ops.read_i2c_eeprom(hw, 1840 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1841 &oui_bytes[0]); 1842 1843 if (status != IXGBE_SUCCESS) 1844 goto err_read_i2c_eeprom; 1845 1846 status = hw->phy.ops.read_i2c_eeprom(hw, 1847 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1848 &oui_bytes[1]); 1849 1850 if (status != IXGBE_SUCCESS) 1851 goto err_read_i2c_eeprom; 1852 1853 status = hw->phy.ops.read_i2c_eeprom(hw, 1854 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1855 &oui_bytes[2]); 1856 1857 if (status != IXGBE_SUCCESS) 1858 goto err_read_i2c_eeprom; 1859 1860 vendor_oui = 1861 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1862 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1863 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1864 1865 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1866 hw->phy.type = ixgbe_phy_qsfp_intel; 1867 else 1868 hw->phy.type = ixgbe_phy_qsfp_unknown; 1869 1870 ixgbe_get_device_caps(hw, &enforce_sfp); 1871 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1872 /* Make sure we're a supported PHY type */ 1873 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1874 status = IXGBE_SUCCESS; 1875 } else { 1876 if (hw->allow_unsupported_sfp == TRUE) { 1877 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1878 status = IXGBE_SUCCESS; 1879 } else { 1880 DEBUGOUT("QSFP module not supported\n"); 1881 hw->phy.type = 1882 ixgbe_phy_sfp_unsupported; 1883 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1884 } 1885 } 1886 } else { 1887 status = IXGBE_SUCCESS; 1888 } 1889 } 1890 1891 out: 1892 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1893 hw->need_unsupported_sfp_recovery = true; 1894 return status; 1895 1896 err_read_i2c_eeprom: 1897 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1898 hw->phy.id = 0; 1899 hw->phy.type = ixgbe_phy_unknown; 1900 1901 return IXGBE_ERR_SFP_NOT_PRESENT; 1902 } 1903 1904 /** 1905 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1906 * @hw: pointer to hardware structure 1907 * @list_offset: offset to the SFP ID list 1908 * @data_offset: offset to the SFP data block 1909 * 1910 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1911 * so it returns the offsets to the phy init sequence block. 1912 **/ 1913 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1914 u16 *list_offset, 1915 u16 *data_offset) 1916 { 1917 u16 sfp_id; 1918 u16 sfp_type = hw->phy.sfp_type; 1919 1920 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1921 1922 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1923 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1924 1925 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1926 return IXGBE_ERR_SFP_NOT_PRESENT; 1927 1928 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1929 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1930 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1931 1932 /* 1933 * Limiting active cables and 1G Phys must be initialized as 1934 * SR modules 1935 */ 1936 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1937 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1938 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1939 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1940 sfp_type = ixgbe_sfp_type_srlr_core0; 1941 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1942 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1943 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1944 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1945 sfp_type = ixgbe_sfp_type_srlr_core1; 1946 1947 /* Read offset to PHY init contents */ 1948 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1949 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1950 "eeprom read at offset %d failed", 1951 IXGBE_PHY_INIT_OFFSET_NL); 1952 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1953 } 1954 1955 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1956 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1957 1958 /* Shift offset to first ID word */ 1959 (*list_offset)++; 1960 1961 /* 1962 * Find the matching SFP ID in the EEPROM 1963 * and program the init sequence 1964 */ 1965 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1966 goto err_phy; 1967 1968 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1969 if (sfp_id == sfp_type) { 1970 (*list_offset)++; 1971 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1972 goto err_phy; 1973 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1974 DEBUGOUT("SFP+ module not supported\n"); 1975 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1976 } else { 1977 break; 1978 } 1979 } else { 1980 (*list_offset) += 2; 1981 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1982 goto err_phy; 1983 } 1984 } 1985 1986 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1987 DEBUGOUT("No matching SFP+ module found\n"); 1988 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1989 } 1990 1991 return IXGBE_SUCCESS; 1992 1993 err_phy: 1994 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1995 "eeprom read at offset %d failed", *list_offset); 1996 return IXGBE_ERR_PHY; 1997 } 1998 1999 /** 2000 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 2001 * @hw: pointer to hardware structure 2002 * @byte_offset: EEPROM byte offset to read 2003 * @eeprom_data: value read 2004 * 2005 * Performs byte read operation to SFP module's EEPROM over I2C interface. 2006 **/ 2007 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2008 u8 *eeprom_data) 2009 { 2010 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 2011 2012 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2013 IXGBE_I2C_EEPROM_DEV_ADDR, 2014 eeprom_data); 2015 } 2016 2017 /** 2018 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 2019 * @hw: pointer to hardware structure 2020 * @byte_offset: byte offset at address 0xA2 2021 * @sff8472_data: value read 2022 * 2023 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2024 **/ 2025 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2026 u8 *sff8472_data) 2027 { 2028 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2029 IXGBE_I2C_EEPROM_DEV_ADDR2, 2030 sff8472_data); 2031 } 2032 2033 /** 2034 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2035 * @hw: pointer to hardware structure 2036 * @byte_offset: EEPROM byte offset to write 2037 * @eeprom_data: value to write 2038 * 2039 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2040 **/ 2041 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2042 u8 eeprom_data) 2043 { 2044 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2045 2046 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2047 IXGBE_I2C_EEPROM_DEV_ADDR, 2048 eeprom_data); 2049 } 2050 2051 /** 2052 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2053 * @hw: pointer to hardware structure 2054 * @offset: eeprom offset to be read 2055 * @addr: I2C address to be read 2056 */ 2057 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2058 { 2059 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2060 offset == IXGBE_SFF_IDENTIFIER && 2061 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2062 return TRUE; 2063 return FALSE; 2064 } 2065 2066 /** 2067 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2068 * @hw: pointer to hardware structure 2069 * @byte_offset: byte offset to read 2070 * @dev_addr: address to read from 2071 * @data: value read 2072 * @lock: TRUE if to take and release semaphore 2073 * 2074 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2075 * a specified device address. 2076 **/ 2077 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2078 u8 dev_addr, u8 *data, bool lock) 2079 { 2080 s32 status; 2081 u32 max_retry = 10; 2082 u32 retry = 0; 2083 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2084 bool nack = 1; 2085 *data = 0; 2086 2087 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2088 2089 if (hw->mac.type >= ixgbe_mac_X550) 2090 max_retry = 3; 2091 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2092 max_retry = IXGBE_SFP_DETECT_RETRIES; 2093 2094 do { 2095 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2096 return IXGBE_ERR_SWFW_SYNC; 2097 2098 ixgbe_i2c_start(hw); 2099 2100 /* Device Address and write indication */ 2101 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2102 if (status != IXGBE_SUCCESS) 2103 goto fail; 2104 2105 status = ixgbe_get_i2c_ack(hw); 2106 if (status != IXGBE_SUCCESS) 2107 goto fail; 2108 2109 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2110 if (status != IXGBE_SUCCESS) 2111 goto fail; 2112 2113 status = ixgbe_get_i2c_ack(hw); 2114 if (status != IXGBE_SUCCESS) 2115 goto fail; 2116 2117 ixgbe_i2c_start(hw); 2118 2119 /* Device Address and read indication */ 2120 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2121 if (status != IXGBE_SUCCESS) 2122 goto fail; 2123 2124 status = ixgbe_get_i2c_ack(hw); 2125 if (status != IXGBE_SUCCESS) 2126 goto fail; 2127 2128 status = ixgbe_clock_in_i2c_byte(hw, data); 2129 if (status != IXGBE_SUCCESS) 2130 goto fail; 2131 2132 status = ixgbe_clock_out_i2c_bit(hw, nack); 2133 if (status != IXGBE_SUCCESS) 2134 goto fail; 2135 2136 ixgbe_i2c_stop(hw); 2137 if (lock) 2138 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2139 return IXGBE_SUCCESS; 2140 2141 fail: 2142 ixgbe_i2c_bus_clear(hw); 2143 if (lock) { 2144 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2145 msec_delay(100); 2146 } 2147 retry++; 2148 if (retry < max_retry) 2149 DEBUGOUT("I2C byte read error - Retrying.\n"); 2150 else 2151 DEBUGOUT("I2C byte read error.\n"); 2152 2153 } while (retry < max_retry); 2154 2155 return status; 2156 } 2157 2158 /** 2159 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2160 * @hw: pointer to hardware structure 2161 * @byte_offset: byte offset to read 2162 * @dev_addr: address to read from 2163 * @data: value read 2164 * 2165 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2166 * a specified device address. 2167 **/ 2168 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2169 u8 dev_addr, u8 *data) 2170 { 2171 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2172 data, TRUE); 2173 } 2174 2175 /** 2176 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2177 * @hw: pointer to hardware structure 2178 * @byte_offset: byte offset to read 2179 * @dev_addr: address to read from 2180 * @data: value read 2181 * 2182 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2183 * a specified device address. 2184 **/ 2185 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2186 u8 dev_addr, u8 *data) 2187 { 2188 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2189 data, FALSE); 2190 } 2191 2192 /** 2193 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2194 * @hw: pointer to hardware structure 2195 * @byte_offset: byte offset to write 2196 * @dev_addr: address to write to 2197 * @data: value to write 2198 * @lock: TRUE if to take and release semaphore 2199 * 2200 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2201 * a specified device address. 2202 **/ 2203 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2204 u8 dev_addr, u8 data, bool lock) 2205 { 2206 s32 status; 2207 u32 max_retry = 2; 2208 u32 retry = 0; 2209 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2210 2211 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2212 2213 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2214 IXGBE_SUCCESS) 2215 return IXGBE_ERR_SWFW_SYNC; 2216 2217 do { 2218 ixgbe_i2c_start(hw); 2219 2220 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2221 if (status != IXGBE_SUCCESS) 2222 goto fail; 2223 2224 status = ixgbe_get_i2c_ack(hw); 2225 if (status != IXGBE_SUCCESS) 2226 goto fail; 2227 2228 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2229 if (status != IXGBE_SUCCESS) 2230 goto fail; 2231 2232 status = ixgbe_get_i2c_ack(hw); 2233 if (status != IXGBE_SUCCESS) 2234 goto fail; 2235 2236 status = ixgbe_clock_out_i2c_byte(hw, data); 2237 if (status != IXGBE_SUCCESS) 2238 goto fail; 2239 2240 status = ixgbe_get_i2c_ack(hw); 2241 if (status != IXGBE_SUCCESS) 2242 goto fail; 2243 2244 ixgbe_i2c_stop(hw); 2245 if (lock) 2246 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2247 return IXGBE_SUCCESS; 2248 2249 fail: 2250 ixgbe_i2c_bus_clear(hw); 2251 retry++; 2252 if (retry < max_retry) 2253 DEBUGOUT("I2C byte write error - Retrying.\n"); 2254 else 2255 DEBUGOUT("I2C byte write error.\n"); 2256 } while (retry < max_retry); 2257 2258 if (lock) 2259 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2260 2261 return status; 2262 } 2263 2264 /** 2265 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2266 * @hw: pointer to hardware structure 2267 * @byte_offset: byte offset to write 2268 * @dev_addr: address to write to 2269 * @data: value to write 2270 * 2271 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2272 * a specified device address. 2273 **/ 2274 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2275 u8 dev_addr, u8 data) 2276 { 2277 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2278 data, TRUE); 2279 } 2280 2281 /** 2282 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2283 * @hw: pointer to hardware structure 2284 * @byte_offset: byte offset to write 2285 * @dev_addr: address to write to 2286 * @data: value to write 2287 * 2288 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2289 * a specified device address. 2290 **/ 2291 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2292 u8 dev_addr, u8 data) 2293 { 2294 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2295 data, FALSE); 2296 } 2297 2298 /** 2299 * ixgbe_i2c_start - Sets I2C start condition 2300 * @hw: pointer to hardware structure 2301 * 2302 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2303 * Set bit-bang mode on X550 hardware. 2304 **/ 2305 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2306 { 2307 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2308 2309 DEBUGFUNC("ixgbe_i2c_start"); 2310 2311 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2312 2313 /* Start condition must begin with data and clock high */ 2314 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2315 ixgbe_raise_i2c_clk(hw, &i2cctl); 2316 2317 /* Setup time for start condition (4.7us) */ 2318 usec_delay(IXGBE_I2C_T_SU_STA); 2319 2320 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2321 2322 /* Hold time for start condition (4us) */ 2323 usec_delay(IXGBE_I2C_T_HD_STA); 2324 2325 ixgbe_lower_i2c_clk(hw, &i2cctl); 2326 2327 /* Minimum low period of clock is 4.7 us */ 2328 usec_delay(IXGBE_I2C_T_LOW); 2329 2330 } 2331 2332 /** 2333 * ixgbe_i2c_stop - Sets I2C stop condition 2334 * @hw: pointer to hardware structure 2335 * 2336 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2337 * Disables bit-bang mode and negates data output enable on X550 2338 * hardware. 2339 **/ 2340 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2341 { 2342 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2343 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2344 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2345 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2346 2347 DEBUGFUNC("ixgbe_i2c_stop"); 2348 2349 /* Stop condition must begin with data low and clock high */ 2350 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2351 ixgbe_raise_i2c_clk(hw, &i2cctl); 2352 2353 /* Setup time for stop condition (4us) */ 2354 usec_delay(IXGBE_I2C_T_SU_STO); 2355 2356 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2357 2358 /* bus free time between stop and start (4.7us)*/ 2359 usec_delay(IXGBE_I2C_T_BUF); 2360 2361 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2362 i2cctl &= ~bb_en_bit; 2363 i2cctl |= data_oe_bit | clk_oe_bit; 2364 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2365 IXGBE_WRITE_FLUSH(hw); 2366 } 2367 } 2368 2369 /** 2370 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2371 * @hw: pointer to hardware structure 2372 * @data: data byte to clock in 2373 * 2374 * Clocks in one byte data via I2C data/clock 2375 **/ 2376 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2377 { 2378 s32 i; 2379 bool bit = 0; 2380 2381 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2382 2383 *data = 0; 2384 for (i = 7; i >= 0; i--) { 2385 ixgbe_clock_in_i2c_bit(hw, &bit); 2386 *data |= bit << i; 2387 } 2388 2389 return IXGBE_SUCCESS; 2390 } 2391 2392 /** 2393 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2394 * @hw: pointer to hardware structure 2395 * @data: data byte clocked out 2396 * 2397 * Clocks out one byte data via I2C data/clock 2398 **/ 2399 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2400 { 2401 s32 status = IXGBE_SUCCESS; 2402 s32 i; 2403 u32 i2cctl; 2404 bool bit; 2405 2406 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2407 2408 for (i = 7; i >= 0; i--) { 2409 bit = (data >> i) & 0x1; 2410 status = ixgbe_clock_out_i2c_bit(hw, bit); 2411 2412 if (status != IXGBE_SUCCESS) 2413 break; 2414 } 2415 2416 /* Release SDA line (set high) */ 2417 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2418 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2419 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2420 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2421 IXGBE_WRITE_FLUSH(hw); 2422 2423 return status; 2424 } 2425 2426 /** 2427 * ixgbe_get_i2c_ack - Polls for I2C ACK 2428 * @hw: pointer to hardware structure 2429 * 2430 * Clocks in/out one bit via I2C data/clock 2431 **/ 2432 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2433 { 2434 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2435 s32 status = IXGBE_SUCCESS; 2436 u32 i = 0; 2437 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2438 u32 timeout = 10; 2439 bool ack = 1; 2440 2441 DEBUGFUNC("ixgbe_get_i2c_ack"); 2442 2443 if (data_oe_bit) { 2444 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2445 i2cctl |= data_oe_bit; 2446 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2447 IXGBE_WRITE_FLUSH(hw); 2448 } 2449 ixgbe_raise_i2c_clk(hw, &i2cctl); 2450 2451 /* Minimum high period of clock is 4us */ 2452 usec_delay(IXGBE_I2C_T_HIGH); 2453 2454 /* Poll for ACK. Note that ACK in I2C spec is 2455 * transition from 1 to 0 */ 2456 for (i = 0; i < timeout; i++) { 2457 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2458 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2459 2460 usec_delay(1); 2461 if (!ack) 2462 break; 2463 } 2464 2465 if (ack) { 2466 DEBUGOUT("I2C ack was not received.\n"); 2467 status = IXGBE_ERR_I2C; 2468 } 2469 2470 ixgbe_lower_i2c_clk(hw, &i2cctl); 2471 2472 /* Minimum low period of clock is 4.7 us */ 2473 usec_delay(IXGBE_I2C_T_LOW); 2474 2475 return status; 2476 } 2477 2478 /** 2479 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2480 * @hw: pointer to hardware structure 2481 * @data: read data value 2482 * 2483 * Clocks in one bit via I2C data/clock 2484 **/ 2485 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2486 { 2487 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2488 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2489 2490 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2491 2492 if (data_oe_bit) { 2493 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2494 i2cctl |= data_oe_bit; 2495 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2496 IXGBE_WRITE_FLUSH(hw); 2497 } 2498 ixgbe_raise_i2c_clk(hw, &i2cctl); 2499 2500 /* Minimum high period of clock is 4us */ 2501 usec_delay(IXGBE_I2C_T_HIGH); 2502 2503 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2504 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2505 2506 ixgbe_lower_i2c_clk(hw, &i2cctl); 2507 2508 /* Minimum low period of clock is 4.7 us */ 2509 usec_delay(IXGBE_I2C_T_LOW); 2510 2511 return IXGBE_SUCCESS; 2512 } 2513 2514 /** 2515 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2516 * @hw: pointer to hardware structure 2517 * @data: data value to write 2518 * 2519 * Clocks out one bit via I2C data/clock 2520 **/ 2521 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2522 { 2523 s32 status; 2524 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2525 2526 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2527 2528 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2529 if (status == IXGBE_SUCCESS) { 2530 ixgbe_raise_i2c_clk(hw, &i2cctl); 2531 2532 /* Minimum high period of clock is 4us */ 2533 usec_delay(IXGBE_I2C_T_HIGH); 2534 2535 ixgbe_lower_i2c_clk(hw, &i2cctl); 2536 2537 /* Minimum low period of clock is 4.7 us. 2538 * This also takes care of the data hold time. 2539 */ 2540 usec_delay(IXGBE_I2C_T_LOW); 2541 } else { 2542 status = IXGBE_ERR_I2C; 2543 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2544 "I2C data was not set to %X\n", data); 2545 } 2546 2547 return status; 2548 } 2549 2550 /** 2551 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2552 * @hw: pointer to hardware structure 2553 * @i2cctl: Current value of I2CCTL register 2554 * 2555 * Raises the I2C clock line '0'->'1' 2556 * Negates the I2C clock output enable on X550 hardware. 2557 **/ 2558 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2559 { 2560 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2561 u32 i = 0; 2562 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2563 u32 i2cctl_r = 0; 2564 2565 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2566 2567 if (clk_oe_bit) { 2568 *i2cctl |= clk_oe_bit; 2569 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2570 } 2571 2572 for (i = 0; i < timeout; i++) { 2573 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2574 2575 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2576 IXGBE_WRITE_FLUSH(hw); 2577 /* SCL rise time (1000ns) */ 2578 usec_delay(IXGBE_I2C_T_RISE); 2579 2580 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2581 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2582 break; 2583 } 2584 } 2585 2586 /** 2587 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2588 * @hw: pointer to hardware structure 2589 * @i2cctl: Current value of I2CCTL register 2590 * 2591 * Lowers the I2C clock line '1'->'0' 2592 * Asserts the I2C clock output enable on X550 hardware. 2593 **/ 2594 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2595 { 2596 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2597 2598 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2599 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2600 2601 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2602 IXGBE_WRITE_FLUSH(hw); 2603 2604 /* SCL fall time (300ns) */ 2605 usec_delay(IXGBE_I2C_T_FALL); 2606 } 2607 2608 /** 2609 * ixgbe_set_i2c_data - Sets the I2C data bit 2610 * @hw: pointer to hardware structure 2611 * @i2cctl: Current value of I2CCTL register 2612 * @data: I2C data value (0 or 1) to set 2613 * 2614 * Sets the I2C data bit 2615 * Asserts the I2C data output enable on X550 hardware. 2616 **/ 2617 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2618 { 2619 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2620 s32 status = IXGBE_SUCCESS; 2621 2622 DEBUGFUNC("ixgbe_set_i2c_data"); 2623 2624 if (data) 2625 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2626 else 2627 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2628 *i2cctl &= ~data_oe_bit; 2629 2630 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2631 IXGBE_WRITE_FLUSH(hw); 2632 2633 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2634 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2635 2636 if (!data) /* Can't verify data in this case */ 2637 return IXGBE_SUCCESS; 2638 if (data_oe_bit) { 2639 *i2cctl |= data_oe_bit; 2640 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2641 IXGBE_WRITE_FLUSH(hw); 2642 } 2643 2644 /* Verify data was set correctly */ 2645 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2646 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2647 status = IXGBE_ERR_I2C; 2648 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2649 "Error - I2C data was not set to %X.\n", 2650 data); 2651 } 2652 2653 return status; 2654 } 2655 2656 /** 2657 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2658 * @hw: pointer to hardware structure 2659 * @i2cctl: Current value of I2CCTL register 2660 * 2661 * Returns the I2C data bit value 2662 * Negates the I2C data output enable on X550 hardware. 2663 **/ 2664 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2665 { 2666 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2667 bool data; 2668 2669 DEBUGFUNC("ixgbe_get_i2c_data"); 2670 2671 if (data_oe_bit) { 2672 *i2cctl |= data_oe_bit; 2673 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2674 IXGBE_WRITE_FLUSH(hw); 2675 usec_delay(IXGBE_I2C_T_FALL); 2676 } 2677 2678 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2679 data = 1; 2680 else 2681 data = 0; 2682 2683 return data; 2684 } 2685 2686 /** 2687 * ixgbe_i2c_bus_clear - Clears the I2C bus 2688 * @hw: pointer to hardware structure 2689 * 2690 * Clears the I2C bus by sending nine clock pulses. 2691 * Used when data line is stuck low. 2692 **/ 2693 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2694 { 2695 u32 i2cctl; 2696 u32 i; 2697 2698 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2699 2700 ixgbe_i2c_start(hw); 2701 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2702 2703 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2704 2705 for (i = 0; i < 9; i++) { 2706 ixgbe_raise_i2c_clk(hw, &i2cctl); 2707 2708 /* Min high period of clock is 4us */ 2709 usec_delay(IXGBE_I2C_T_HIGH); 2710 2711 ixgbe_lower_i2c_clk(hw, &i2cctl); 2712 2713 /* Min low period of clock is 4.7us*/ 2714 usec_delay(IXGBE_I2C_T_LOW); 2715 } 2716 2717 ixgbe_i2c_start(hw); 2718 2719 /* Put the i2c bus back to default state */ 2720 ixgbe_i2c_stop(hw); 2721 } 2722 2723 /** 2724 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2725 * @hw: pointer to hardware structure 2726 * 2727 * Checks if the LASI temp alarm status was triggered due to overtemp 2728 **/ 2729 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2730 { 2731 s32 status = IXGBE_SUCCESS; 2732 u16 phy_data = 0; 2733 2734 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2735 2736 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2737 goto out; 2738 2739 /* Check that the LASI temp alarm status was triggered */ 2740 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2741 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2742 2743 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2744 goto out; 2745 2746 status = IXGBE_ERR_OVERTEMP; 2747 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2748 out: 2749 return status; 2750 } 2751 2752 /** 2753 * ixgbe_set_copper_phy_power - Control power for copper phy 2754 * @hw: pointer to hardware structure 2755 * @on: TRUE for on, FALSE for off 2756 */ 2757 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2758 { 2759 u32 status; 2760 u16 reg; 2761 2762 if (!on && ixgbe_mng_present(hw)) 2763 return 0; 2764 2765 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2766 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2767 ®); 2768 if (status) 2769 return status; 2770 2771 if (on) { 2772 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2773 } else { 2774 if (ixgbe_check_reset_blocked(hw)) 2775 return 0; 2776 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2777 } 2778 2779 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2780 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2781 reg); 2782 return status; 2783 } 2784
Indexes created Thu Sep 25 16:09:42 GMT 2025