ixgbe_phy.c revision 1.26
1 /* $NetBSD: ixgbe_phy.c,v 1.26 2021/12/10 11:28:40 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ixgbe_phy.c,v 1.26 2021/12/10 11:28:40 msaitoh Exp $"); 40 41 #include "ixgbe_api.h" 42 #include "ixgbe_common.h" 43 #include "ixgbe_phy.h" 44 45 #include <dev/mii/mdio.h> 46 47 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 48 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 49 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 50 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 51 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 52 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 53 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 54 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 55 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 56 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 57 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 58 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 59 u8 *sff8472_data); 60 61 /** 62 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 63 * @hw: pointer to the hardware structure 64 * @byte: byte to send 65 * 66 * Returns an error code on error. 67 */ 68 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 69 { 70 s32 status; 71 72 status = ixgbe_clock_out_i2c_byte(hw, byte); 73 if (status) 74 return status; 75 return ixgbe_get_i2c_ack(hw); 76 } 77 78 /** 79 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 80 * @hw: pointer to the hardware structure 81 * @byte: pointer to a u8 to receive the byte 82 * 83 * Returns an error code on error. 84 */ 85 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 86 { 87 ixgbe_clock_in_i2c_byte(hw, byte); 88 /* ACK */ 89 return ixgbe_clock_out_i2c_bit(hw, FALSE); 90 } 91 92 /** 93 * ixgbe_ones_comp_byte_add - Perform one's complement addition 94 * @add1: addend 1 95 * @add2: addend 2 96 * 97 * Returns one's complement 8-bit sum. 98 */ 99 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 100 { 101 u16 sum = add1 + add2; 102 103 sum = (sum & 0xFF) + (sum >> 8); 104 return sum & 0xFF; 105 } 106 107 /** 108 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 109 * @hw: pointer to the hardware structure 110 * @addr: I2C bus address to read from 111 * @reg: I2C device register to read from 112 * @val: pointer to location to receive read value 113 * @lock: TRUE if to take and release semaphore 114 * 115 * Returns an error code on error. 116 */ 117 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 118 u16 *val, bool lock) 119 { 120 u32 swfw_mask = hw->phy.phy_semaphore_mask; 121 int max_retry = 3; 122 int retry = 0; 123 u8 csum_byte; 124 u8 high_bits; 125 u8 low_bits; 126 u8 reg_high; 127 u8 csum; 128 129 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 130 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 131 csum = ~csum; 132 do { 133 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 134 return IXGBE_ERR_SWFW_SYNC; 135 ixgbe_i2c_start(hw); 136 /* Device Address and write indication */ 137 if (ixgbe_out_i2c_byte_ack(hw, addr)) 138 goto fail; 139 /* Write bits 14:8 */ 140 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 141 goto fail; 142 /* Write bits 7:0 */ 143 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 144 goto fail; 145 /* Write csum */ 146 if (ixgbe_out_i2c_byte_ack(hw, csum)) 147 goto fail; 148 /* Re-start condition */ 149 ixgbe_i2c_start(hw); 150 /* Device Address and read indication */ 151 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 152 goto fail; 153 /* Get upper bits */ 154 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 155 goto fail; 156 /* Get low bits */ 157 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 158 goto fail; 159 /* Get csum */ 160 ixgbe_clock_in_i2c_byte(hw, &csum_byte); 161 /* NACK */ 162 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 163 goto fail; 164 ixgbe_i2c_stop(hw); 165 if (lock) 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 *val = (high_bits << 8) | low_bits; 168 return 0; 169 170 fail: 171 ixgbe_i2c_bus_clear(hw); 172 if (lock) 173 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 174 if (retry < max_retry) 175 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 176 else 177 DEBUGOUT("I2C byte read combined error.\n"); 178 retry++; 179 } while (retry <= max_retry); 180 181 return IXGBE_ERR_I2C; 182 } 183 184 /** 185 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 186 * @hw: pointer to the hardware structure 187 * @addr: I2C bus address to write to 188 * @reg: I2C device register to write to 189 * @val: value to write 190 * @lock: TRUE if to take and release semaphore 191 * 192 * Returns an error code on error. 193 */ 194 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 195 u16 val, bool lock) 196 { 197 u32 swfw_mask = hw->phy.phy_semaphore_mask; 198 int max_retry = 1; 199 int retry = 0; 200 u8 reg_high; 201 u8 csum; 202 203 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 204 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 205 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 206 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 207 csum = ~csum; 208 do { 209 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 210 return IXGBE_ERR_SWFW_SYNC; 211 ixgbe_i2c_start(hw); 212 /* Device Address and write indication */ 213 if (ixgbe_out_i2c_byte_ack(hw, addr)) 214 goto fail; 215 /* Write bits 14:8 */ 216 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 217 goto fail; 218 /* Write bits 7:0 */ 219 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 220 goto fail; 221 /* Write data 15:8 */ 222 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 223 goto fail; 224 /* Write data 7:0 */ 225 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 226 goto fail; 227 /* Write csum */ 228 if (ixgbe_out_i2c_byte_ack(hw, csum)) 229 goto fail; 230 ixgbe_i2c_stop(hw); 231 if (lock) 232 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 233 return 0; 234 235 fail: 236 ixgbe_i2c_bus_clear(hw); 237 if (lock) 238 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 239 if (retry < max_retry) 240 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 241 else 242 DEBUGOUT("I2C byte write combined error.\n"); 243 retry++; 244 } while (retry <= max_retry); 245 246 return IXGBE_ERR_I2C; 247 } 248 249 /** 250 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 251 * @hw: pointer to the hardware structure 252 * 253 * Initialize the function pointers. 254 **/ 255 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 256 { 257 struct ixgbe_phy_info *phy = &hw->phy; 258 259 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 260 261 /* PHY */ 262 phy->ops.identify = ixgbe_identify_phy_generic; 263 phy->ops.reset = ixgbe_reset_phy_generic; 264 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 265 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 266 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 267 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 268 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 269 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 270 phy->ops.check_link = NULL; 271 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 272 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 273 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 274 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 275 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 276 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 277 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 278 phy->ops.identify_sfp = ixgbe_identify_module_generic; 279 phy->sfp_type = ixgbe_sfp_type_unknown; 280 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 281 phy->ops.write_i2c_byte_unlocked = 282 ixgbe_write_i2c_byte_generic_unlocked; 283 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 284 return IXGBE_SUCCESS; 285 } 286 287 /** 288 * ixgbe_probe_phy - Probe a single address for a PHY 289 * @hw: pointer to hardware structure 290 * @phy_addr: PHY address to probe 291 * 292 * Returns TRUE if PHY found 293 */ 294 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 295 { 296 u16 ext_ability = 0; 297 298 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 299 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 300 phy_addr); 301 return FALSE; 302 } 303 304 if (ixgbe_get_phy_id(hw)) 305 return FALSE; 306 307 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 308 309 if (hw->phy.type == ixgbe_phy_unknown) { 310 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 311 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 312 if (ext_ability & 313 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 314 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 315 hw->phy.type = ixgbe_phy_cu_unknown; 316 else 317 hw->phy.type = ixgbe_phy_generic; 318 } 319 320 return TRUE; 321 } 322 323 /** 324 * ixgbe_identify_phy_generic - Get physical layer module 325 * @hw: pointer to hardware structure 326 * 327 * Determines the physical layer module found on the current adapter. 328 **/ 329 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 330 { 331 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 332 u16 phy_addr; 333 334 DEBUGFUNC("ixgbe_identify_phy_generic"); 335 336 if (!hw->phy.phy_semaphore_mask) { 337 if (hw->bus.lan_id) 338 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 339 else 340 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 341 } 342 343 if (hw->phy.type != ixgbe_phy_unknown) 344 return IXGBE_SUCCESS; 345 346 if (hw->phy.nw_mng_if_sel) { 347 phy_addr = (hw->phy.nw_mng_if_sel & 348 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 349 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 350 if (ixgbe_probe_phy(hw, phy_addr)) 351 return IXGBE_SUCCESS; 352 else 353 return IXGBE_ERR_PHY_ADDR_INVALID; 354 } 355 356 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 357 if (ixgbe_probe_phy(hw, phy_addr)) { 358 status = IXGBE_SUCCESS; 359 break; 360 } 361 } 362 363 /* Certain media types do not have a phy so an address will not 364 * be found and the code will take this path. Caller has to 365 * decide if it is an error or not. 366 */ 367 if (status != IXGBE_SUCCESS) 368 hw->phy.addr = 0; 369 370 return status; 371 } 372 373 /** 374 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 375 * @hw: pointer to the hardware structure 376 * 377 * This function checks the MMNGC.MNG_VETO bit to see if there are 378 * any constraints on link from manageability. For MAC's that don't 379 * have this bit just return faluse since the link can not be blocked 380 * via this method. 381 **/ 382 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 383 { 384 u32 mmngc; 385 386 DEBUGFUNC("ixgbe_check_reset_blocked"); 387 388 /* If we don't have this bit, it can't be blocking */ 389 if (hw->mac.type == ixgbe_mac_82598EB) 390 return FALSE; 391 392 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 393 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 394 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 395 "MNG_VETO bit detected.\n"); 396 return TRUE; 397 } 398 399 return FALSE; 400 } 401 402 /** 403 * ixgbe_validate_phy_addr - Determines phy address is valid 404 * @hw: pointer to hardware structure 405 * @phy_addr: PHY address 406 * 407 **/ 408 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 409 { 410 u16 phy_id = 0; 411 bool valid = FALSE; 412 413 DEBUGFUNC("ixgbe_validate_phy_addr"); 414 415 hw->phy.addr = phy_addr; 416 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 417 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 418 419 if (phy_id != 0xFFFF && phy_id != 0x0) 420 valid = TRUE; 421 422 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 423 424 return valid; 425 } 426 427 /** 428 * ixgbe_get_phy_id - Get the phy type 429 * @hw: pointer to hardware structure 430 * 431 **/ 432 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 433 { 434 u32 status; 435 u16 phy_id_high = 0; 436 u16 phy_id_low = 0; 437 438 DEBUGFUNC("ixgbe_get_phy_id"); 439 440 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 441 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 442 &phy_id_high); 443 444 if (status == IXGBE_SUCCESS) { 445 hw->phy.id = (u32)(phy_id_high << 16); 446 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 447 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 448 &phy_id_low); 449 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 450 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 451 } 452 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 453 phy_id_high, phy_id_low); 454 455 return status; 456 } 457 458 /** 459 * ixgbe_get_phy_type_from_id - Get the phy type 460 * @phy_id: PHY ID information 461 * 462 **/ 463 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 464 { 465 enum ixgbe_phy_type phy_type; 466 467 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 468 469 switch (phy_id) { 470 case TN1010_PHY_ID: 471 phy_type = ixgbe_phy_tn; 472 break; 473 case X550_PHY_ID2: 474 case X550_PHY_ID3: 475 case X540_PHY_ID: 476 phy_type = ixgbe_phy_aq; 477 break; 478 case QT2022_PHY_ID: 479 phy_type = ixgbe_phy_qt; 480 break; 481 case ATH_PHY_ID: 482 phy_type = ixgbe_phy_nl; 483 break; 484 case X557_PHY_ID: 485 case X557_PHY_ID2: 486 phy_type = ixgbe_phy_x550em_ext_t; 487 break; 488 case IXGBE_M88E1500_E_PHY_ID: 489 case IXGBE_M88E1543_E_PHY_ID: 490 phy_type = ixgbe_phy_ext_1g_t; 491 break; 492 default: 493 phy_type = ixgbe_phy_unknown; 494 break; 495 } 496 return phy_type; 497 } 498 499 /** 500 * ixgbe_reset_phy_generic - Performs a PHY reset 501 * @hw: pointer to hardware structure 502 **/ 503 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 504 { 505 u32 i; 506 u16 ctrl = 0; 507 s32 status = IXGBE_SUCCESS; 508 509 DEBUGFUNC("ixgbe_reset_phy_generic"); 510 511 if (hw->phy.type == ixgbe_phy_unknown) 512 status = ixgbe_identify_phy_generic(hw); 513 514 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 515 goto out; 516 517 /* Don't reset PHY if it's shut down due to overtemp. */ 518 if (!hw->phy.reset_if_overtemp && 519 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 520 goto out; 521 522 /* Blocked by MNG FW so bail */ 523 if (ixgbe_check_reset_blocked(hw)) 524 goto out; 525 526 /* 527 * Perform soft PHY reset to the PHY_XS. 528 * This will cause a soft reset to the PHY 529 */ 530 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 531 IXGBE_MDIO_PHY_XS_DEV_TYPE, 532 IXGBE_MDIO_PHY_XS_RESET); 533 534 /* 535 * Poll for reset bit to self-clear indicating reset is complete. 536 * Some PHYs could take up to 3 seconds to complete and need about 537 * 1.7 usec delay after the reset is complete. 538 */ 539 for (i = 0; i < 30; i++) { 540 msec_delay(100); 541 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 542 status = hw->phy.ops.read_reg(hw, 543 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 544 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 545 &ctrl); 546 if (status != IXGBE_SUCCESS) 547 return status; 548 549 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 550 usec_delay(2); 551 break; 552 } 553 } else { 554 status = hw->phy.ops.read_reg(hw, 555 IXGBE_MDIO_PHY_XS_CONTROL, 556 IXGBE_MDIO_PHY_XS_DEV_TYPE, 557 &ctrl); 558 if (status != IXGBE_SUCCESS) 559 return status; 560 561 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 562 usec_delay(2); 563 break; 564 } 565 } 566 } 567 568 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 569 status = IXGBE_ERR_RESET_FAILED; 570 ERROR_REPORT1(IXGBE_ERROR_POLLING, 571 "PHY reset polling failed to complete.\n"); 572 } 573 574 out: 575 return status; 576 } 577 578 /** 579 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 580 * the SWFW lock 581 * @hw: pointer to hardware structure 582 * @reg_addr: 32 bit address of PHY register to read 583 * @device_type: 5 bit device type 584 * @phy_data: Pointer to read data from PHY register 585 **/ 586 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 587 u16 *phy_data) 588 { 589 u32 i, data, command; 590 591 /* Setup and write the address cycle command */ 592 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 593 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 594 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 595 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 596 597 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 598 599 /* 600 * Check every 10 usec to see if the address cycle completed. 601 * The MDI Command bit will clear when the operation is 602 * complete 603 */ 604 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 605 usec_delay(10); 606 607 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 608 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 609 break; 610 } 611 612 613 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 614 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 615 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 616 return IXGBE_ERR_PHY; 617 } 618 619 /* 620 * Address cycle complete, setup and write the read 621 * command 622 */ 623 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 624 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 625 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 626 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 627 628 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 629 630 /* 631 * Check every 10 usec to see if the address cycle 632 * completed. The MDI Command bit will clear when the 633 * operation is complete 634 */ 635 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 636 usec_delay(10); 637 638 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 639 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 640 break; 641 } 642 643 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 644 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 645 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 646 return IXGBE_ERR_PHY; 647 } 648 649 /* 650 * Read operation is complete. Get the data 651 * from MSRWD 652 */ 653 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 654 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 655 *phy_data = (u16)(data); 656 657 return IXGBE_SUCCESS; 658 } 659 660 /** 661 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 662 * using the SWFW lock - this function is needed in most cases 663 * @hw: pointer to hardware structure 664 * @reg_addr: 32 bit address of PHY register to read 665 * @device_type: 5 bit device type 666 * @phy_data: Pointer to read data from PHY register 667 **/ 668 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 669 u32 device_type, u16 *phy_data) 670 { 671 s32 status; 672 u32 gssr = hw->phy.phy_semaphore_mask; 673 674 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 675 676 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 677 return IXGBE_ERR_SWFW_SYNC; 678 679 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 680 681 hw->mac.ops.release_swfw_sync(hw, gssr); 682 683 return status; 684 } 685 686 /** 687 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 688 * without SWFW lock 689 * @hw: pointer to hardware structure 690 * @reg_addr: 32 bit PHY register to write 691 * @device_type: 5 bit device type 692 * @phy_data: Data to write to the PHY register 693 **/ 694 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 695 u32 device_type, u16 phy_data) 696 { 697 u32 i, command; 698 699 /* Put the data in the MDI single read and write data register*/ 700 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 701 702 /* Setup and write the address cycle command */ 703 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 704 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 705 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 706 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 707 708 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 709 710 /* 711 * Check every 10 usec to see if the address cycle completed. 712 * The MDI Command bit will clear when the operation is 713 * complete 714 */ 715 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 716 usec_delay(10); 717 718 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 719 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 720 break; 721 } 722 723 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 724 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 725 return IXGBE_ERR_PHY; 726 } 727 728 /* 729 * Address cycle complete, setup and write the write 730 * command 731 */ 732 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 733 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 734 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 735 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 736 737 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 738 739 /* 740 * Check every 10 usec to see if the address cycle 741 * completed. The MDI Command bit will clear when the 742 * operation is complete 743 */ 744 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 745 usec_delay(10); 746 747 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 748 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 749 break; 750 } 751 752 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 753 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 754 return IXGBE_ERR_PHY; 755 } 756 757 return IXGBE_SUCCESS; 758 } 759 760 /** 761 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 762 * using SWFW lock- this function is needed in most cases 763 * @hw: pointer to hardware structure 764 * @reg_addr: 32 bit PHY register to write 765 * @device_type: 5 bit device type 766 * @phy_data: Data to write to the PHY register 767 **/ 768 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 769 u32 device_type, u16 phy_data) 770 { 771 s32 status; 772 u32 gssr = hw->phy.phy_semaphore_mask; 773 774 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 775 776 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 777 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 778 phy_data); 779 hw->mac.ops.release_swfw_sync(hw, gssr); 780 } else { 781 status = IXGBE_ERR_SWFW_SYNC; 782 } 783 784 return status; 785 } 786 787 /** 788 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 789 * @hw: pointer to hardware structure 790 * 791 * Restart auto-negotiation and PHY and waits for completion. 792 **/ 793 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 794 { 795 s32 status = IXGBE_SUCCESS; 796 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 797 bool autoneg = FALSE; 798 ixgbe_link_speed speed; 799 800 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 801 802 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 803 804 /* Set or unset auto-negotiation 10G advertisement */ 805 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 806 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 807 &autoneg_reg); 808 809 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 810 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 811 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 812 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 813 814 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 815 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 816 autoneg_reg); 817 818 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 820 &autoneg_reg); 821 822 if (hw->mac.type == ixgbe_mac_X550) { 823 /* Set or unset auto-negotiation 5G advertisement */ 824 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 825 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 826 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 827 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 828 829 /* Set or unset auto-negotiation 2.5G advertisement */ 830 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 831 if ((hw->phy.autoneg_advertised & 832 IXGBE_LINK_SPEED_2_5GB_FULL) && 833 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 834 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 835 } 836 837 /* Set or unset auto-negotiation 1G advertisement */ 838 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 839 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 840 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 841 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 842 843 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 844 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 845 autoneg_reg); 846 847 /* Set or unset auto-negotiation 100M advertisement */ 848 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 849 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 850 &autoneg_reg); 851 852 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 853 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 854 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 855 (speed & IXGBE_LINK_SPEED_100_FULL)) 856 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 857 858 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 859 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 860 autoneg_reg); 861 862 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) { 863 u16 ctrl; 864 865 /* Force 100Mbps */ 866 hw->phy.ops.read_reg(hw, MDIO_PMAPMD_CTRL1, MDIO_MMD_PMAPMD, 867 &ctrl); 868 ctrl &= ~PMAPMD_CTRL1_SPEED_MASK; 869 ctrl |= PMAPMD_CTRL1_SPEED_100; 870 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD, 871 ctrl); 872 873 /* Don't use auto-nego for 100Mbps */ 874 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 875 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 876 877 autoneg_reg &= ~AN_CTRL1_AUTOEN; 878 879 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 880 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 881 } else { 882 /* Blocked by MNG FW so don't reset PHY */ 883 if (ixgbe_check_reset_blocked(hw)) 884 return status; 885 886 /* Restart PHY auto-negotiation. */ 887 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 888 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 889 890 autoneg_reg |= IXGBE_MII_RESTART | AN_CTRL1_AUTOEN; 891 892 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 893 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 894 } 895 896 return status; 897 } 898 899 /** 900 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 901 * @hw: pointer to hardware structure 902 * @speed: new link speed 903 * @autoneg_wait_to_complete: unused 904 **/ 905 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 906 ixgbe_link_speed speed, 907 bool autoneg_wait_to_complete) 908 { 909 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 910 911 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 912 913 /* 914 * Clear autoneg_advertised and set new values based on input link 915 * speed. 916 */ 917 hw->phy.autoneg_advertised = 0; 918 919 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 920 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 921 922 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 923 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 924 925 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 926 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 927 928 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 929 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 930 931 if (speed & IXGBE_LINK_SPEED_100_FULL) 932 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 933 934 if (speed & IXGBE_LINK_SPEED_10_FULL) 935 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 936 937 /* Setup link based on the new speed settings */ 938 ixgbe_setup_phy_link(hw); 939 940 return IXGBE_SUCCESS; 941 } 942 943 /** 944 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 945 * @hw: pointer to hardware structure 946 * 947 * Determines the supported link capabilities by reading the PHY auto 948 * negotiation register. 949 **/ 950 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 951 { 952 s32 status; 953 u16 speed_ability; 954 955 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 956 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 957 &speed_ability); 958 if (status) 959 return status; 960 961 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 962 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 963 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 964 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 965 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 966 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 967 968 switch (hw->mac.type) { 969 case ixgbe_mac_X550: 970 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 971 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 972 break; 973 case ixgbe_mac_X550EM_x: 974 case ixgbe_mac_X550EM_a: 975 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 976 break; 977 default: 978 break; 979 } 980 981 return status; 982 } 983 984 /** 985 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 986 * @hw: pointer to hardware structure 987 * @speed: pointer to link speed 988 * @autoneg: boolean auto-negotiation value 989 **/ 990 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 991 ixgbe_link_speed *speed, 992 bool *autoneg) 993 { 994 s32 status = IXGBE_SUCCESS; 995 996 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 997 998 *autoneg = TRUE; 999 if (!hw->phy.speeds_supported) 1000 status = ixgbe_get_copper_speeds_supported(hw); 1001 1002 *speed = hw->phy.speeds_supported; 1003 return status; 1004 } 1005 1006 /** 1007 * ixgbe_check_phy_link_tnx - Determine link and speed status 1008 * @hw: pointer to hardware structure 1009 * @speed: current link speed 1010 * @link_up: TRUE is link is up, FALSE otherwise 1011 * 1012 * Reads the VS1 register to determine if link is up and the current speed for 1013 * the PHY. 1014 **/ 1015 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1016 bool *link_up) 1017 { 1018 s32 status = IXGBE_SUCCESS; 1019 u32 time_out; 1020 u32 max_time_out = 10; 1021 u16 phy_link = 0; 1022 u16 phy_speed = 0; 1023 u16 phy_data = 0; 1024 1025 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1026 1027 /* Initialize speed and link to default case */ 1028 *link_up = FALSE; 1029 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1030 1031 /* 1032 * Check current speed and link status of the PHY register. 1033 * This is a vendor specific register and may have to 1034 * be changed for other copper PHYs. 1035 */ 1036 for (time_out = 0; time_out < max_time_out; time_out++) { 1037 usec_delay(10); 1038 status = hw->phy.ops.read_reg(hw, 1039 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1040 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1041 &phy_data); 1042 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1043 phy_speed = phy_data & 1044 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1045 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1046 *link_up = TRUE; 1047 if (phy_speed == 1048 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1049 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1050 break; 1051 } 1052 } 1053 1054 return status; 1055 } 1056 1057 /** 1058 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1059 * @hw: pointer to hardware structure 1060 * 1061 * Restart auto-negotiation and PHY and waits for completion. 1062 **/ 1063 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1064 { 1065 s32 status = IXGBE_SUCCESS; 1066 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1067 bool autoneg = FALSE; 1068 ixgbe_link_speed speed; 1069 1070 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1071 1072 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1073 1074 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1075 /* Set or unset auto-negotiation 10G advertisement */ 1076 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1077 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1078 &autoneg_reg); 1079 1080 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1081 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1082 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1083 1084 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1086 autoneg_reg); 1087 } 1088 1089 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1090 /* Set or unset auto-negotiation 1G advertisement */ 1091 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1092 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1093 &autoneg_reg); 1094 1095 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1096 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1097 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1098 1099 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1100 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1101 autoneg_reg); 1102 } 1103 1104 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1105 /* Set or unset auto-negotiation 100M advertisement */ 1106 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1107 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1108 &autoneg_reg); 1109 1110 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1111 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1112 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1113 1114 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1115 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1116 autoneg_reg); 1117 } 1118 1119 /* Blocked by MNG FW so don't reset PHY */ 1120 if (ixgbe_check_reset_blocked(hw)) 1121 return status; 1122 1123 /* Restart PHY auto-negotiation. */ 1124 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1125 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1126 1127 autoneg_reg |= IXGBE_MII_RESTART; 1128 1129 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1130 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1131 1132 return status; 1133 } 1134 1135 /** 1136 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1137 * @hw: pointer to hardware structure 1138 * @firmware_version: pointer to the PHY Firmware Version 1139 **/ 1140 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1141 u16 *firmware_version) 1142 { 1143 s32 status; 1144 1145 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1146 1147 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1148 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1149 firmware_version); 1150 1151 return status; 1152 } 1153 1154 /** 1155 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1156 * @hw: pointer to hardware structure 1157 * @firmware_version: pointer to the PHY Firmware Version 1158 **/ 1159 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1160 u16 *firmware_version) 1161 { 1162 s32 status; 1163 1164 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1165 1166 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1167 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1168 firmware_version); 1169 1170 return status; 1171 } 1172 1173 /** 1174 * ixgbe_reset_phy_nl - Performs a PHY reset 1175 * @hw: pointer to hardware structure 1176 **/ 1177 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1178 { 1179 u16 phy_offset, control, eword, edata, block_crc; 1180 bool end_data = FALSE; 1181 u16 list_offset, data_offset; 1182 u16 phy_data = 0; 1183 s32 ret_val = IXGBE_SUCCESS; 1184 u32 i; 1185 1186 DEBUGFUNC("ixgbe_reset_phy_nl"); 1187 1188 /* Blocked by MNG FW so bail */ 1189 if (ixgbe_check_reset_blocked(hw)) 1190 goto out; 1191 1192 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1193 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1194 1195 /* reset the PHY and poll for completion */ 1196 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1197 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1198 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1199 1200 for (i = 0; i < 100; i++) { 1201 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1202 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1203 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1204 break; 1205 msec_delay(10); 1206 } 1207 1208 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1209 DEBUGOUT("PHY reset did not complete.\n"); 1210 ret_val = IXGBE_ERR_PHY; 1211 goto out; 1212 } 1213 1214 /* Get init offsets */ 1215 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1216 &data_offset); 1217 if (ret_val != IXGBE_SUCCESS) 1218 goto out; 1219 1220 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1221 data_offset++; 1222 while (!end_data) { 1223 /* 1224 * Read control word from PHY init contents offset 1225 */ 1226 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1227 if (ret_val) 1228 goto err_eeprom; 1229 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1230 IXGBE_CONTROL_SHIFT_NL; 1231 edata = eword & IXGBE_DATA_MASK_NL; 1232 switch (control) { 1233 case IXGBE_DELAY_NL: 1234 data_offset++; 1235 DEBUGOUT1("DELAY: %d MS\n", edata); 1236 msec_delay(edata); 1237 break; 1238 case IXGBE_DATA_NL: 1239 DEBUGOUT("DATA:\n"); 1240 data_offset++; 1241 ret_val = hw->eeprom.ops.read(hw, data_offset, 1242 &phy_offset); 1243 if (ret_val) 1244 goto err_eeprom; 1245 data_offset++; 1246 for (i = 0; i < edata; i++) { 1247 ret_val = hw->eeprom.ops.read(hw, data_offset, 1248 &eword); 1249 if (ret_val) 1250 goto err_eeprom; 1251 hw->phy.ops.write_reg(hw, phy_offset, 1252 IXGBE_TWINAX_DEV, eword); 1253 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1254 phy_offset); 1255 data_offset++; 1256 phy_offset++; 1257 } 1258 break; 1259 case IXGBE_CONTROL_NL: 1260 data_offset++; 1261 DEBUGOUT("CONTROL:\n"); 1262 if (edata == IXGBE_CONTROL_EOL_NL) { 1263 DEBUGOUT("EOL\n"); 1264 end_data = TRUE; 1265 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1266 DEBUGOUT("SOL\n"); 1267 } else { 1268 DEBUGOUT("Bad control value\n"); 1269 ret_val = IXGBE_ERR_PHY; 1270 goto out; 1271 } 1272 break; 1273 default: 1274 DEBUGOUT("Bad control type\n"); 1275 ret_val = IXGBE_ERR_PHY; 1276 goto out; 1277 } 1278 } 1279 1280 out: 1281 return ret_val; 1282 1283 err_eeprom: 1284 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1285 "eeprom read at offset %d failed", data_offset); 1286 return IXGBE_ERR_PHY; 1287 } 1288 1289 /************************************************************************ 1290 * ixgbe_sfp_cage_full 1291 * 1292 * Determine if an SFP+ module is inserted to the cage. 1293 ************************************************************************/ 1294 bool 1295 ixgbe_sfp_cage_full(struct ixgbe_hw *hw) 1296 { 1297 uint32_t mask; 1298 int rv; 1299 1300 KASSERT(hw->mac.type != ixgbe_mac_82598EB); 1301 1302 if (hw->mac.type >= ixgbe_mac_X540) 1303 mask = IXGBE_ESDP_SDP0; 1304 else 1305 mask = IXGBE_ESDP_SDP2; 1306 1307 rv = IXGBE_READ_REG(hw, IXGBE_ESDP) & mask; 1308 if ((hw->quirks & IXGBE_QUIRK_MOD_ABS_INVERT) != 0) 1309 rv = !rv; 1310 1311 if (hw->mac.type == ixgbe_mac_X550EM_a) { 1312 /* X550EM_a's SDP0 is inverted than others. */ 1313 return !rv; 1314 } 1315 1316 return rv; 1317 } /* ixgbe_sfp_cage_full */ 1318 1319 /** 1320 * ixgbe_identify_module_generic - Identifies module type 1321 * @hw: pointer to hardware structure 1322 * 1323 * Determines HW type and calls appropriate function. 1324 **/ 1325 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1326 { 1327 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1328 1329 DEBUGFUNC("ixgbe_identify_module_generic"); 1330 1331 /* Lightweight way to check if the cage is not full. */ 1332 if (hw->mac.type != ixgbe_mac_82598EB) { 1333 if (!ixgbe_sfp_cage_full(hw)) { 1334 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1335 return IXGBE_ERR_SFP_NOT_PRESENT; 1336 } 1337 } 1338 1339 switch (hw->mac.ops.get_media_type(hw)) { 1340 case ixgbe_media_type_fiber: 1341 status = ixgbe_identify_sfp_module_generic(hw); 1342 break; 1343 1344 case ixgbe_media_type_fiber_qsfp: 1345 status = ixgbe_identify_qsfp_module_generic(hw); 1346 break; 1347 1348 default: 1349 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1350 status = IXGBE_ERR_SFP_NOT_PRESENT; 1351 break; 1352 } 1353 1354 return status; 1355 } 1356 1357 /** 1358 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1359 * @hw: pointer to hardware structure 1360 * 1361 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1362 **/ 1363 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1364 { 1365 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1366 u32 vendor_oui = 0; 1367 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1368 u8 identifier = 0; 1369 u8 comp_codes_1g = 0; 1370 u8 comp_codes_10g = 0; 1371 u8 oui_bytes[3] = {0, 0, 0}; 1372 u8 cable_tech = 0; 1373 u8 cable_spec = 0; 1374 u16 enforce_sfp = 0; 1375 1376 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1377 1378 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1379 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1380 status = IXGBE_ERR_SFP_NOT_PRESENT; 1381 goto out; 1382 } 1383 1384 /* LAN ID is needed for I2C access */ 1385 hw->mac.ops.set_lan_id(hw); 1386 1387 status = hw->phy.ops.read_i2c_eeprom(hw, 1388 IXGBE_SFF_IDENTIFIER, 1389 &identifier); 1390 1391 if (status != IXGBE_SUCCESS) 1392 goto err_read_i2c_eeprom; 1393 1394 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1395 if (hw->phy.type != ixgbe_phy_nl) 1396 hw->phy.type = ixgbe_phy_sfp_unsupported; 1397 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1398 } else { 1399 status = hw->phy.ops.read_i2c_eeprom(hw, 1400 IXGBE_SFF_1GBE_COMP_CODES, 1401 &comp_codes_1g); 1402 1403 if (status != IXGBE_SUCCESS) 1404 goto err_read_i2c_eeprom; 1405 1406 status = hw->phy.ops.read_i2c_eeprom(hw, 1407 IXGBE_SFF_10GBE_COMP_CODES, 1408 &comp_codes_10g); 1409 1410 if (status != IXGBE_SUCCESS) 1411 goto err_read_i2c_eeprom; 1412 status = hw->phy.ops.read_i2c_eeprom(hw, 1413 IXGBE_SFF_CABLE_TECHNOLOGY, 1414 &cable_tech); 1415 1416 if (status != IXGBE_SUCCESS) 1417 goto err_read_i2c_eeprom; 1418 1419 /* ID Module 1420 * ========= 1421 * 0 SFP_DA_CU 1422 * 1 SFP_SR 1423 * 2 SFP_LR 1424 * 3 SFP_DA_CORE0 - 82599-specific 1425 * 4 SFP_DA_CORE1 - 82599-specific 1426 * 5 SFP_SR/LR_CORE0 - 82599-specific 1427 * 6 SFP_SR/LR_CORE1 - 82599-specific 1428 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1429 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1430 * 9 SFP_1g_cu_CORE0 - 82599-specific 1431 * 10 SFP_1g_cu_CORE1 - 82599-specific 1432 * 11 SFP_1g_sx_CORE0 - 82599-specific 1433 * 12 SFP_1g_sx_CORE1 - 82599-specific 1434 */ 1435 if (hw->mac.type == ixgbe_mac_82598EB) { 1436 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1437 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1438 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1439 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1440 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1441 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1442 else 1443 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1444 } else { 1445 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1446 if (hw->bus.lan_id == 0) 1447 hw->phy.sfp_type = 1448 ixgbe_sfp_type_da_cu_core0; 1449 else 1450 hw->phy.sfp_type = 1451 ixgbe_sfp_type_da_cu_core1; 1452 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1453 hw->phy.ops.read_i2c_eeprom( 1454 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1455 &cable_spec); 1456 if (cable_spec & 1457 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1458 if (hw->bus.lan_id == 0) 1459 hw->phy.sfp_type = 1460 ixgbe_sfp_type_da_act_lmt_core0; 1461 else 1462 hw->phy.sfp_type = 1463 ixgbe_sfp_type_da_act_lmt_core1; 1464 } else { 1465 hw->phy.sfp_type = 1466 ixgbe_sfp_type_unknown; 1467 } 1468 } else if (comp_codes_10g & 1469 (IXGBE_SFF_10GBASESR_CAPABLE | 1470 IXGBE_SFF_10GBASELR_CAPABLE)) { 1471 if (hw->bus.lan_id == 0) 1472 hw->phy.sfp_type = 1473 ixgbe_sfp_type_srlr_core0; 1474 else 1475 hw->phy.sfp_type = 1476 ixgbe_sfp_type_srlr_core1; 1477 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1478 if (hw->bus.lan_id == 0) 1479 hw->phy.sfp_type = 1480 ixgbe_sfp_type_1g_cu_core0; 1481 else 1482 hw->phy.sfp_type = 1483 ixgbe_sfp_type_1g_cu_core1; 1484 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1485 if (hw->bus.lan_id == 0) 1486 hw->phy.sfp_type = 1487 ixgbe_sfp_type_1g_sx_core0; 1488 else 1489 hw->phy.sfp_type = 1490 ixgbe_sfp_type_1g_sx_core1; 1491 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1492 if (hw->bus.lan_id == 0) 1493 hw->phy.sfp_type = 1494 ixgbe_sfp_type_1g_lx_core0; 1495 else 1496 hw->phy.sfp_type = 1497 ixgbe_sfp_type_1g_lx_core1; 1498 } else { 1499 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1500 } 1501 } 1502 1503 if (hw->phy.sfp_type != stored_sfp_type) 1504 hw->phy.sfp_setup_needed = TRUE; 1505 1506 /* Determine if the SFP+ PHY is dual speed or not. */ 1507 hw->phy.multispeed_fiber = FALSE; 1508 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1509 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1510 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1511 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1512 hw->phy.multispeed_fiber = TRUE; 1513 1514 /* Determine PHY vendor */ 1515 if (hw->phy.type != ixgbe_phy_nl) { 1516 hw->phy.id = identifier; 1517 status = hw->phy.ops.read_i2c_eeprom(hw, 1518 IXGBE_SFF_VENDOR_OUI_BYTE0, 1519 &oui_bytes[0]); 1520 1521 if (status != IXGBE_SUCCESS) 1522 goto err_read_i2c_eeprom; 1523 1524 status = hw->phy.ops.read_i2c_eeprom(hw, 1525 IXGBE_SFF_VENDOR_OUI_BYTE1, 1526 &oui_bytes[1]); 1527 1528 if (status != IXGBE_SUCCESS) 1529 goto err_read_i2c_eeprom; 1530 1531 status = hw->phy.ops.read_i2c_eeprom(hw, 1532 IXGBE_SFF_VENDOR_OUI_BYTE2, 1533 &oui_bytes[2]); 1534 1535 if (status != IXGBE_SUCCESS) 1536 goto err_read_i2c_eeprom; 1537 1538 vendor_oui = 1539 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1540 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1541 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1542 1543 switch (vendor_oui) { 1544 case IXGBE_SFF_VENDOR_OUI_TYCO: 1545 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1546 hw->phy.type = 1547 ixgbe_phy_sfp_passive_tyco; 1548 break; 1549 case IXGBE_SFF_VENDOR_OUI_FTL: 1550 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1551 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1552 else 1553 hw->phy.type = ixgbe_phy_sfp_ftl; 1554 break; 1555 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1556 hw->phy.type = ixgbe_phy_sfp_avago; 1557 break; 1558 case IXGBE_SFF_VENDOR_OUI_INTEL: 1559 hw->phy.type = ixgbe_phy_sfp_intel; 1560 break; 1561 default: 1562 hw->phy.type = ixgbe_phy_sfp_unknown; 1563 break; 1564 } 1565 } 1566 1567 /* Allow any DA cable vendor */ 1568 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1569 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1570 status = IXGBE_SUCCESS; 1571 1572 /* Keep phy.type for ixgbe_phy_nl */ 1573 if (hw->phy.type == ixgbe_phy_nl) 1574 goto out; 1575 1576 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1577 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1578 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1579 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1580 goto out; 1581 } 1582 1583 /* Verify supported 1G SFP modules */ 1584 if (comp_codes_10g == 0 && 1585 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1586 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1587 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1588 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1589 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1590 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1591 if (hw->phy.type != ixgbe_phy_nl) 1592 hw->phy.type = ixgbe_phy_sfp_unsupported; 1593 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1594 goto out; 1595 } 1596 1597 /* Anything else 82598-based is supported */ 1598 if (hw->mac.type == ixgbe_mac_82598EB) { 1599 status = IXGBE_SUCCESS; 1600 goto out; 1601 } 1602 1603 ixgbe_get_device_caps(hw, &enforce_sfp); 1604 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1605 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1606 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1607 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1608 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1609 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1610 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1611 /* Make sure we're a supported PHY type */ 1612 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1613 status = IXGBE_SUCCESS; 1614 } else { 1615 if (hw->allow_unsupported_sfp == TRUE) { 1616 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1617 status = IXGBE_SUCCESS; 1618 } else { 1619 DEBUGOUT("SFP+ module not supported\n"); 1620 if (hw->phy.type != ixgbe_phy_nl) 1621 hw->phy.type = 1622 ixgbe_phy_sfp_unsupported; 1623 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1624 } 1625 } 1626 } else { 1627 status = IXGBE_SUCCESS; 1628 } 1629 } 1630 1631 out: 1632 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1633 hw->need_unsupported_sfp_recovery = true; 1634 return status; 1635 1636 err_read_i2c_eeprom: 1637 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1638 if (hw->phy.type != ixgbe_phy_nl) { 1639 hw->phy.id = 0; 1640 hw->phy.type = ixgbe_phy_unknown; 1641 } 1642 return IXGBE_ERR_SFP_NOT_PRESENT; 1643 } 1644 1645 /** 1646 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1647 * @hw: pointer to hardware structure 1648 * 1649 * Determines physical layer capabilities of the current SFP. 1650 */ 1651 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1652 { 1653 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1654 u8 comp_codes_10g = 0; 1655 u8 comp_codes_1g = 0; 1656 1657 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1658 1659 hw->phy.ops.identify_sfp(hw); 1660 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1661 return physical_layer; 1662 1663 switch (hw->phy.type) { 1664 case ixgbe_phy_sfp_passive_tyco: 1665 case ixgbe_phy_sfp_passive_unknown: 1666 case ixgbe_phy_qsfp_passive_unknown: 1667 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1668 break; 1669 case ixgbe_phy_sfp_ftl_active: 1670 case ixgbe_phy_sfp_active_unknown: 1671 case ixgbe_phy_qsfp_active_unknown: 1672 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1673 break; 1674 case ixgbe_phy_sfp_avago: 1675 case ixgbe_phy_sfp_ftl: 1676 case ixgbe_phy_sfp_intel: 1677 case ixgbe_phy_sfp_unknown: 1678 hw->phy.ops.read_i2c_eeprom(hw, 1679 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1680 hw->phy.ops.read_i2c_eeprom(hw, 1681 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1682 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1683 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1684 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1685 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1686 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1687 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1688 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1689 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1690 break; 1691 case ixgbe_phy_qsfp_intel: 1692 case ixgbe_phy_qsfp_unknown: 1693 hw->phy.ops.read_i2c_eeprom(hw, 1694 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1695 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1696 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1697 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1698 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1699 break; 1700 default: 1701 break; 1702 } 1703 1704 return physical_layer; 1705 } 1706 1707 /** 1708 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1709 * @hw: pointer to hardware structure 1710 * 1711 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1712 **/ 1713 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1714 { 1715 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1716 u32 vendor_oui = 0; 1717 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1718 u8 identifier = 0; 1719 u8 comp_codes_1g = 0; 1720 u8 comp_codes_10g = 0; 1721 u8 oui_bytes[3] = {0, 0, 0}; 1722 u16 enforce_sfp = 0; 1723 u8 connector = 0; 1724 u8 cable_length = 0; 1725 u8 device_tech = 0; 1726 bool active_cable = FALSE; 1727 1728 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1729 1730 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1731 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1732 status = IXGBE_ERR_SFP_NOT_PRESENT; 1733 goto out; 1734 } 1735 1736 /* LAN ID is needed for I2C access */ 1737 hw->mac.ops.set_lan_id(hw); 1738 1739 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1740 &identifier); 1741 1742 if (status != IXGBE_SUCCESS) 1743 goto err_read_i2c_eeprom; 1744 1745 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1746 hw->phy.type = ixgbe_phy_sfp_unsupported; 1747 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1748 goto out; 1749 } 1750 1751 hw->phy.id = identifier; 1752 1753 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1754 &comp_codes_10g); 1755 1756 if (status != IXGBE_SUCCESS) 1757 goto err_read_i2c_eeprom; 1758 1759 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1760 &comp_codes_1g); 1761 1762 if (status != IXGBE_SUCCESS) 1763 goto err_read_i2c_eeprom; 1764 1765 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1766 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1767 if (hw->bus.lan_id == 0) 1768 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1769 else 1770 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1771 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1772 IXGBE_SFF_10GBASELR_CAPABLE)) { 1773 if (hw->bus.lan_id == 0) 1774 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1775 else 1776 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1777 } else { 1778 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1779 active_cable = TRUE; 1780 1781 if (!active_cable) { 1782 /* check for active DA cables that pre-date 1783 * SFF-8436 v3.6 */ 1784 hw->phy.ops.read_i2c_eeprom(hw, 1785 IXGBE_SFF_QSFP_CONNECTOR, 1786 &connector); 1787 1788 hw->phy.ops.read_i2c_eeprom(hw, 1789 IXGBE_SFF_QSFP_CABLE_LENGTH, 1790 &cable_length); 1791 1792 hw->phy.ops.read_i2c_eeprom(hw, 1793 IXGBE_SFF_QSFP_DEVICE_TECH, 1794 &device_tech); 1795 1796 if ((connector == 1797 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1798 (cable_length > 0) && 1799 ((device_tech >> 4) == 1800 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1801 active_cable = TRUE; 1802 } 1803 1804 if (active_cable) { 1805 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1806 if (hw->bus.lan_id == 0) 1807 hw->phy.sfp_type = 1808 ixgbe_sfp_type_da_act_lmt_core0; 1809 else 1810 hw->phy.sfp_type = 1811 ixgbe_sfp_type_da_act_lmt_core1; 1812 } else { 1813 /* unsupported module type */ 1814 hw->phy.type = ixgbe_phy_sfp_unsupported; 1815 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1816 goto out; 1817 } 1818 } 1819 1820 if (hw->phy.sfp_type != stored_sfp_type) 1821 hw->phy.sfp_setup_needed = TRUE; 1822 1823 /* Determine if the QSFP+ PHY is dual speed or not. */ 1824 hw->phy.multispeed_fiber = FALSE; 1825 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1826 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1827 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1828 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1829 hw->phy.multispeed_fiber = TRUE; 1830 1831 /* Determine PHY vendor for optical modules */ 1832 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1833 IXGBE_SFF_10GBASELR_CAPABLE)) { 1834 status = hw->phy.ops.read_i2c_eeprom(hw, 1835 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1836 &oui_bytes[0]); 1837 1838 if (status != IXGBE_SUCCESS) 1839 goto err_read_i2c_eeprom; 1840 1841 status = hw->phy.ops.read_i2c_eeprom(hw, 1842 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1843 &oui_bytes[1]); 1844 1845 if (status != IXGBE_SUCCESS) 1846 goto err_read_i2c_eeprom; 1847 1848 status = hw->phy.ops.read_i2c_eeprom(hw, 1849 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1850 &oui_bytes[2]); 1851 1852 if (status != IXGBE_SUCCESS) 1853 goto err_read_i2c_eeprom; 1854 1855 vendor_oui = 1856 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1857 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1858 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1859 1860 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1861 hw->phy.type = ixgbe_phy_qsfp_intel; 1862 else 1863 hw->phy.type = ixgbe_phy_qsfp_unknown; 1864 1865 ixgbe_get_device_caps(hw, &enforce_sfp); 1866 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1867 /* Make sure we're a supported PHY type */ 1868 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1869 status = IXGBE_SUCCESS; 1870 } else { 1871 if (hw->allow_unsupported_sfp == TRUE) { 1872 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1873 status = IXGBE_SUCCESS; 1874 } else { 1875 DEBUGOUT("QSFP module not supported\n"); 1876 hw->phy.type = 1877 ixgbe_phy_sfp_unsupported; 1878 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1879 } 1880 } 1881 } else { 1882 status = IXGBE_SUCCESS; 1883 } 1884 } 1885 1886 out: 1887 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1888 hw->need_unsupported_sfp_recovery = true; 1889 return status; 1890 1891 err_read_i2c_eeprom: 1892 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1893 hw->phy.id = 0; 1894 hw->phy.type = ixgbe_phy_unknown; 1895 1896 return IXGBE_ERR_SFP_NOT_PRESENT; 1897 } 1898 1899 /** 1900 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1901 * @hw: pointer to hardware structure 1902 * @list_offset: offset to the SFP ID list 1903 * @data_offset: offset to the SFP data block 1904 * 1905 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1906 * so it returns the offsets to the phy init sequence block. 1907 **/ 1908 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1909 u16 *list_offset, 1910 u16 *data_offset) 1911 { 1912 u16 sfp_id; 1913 u16 sfp_type = hw->phy.sfp_type; 1914 1915 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1916 1917 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1918 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1919 1920 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1921 return IXGBE_ERR_SFP_NOT_PRESENT; 1922 1923 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1924 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1925 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1926 1927 /* 1928 * Limiting active cables and 1G Phys must be initialized as 1929 * SR modules 1930 */ 1931 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1932 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1933 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1934 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1935 sfp_type = ixgbe_sfp_type_srlr_core0; 1936 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1937 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1938 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1939 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1940 sfp_type = ixgbe_sfp_type_srlr_core1; 1941 1942 /* Read offset to PHY init contents */ 1943 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1944 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1945 "eeprom read at offset %d failed", 1946 IXGBE_PHY_INIT_OFFSET_NL); 1947 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1948 } 1949 1950 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1951 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1952 1953 /* Shift offset to first ID word */ 1954 (*list_offset)++; 1955 1956 /* 1957 * Find the matching SFP ID in the EEPROM 1958 * and program the init sequence 1959 */ 1960 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1961 goto err_phy; 1962 1963 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1964 if (sfp_id == sfp_type) { 1965 (*list_offset)++; 1966 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1967 goto err_phy; 1968 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1969 DEBUGOUT("SFP+ module not supported\n"); 1970 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1971 } else { 1972 break; 1973 } 1974 } else { 1975 (*list_offset) += 2; 1976 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1977 goto err_phy; 1978 } 1979 } 1980 1981 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1982 DEBUGOUT("No matching SFP+ module found\n"); 1983 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1984 } 1985 1986 return IXGBE_SUCCESS; 1987 1988 err_phy: 1989 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1990 "eeprom read at offset %d failed", *list_offset); 1991 return IXGBE_ERR_PHY; 1992 } 1993 1994 /** 1995 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1996 * @hw: pointer to hardware structure 1997 * @byte_offset: EEPROM byte offset to read 1998 * @eeprom_data: value read 1999 * 2000 * Performs byte read operation to SFP module's EEPROM over I2C interface. 2001 **/ 2002 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2003 u8 *eeprom_data) 2004 { 2005 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 2006 2007 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2008 IXGBE_I2C_EEPROM_DEV_ADDR, 2009 eeprom_data); 2010 } 2011 2012 /** 2013 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 2014 * @hw: pointer to hardware structure 2015 * @byte_offset: byte offset at address 0xA2 2016 * @sff8472_data: value read 2017 * 2018 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2019 **/ 2020 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2021 u8 *sff8472_data) 2022 { 2023 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2024 IXGBE_I2C_EEPROM_DEV_ADDR2, 2025 sff8472_data); 2026 } 2027 2028 /** 2029 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2030 * @hw: pointer to hardware structure 2031 * @byte_offset: EEPROM byte offset to write 2032 * @eeprom_data: value to write 2033 * 2034 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2035 **/ 2036 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2037 u8 eeprom_data) 2038 { 2039 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2040 2041 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2042 IXGBE_I2C_EEPROM_DEV_ADDR, 2043 eeprom_data); 2044 } 2045 2046 /** 2047 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2048 * @hw: pointer to hardware structure 2049 * @offset: eeprom offset to be read 2050 * @addr: I2C address to be read 2051 */ 2052 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2053 { 2054 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2055 offset == IXGBE_SFF_IDENTIFIER && 2056 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2057 return TRUE; 2058 return FALSE; 2059 } 2060 2061 /** 2062 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2063 * @hw: pointer to hardware structure 2064 * @byte_offset: byte offset to read 2065 * @dev_addr: address to read from 2066 * @data: value read 2067 * @lock: TRUE if to take and release semaphore 2068 * 2069 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2070 * a specified device address. 2071 **/ 2072 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2073 u8 dev_addr, u8 *data, bool lock) 2074 { 2075 s32 status; 2076 u32 max_retry = 10; 2077 u32 retry = 0; 2078 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2079 bool nack = 1; 2080 *data = 0; 2081 2082 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2083 2084 if (hw->mac.type >= ixgbe_mac_X550) 2085 max_retry = 3; 2086 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2087 max_retry = IXGBE_SFP_DETECT_RETRIES; 2088 2089 do { 2090 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2091 return IXGBE_ERR_SWFW_SYNC; 2092 2093 ixgbe_i2c_start(hw); 2094 2095 /* Device Address and write indication */ 2096 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2097 if (status != IXGBE_SUCCESS) 2098 goto fail; 2099 2100 status = ixgbe_get_i2c_ack(hw); 2101 if (status != IXGBE_SUCCESS) 2102 goto fail; 2103 2104 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2105 if (status != IXGBE_SUCCESS) 2106 goto fail; 2107 2108 status = ixgbe_get_i2c_ack(hw); 2109 if (status != IXGBE_SUCCESS) 2110 goto fail; 2111 2112 ixgbe_i2c_start(hw); 2113 2114 /* Device Address and read indication */ 2115 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2116 if (status != IXGBE_SUCCESS) 2117 goto fail; 2118 2119 status = ixgbe_get_i2c_ack(hw); 2120 if (status != IXGBE_SUCCESS) 2121 goto fail; 2122 2123 ixgbe_clock_in_i2c_byte(hw, data); 2124 2125 status = ixgbe_clock_out_i2c_bit(hw, nack); 2126 if (status != IXGBE_SUCCESS) 2127 goto fail; 2128 2129 ixgbe_i2c_stop(hw); 2130 if (lock) 2131 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2132 return IXGBE_SUCCESS; 2133 2134 fail: 2135 ixgbe_i2c_bus_clear(hw); 2136 if (lock) { 2137 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2138 msec_delay(100); 2139 } 2140 if (retry < max_retry) 2141 DEBUGOUT("I2C byte read error - Retrying.\n"); 2142 else 2143 DEBUGOUT("I2C byte read error.\n"); 2144 retry++; 2145 2146 } while (retry <= max_retry); 2147 2148 return status; 2149 } 2150 2151 /** 2152 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2153 * @hw: pointer to hardware structure 2154 * @byte_offset: byte offset to read 2155 * @dev_addr: address to read from 2156 * @data: value read 2157 * 2158 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2159 * a specified device address. 2160 **/ 2161 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2162 u8 dev_addr, u8 *data) 2163 { 2164 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2165 data, TRUE); 2166 } 2167 2168 /** 2169 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2170 * @hw: pointer to hardware structure 2171 * @byte_offset: byte offset to read 2172 * @dev_addr: address to read from 2173 * @data: value read 2174 * 2175 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2176 * a specified device address. 2177 **/ 2178 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2179 u8 dev_addr, u8 *data) 2180 { 2181 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2182 data, FALSE); 2183 } 2184 2185 /** 2186 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2187 * @hw: pointer to hardware structure 2188 * @byte_offset: byte offset to write 2189 * @dev_addr: address to write to 2190 * @data: value to write 2191 * @lock: TRUE if to take and release semaphore 2192 * 2193 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2194 * a specified device address. 2195 **/ 2196 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2197 u8 dev_addr, u8 data, bool lock) 2198 { 2199 s32 status; 2200 u32 max_retry = 2; 2201 u32 retry = 0; 2202 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2203 2204 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2205 2206 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2207 IXGBE_SUCCESS) 2208 return IXGBE_ERR_SWFW_SYNC; 2209 2210 do { 2211 ixgbe_i2c_start(hw); 2212 2213 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2214 if (status != IXGBE_SUCCESS) 2215 goto fail; 2216 2217 status = ixgbe_get_i2c_ack(hw); 2218 if (status != IXGBE_SUCCESS) 2219 goto fail; 2220 2221 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2222 if (status != IXGBE_SUCCESS) 2223 goto fail; 2224 2225 status = ixgbe_get_i2c_ack(hw); 2226 if (status != IXGBE_SUCCESS) 2227 goto fail; 2228 2229 status = ixgbe_clock_out_i2c_byte(hw, data); 2230 if (status != IXGBE_SUCCESS) 2231 goto fail; 2232 2233 status = ixgbe_get_i2c_ack(hw); 2234 if (status != IXGBE_SUCCESS) 2235 goto fail; 2236 2237 ixgbe_i2c_stop(hw); 2238 if (lock) 2239 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2240 return IXGBE_SUCCESS; 2241 2242 fail: 2243 ixgbe_i2c_bus_clear(hw); 2244 if (retry < max_retry) 2245 DEBUGOUT("I2C byte write error - Retrying.\n"); 2246 else 2247 DEBUGOUT("I2C byte write error.\n"); 2248 retry++; 2249 } while (retry <= max_retry); 2250 2251 if (lock) 2252 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2253 2254 return status; 2255 } 2256 2257 /** 2258 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2259 * @hw: pointer to hardware structure 2260 * @byte_offset: byte offset to write 2261 * @dev_addr: address to write to 2262 * @data: value to write 2263 * 2264 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2265 * a specified device address. 2266 **/ 2267 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2268 u8 dev_addr, u8 data) 2269 { 2270 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2271 data, TRUE); 2272 } 2273 2274 /** 2275 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2276 * @hw: pointer to hardware structure 2277 * @byte_offset: byte offset to write 2278 * @dev_addr: address to write to 2279 * @data: value to write 2280 * 2281 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2282 * a specified device address. 2283 **/ 2284 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2285 u8 dev_addr, u8 data) 2286 { 2287 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2288 data, FALSE); 2289 } 2290 2291 /** 2292 * ixgbe_i2c_start - Sets I2C start condition 2293 * @hw: pointer to hardware structure 2294 * 2295 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2296 * Set bit-bang mode on X550 hardware. 2297 **/ 2298 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2299 { 2300 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2301 2302 DEBUGFUNC("ixgbe_i2c_start"); 2303 2304 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2305 2306 /* Start condition must begin with data and clock high */ 2307 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2308 ixgbe_raise_i2c_clk(hw, &i2cctl); 2309 2310 /* Setup time for start condition (4.7us) */ 2311 usec_delay(IXGBE_I2C_T_SU_STA); 2312 2313 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2314 2315 /* Hold time for start condition (4us) */ 2316 usec_delay(IXGBE_I2C_T_HD_STA); 2317 2318 ixgbe_lower_i2c_clk(hw, &i2cctl); 2319 2320 /* Minimum low period of clock is 4.7 us */ 2321 usec_delay(IXGBE_I2C_T_LOW); 2322 2323 } 2324 2325 /** 2326 * ixgbe_i2c_stop - Sets I2C stop condition 2327 * @hw: pointer to hardware structure 2328 * 2329 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2330 * Disables bit-bang mode and negates data output enable on X550 2331 * hardware. 2332 **/ 2333 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2334 { 2335 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2336 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2337 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2338 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2339 2340 DEBUGFUNC("ixgbe_i2c_stop"); 2341 2342 /* Stop condition must begin with data low and clock high */ 2343 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2344 ixgbe_raise_i2c_clk(hw, &i2cctl); 2345 2346 /* Setup time for stop condition (4us) */ 2347 usec_delay(IXGBE_I2C_T_SU_STO); 2348 2349 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2350 2351 /* bus free time between stop and start (4.7us)*/ 2352 usec_delay(IXGBE_I2C_T_BUF); 2353 2354 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2355 i2cctl &= ~bb_en_bit; 2356 i2cctl |= data_oe_bit | clk_oe_bit; 2357 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2358 IXGBE_WRITE_FLUSH(hw); 2359 } 2360 } 2361 2362 /** 2363 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2364 * @hw: pointer to hardware structure 2365 * @data: data byte to clock in 2366 * 2367 * Clocks in one byte data via I2C data/clock 2368 **/ 2369 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2370 { 2371 s32 i; 2372 bool bit = 0; 2373 2374 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2375 2376 *data = 0; 2377 for (i = 7; i >= 0; i--) { 2378 ixgbe_clock_in_i2c_bit(hw, &bit); 2379 *data |= bit << i; 2380 } 2381 } 2382 2383 /** 2384 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2385 * @hw: pointer to hardware structure 2386 * @data: data byte clocked out 2387 * 2388 * Clocks out one byte data via I2C data/clock 2389 **/ 2390 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2391 { 2392 s32 status = IXGBE_SUCCESS; 2393 s32 i; 2394 u32 i2cctl; 2395 bool bit; 2396 2397 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2398 2399 for (i = 7; i >= 0; i--) { 2400 bit = (data >> i) & 0x1; 2401 status = ixgbe_clock_out_i2c_bit(hw, bit); 2402 2403 if (status != IXGBE_SUCCESS) 2404 break; 2405 } 2406 2407 /* Release SDA line (set high) */ 2408 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2409 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2410 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2411 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2412 IXGBE_WRITE_FLUSH(hw); 2413 2414 return status; 2415 } 2416 2417 /** 2418 * ixgbe_get_i2c_ack - Polls for I2C ACK 2419 * @hw: pointer to hardware structure 2420 * 2421 * Clocks in/out one bit via I2C data/clock 2422 **/ 2423 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2424 { 2425 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2426 s32 status = IXGBE_SUCCESS; 2427 u32 i = 0; 2428 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2429 u32 timeout = 10; 2430 bool ack = 1; 2431 2432 DEBUGFUNC("ixgbe_get_i2c_ack"); 2433 2434 if (data_oe_bit) { 2435 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2436 i2cctl |= data_oe_bit; 2437 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2438 IXGBE_WRITE_FLUSH(hw); 2439 } 2440 ixgbe_raise_i2c_clk(hw, &i2cctl); 2441 2442 /* Minimum high period of clock is 4us */ 2443 usec_delay(IXGBE_I2C_T_HIGH); 2444 2445 /* Poll for ACK. Note that ACK in I2C spec is 2446 * transition from 1 to 0 */ 2447 for (i = 0; i < timeout; i++) { 2448 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2449 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2450 2451 usec_delay(1); 2452 if (!ack) 2453 break; 2454 } 2455 2456 if (ack) { 2457 DEBUGOUT("I2C ack was not received.\n"); 2458 status = IXGBE_ERR_I2C; 2459 } 2460 2461 ixgbe_lower_i2c_clk(hw, &i2cctl); 2462 2463 /* Minimum low period of clock is 4.7 us */ 2464 usec_delay(IXGBE_I2C_T_LOW); 2465 2466 return status; 2467 } 2468 2469 /** 2470 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2471 * @hw: pointer to hardware structure 2472 * @data: read data value 2473 * 2474 * Clocks in one bit via I2C data/clock 2475 **/ 2476 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2477 { 2478 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2479 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2480 2481 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2482 2483 if (data_oe_bit) { 2484 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2485 i2cctl |= data_oe_bit; 2486 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2487 IXGBE_WRITE_FLUSH(hw); 2488 } 2489 ixgbe_raise_i2c_clk(hw, &i2cctl); 2490 2491 /* Minimum high period of clock is 4us */ 2492 usec_delay(IXGBE_I2C_T_HIGH); 2493 2494 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2495 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2496 2497 ixgbe_lower_i2c_clk(hw, &i2cctl); 2498 2499 /* Minimum low period of clock is 4.7 us */ 2500 usec_delay(IXGBE_I2C_T_LOW); 2501 } 2502 2503 /** 2504 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2505 * @hw: pointer to hardware structure 2506 * @data: data value to write 2507 * 2508 * Clocks out one bit via I2C data/clock 2509 **/ 2510 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2511 { 2512 s32 status; 2513 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2514 2515 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2516 2517 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2518 if (status == IXGBE_SUCCESS) { 2519 ixgbe_raise_i2c_clk(hw, &i2cctl); 2520 2521 /* Minimum high period of clock is 4us */ 2522 usec_delay(IXGBE_I2C_T_HIGH); 2523 2524 ixgbe_lower_i2c_clk(hw, &i2cctl); 2525 2526 /* Minimum low period of clock is 4.7 us. 2527 * This also takes care of the data hold time. 2528 */ 2529 usec_delay(IXGBE_I2C_T_LOW); 2530 } else { 2531 status = IXGBE_ERR_I2C; 2532 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2533 "I2C data was not set to %X\n", data); 2534 } 2535 2536 return status; 2537 } 2538 2539 /** 2540 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2541 * @hw: pointer to hardware structure 2542 * @i2cctl: Current value of I2CCTL register 2543 * 2544 * Raises the I2C clock line '0'->'1' 2545 * Negates the I2C clock output enable on X550 hardware. 2546 **/ 2547 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2548 { 2549 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2550 u32 i = 0; 2551 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2552 u32 i2cctl_r = 0; 2553 2554 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2555 2556 if (clk_oe_bit) { 2557 *i2cctl |= clk_oe_bit; 2558 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2559 } 2560 2561 for (i = 0; i < timeout; i++) { 2562 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2563 2564 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2565 IXGBE_WRITE_FLUSH(hw); 2566 /* SCL rise time (1000ns) */ 2567 usec_delay(IXGBE_I2C_T_RISE); 2568 2569 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2570 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2571 break; 2572 } 2573 } 2574 2575 /** 2576 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2577 * @hw: pointer to hardware structure 2578 * @i2cctl: Current value of I2CCTL register 2579 * 2580 * Lowers the I2C clock line '1'->'0' 2581 * Asserts the I2C clock output enable on X550 hardware. 2582 **/ 2583 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2584 { 2585 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2586 2587 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2588 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2589 2590 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2591 IXGBE_WRITE_FLUSH(hw); 2592 2593 /* SCL fall time (300ns) */ 2594 usec_delay(IXGBE_I2C_T_FALL); 2595 } 2596 2597 /** 2598 * ixgbe_set_i2c_data - Sets the I2C data bit 2599 * @hw: pointer to hardware structure 2600 * @i2cctl: Current value of I2CCTL register 2601 * @data: I2C data value (0 or 1) to set 2602 * 2603 * Sets the I2C data bit 2604 * Asserts the I2C data output enable on X550 hardware. 2605 **/ 2606 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2607 { 2608 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2609 s32 status = IXGBE_SUCCESS; 2610 2611 DEBUGFUNC("ixgbe_set_i2c_data"); 2612 2613 if (data) 2614 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2615 else 2616 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2617 *i2cctl &= ~data_oe_bit; 2618 2619 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2620 IXGBE_WRITE_FLUSH(hw); 2621 2622 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2623 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2624 2625 if (!data) /* Can't verify data in this case */ 2626 return IXGBE_SUCCESS; 2627 if (data_oe_bit) { 2628 *i2cctl |= data_oe_bit; 2629 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2630 IXGBE_WRITE_FLUSH(hw); 2631 } 2632 2633 /* Verify data was set correctly */ 2634 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2635 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2636 status = IXGBE_ERR_I2C; 2637 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2638 "Error - I2C data was not set to %X.\n", 2639 data); 2640 } 2641 2642 return status; 2643 } 2644 2645 /** 2646 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2647 * @hw: pointer to hardware structure 2648 * @i2cctl: Current value of I2CCTL register 2649 * 2650 * Returns the I2C data bit value 2651 * Negates the I2C data output enable on X550 hardware. 2652 **/ 2653 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2654 { 2655 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2656 bool data; 2657 2658 DEBUGFUNC("ixgbe_get_i2c_data"); 2659 2660 if (data_oe_bit) { 2661 *i2cctl |= data_oe_bit; 2662 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2663 IXGBE_WRITE_FLUSH(hw); 2664 usec_delay(IXGBE_I2C_T_FALL); 2665 } 2666 2667 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2668 data = 1; 2669 else 2670 data = 0; 2671 2672 return data; 2673 } 2674 2675 /** 2676 * ixgbe_i2c_bus_clear - Clears the I2C bus 2677 * @hw: pointer to hardware structure 2678 * 2679 * Clears the I2C bus by sending nine clock pulses. 2680 * Used when data line is stuck low. 2681 **/ 2682 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2683 { 2684 u32 i2cctl; 2685 u32 i; 2686 2687 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2688 2689 ixgbe_i2c_start(hw); 2690 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2691 2692 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2693 2694 for (i = 0; i < 9; i++) { 2695 ixgbe_raise_i2c_clk(hw, &i2cctl); 2696 2697 /* Min high period of clock is 4us */ 2698 usec_delay(IXGBE_I2C_T_HIGH); 2699 2700 ixgbe_lower_i2c_clk(hw, &i2cctl); 2701 2702 /* Min low period of clock is 4.7us*/ 2703 usec_delay(IXGBE_I2C_T_LOW); 2704 } 2705 2706 ixgbe_i2c_start(hw); 2707 2708 /* Put the i2c bus back to default state */ 2709 ixgbe_i2c_stop(hw); 2710 } 2711 2712 /** 2713 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2714 * @hw: pointer to hardware structure 2715 * 2716 * Checks if the LASI temp alarm status was triggered due to overtemp 2717 **/ 2718 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2719 { 2720 s32 status = IXGBE_SUCCESS; 2721 u16 phy_data = 0; 2722 2723 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2724 2725 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2726 goto out; 2727 2728 /* Check that the LASI temp alarm status was triggered */ 2729 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2730 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2731 2732 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2733 goto out; 2734 2735 status = IXGBE_ERR_OVERTEMP; 2736 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2737 out: 2738 return status; 2739 } 2740 2741 /** 2742 * ixgbe_set_copper_phy_power - Control power for copper phy 2743 * @hw: pointer to hardware structure 2744 * @on: TRUE for on, FALSE for off 2745 */ 2746 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2747 { 2748 u32 status; 2749 u16 reg; 2750 2751 if (!on && ixgbe_mng_present(hw)) 2752 return 0; 2753 2754 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2755 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2756 ®); 2757 if (status) 2758 return status; 2759 2760 if (on) { 2761 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2762 } else { 2763 if (ixgbe_check_reset_blocked(hw)) 2764 return 0; 2765 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2766 } 2767 2768 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2769 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2770 reg); 2771 return status; 2772 } 2773
Indexes created Thu Sep 25 06:09:39 GMT 2025