ixgbe_phy.c revision 1.4
1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 238149 2012-07-05 20:51:44Z jfv $*/ 34 /*$NetBSD: ixgbe_phy.c,v 1.4 2015/04/02 09:26:55 msaitoh Exp $*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 50 static bool ixgbe_get_i2c_data(u32 *i2cctl); 51 52 /** 53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 54 * @hw: pointer to the hardware structure 55 * 56 * Initialize the function pointers. 57 **/ 58 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 63 64 /* PHY */ 65 phy->ops.identify = &ixgbe_identify_phy_generic; 66 phy->ops.reset = &ixgbe_reset_phy_generic; 67 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 68 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 69 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 70 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 71 phy->ops.check_link = NULL; 72 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 73 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 74 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 75 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 76 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 77 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 78 phy->ops.identify_sfp = &ixgbe_identify_module_generic; 79 phy->sfp_type = ixgbe_sfp_type_unknown; 80 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 81 return IXGBE_SUCCESS; 82 } 83 84 /** 85 * ixgbe_identify_phy_generic - Get physical layer module 86 * @hw: pointer to hardware structure 87 * 88 * Determines the physical layer module found on the current adapter. 89 **/ 90 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 91 { 92 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 93 u32 phy_addr; 94 u16 ext_ability = 0; 95 96 DEBUGFUNC("ixgbe_identify_phy_generic"); 97 98 if (hw->phy.type == ixgbe_phy_unknown) { 99 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 100 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 101 hw->phy.addr = phy_addr; 102 ixgbe_get_phy_id(hw); 103 hw->phy.type = 104 ixgbe_get_phy_type_from_id(hw->phy.id); 105 106 if (hw->phy.type == ixgbe_phy_unknown) { 107 hw->phy.ops.read_reg(hw, 108 IXGBE_MDIO_PHY_EXT_ABILITY, 109 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 110 &ext_ability); 111 if (ext_ability & 112 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 113 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 114 hw->phy.type = 115 ixgbe_phy_cu_unknown; 116 else 117 hw->phy.type = 118 ixgbe_phy_generic; 119 } 120 121 status = IXGBE_SUCCESS; 122 break; 123 } 124 } 125 /* clear value if nothing found */ 126 if (status != IXGBE_SUCCESS) 127 hw->phy.addr = 0; 128 } else { 129 status = IXGBE_SUCCESS; 130 } 131 132 return status; 133 } 134 135 /** 136 * ixgbe_validate_phy_addr - Determines phy address is valid 137 * @hw: pointer to hardware structure 138 * 139 **/ 140 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 141 { 142 u16 phy_id = 0; 143 bool valid = FALSE; 144 145 DEBUGFUNC("ixgbe_validate_phy_addr"); 146 147 hw->phy.addr = phy_addr; 148 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 149 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 150 151 if (phy_id != 0xFFFF && phy_id != 0x0) 152 valid = TRUE; 153 154 return valid; 155 } 156 157 /** 158 * ixgbe_get_phy_id - Get the phy type 159 * @hw: pointer to hardware structure 160 * 161 **/ 162 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 163 { 164 u32 status; 165 u16 phy_id_high = 0; 166 u16 phy_id_low = 0; 167 168 DEBUGFUNC("ixgbe_get_phy_id"); 169 170 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 171 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 172 &phy_id_high); 173 174 if (status == IXGBE_SUCCESS) { 175 hw->phy.id = (u32)(phy_id_high << 16); 176 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 177 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 178 &phy_id_low); 179 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 180 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 181 } 182 return status; 183 } 184 185 /** 186 * ixgbe_get_phy_type_from_id - Get the phy type 187 * @hw: pointer to hardware structure 188 * 189 **/ 190 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 191 { 192 enum ixgbe_phy_type phy_type; 193 194 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 195 196 switch (phy_id) { 197 case TN1010_PHY_ID: 198 phy_type = ixgbe_phy_tn; 199 break; 200 case X540_PHY_ID: 201 phy_type = ixgbe_phy_aq; 202 break; 203 case QT2022_PHY_ID: 204 phy_type = ixgbe_phy_qt; 205 break; 206 case ATH_PHY_ID: 207 phy_type = ixgbe_phy_nl; 208 break; 209 default: 210 phy_type = ixgbe_phy_unknown; 211 break; 212 } 213 214 DEBUGOUT1("phy type found is %d\n", phy_type); 215 return phy_type; 216 } 217 218 /** 219 * ixgbe_reset_phy_generic - Performs a PHY reset 220 * @hw: pointer to hardware structure 221 **/ 222 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 223 { 224 u32 i; 225 u16 ctrl = 0; 226 s32 status = IXGBE_SUCCESS; 227 228 DEBUGFUNC("ixgbe_reset_phy_generic"); 229 230 if (hw->phy.type == ixgbe_phy_unknown) 231 status = ixgbe_identify_phy_generic(hw); 232 233 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 234 goto out; 235 236 /* Don't reset PHY if it's shut down due to overtemp. */ 237 if (!hw->phy.reset_if_overtemp && 238 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 239 goto out; 240 241 /* 242 * Perform soft PHY reset to the PHY_XS. 243 * This will cause a soft reset to the PHY 244 */ 245 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 246 IXGBE_MDIO_PHY_XS_DEV_TYPE, 247 IXGBE_MDIO_PHY_XS_RESET); 248 249 /* 250 * Poll for reset bit to self-clear indicating reset is complete. 251 * Some PHYs could take up to 3 seconds to complete and need about 252 * 1.7 usec delay after the reset is complete. 253 */ 254 for (i = 0; i < 30; i++) { 255 msec_delay(100); 256 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 257 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 258 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 259 usec_delay(2); 260 break; 261 } 262 } 263 264 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 265 status = IXGBE_ERR_RESET_FAILED; 266 DEBUGOUT("PHY reset polling failed to complete.\n"); 267 } 268 269 out: 270 return status; 271 } 272 273 /** 274 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 275 * @hw: pointer to hardware structure 276 * @reg_addr: 32 bit address of PHY register to read 277 * @phy_data: Pointer to read data from PHY register 278 **/ 279 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 280 u32 device_type, u16 *phy_data) 281 { 282 u32 command; 283 u32 i; 284 u32 data; 285 s32 status = IXGBE_SUCCESS; 286 u16 gssr; 287 288 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 289 290 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 291 gssr = IXGBE_GSSR_PHY1_SM; 292 else 293 gssr = IXGBE_GSSR_PHY0_SM; 294 295 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 296 status = IXGBE_ERR_SWFW_SYNC; 297 298 if (status == IXGBE_SUCCESS) { 299 /* Setup and write the address cycle command */ 300 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 301 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 302 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 303 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 304 305 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 306 307 /* 308 * Check every 10 usec to see if the address cycle completed. 309 * The MDI Command bit will clear when the operation is 310 * complete 311 */ 312 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 313 usec_delay(10); 314 315 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 316 317 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 318 break; 319 } 320 321 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 322 DEBUGOUT("PHY address command did not complete.\n"); 323 status = IXGBE_ERR_PHY; 324 } 325 326 if (status == IXGBE_SUCCESS) { 327 /* 328 * Address cycle complete, setup and write the read 329 * command 330 */ 331 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 332 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 333 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 334 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 335 336 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 337 338 /* 339 * Check every 10 usec to see if the address cycle 340 * completed. The MDI Command bit will clear when the 341 * operation is complete 342 */ 343 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 344 usec_delay(10); 345 346 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 347 348 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 349 break; 350 } 351 352 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 353 DEBUGOUT("PHY read command didn't complete\n"); 354 status = IXGBE_ERR_PHY; 355 } else { 356 /* 357 * Read operation is complete. Get the data 358 * from MSRWD 359 */ 360 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 361 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 362 *phy_data = (u16)(data); 363 } 364 } 365 366 hw->mac.ops.release_swfw_sync(hw, gssr); 367 } 368 369 return status; 370 } 371 372 /** 373 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 374 * @hw: pointer to hardware structure 375 * @reg_addr: 32 bit PHY register to write 376 * @device_type: 5 bit device type 377 * @phy_data: Data to write to the PHY register 378 **/ 379 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 380 u32 device_type, u16 phy_data) 381 { 382 u32 command; 383 u32 i; 384 s32 status = IXGBE_SUCCESS; 385 u16 gssr; 386 387 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 388 389 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 390 gssr = IXGBE_GSSR_PHY1_SM; 391 else 392 gssr = IXGBE_GSSR_PHY0_SM; 393 394 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 395 status = IXGBE_ERR_SWFW_SYNC; 396 397 if (status == IXGBE_SUCCESS) { 398 /* Put the data in the MDI single read and write data register*/ 399 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 400 401 /* Setup and write the address cycle command */ 402 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 403 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 404 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 405 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 406 407 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 408 409 /* 410 * Check every 10 usec to see if the address cycle completed. 411 * The MDI Command bit will clear when the operation is 412 * complete 413 */ 414 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 415 usec_delay(10); 416 417 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 418 419 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 420 break; 421 } 422 423 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 424 DEBUGOUT("PHY address cmd didn't complete\n"); 425 status = IXGBE_ERR_PHY; 426 } 427 428 if (status == IXGBE_SUCCESS) { 429 /* 430 * Address cycle complete, setup and write the write 431 * command 432 */ 433 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 434 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 435 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 436 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 437 438 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 439 440 /* 441 * Check every 10 usec to see if the address cycle 442 * completed. The MDI Command bit will clear when the 443 * operation is complete 444 */ 445 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 446 usec_delay(10); 447 448 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 449 450 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 451 break; 452 } 453 454 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 455 DEBUGOUT("PHY address cmd didn't complete\n"); 456 status = IXGBE_ERR_PHY; 457 } 458 } 459 460 hw->mac.ops.release_swfw_sync(hw, gssr); 461 } 462 463 return status; 464 } 465 466 /** 467 * ixgbe_setup_phy_link_generic - Set and restart autoneg 468 * @hw: pointer to hardware structure 469 * 470 * Restart autonegotiation and PHY and waits for completion. 471 **/ 472 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 473 { 474 s32 status = IXGBE_SUCCESS; 475 u32 time_out; 476 u32 max_time_out = 10; 477 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 478 bool autoneg = FALSE; 479 ixgbe_link_speed speed; 480 481 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 482 483 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 484 485 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 486 /* Set or unset auto-negotiation 10G advertisement */ 487 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 488 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 489 &autoneg_reg); 490 491 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 492 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 493 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 494 495 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 496 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 497 autoneg_reg); 498 } 499 500 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 501 /* Set or unset auto-negotiation 1G advertisement */ 502 hw->phy.ops.read_reg(hw, 503 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 504 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 505 &autoneg_reg); 506 507 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 508 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 509 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 510 511 hw->phy.ops.write_reg(hw, 512 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 513 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 514 autoneg_reg); 515 } 516 517 if (speed & IXGBE_LINK_SPEED_100_FULL) { 518 /* Set or unset auto-negotiation 100M advertisement */ 519 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 520 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 521 &autoneg_reg); 522 523 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 524 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 525 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 526 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 527 528 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 529 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 530 autoneg_reg); 531 } 532 533 /* Restart PHY autonegotiation and wait for completion */ 534 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 535 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 536 537 autoneg_reg |= IXGBE_MII_RESTART; 538 539 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 540 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 541 542 /* Wait for autonegotiation to finish */ 543 for (time_out = 0; time_out < max_time_out; time_out++) { 544 usec_delay(10); 545 /* Restart PHY autonegotiation and wait for completion */ 546 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 547 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 548 &autoneg_reg); 549 550 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 551 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 552 break; 553 } 554 555 if (time_out == max_time_out) { 556 status = IXGBE_ERR_LINK_SETUP; 557 DEBUGOUT("ixgbe_setup_phy_link_generic: time out"); 558 } 559 560 return status; 561 } 562 563 /** 564 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 565 * @hw: pointer to hardware structure 566 * @speed: new link speed 567 * @autoneg: TRUE if autonegotiation enabled 568 **/ 569 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 570 ixgbe_link_speed speed, 571 bool autoneg, 572 bool autoneg_wait_to_complete) 573 { 574 UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete); 575 576 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 577 578 /* 579 * Clear autoneg_advertised and set new values based on input link 580 * speed. 581 */ 582 hw->phy.autoneg_advertised = 0; 583 584 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 585 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 586 587 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 588 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 589 590 if (speed & IXGBE_LINK_SPEED_100_FULL) 591 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 592 593 /* Setup link based on the new speed settings */ 594 hw->phy.ops.setup_link(hw); 595 596 return IXGBE_SUCCESS; 597 } 598 599 /** 600 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 601 * @hw: pointer to hardware structure 602 * @speed: pointer to link speed 603 * @autoneg: boolean auto-negotiation value 604 * 605 * Determines the link capabilities by reading the AUTOC register. 606 **/ 607 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 608 ixgbe_link_speed *speed, 609 bool *autoneg) 610 { 611 s32 status = IXGBE_ERR_LINK_SETUP; 612 u16 speed_ability; 613 614 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 615 616 *speed = 0; 617 *autoneg = TRUE; 618 619 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 620 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 621 &speed_ability); 622 623 if (status == IXGBE_SUCCESS) { 624 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 625 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 626 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 627 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 628 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 629 *speed |= IXGBE_LINK_SPEED_100_FULL; 630 } 631 632 return status; 633 } 634 635 /** 636 * ixgbe_check_phy_link_tnx - Determine link and speed status 637 * @hw: pointer to hardware structure 638 * 639 * Reads the VS1 register to determine if link is up and the current speed for 640 * the PHY. 641 **/ 642 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 643 bool *link_up) 644 { 645 s32 status = IXGBE_SUCCESS; 646 u32 time_out; 647 u32 max_time_out = 10; 648 u16 phy_link = 0; 649 u16 phy_speed = 0; 650 u16 phy_data = 0; 651 652 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 653 654 /* Initialize speed and link to default case */ 655 *link_up = FALSE; 656 *speed = IXGBE_LINK_SPEED_10GB_FULL; 657 658 /* 659 * Check current speed and link status of the PHY register. 660 * This is a vendor specific register and may have to 661 * be changed for other copper PHYs. 662 */ 663 for (time_out = 0; time_out < max_time_out; time_out++) { 664 usec_delay(10); 665 status = hw->phy.ops.read_reg(hw, 666 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 667 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 668 &phy_data); 669 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 670 phy_speed = phy_data & 671 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 672 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 673 *link_up = TRUE; 674 if (phy_speed == 675 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 676 *speed = IXGBE_LINK_SPEED_1GB_FULL; 677 break; 678 } 679 } 680 681 return status; 682 } 683 684 /** 685 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 686 * @hw: pointer to hardware structure 687 * 688 * Restart autonegotiation and PHY and waits for completion. 689 **/ 690 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 691 { 692 s32 status = IXGBE_SUCCESS; 693 u32 time_out; 694 u32 max_time_out = 10; 695 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 696 bool autoneg = FALSE; 697 ixgbe_link_speed speed; 698 699 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 700 701 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 702 703 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 704 /* Set or unset auto-negotiation 10G advertisement */ 705 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 706 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 707 &autoneg_reg); 708 709 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 710 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 711 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 712 713 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 714 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 715 autoneg_reg); 716 } 717 718 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 719 /* Set or unset auto-negotiation 1G advertisement */ 720 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 721 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 722 &autoneg_reg); 723 724 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 725 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 726 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 727 728 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 729 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 730 autoneg_reg); 731 } 732 733 if (speed & IXGBE_LINK_SPEED_100_FULL) { 734 /* Set or unset auto-negotiation 100M advertisement */ 735 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 736 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 737 &autoneg_reg); 738 739 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 740 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 741 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 742 743 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 744 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 745 autoneg_reg); 746 } 747 748 /* Restart PHY autonegotiation and wait for completion */ 749 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 750 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 751 752 autoneg_reg |= IXGBE_MII_RESTART; 753 754 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 756 757 /* Wait for autonegotiation to finish */ 758 for (time_out = 0; time_out < max_time_out; time_out++) { 759 usec_delay(10); 760 /* Restart PHY autonegotiation and wait for completion */ 761 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 762 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 763 &autoneg_reg); 764 765 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 766 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 767 break; 768 } 769 770 if (time_out == max_time_out) { 771 status = IXGBE_ERR_LINK_SETUP; 772 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 773 } 774 775 return status; 776 } 777 778 /** 779 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 780 * @hw: pointer to hardware structure 781 * @firmware_version: pointer to the PHY Firmware Version 782 **/ 783 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 784 u16 *firmware_version) 785 { 786 s32 status = IXGBE_SUCCESS; 787 788 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 789 790 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 791 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 792 firmware_version); 793 794 return status; 795 } 796 797 /** 798 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 799 * @hw: pointer to hardware structure 800 * @firmware_version: pointer to the PHY Firmware Version 801 **/ 802 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 803 u16 *firmware_version) 804 { 805 s32 status = IXGBE_SUCCESS; 806 807 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 808 809 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 810 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 811 firmware_version); 812 813 return status; 814 } 815 816 /** 817 * ixgbe_reset_phy_nl - Performs a PHY reset 818 * @hw: pointer to hardware structure 819 **/ 820 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 821 { 822 u16 phy_offset, control, eword, edata, block_crc; 823 bool end_data = FALSE; 824 u16 list_offset, data_offset; 825 u16 phy_data = 0; 826 s32 ret_val = IXGBE_SUCCESS; 827 u32 i; 828 829 DEBUGFUNC("ixgbe_reset_phy_nl"); 830 831 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 832 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 833 834 /* reset the PHY and poll for completion */ 835 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 836 IXGBE_MDIO_PHY_XS_DEV_TYPE, 837 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 838 839 for (i = 0; i < 100; i++) { 840 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 841 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 842 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 843 break; 844 msec_delay(10); 845 } 846 847 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 848 DEBUGOUT("PHY reset did not complete.\n"); 849 ret_val = IXGBE_ERR_PHY; 850 goto out; 851 } 852 853 /* Get init offsets */ 854 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 855 &data_offset); 856 if (ret_val != IXGBE_SUCCESS) 857 goto out; 858 859 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 860 data_offset++; 861 while (!end_data) { 862 /* 863 * Read control word from PHY init contents offset 864 */ 865 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 866 control = (eword & IXGBE_CONTROL_MASK_NL) >> 867 IXGBE_CONTROL_SHIFT_NL; 868 edata = eword & IXGBE_DATA_MASK_NL; 869 switch (control) { 870 case IXGBE_DELAY_NL: 871 data_offset++; 872 DEBUGOUT1("DELAY: %d MS\n", edata); 873 msec_delay(edata); 874 break; 875 case IXGBE_DATA_NL: 876 DEBUGOUT("DATA:\n"); 877 data_offset++; 878 hw->eeprom.ops.read(hw, data_offset++, 879 &phy_offset); 880 for (i = 0; i < edata; i++) { 881 hw->eeprom.ops.read(hw, data_offset, &eword); 882 hw->phy.ops.write_reg(hw, phy_offset, 883 IXGBE_TWINAX_DEV, eword); 884 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 885 phy_offset); 886 data_offset++; 887 phy_offset++; 888 } 889 break; 890 case IXGBE_CONTROL_NL: 891 data_offset++; 892 DEBUGOUT("CONTROL:\n"); 893 if (edata == IXGBE_CONTROL_EOL_NL) { 894 DEBUGOUT("EOL\n"); 895 end_data = TRUE; 896 } else if (edata == IXGBE_CONTROL_SOL_NL) { 897 DEBUGOUT("SOL\n"); 898 } else { 899 DEBUGOUT("Bad control value\n"); 900 ret_val = IXGBE_ERR_PHY; 901 goto out; 902 } 903 break; 904 default: 905 DEBUGOUT("Bad control type\n"); 906 ret_val = IXGBE_ERR_PHY; 907 goto out; 908 } 909 } 910 911 out: 912 return ret_val; 913 } 914 915 /** 916 * ixgbe_identify_module_generic - Identifies module type 917 * @hw: pointer to hardware structure 918 * 919 * Determines HW type and calls appropriate function. 920 **/ 921 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 922 { 923 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 924 925 DEBUGFUNC("ixgbe_identify_module_generic"); 926 927 switch (hw->mac.ops.get_media_type(hw)) { 928 case ixgbe_media_type_fiber: 929 status = ixgbe_identify_sfp_module_generic(hw); 930 break; 931 932 933 default: 934 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 935 status = IXGBE_ERR_SFP_NOT_PRESENT; 936 break; 937 } 938 939 return status; 940 } 941 942 /** 943 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 944 * @hw: pointer to hardware structure 945 * 946 * Searches for and identifies the SFP module and assigns appropriate PHY type. 947 **/ 948 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 949 { 950 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 951 u32 vendor_oui = 0; 952 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 953 u8 identifier = 0; 954 u8 comp_codes_1g = 0; 955 u8 comp_codes_10g = 0; 956 u8 oui_bytes[3] = {0, 0, 0}; 957 u8 cable_tech = 0; 958 u8 cable_spec = 0; 959 u16 enforce_sfp = 0; 960 961 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 962 963 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 964 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 965 status = IXGBE_ERR_SFP_NOT_PRESENT; 966 goto out; 967 } 968 969 status = hw->phy.ops.read_i2c_eeprom(hw, 970 IXGBE_SFF_IDENTIFIER, 971 &identifier); 972 973 if (status == IXGBE_ERR_SWFW_SYNC || 974 status == IXGBE_ERR_I2C || 975 status == IXGBE_ERR_SFP_NOT_PRESENT) 976 goto err_read_i2c_eeprom; 977 978 /* LAN ID is needed for sfp_type determination */ 979 hw->mac.ops.set_lan_id(hw); 980 981 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 982 hw->phy.type = ixgbe_phy_sfp_unsupported; 983 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 984 } else { 985 status = hw->phy.ops.read_i2c_eeprom(hw, 986 IXGBE_SFF_1GBE_COMP_CODES, 987 &comp_codes_1g); 988 989 if (status == IXGBE_ERR_SWFW_SYNC || 990 status == IXGBE_ERR_I2C || 991 status == IXGBE_ERR_SFP_NOT_PRESENT) 992 goto err_read_i2c_eeprom; 993 994 status = hw->phy.ops.read_i2c_eeprom(hw, 995 IXGBE_SFF_10GBE_COMP_CODES, 996 &comp_codes_10g); 997 998 if (status == IXGBE_ERR_SWFW_SYNC || 999 status == IXGBE_ERR_I2C || 1000 status == IXGBE_ERR_SFP_NOT_PRESENT) 1001 goto err_read_i2c_eeprom; 1002 status = hw->phy.ops.read_i2c_eeprom(hw, 1003 IXGBE_SFF_CABLE_TECHNOLOGY, 1004 &cable_tech); 1005 1006 if (status == IXGBE_ERR_SWFW_SYNC || 1007 status == IXGBE_ERR_I2C || 1008 status == IXGBE_ERR_SFP_NOT_PRESENT) 1009 goto err_read_i2c_eeprom; 1010 1011 /* ID Module 1012 * ========= 1013 * 0 SFP_DA_CU 1014 * 1 SFP_SR 1015 * 2 SFP_LR 1016 * 3 SFP_DA_CORE0 - 82599-specific 1017 * 4 SFP_DA_CORE1 - 82599-specific 1018 * 5 SFP_SR/LR_CORE0 - 82599-specific 1019 * 6 SFP_SR/LR_CORE1 - 82599-specific 1020 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1021 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1022 * 9 SFP_1g_cu_CORE0 - 82599-specific 1023 * 10 SFP_1g_cu_CORE1 - 82599-specific 1024 * 11 SFP_1g_sx_CORE0 - 82599-specific 1025 * 12 SFP_1g_sx_CORE1 - 82599-specific 1026 */ 1027 if (hw->mac.type == ixgbe_mac_82598EB) { 1028 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1029 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1030 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1031 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1032 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1033 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1034 else 1035 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1036 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1037 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1038 if (hw->bus.lan_id == 0) 1039 hw->phy.sfp_type = 1040 ixgbe_sfp_type_da_cu_core0; 1041 else 1042 hw->phy.sfp_type = 1043 ixgbe_sfp_type_da_cu_core1; 1044 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1045 hw->phy.ops.read_i2c_eeprom( 1046 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1047 &cable_spec); 1048 if (cable_spec & 1049 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1050 if (hw->bus.lan_id == 0) 1051 hw->phy.sfp_type = 1052 ixgbe_sfp_type_da_act_lmt_core0; 1053 else 1054 hw->phy.sfp_type = 1055 ixgbe_sfp_type_da_act_lmt_core1; 1056 } else { 1057 hw->phy.sfp_type = 1058 ixgbe_sfp_type_unknown; 1059 } 1060 } else if (comp_codes_10g & 1061 (IXGBE_SFF_10GBASESR_CAPABLE | 1062 IXGBE_SFF_10GBASELR_CAPABLE)) { 1063 if (hw->bus.lan_id == 0) 1064 hw->phy.sfp_type = 1065 ixgbe_sfp_type_srlr_core0; 1066 else 1067 hw->phy.sfp_type = 1068 ixgbe_sfp_type_srlr_core1; 1069 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1070 if (hw->bus.lan_id == 0) 1071 hw->phy.sfp_type = 1072 ixgbe_sfp_type_1g_cu_core0; 1073 else 1074 hw->phy.sfp_type = 1075 ixgbe_sfp_type_1g_cu_core1; 1076 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1077 if (hw->bus.lan_id == 0) 1078 hw->phy.sfp_type = 1079 ixgbe_sfp_type_1g_sx_core0; 1080 else 1081 hw->phy.sfp_type = 1082 ixgbe_sfp_type_1g_sx_core1; 1083 } else { 1084 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1085 } 1086 } 1087 1088 if (hw->phy.sfp_type != stored_sfp_type) 1089 hw->phy.sfp_setup_needed = TRUE; 1090 1091 /* Determine if the SFP+ PHY is dual speed or not. */ 1092 hw->phy.multispeed_fiber = FALSE; 1093 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1094 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1095 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1096 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1097 hw->phy.multispeed_fiber = TRUE; 1098 1099 /* Determine PHY vendor */ 1100 if (hw->phy.type != ixgbe_phy_nl) { 1101 hw->phy.id = identifier; 1102 status = hw->phy.ops.read_i2c_eeprom(hw, 1103 IXGBE_SFF_VENDOR_OUI_BYTE0, 1104 &oui_bytes[0]); 1105 1106 if (status == IXGBE_ERR_SWFW_SYNC || 1107 status == IXGBE_ERR_I2C || 1108 status == IXGBE_ERR_SFP_NOT_PRESENT) 1109 goto err_read_i2c_eeprom; 1110 1111 status = hw->phy.ops.read_i2c_eeprom(hw, 1112 IXGBE_SFF_VENDOR_OUI_BYTE1, 1113 &oui_bytes[1]); 1114 1115 if (status == IXGBE_ERR_SWFW_SYNC || 1116 status == IXGBE_ERR_I2C || 1117 status == IXGBE_ERR_SFP_NOT_PRESENT) 1118 goto err_read_i2c_eeprom; 1119 1120 status = hw->phy.ops.read_i2c_eeprom(hw, 1121 IXGBE_SFF_VENDOR_OUI_BYTE2, 1122 &oui_bytes[2]); 1123 1124 if (status == IXGBE_ERR_SWFW_SYNC || 1125 status == IXGBE_ERR_I2C || 1126 status == IXGBE_ERR_SFP_NOT_PRESENT) 1127 goto err_read_i2c_eeprom; 1128 1129 vendor_oui = 1130 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1131 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1132 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1133 1134 switch (vendor_oui) { 1135 case IXGBE_SFF_VENDOR_OUI_TYCO: 1136 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1137 hw->phy.type = 1138 ixgbe_phy_sfp_passive_tyco; 1139 break; 1140 case IXGBE_SFF_VENDOR_OUI_FTL: 1141 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1142 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1143 else 1144 hw->phy.type = ixgbe_phy_sfp_ftl; 1145 break; 1146 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1147 hw->phy.type = ixgbe_phy_sfp_avago; 1148 break; 1149 case IXGBE_SFF_VENDOR_OUI_INTEL: 1150 hw->phy.type = ixgbe_phy_sfp_intel; 1151 break; 1152 default: 1153 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1154 hw->phy.type = 1155 ixgbe_phy_sfp_passive_unknown; 1156 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1157 hw->phy.type = 1158 ixgbe_phy_sfp_active_unknown; 1159 else 1160 hw->phy.type = ixgbe_phy_sfp_unknown; 1161 break; 1162 } 1163 } 1164 1165 /* Allow any DA cable vendor */ 1166 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1167 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1168 status = IXGBE_SUCCESS; 1169 goto out; 1170 } 1171 1172 /* Verify supported 1G SFP modules */ 1173 if (comp_codes_10g == 0 && 1174 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1175 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1176 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1177 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1178 hw->phy.type = ixgbe_phy_sfp_unsupported; 1179 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1180 goto out; 1181 } 1182 1183 /* Anything else 82598-based is supported */ 1184 if (hw->mac.type == ixgbe_mac_82598EB) { 1185 status = IXGBE_SUCCESS; 1186 goto out; 1187 } 1188 1189 ixgbe_get_device_caps(hw, &enforce_sfp); 1190 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1191 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || 1192 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) || 1193 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) || 1194 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) { 1195 /* Make sure we're a supported PHY type */ 1196 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1197 status = IXGBE_SUCCESS; 1198 } else { 1199 if (hw->allow_unsupported_sfp == TRUE) { 1200 EWARN(hw, "WARNING: Intel (R) Network " 1201 "Connections are quality tested " 1202 "using Intel (R) Ethernet Optics." 1203 " Using untested modules is not " 1204 "supported and may cause unstable" 1205 " operation or damage to the " 1206 "module or the adapter. Intel " 1207 "Corporation is not responsible " 1208 "for any harm caused by using " 1209 "untested modules.\n", status); 1210 status = IXGBE_SUCCESS; 1211 } else { 1212 DEBUGOUT("SFP+ module not supported\n"); 1213 hw->phy.type = 1214 ixgbe_phy_sfp_unsupported; 1215 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1216 } 1217 } 1218 } else { 1219 status = IXGBE_SUCCESS; 1220 } 1221 } 1222 1223 out: 1224 return status; 1225 1226 err_read_i2c_eeprom: 1227 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1228 if (hw->phy.type != ixgbe_phy_nl) { 1229 hw->phy.id = 0; 1230 hw->phy.type = ixgbe_phy_unknown; 1231 } 1232 return IXGBE_ERR_SFP_NOT_PRESENT; 1233 } 1234 1235 1236 1237 /** 1238 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1239 * @hw: pointer to hardware structure 1240 * @list_offset: offset to the SFP ID list 1241 * @data_offset: offset to the SFP data block 1242 * 1243 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1244 * so it returns the offsets to the phy init sequence block. 1245 **/ 1246 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1247 u16 *list_offset, 1248 u16 *data_offset) 1249 { 1250 u16 sfp_id; 1251 u16 sfp_type = hw->phy.sfp_type; 1252 1253 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1254 1255 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1256 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1257 1258 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1259 return IXGBE_ERR_SFP_NOT_PRESENT; 1260 1261 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1262 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1263 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1264 1265 /* 1266 * Limiting active cables and 1G Phys must be initialized as 1267 * SR modules 1268 */ 1269 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1270 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1271 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1272 sfp_type = ixgbe_sfp_type_srlr_core0; 1273 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1274 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1275 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1276 sfp_type = ixgbe_sfp_type_srlr_core1; 1277 1278 /* Read offset to PHY init contents */ 1279 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1280 1281 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1282 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1283 1284 /* Shift offset to first ID word */ 1285 (*list_offset)++; 1286 1287 /* 1288 * Find the matching SFP ID in the EEPROM 1289 * and program the init sequence 1290 */ 1291 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1292 1293 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1294 if (sfp_id == sfp_type) { 1295 (*list_offset)++; 1296 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1297 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1298 DEBUGOUT("SFP+ module not supported\n"); 1299 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1300 } else { 1301 break; 1302 } 1303 } else { 1304 (*list_offset) += 2; 1305 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1306 return IXGBE_ERR_PHY; 1307 } 1308 } 1309 1310 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1311 DEBUGOUT("No matching SFP+ module found\n"); 1312 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1313 } 1314 1315 return IXGBE_SUCCESS; 1316 } 1317 1318 /** 1319 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1320 * @hw: pointer to hardware structure 1321 * @byte_offset: EEPROM byte offset to read 1322 * @eeprom_data: value read 1323 * 1324 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1325 **/ 1326 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1327 u8 *eeprom_data) 1328 { 1329 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1330 1331 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1332 IXGBE_I2C_EEPROM_DEV_ADDR, 1333 eeprom_data); 1334 } 1335 1336 /** 1337 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1338 * @hw: pointer to hardware structure 1339 * @byte_offset: EEPROM byte offset to write 1340 * @eeprom_data: value to write 1341 * 1342 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1343 **/ 1344 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1345 u8 eeprom_data) 1346 { 1347 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1348 1349 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1350 IXGBE_I2C_EEPROM_DEV_ADDR, 1351 eeprom_data); 1352 } 1353 1354 /** 1355 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1356 * @hw: pointer to hardware structure 1357 * @byte_offset: byte offset to read 1358 * @data: value read 1359 * 1360 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1361 * a specified device address. 1362 **/ 1363 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1364 u8 dev_addr, u8 *data) 1365 { 1366 s32 status = IXGBE_SUCCESS; 1367 u32 max_retry = 10; 1368 u32 retry = 0; 1369 u16 swfw_mask = 0; 1370 bool nack = 1; 1371 *data = 0; 1372 1373 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1374 1375 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1376 swfw_mask = IXGBE_GSSR_PHY1_SM; 1377 else 1378 swfw_mask = IXGBE_GSSR_PHY0_SM; 1379 1380 do { 1381 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 1382 != IXGBE_SUCCESS) { 1383 status = IXGBE_ERR_SWFW_SYNC; 1384 goto read_byte_out; 1385 } 1386 1387 ixgbe_i2c_start(hw); 1388 1389 /* Device Address and write indication */ 1390 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1391 if (status != IXGBE_SUCCESS) 1392 goto fail; 1393 1394 status = ixgbe_get_i2c_ack(hw); 1395 if (status != IXGBE_SUCCESS) 1396 goto fail; 1397 1398 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1399 if (status != IXGBE_SUCCESS) 1400 goto fail; 1401 1402 status = ixgbe_get_i2c_ack(hw); 1403 if (status != IXGBE_SUCCESS) 1404 goto fail; 1405 1406 ixgbe_i2c_start(hw); 1407 1408 /* Device Address and read indication */ 1409 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1410 if (status != IXGBE_SUCCESS) 1411 goto fail; 1412 1413 status = ixgbe_get_i2c_ack(hw); 1414 if (status != IXGBE_SUCCESS) 1415 goto fail; 1416 1417 status = ixgbe_clock_in_i2c_byte(hw, data); 1418 if (status != IXGBE_SUCCESS) 1419 goto fail; 1420 1421 status = ixgbe_clock_out_i2c_bit(hw, nack); 1422 if (status != IXGBE_SUCCESS) 1423 goto fail; 1424 1425 ixgbe_i2c_stop(hw); 1426 break; 1427 1428 fail: 1429 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1430 msec_delay(100); 1431 ixgbe_i2c_bus_clear(hw); 1432 retry++; 1433 if (retry < max_retry) 1434 DEBUGOUT("I2C byte read error - Retrying.\n"); 1435 else 1436 DEBUGOUT("I2C byte read error.\n"); 1437 1438 } while (retry < max_retry); 1439 1440 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1441 1442 read_byte_out: 1443 return status; 1444 } 1445 1446 /** 1447 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1448 * @hw: pointer to hardware structure 1449 * @byte_offset: byte offset to write 1450 * @data: value to write 1451 * 1452 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1453 * a specified device address. 1454 **/ 1455 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1456 u8 dev_addr, u8 data) 1457 { 1458 s32 status = IXGBE_SUCCESS; 1459 u32 max_retry = 2; 1460 u32 retry = 0; 1461 u16 swfw_mask = 0; 1462 1463 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1464 1465 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1466 swfw_mask = IXGBE_GSSR_PHY1_SM; 1467 else 1468 swfw_mask = IXGBE_GSSR_PHY0_SM; 1469 1470 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1471 status = IXGBE_ERR_SWFW_SYNC; 1472 goto write_byte_out; 1473 } 1474 1475 do { 1476 ixgbe_i2c_start(hw); 1477 1478 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1479 if (status != IXGBE_SUCCESS) 1480 goto fail; 1481 1482 status = ixgbe_get_i2c_ack(hw); 1483 if (status != IXGBE_SUCCESS) 1484 goto fail; 1485 1486 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1487 if (status != IXGBE_SUCCESS) 1488 goto fail; 1489 1490 status = ixgbe_get_i2c_ack(hw); 1491 if (status != IXGBE_SUCCESS) 1492 goto fail; 1493 1494 status = ixgbe_clock_out_i2c_byte(hw, data); 1495 if (status != IXGBE_SUCCESS) 1496 goto fail; 1497 1498 status = ixgbe_get_i2c_ack(hw); 1499 if (status != IXGBE_SUCCESS) 1500 goto fail; 1501 1502 ixgbe_i2c_stop(hw); 1503 break; 1504 1505 fail: 1506 ixgbe_i2c_bus_clear(hw); 1507 retry++; 1508 if (retry < max_retry) 1509 DEBUGOUT("I2C byte write error - Retrying.\n"); 1510 else 1511 DEBUGOUT("I2C byte write error.\n"); 1512 } while (retry < max_retry); 1513 1514 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1515 1516 write_byte_out: 1517 return status; 1518 } 1519 1520 /** 1521 * ixgbe_i2c_start - Sets I2C start condition 1522 * @hw: pointer to hardware structure 1523 * 1524 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1525 **/ 1526 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1527 { 1528 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1529 1530 DEBUGFUNC("ixgbe_i2c_start"); 1531 1532 /* Start condition must begin with data and clock high */ 1533 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1534 ixgbe_raise_i2c_clk(hw, &i2cctl); 1535 1536 /* Setup time for start condition (4.7us) */ 1537 usec_delay(IXGBE_I2C_T_SU_STA); 1538 1539 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1540 1541 /* Hold time for start condition (4us) */ 1542 usec_delay(IXGBE_I2C_T_HD_STA); 1543 1544 ixgbe_lower_i2c_clk(hw, &i2cctl); 1545 1546 /* Minimum low period of clock is 4.7 us */ 1547 usec_delay(IXGBE_I2C_T_LOW); 1548 1549 } 1550 1551 /** 1552 * ixgbe_i2c_stop - Sets I2C stop condition 1553 * @hw: pointer to hardware structure 1554 * 1555 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1556 **/ 1557 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1558 { 1559 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1560 1561 DEBUGFUNC("ixgbe_i2c_stop"); 1562 1563 /* Stop condition must begin with data low and clock high */ 1564 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1565 ixgbe_raise_i2c_clk(hw, &i2cctl); 1566 1567 /* Setup time for stop condition (4us) */ 1568 usec_delay(IXGBE_I2C_T_SU_STO); 1569 1570 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1571 1572 /* bus free time between stop and start (4.7us)*/ 1573 usec_delay(IXGBE_I2C_T_BUF); 1574 } 1575 1576 /** 1577 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1578 * @hw: pointer to hardware structure 1579 * @data: data byte to clock in 1580 * 1581 * Clocks in one byte data via I2C data/clock 1582 **/ 1583 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1584 { 1585 s32 i; 1586 bool bit = 0; 1587 1588 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1589 1590 for (i = 7; i >= 0; i--) { 1591 ixgbe_clock_in_i2c_bit(hw, &bit); 1592 *data |= bit << i; 1593 } 1594 1595 return IXGBE_SUCCESS; 1596 } 1597 1598 /** 1599 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1600 * @hw: pointer to hardware structure 1601 * @data: data byte clocked out 1602 * 1603 * Clocks out one byte data via I2C data/clock 1604 **/ 1605 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1606 { 1607 s32 status = IXGBE_SUCCESS; 1608 s32 i; 1609 u32 i2cctl; 1610 bool bit = 0; 1611 1612 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1613 1614 for (i = 7; i >= 0; i--) { 1615 bit = (data >> i) & 0x1; 1616 status = ixgbe_clock_out_i2c_bit(hw, bit); 1617 1618 if (status != IXGBE_SUCCESS) 1619 break; 1620 } 1621 1622 /* Release SDA line (set high) */ 1623 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1624 i2cctl |= IXGBE_I2C_DATA_OUT; 1625 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1626 IXGBE_WRITE_FLUSH(hw); 1627 1628 return status; 1629 } 1630 1631 /** 1632 * ixgbe_get_i2c_ack - Polls for I2C ACK 1633 * @hw: pointer to hardware structure 1634 * 1635 * Clocks in/out one bit via I2C data/clock 1636 **/ 1637 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1638 { 1639 s32 status = IXGBE_SUCCESS; 1640 u32 i = 0; 1641 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1642 u32 timeout = 10; 1643 bool ack = 1; 1644 1645 DEBUGFUNC("ixgbe_get_i2c_ack"); 1646 1647 ixgbe_raise_i2c_clk(hw, &i2cctl); 1648 1649 1650 /* Minimum high period of clock is 4us */ 1651 usec_delay(IXGBE_I2C_T_HIGH); 1652 1653 /* Poll for ACK. Note that ACK in I2C spec is 1654 * transition from 1 to 0 */ 1655 for (i = 0; i < timeout; i++) { 1656 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1657 ack = ixgbe_get_i2c_data(&i2cctl); 1658 1659 usec_delay(1); 1660 if (ack == 0) 1661 break; 1662 } 1663 1664 if (ack == 1) { 1665 DEBUGOUT("I2C ack was not received.\n"); 1666 status = IXGBE_ERR_I2C; 1667 } 1668 1669 ixgbe_lower_i2c_clk(hw, &i2cctl); 1670 1671 /* Minimum low period of clock is 4.7 us */ 1672 usec_delay(IXGBE_I2C_T_LOW); 1673 1674 return status; 1675 } 1676 1677 /** 1678 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1679 * @hw: pointer to hardware structure 1680 * @data: read data value 1681 * 1682 * Clocks in one bit via I2C data/clock 1683 **/ 1684 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1685 { 1686 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1687 1688 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1689 1690 ixgbe_raise_i2c_clk(hw, &i2cctl); 1691 1692 /* Minimum high period of clock is 4us */ 1693 usec_delay(IXGBE_I2C_T_HIGH); 1694 1695 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1696 *data = ixgbe_get_i2c_data(&i2cctl); 1697 1698 ixgbe_lower_i2c_clk(hw, &i2cctl); 1699 1700 /* Minimum low period of clock is 4.7 us */ 1701 usec_delay(IXGBE_I2C_T_LOW); 1702 1703 return IXGBE_SUCCESS; 1704 } 1705 1706 /** 1707 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1708 * @hw: pointer to hardware structure 1709 * @data: data value to write 1710 * 1711 * Clocks out one bit via I2C data/clock 1712 **/ 1713 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1714 { 1715 s32 status; 1716 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1717 1718 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1719 1720 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1721 if (status == IXGBE_SUCCESS) { 1722 ixgbe_raise_i2c_clk(hw, &i2cctl); 1723 1724 /* Minimum high period of clock is 4us */ 1725 usec_delay(IXGBE_I2C_T_HIGH); 1726 1727 ixgbe_lower_i2c_clk(hw, &i2cctl); 1728 1729 /* Minimum low period of clock is 4.7 us. 1730 * This also takes care of the data hold time. 1731 */ 1732 usec_delay(IXGBE_I2C_T_LOW); 1733 } else { 1734 status = IXGBE_ERR_I2C; 1735 DEBUGOUT1("I2C data was not set to %X\n", data); 1736 } 1737 1738 return status; 1739 } 1740 /** 1741 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1742 * @hw: pointer to hardware structure 1743 * @i2cctl: Current value of I2CCTL register 1744 * 1745 * Raises the I2C clock line '0'->'1' 1746 **/ 1747 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1748 { 1749 u32 i = 0; 1750 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 1751 u32 i2cctl_r = 0; 1752 1753 DEBUGFUNC("ixgbe_raise_i2c_clk"); 1754 1755 for (i = 0; i < timeout; i++) { 1756 *i2cctl |= IXGBE_I2C_CLK_OUT; 1757 1758 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1759 IXGBE_WRITE_FLUSH(hw); 1760 /* SCL rise time (1000ns) */ 1761 usec_delay(IXGBE_I2C_T_RISE); 1762 1763 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1764 if (i2cctl_r & IXGBE_I2C_CLK_IN) 1765 break; 1766 } 1767 } 1768 1769 /** 1770 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1771 * @hw: pointer to hardware structure 1772 * @i2cctl: Current value of I2CCTL register 1773 * 1774 * Lowers the I2C clock line '1'->'0' 1775 **/ 1776 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1777 { 1778 1779 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1780 1781 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1782 1783 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1784 IXGBE_WRITE_FLUSH(hw); 1785 1786 /* SCL fall time (300ns) */ 1787 usec_delay(IXGBE_I2C_T_FALL); 1788 } 1789 1790 /** 1791 * ixgbe_set_i2c_data - Sets the I2C data bit 1792 * @hw: pointer to hardware structure 1793 * @i2cctl: Current value of I2CCTL register 1794 * @data: I2C data value (0 or 1) to set 1795 * 1796 * Sets the I2C data bit 1797 **/ 1798 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1799 { 1800 s32 status = IXGBE_SUCCESS; 1801 1802 DEBUGFUNC("ixgbe_set_i2c_data"); 1803 1804 if (data) 1805 *i2cctl |= IXGBE_I2C_DATA_OUT; 1806 else 1807 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1808 1809 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1810 IXGBE_WRITE_FLUSH(hw); 1811 1812 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1813 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1814 1815 /* Verify data was set correctly */ 1816 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1817 if (data != ixgbe_get_i2c_data(i2cctl)) { 1818 status = IXGBE_ERR_I2C; 1819 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1820 } 1821 1822 return status; 1823 } 1824 1825 /** 1826 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1827 * @hw: pointer to hardware structure 1828 * @i2cctl: Current value of I2CCTL register 1829 * 1830 * Returns the I2C data bit value 1831 **/ 1832 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1833 { 1834 bool data; 1835 1836 DEBUGFUNC("ixgbe_get_i2c_data"); 1837 1838 if (*i2cctl & IXGBE_I2C_DATA_IN) 1839 data = 1; 1840 else 1841 data = 0; 1842 1843 return data; 1844 } 1845 1846 /** 1847 * ixgbe_i2c_bus_clear - Clears the I2C bus 1848 * @hw: pointer to hardware structure 1849 * 1850 * Clears the I2C bus by sending nine clock pulses. 1851 * Used when data line is stuck low. 1852 **/ 1853 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1854 { 1855 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1856 u32 i; 1857 1858 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1859 1860 ixgbe_i2c_start(hw); 1861 1862 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1863 1864 for (i = 0; i < 9; i++) { 1865 ixgbe_raise_i2c_clk(hw, &i2cctl); 1866 1867 /* Min high period of clock is 4us */ 1868 usec_delay(IXGBE_I2C_T_HIGH); 1869 1870 ixgbe_lower_i2c_clk(hw, &i2cctl); 1871 1872 /* Min low period of clock is 4.7us*/ 1873 usec_delay(IXGBE_I2C_T_LOW); 1874 } 1875 1876 ixgbe_i2c_start(hw); 1877 1878 /* Put the i2c bus back to default state */ 1879 ixgbe_i2c_stop(hw); 1880 } 1881 1882 /** 1883 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1884 * @hw: pointer to hardware structure 1885 * 1886 * Checks if the LASI temp alarm status was triggered due to overtemp 1887 **/ 1888 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1889 { 1890 s32 status = IXGBE_SUCCESS; 1891 u16 phy_data = 0; 1892 1893 DEBUGFUNC("ixgbe_tn_check_overtemp"); 1894 1895 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1896 goto out; 1897 1898 /* Check that the LASI temp alarm status was triggered */ 1899 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1900 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1901 1902 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1903 goto out; 1904 1905 status = IXGBE_ERR_OVERTEMP; 1906 out: 1907 return status; 1908 } 1909
Indexes created Thu Sep 25 16:09:42 GMT 2025