ixgbe_phy.c revision 1.5
1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 247822 2013-03-04 23:07:40Z jfv $*/ 34 /*$NetBSD: ixgbe_phy.c,v 1.5 2015/04/24 07:00:51 msaitoh Exp $*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 50 static bool ixgbe_get_i2c_data(u32 *i2cctl); 51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 52 u8 *sff8472_data); 53 54 /** 55 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 56 * @hw: pointer to the hardware structure 57 * 58 * Initialize the function pointers. 59 **/ 60 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 61 { 62 struct ixgbe_phy_info *phy = &hw->phy; 63 64 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 65 66 /* PHY */ 67 phy->ops.identify = &ixgbe_identify_phy_generic; 68 phy->ops.reset = &ixgbe_reset_phy_generic; 69 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 70 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 71 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 72 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 73 phy->ops.check_link = NULL; 74 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 75 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 76 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 77 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic; 78 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 79 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 80 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 81 phy->ops.identify_sfp = &ixgbe_identify_module_generic; 82 phy->sfp_type = ixgbe_sfp_type_unknown; 83 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 84 return IXGBE_SUCCESS; 85 } 86 87 /** 88 * ixgbe_identify_phy_generic - Get physical layer module 89 * @hw: pointer to hardware structure 90 * 91 * Determines the physical layer module found on the current adapter. 92 **/ 93 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 94 { 95 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 96 u32 phy_addr; 97 u16 ext_ability = 0; 98 99 DEBUGFUNC("ixgbe_identify_phy_generic"); 100 101 if (hw->phy.type == ixgbe_phy_unknown) { 102 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 103 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 104 hw->phy.addr = phy_addr; 105 ixgbe_get_phy_id(hw); 106 hw->phy.type = 107 ixgbe_get_phy_type_from_id(hw->phy.id); 108 109 if (hw->phy.type == ixgbe_phy_unknown) { 110 hw->phy.ops.read_reg(hw, 111 IXGBE_MDIO_PHY_EXT_ABILITY, 112 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 113 &ext_ability); 114 if (ext_ability & 115 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 116 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 117 hw->phy.type = 118 ixgbe_phy_cu_unknown; 119 else 120 hw->phy.type = 121 ixgbe_phy_generic; 122 } 123 124 status = IXGBE_SUCCESS; 125 break; 126 } 127 } 128 /* clear value if nothing found */ 129 if (status != IXGBE_SUCCESS) 130 hw->phy.addr = 0; 131 } else { 132 status = IXGBE_SUCCESS; 133 } 134 135 return status; 136 } 137 138 /** 139 * ixgbe_validate_phy_addr - Determines phy address is valid 140 * @hw: pointer to hardware structure 141 * 142 **/ 143 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 144 { 145 u16 phy_id = 0; 146 bool valid = FALSE; 147 148 DEBUGFUNC("ixgbe_validate_phy_addr"); 149 150 hw->phy.addr = phy_addr; 151 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 152 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 153 154 if (phy_id != 0xFFFF && phy_id != 0x0) 155 valid = TRUE; 156 157 return valid; 158 } 159 160 /** 161 * ixgbe_get_phy_id - Get the phy type 162 * @hw: pointer to hardware structure 163 * 164 **/ 165 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 166 { 167 u32 status; 168 u16 phy_id_high = 0; 169 u16 phy_id_low = 0; 170 171 DEBUGFUNC("ixgbe_get_phy_id"); 172 173 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 174 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 175 &phy_id_high); 176 177 if (status == IXGBE_SUCCESS) { 178 hw->phy.id = (u32)(phy_id_high << 16); 179 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 180 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 181 &phy_id_low); 182 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 183 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 184 } 185 return status; 186 } 187 188 /** 189 * ixgbe_get_phy_type_from_id - Get the phy type 190 * @hw: pointer to hardware structure 191 * 192 **/ 193 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 194 { 195 enum ixgbe_phy_type phy_type; 196 197 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 198 199 switch (phy_id) { 200 case TN1010_PHY_ID: 201 phy_type = ixgbe_phy_tn; 202 break; 203 case X540_PHY_ID: 204 phy_type = ixgbe_phy_aq; 205 break; 206 case QT2022_PHY_ID: 207 phy_type = ixgbe_phy_qt; 208 break; 209 case ATH_PHY_ID: 210 phy_type = ixgbe_phy_nl; 211 break; 212 default: 213 phy_type = ixgbe_phy_unknown; 214 break; 215 } 216 217 DEBUGOUT1("phy type found is %d\n", phy_type); 218 return phy_type; 219 } 220 221 /** 222 * ixgbe_reset_phy_generic - Performs a PHY reset 223 * @hw: pointer to hardware structure 224 **/ 225 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 226 { 227 u32 i; 228 u16 ctrl = 0; 229 s32 status = IXGBE_SUCCESS; 230 231 DEBUGFUNC("ixgbe_reset_phy_generic"); 232 233 if (hw->phy.type == ixgbe_phy_unknown) 234 status = ixgbe_identify_phy_generic(hw); 235 236 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 237 goto out; 238 239 /* Don't reset PHY if it's shut down due to overtemp. */ 240 if (!hw->phy.reset_if_overtemp && 241 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 242 goto out; 243 244 /* 245 * Perform soft PHY reset to the PHY_XS. 246 * This will cause a soft reset to the PHY 247 */ 248 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 249 IXGBE_MDIO_PHY_XS_DEV_TYPE, 250 IXGBE_MDIO_PHY_XS_RESET); 251 252 /* 253 * Poll for reset bit to self-clear indicating reset is complete. 254 * Some PHYs could take up to 3 seconds to complete and need about 255 * 1.7 usec delay after the reset is complete. 256 */ 257 for (i = 0; i < 30; i++) { 258 msec_delay(100); 259 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 260 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 261 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 262 usec_delay(2); 263 break; 264 } 265 } 266 267 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 268 status = IXGBE_ERR_RESET_FAILED; 269 DEBUGOUT("PHY reset polling failed to complete.\n"); 270 } 271 272 out: 273 return status; 274 } 275 276 /** 277 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 278 * @hw: pointer to hardware structure 279 * @reg_addr: 32 bit address of PHY register to read 280 * @phy_data: Pointer to read data from PHY register 281 **/ 282 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 283 u32 device_type, u16 *phy_data) 284 { 285 u32 command; 286 u32 i; 287 u32 data; 288 s32 status = IXGBE_SUCCESS; 289 u16 gssr; 290 291 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 292 293 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 294 gssr = IXGBE_GSSR_PHY1_SM; 295 else 296 gssr = IXGBE_GSSR_PHY0_SM; 297 298 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 299 status = IXGBE_ERR_SWFW_SYNC; 300 301 if (status == IXGBE_SUCCESS) { 302 /* Setup and write the address cycle command */ 303 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 304 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 305 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 306 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 307 308 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 309 310 /* 311 * Check every 10 usec to see if the address cycle completed. 312 * The MDI Command bit will clear when the operation is 313 * complete 314 */ 315 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 316 usec_delay(10); 317 318 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 319 320 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 321 break; 322 } 323 324 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 325 DEBUGOUT("PHY address command did not complete.\n"); 326 status = IXGBE_ERR_PHY; 327 } 328 329 if (status == IXGBE_SUCCESS) { 330 /* 331 * Address cycle complete, setup and write the read 332 * command 333 */ 334 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 335 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 336 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 337 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 338 339 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 340 341 /* 342 * Check every 10 usec to see if the address cycle 343 * completed. The MDI Command bit will clear when the 344 * operation is complete 345 */ 346 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 347 usec_delay(10); 348 349 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 350 351 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 352 break; 353 } 354 355 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 356 DEBUGOUT("PHY read command didn't complete\n"); 357 status = IXGBE_ERR_PHY; 358 } else { 359 /* 360 * Read operation is complete. Get the data 361 * from MSRWD 362 */ 363 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 364 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 365 *phy_data = (u16)(data); 366 } 367 } 368 369 hw->mac.ops.release_swfw_sync(hw, gssr); 370 } 371 372 return status; 373 } 374 375 /** 376 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 377 * @hw: pointer to hardware structure 378 * @reg_addr: 32 bit PHY register to write 379 * @device_type: 5 bit device type 380 * @phy_data: Data to write to the PHY register 381 **/ 382 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 383 u32 device_type, u16 phy_data) 384 { 385 u32 command; 386 u32 i; 387 s32 status = IXGBE_SUCCESS; 388 u16 gssr; 389 390 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 391 392 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 393 gssr = IXGBE_GSSR_PHY1_SM; 394 else 395 gssr = IXGBE_GSSR_PHY0_SM; 396 397 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 398 status = IXGBE_ERR_SWFW_SYNC; 399 400 if (status == IXGBE_SUCCESS) { 401 /* Put the data in the MDI single read and write data register*/ 402 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 403 404 /* Setup and write the address cycle command */ 405 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 406 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 407 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 408 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 409 410 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 411 412 /* 413 * Check every 10 usec to see if the address cycle completed. 414 * The MDI Command bit will clear when the operation is 415 * complete 416 */ 417 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 418 usec_delay(10); 419 420 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 421 422 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 423 break; 424 } 425 426 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 427 DEBUGOUT("PHY address cmd didn't complete\n"); 428 status = IXGBE_ERR_PHY; 429 } 430 431 if (status == IXGBE_SUCCESS) { 432 /* 433 * Address cycle complete, setup and write the write 434 * command 435 */ 436 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 437 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 438 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 439 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 440 441 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 442 443 /* 444 * Check every 10 usec to see if the address cycle 445 * completed. The MDI Command bit will clear when the 446 * operation is complete 447 */ 448 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 449 usec_delay(10); 450 451 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 452 453 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 454 break; 455 } 456 457 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 458 DEBUGOUT("PHY address cmd didn't complete\n"); 459 status = IXGBE_ERR_PHY; 460 } 461 } 462 463 hw->mac.ops.release_swfw_sync(hw, gssr); 464 } 465 466 return status; 467 } 468 469 /** 470 * ixgbe_setup_phy_link_generic - Set and restart autoneg 471 * @hw: pointer to hardware structure 472 * 473 * Restart autonegotiation and PHY and waits for completion. 474 **/ 475 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 476 { 477 s32 status = IXGBE_SUCCESS; 478 u32 time_out; 479 u32 max_time_out = 10; 480 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 481 bool autoneg = FALSE; 482 ixgbe_link_speed speed; 483 484 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 485 486 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 487 488 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 489 /* Set or unset auto-negotiation 10G advertisement */ 490 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 491 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 492 &autoneg_reg); 493 494 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 495 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 496 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 497 498 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 499 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 500 autoneg_reg); 501 } 502 503 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 504 /* Set or unset auto-negotiation 1G advertisement */ 505 hw->phy.ops.read_reg(hw, 506 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 507 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 508 &autoneg_reg); 509 510 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 511 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 512 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 513 514 hw->phy.ops.write_reg(hw, 515 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 516 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 517 autoneg_reg); 518 } 519 520 if (speed & IXGBE_LINK_SPEED_100_FULL) { 521 /* Set or unset auto-negotiation 100M advertisement */ 522 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 523 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 524 &autoneg_reg); 525 526 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 527 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 528 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 529 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 530 531 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 532 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 533 autoneg_reg); 534 } 535 536 /* Restart PHY autonegotiation and wait for completion */ 537 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 538 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 539 540 autoneg_reg |= IXGBE_MII_RESTART; 541 542 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 543 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 544 545 /* Wait for autonegotiation to finish */ 546 for (time_out = 0; time_out < max_time_out; time_out++) { 547 usec_delay(10); 548 /* Restart PHY autonegotiation and wait for completion */ 549 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 550 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 551 &autoneg_reg); 552 553 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 554 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 555 break; 556 } 557 558 if (time_out == max_time_out) { 559 status = IXGBE_ERR_LINK_SETUP; 560 DEBUGOUT("ixgbe_setup_phy_link_generic: time out"); 561 } 562 563 return status; 564 } 565 566 /** 567 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 568 * @hw: pointer to hardware structure 569 * @speed: new link speed 570 **/ 571 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 572 ixgbe_link_speed speed, 573 bool autoneg_wait_to_complete) 574 { 575 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 576 577 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 578 579 /* 580 * Clear autoneg_advertised and set new values based on input link 581 * speed. 582 */ 583 hw->phy.autoneg_advertised = 0; 584 585 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 586 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 587 588 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 589 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 590 591 if (speed & IXGBE_LINK_SPEED_100_FULL) 592 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 593 594 /* Setup link based on the new speed settings */ 595 hw->phy.ops.setup_link(hw); 596 597 return IXGBE_SUCCESS; 598 } 599 600 /** 601 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 602 * @hw: pointer to hardware structure 603 * @speed: pointer to link speed 604 * @autoneg: boolean auto-negotiation value 605 * 606 * Determines the link capabilities by reading the AUTOC register. 607 **/ 608 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 609 ixgbe_link_speed *speed, 610 bool *autoneg) 611 { 612 s32 status = IXGBE_ERR_LINK_SETUP; 613 u16 speed_ability; 614 615 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 616 617 *speed = 0; 618 *autoneg = TRUE; 619 620 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 621 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 622 &speed_ability); 623 624 if (status == IXGBE_SUCCESS) { 625 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 626 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 627 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 628 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 629 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 630 *speed |= IXGBE_LINK_SPEED_100_FULL; 631 } 632 633 return status; 634 } 635 636 /** 637 * ixgbe_check_phy_link_tnx - Determine link and speed status 638 * @hw: pointer to hardware structure 639 * 640 * Reads the VS1 register to determine if link is up and the current speed for 641 * the PHY. 642 **/ 643 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 644 bool *link_up) 645 { 646 s32 status = IXGBE_SUCCESS; 647 u32 time_out; 648 u32 max_time_out = 10; 649 u16 phy_link = 0; 650 u16 phy_speed = 0; 651 u16 phy_data = 0; 652 653 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 654 655 /* Initialize speed and link to default case */ 656 *link_up = FALSE; 657 *speed = IXGBE_LINK_SPEED_10GB_FULL; 658 659 /* 660 * Check current speed and link status of the PHY register. 661 * This is a vendor specific register and may have to 662 * be changed for other copper PHYs. 663 */ 664 for (time_out = 0; time_out < max_time_out; time_out++) { 665 usec_delay(10); 666 status = hw->phy.ops.read_reg(hw, 667 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 668 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 669 &phy_data); 670 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 671 phy_speed = phy_data & 672 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 673 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 674 *link_up = TRUE; 675 if (phy_speed == 676 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 677 *speed = IXGBE_LINK_SPEED_1GB_FULL; 678 break; 679 } 680 } 681 682 return status; 683 } 684 685 /** 686 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 687 * @hw: pointer to hardware structure 688 * 689 * Restart autonegotiation and PHY and waits for completion. 690 **/ 691 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 692 { 693 s32 status = IXGBE_SUCCESS; 694 u32 time_out; 695 u32 max_time_out = 10; 696 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 697 bool autoneg = FALSE; 698 ixgbe_link_speed speed; 699 700 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 701 702 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 703 704 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 705 /* Set or unset auto-negotiation 10G advertisement */ 706 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 707 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 708 &autoneg_reg); 709 710 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 711 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 712 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 713 714 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 715 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 716 autoneg_reg); 717 } 718 719 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 720 /* Set or unset auto-negotiation 1G advertisement */ 721 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 722 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 723 &autoneg_reg); 724 725 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 726 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 727 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 728 729 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 730 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 731 autoneg_reg); 732 } 733 734 if (speed & IXGBE_LINK_SPEED_100_FULL) { 735 /* Set or unset auto-negotiation 100M advertisement */ 736 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 737 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 738 &autoneg_reg); 739 740 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 741 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 742 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 743 744 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 745 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 746 autoneg_reg); 747 } 748 749 /* Restart PHY autonegotiation and wait for completion */ 750 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 751 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 752 753 autoneg_reg |= IXGBE_MII_RESTART; 754 755 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 756 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 757 758 /* Wait for autonegotiation to finish */ 759 for (time_out = 0; time_out < max_time_out; time_out++) { 760 usec_delay(10); 761 /* Restart PHY autonegotiation and wait for completion */ 762 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 763 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 764 &autoneg_reg); 765 766 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 767 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 768 break; 769 } 770 771 if (time_out == max_time_out) { 772 status = IXGBE_ERR_LINK_SETUP; 773 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 774 } 775 776 return status; 777 } 778 779 /** 780 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 781 * @hw: pointer to hardware structure 782 * @firmware_version: pointer to the PHY Firmware Version 783 **/ 784 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 785 u16 *firmware_version) 786 { 787 s32 status = IXGBE_SUCCESS; 788 789 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 790 791 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 792 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 793 firmware_version); 794 795 return status; 796 } 797 798 /** 799 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 800 * @hw: pointer to hardware structure 801 * @firmware_version: pointer to the PHY Firmware Version 802 **/ 803 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 804 u16 *firmware_version) 805 { 806 s32 status = IXGBE_SUCCESS; 807 808 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 809 810 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 811 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 812 firmware_version); 813 814 return status; 815 } 816 817 /** 818 * ixgbe_reset_phy_nl - Performs a PHY reset 819 * @hw: pointer to hardware structure 820 **/ 821 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 822 { 823 u16 phy_offset, control, eword, edata, block_crc; 824 bool end_data = FALSE; 825 u16 list_offset, data_offset; 826 u16 phy_data = 0; 827 s32 ret_val = IXGBE_SUCCESS; 828 u32 i; 829 830 DEBUGFUNC("ixgbe_reset_phy_nl"); 831 832 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 833 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 834 835 /* reset the PHY and poll for completion */ 836 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 837 IXGBE_MDIO_PHY_XS_DEV_TYPE, 838 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 839 840 for (i = 0; i < 100; i++) { 841 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 842 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 843 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 844 break; 845 msec_delay(10); 846 } 847 848 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 849 DEBUGOUT("PHY reset did not complete.\n"); 850 ret_val = IXGBE_ERR_PHY; 851 goto out; 852 } 853 854 /* Get init offsets */ 855 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 856 &data_offset); 857 if (ret_val != IXGBE_SUCCESS) 858 goto out; 859 860 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 861 data_offset++; 862 while (!end_data) { 863 /* 864 * Read control word from PHY init contents offset 865 */ 866 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 867 control = (eword & IXGBE_CONTROL_MASK_NL) >> 868 IXGBE_CONTROL_SHIFT_NL; 869 edata = eword & IXGBE_DATA_MASK_NL; 870 switch (control) { 871 case IXGBE_DELAY_NL: 872 data_offset++; 873 DEBUGOUT1("DELAY: %d MS\n", edata); 874 msec_delay(edata); 875 break; 876 case IXGBE_DATA_NL: 877 DEBUGOUT("DATA:\n"); 878 data_offset++; 879 hw->eeprom.ops.read(hw, data_offset++, 880 &phy_offset); 881 for (i = 0; i < edata; i++) { 882 hw->eeprom.ops.read(hw, data_offset, &eword); 883 hw->phy.ops.write_reg(hw, phy_offset, 884 IXGBE_TWINAX_DEV, eword); 885 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 886 phy_offset); 887 data_offset++; 888 phy_offset++; 889 } 890 break; 891 case IXGBE_CONTROL_NL: 892 data_offset++; 893 DEBUGOUT("CONTROL:\n"); 894 if (edata == IXGBE_CONTROL_EOL_NL) { 895 DEBUGOUT("EOL\n"); 896 end_data = TRUE; 897 } else if (edata == IXGBE_CONTROL_SOL_NL) { 898 DEBUGOUT("SOL\n"); 899 } else { 900 DEBUGOUT("Bad control value\n"); 901 ret_val = IXGBE_ERR_PHY; 902 goto out; 903 } 904 break; 905 default: 906 DEBUGOUT("Bad control type\n"); 907 ret_val = IXGBE_ERR_PHY; 908 goto out; 909 } 910 } 911 912 out: 913 return ret_val; 914 } 915 916 /** 917 * ixgbe_identify_module_generic - Identifies module type 918 * @hw: pointer to hardware structure 919 * 920 * Determines HW type and calls appropriate function. 921 **/ 922 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 923 { 924 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 925 926 DEBUGFUNC("ixgbe_identify_module_generic"); 927 928 switch (hw->mac.ops.get_media_type(hw)) { 929 case ixgbe_media_type_fiber: 930 status = ixgbe_identify_sfp_module_generic(hw); 931 break; 932 933 934 default: 935 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 936 status = IXGBE_ERR_SFP_NOT_PRESENT; 937 break; 938 } 939 940 return status; 941 } 942 943 /** 944 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 945 * @hw: pointer to hardware structure 946 * 947 * Searches for and identifies the SFP module and assigns appropriate PHY type. 948 **/ 949 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 950 { 951 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 952 u32 vendor_oui = 0; 953 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 954 u8 identifier = 0; 955 u8 comp_codes_1g = 0; 956 u8 comp_codes_10g = 0; 957 u8 oui_bytes[3] = {0, 0, 0}; 958 u8 cable_tech = 0; 959 u8 cable_spec = 0; 960 u16 enforce_sfp = 0; 961 962 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 963 964 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 965 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 966 status = IXGBE_ERR_SFP_NOT_PRESENT; 967 goto out; 968 } 969 970 status = hw->phy.ops.read_i2c_eeprom(hw, 971 IXGBE_SFF_IDENTIFIER, 972 &identifier); 973 974 if (status != IXGBE_SUCCESS) 975 goto err_read_i2c_eeprom; 976 977 /* LAN ID is needed for sfp_type determination */ 978 hw->mac.ops.set_lan_id(hw); 979 980 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 981 hw->phy.type = ixgbe_phy_sfp_unsupported; 982 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 983 } else { 984 status = hw->phy.ops.read_i2c_eeprom(hw, 985 IXGBE_SFF_1GBE_COMP_CODES, 986 &comp_codes_1g); 987 988 if (status != IXGBE_SUCCESS) 989 goto err_read_i2c_eeprom; 990 991 status = hw->phy.ops.read_i2c_eeprom(hw, 992 IXGBE_SFF_10GBE_COMP_CODES, 993 &comp_codes_10g); 994 995 if (status != IXGBE_SUCCESS) 996 goto err_read_i2c_eeprom; 997 status = hw->phy.ops.read_i2c_eeprom(hw, 998 IXGBE_SFF_CABLE_TECHNOLOGY, 999 &cable_tech); 1000 1001 if (status != IXGBE_SUCCESS) 1002 goto err_read_i2c_eeprom; 1003 1004 /* ID Module 1005 * ========= 1006 * 0 SFP_DA_CU 1007 * 1 SFP_SR 1008 * 2 SFP_LR 1009 * 3 SFP_DA_CORE0 - 82599-specific 1010 * 4 SFP_DA_CORE1 - 82599-specific 1011 * 5 SFP_SR/LR_CORE0 - 82599-specific 1012 * 6 SFP_SR/LR_CORE1 - 82599-specific 1013 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1014 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1015 * 9 SFP_1g_cu_CORE0 - 82599-specific 1016 * 10 SFP_1g_cu_CORE1 - 82599-specific 1017 * 11 SFP_1g_sx_CORE0 - 82599-specific 1018 * 12 SFP_1g_sx_CORE1 - 82599-specific 1019 */ 1020 if (hw->mac.type == ixgbe_mac_82598EB) { 1021 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1022 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1023 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1024 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1025 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1026 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1027 else 1028 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1029 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1030 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1031 if (hw->bus.lan_id == 0) 1032 hw->phy.sfp_type = 1033 ixgbe_sfp_type_da_cu_core0; 1034 else 1035 hw->phy.sfp_type = 1036 ixgbe_sfp_type_da_cu_core1; 1037 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1038 hw->phy.ops.read_i2c_eeprom( 1039 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1040 &cable_spec); 1041 if (cable_spec & 1042 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1043 if (hw->bus.lan_id == 0) 1044 hw->phy.sfp_type = 1045 ixgbe_sfp_type_da_act_lmt_core0; 1046 else 1047 hw->phy.sfp_type = 1048 ixgbe_sfp_type_da_act_lmt_core1; 1049 } else { 1050 hw->phy.sfp_type = 1051 ixgbe_sfp_type_unknown; 1052 } 1053 } else if (comp_codes_10g & 1054 (IXGBE_SFF_10GBASESR_CAPABLE | 1055 IXGBE_SFF_10GBASELR_CAPABLE)) { 1056 if (hw->bus.lan_id == 0) 1057 hw->phy.sfp_type = 1058 ixgbe_sfp_type_srlr_core0; 1059 else 1060 hw->phy.sfp_type = 1061 ixgbe_sfp_type_srlr_core1; 1062 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1063 if (hw->bus.lan_id == 0) 1064 hw->phy.sfp_type = 1065 ixgbe_sfp_type_1g_cu_core0; 1066 else 1067 hw->phy.sfp_type = 1068 ixgbe_sfp_type_1g_cu_core1; 1069 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1070 if (hw->bus.lan_id == 0) 1071 hw->phy.sfp_type = 1072 ixgbe_sfp_type_1g_sx_core0; 1073 else 1074 hw->phy.sfp_type = 1075 ixgbe_sfp_type_1g_sx_core1; 1076 } else { 1077 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1078 } 1079 } 1080 1081 if (hw->phy.sfp_type != stored_sfp_type) 1082 hw->phy.sfp_setup_needed = TRUE; 1083 1084 /* Determine if the SFP+ PHY is dual speed or not. */ 1085 hw->phy.multispeed_fiber = FALSE; 1086 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1087 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1088 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1089 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1090 hw->phy.multispeed_fiber = TRUE; 1091 1092 /* Determine PHY vendor */ 1093 if (hw->phy.type != ixgbe_phy_nl) { 1094 hw->phy.id = identifier; 1095 status = hw->phy.ops.read_i2c_eeprom(hw, 1096 IXGBE_SFF_VENDOR_OUI_BYTE0, 1097 &oui_bytes[0]); 1098 1099 if (status != IXGBE_SUCCESS) 1100 goto err_read_i2c_eeprom; 1101 1102 status = hw->phy.ops.read_i2c_eeprom(hw, 1103 IXGBE_SFF_VENDOR_OUI_BYTE1, 1104 &oui_bytes[1]); 1105 1106 if (status != IXGBE_SUCCESS) 1107 goto err_read_i2c_eeprom; 1108 1109 status = hw->phy.ops.read_i2c_eeprom(hw, 1110 IXGBE_SFF_VENDOR_OUI_BYTE2, 1111 &oui_bytes[2]); 1112 1113 if (status != IXGBE_SUCCESS) 1114 goto err_read_i2c_eeprom; 1115 1116 vendor_oui = 1117 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1118 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1119 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1120 1121 switch (vendor_oui) { 1122 case IXGBE_SFF_VENDOR_OUI_TYCO: 1123 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1124 hw->phy.type = 1125 ixgbe_phy_sfp_passive_tyco; 1126 break; 1127 case IXGBE_SFF_VENDOR_OUI_FTL: 1128 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1129 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1130 else 1131 hw->phy.type = ixgbe_phy_sfp_ftl; 1132 break; 1133 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1134 hw->phy.type = ixgbe_phy_sfp_avago; 1135 break; 1136 case IXGBE_SFF_VENDOR_OUI_INTEL: 1137 hw->phy.type = ixgbe_phy_sfp_intel; 1138 break; 1139 default: 1140 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1141 hw->phy.type = 1142 ixgbe_phy_sfp_passive_unknown; 1143 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1144 hw->phy.type = 1145 ixgbe_phy_sfp_active_unknown; 1146 else 1147 hw->phy.type = ixgbe_phy_sfp_unknown; 1148 break; 1149 } 1150 } 1151 1152 /* Allow any DA cable vendor */ 1153 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1154 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1155 status = IXGBE_SUCCESS; 1156 goto out; 1157 } 1158 1159 /* Verify supported 1G SFP modules */ 1160 if (comp_codes_10g == 0 && 1161 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1162 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1163 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1164 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1165 hw->phy.type = ixgbe_phy_sfp_unsupported; 1166 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1167 goto out; 1168 } 1169 1170 /* Anything else 82598-based is supported */ 1171 if (hw->mac.type == ixgbe_mac_82598EB) { 1172 status = IXGBE_SUCCESS; 1173 goto out; 1174 } 1175 1176 ixgbe_get_device_caps(hw, &enforce_sfp); 1177 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1178 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || 1179 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) || 1180 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) || 1181 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) { 1182 /* Make sure we're a supported PHY type */ 1183 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1184 status = IXGBE_SUCCESS; 1185 } else { 1186 if (hw->allow_unsupported_sfp == TRUE) { 1187 EWARN(hw, "WARNING: Intel (R) Network " 1188 "Connections are quality tested " 1189 "using Intel (R) Ethernet Optics." 1190 " Using untested modules is not " 1191 "supported and may cause unstable" 1192 " operation or damage to the " 1193 "module or the adapter. Intel " 1194 "Corporation is not responsible " 1195 "for any harm caused by using " 1196 "untested modules.\n", status); 1197 status = IXGBE_SUCCESS; 1198 } else { 1199 DEBUGOUT("SFP+ module not supported\n"); 1200 hw->phy.type = 1201 ixgbe_phy_sfp_unsupported; 1202 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1203 } 1204 } 1205 } else { 1206 status = IXGBE_SUCCESS; 1207 } 1208 } 1209 1210 out: 1211 return status; 1212 1213 err_read_i2c_eeprom: 1214 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1215 if (hw->phy.type != ixgbe_phy_nl) { 1216 hw->phy.id = 0; 1217 hw->phy.type = ixgbe_phy_unknown; 1218 } 1219 return IXGBE_ERR_SFP_NOT_PRESENT; 1220 } 1221 1222 1223 1224 /** 1225 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1226 * @hw: pointer to hardware structure 1227 * @list_offset: offset to the SFP ID list 1228 * @data_offset: offset to the SFP data block 1229 * 1230 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1231 * so it returns the offsets to the phy init sequence block. 1232 **/ 1233 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1234 u16 *list_offset, 1235 u16 *data_offset) 1236 { 1237 u16 sfp_id; 1238 u16 sfp_type = hw->phy.sfp_type; 1239 1240 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1241 1242 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1243 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1244 1245 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1246 return IXGBE_ERR_SFP_NOT_PRESENT; 1247 1248 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1249 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1250 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1251 1252 /* 1253 * Limiting active cables and 1G Phys must be initialized as 1254 * SR modules 1255 */ 1256 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1257 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1258 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1259 sfp_type = ixgbe_sfp_type_srlr_core0; 1260 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1261 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1262 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1263 sfp_type = ixgbe_sfp_type_srlr_core1; 1264 1265 /* Read offset to PHY init contents */ 1266 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1267 1268 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1269 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1270 1271 /* Shift offset to first ID word */ 1272 (*list_offset)++; 1273 1274 /* 1275 * Find the matching SFP ID in the EEPROM 1276 * and program the init sequence 1277 */ 1278 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1279 1280 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1281 if (sfp_id == sfp_type) { 1282 (*list_offset)++; 1283 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1284 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1285 DEBUGOUT("SFP+ module not supported\n"); 1286 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1287 } else { 1288 break; 1289 } 1290 } else { 1291 (*list_offset) += 2; 1292 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1293 return IXGBE_ERR_PHY; 1294 } 1295 } 1296 1297 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1298 DEBUGOUT("No matching SFP+ module found\n"); 1299 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1300 } 1301 1302 return IXGBE_SUCCESS; 1303 } 1304 1305 /** 1306 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1307 * @hw: pointer to hardware structure 1308 * @byte_offset: EEPROM byte offset to read 1309 * @eeprom_data: value read 1310 * 1311 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1312 **/ 1313 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1314 u8 *eeprom_data) 1315 { 1316 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1317 1318 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1319 IXGBE_I2C_EEPROM_DEV_ADDR, 1320 eeprom_data); 1321 } 1322 1323 /** 1324 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1325 * @hw: pointer to hardware structure 1326 * @byte_offset: byte offset at address 0xA2 1327 * @eeprom_data: value read 1328 * 1329 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1330 **/ 1331 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1332 u8 *sff8472_data) 1333 { 1334 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1335 IXGBE_I2C_EEPROM_DEV_ADDR2, 1336 sff8472_data); 1337 } 1338 1339 /** 1340 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1341 * @hw: pointer to hardware structure 1342 * @byte_offset: EEPROM byte offset to write 1343 * @eeprom_data: value to write 1344 * 1345 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1346 **/ 1347 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1348 u8 eeprom_data) 1349 { 1350 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1351 1352 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1353 IXGBE_I2C_EEPROM_DEV_ADDR, 1354 eeprom_data); 1355 } 1356 1357 /** 1358 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1359 * @hw: pointer to hardware structure 1360 * @byte_offset: byte offset to read 1361 * @data: value read 1362 * 1363 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1364 * a specified device address. 1365 **/ 1366 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1367 u8 dev_addr, u8 *data) 1368 { 1369 s32 status = IXGBE_SUCCESS; 1370 u32 max_retry = 10; 1371 u32 retry = 0; 1372 u16 swfw_mask = 0; 1373 bool nack = 1; 1374 *data = 0; 1375 1376 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1377 1378 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1379 swfw_mask = IXGBE_GSSR_PHY1_SM; 1380 else 1381 swfw_mask = IXGBE_GSSR_PHY0_SM; 1382 1383 do { 1384 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 1385 != IXGBE_SUCCESS) { 1386 status = IXGBE_ERR_SWFW_SYNC; 1387 goto read_byte_out; 1388 } 1389 1390 ixgbe_i2c_start(hw); 1391 1392 /* Device Address and write indication */ 1393 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1394 if (status != IXGBE_SUCCESS) 1395 goto fail; 1396 1397 status = ixgbe_get_i2c_ack(hw); 1398 if (status != IXGBE_SUCCESS) 1399 goto fail; 1400 1401 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1402 if (status != IXGBE_SUCCESS) 1403 goto fail; 1404 1405 status = ixgbe_get_i2c_ack(hw); 1406 if (status != IXGBE_SUCCESS) 1407 goto fail; 1408 1409 ixgbe_i2c_start(hw); 1410 1411 /* Device Address and read indication */ 1412 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1413 if (status != IXGBE_SUCCESS) 1414 goto fail; 1415 1416 status = ixgbe_get_i2c_ack(hw); 1417 if (status != IXGBE_SUCCESS) 1418 goto fail; 1419 1420 status = ixgbe_clock_in_i2c_byte(hw, data); 1421 if (status != IXGBE_SUCCESS) 1422 goto fail; 1423 1424 status = ixgbe_clock_out_i2c_bit(hw, nack); 1425 if (status != IXGBE_SUCCESS) 1426 goto fail; 1427 1428 ixgbe_i2c_stop(hw); 1429 break; 1430 1431 fail: 1432 ixgbe_i2c_bus_clear(hw); 1433 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1434 msec_delay(100); 1435 retry++; 1436 if (retry < max_retry) 1437 DEBUGOUT("I2C byte read error - Retrying.\n"); 1438 else 1439 DEBUGOUT("I2C byte read error.\n"); 1440 1441 } while (retry < max_retry); 1442 1443 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1444 1445 read_byte_out: 1446 return status; 1447 } 1448 1449 /** 1450 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1451 * @hw: pointer to hardware structure 1452 * @byte_offset: byte offset to write 1453 * @data: value to write 1454 * 1455 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1456 * a specified device address. 1457 **/ 1458 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1459 u8 dev_addr, u8 data) 1460 { 1461 s32 status = IXGBE_SUCCESS; 1462 u32 max_retry = 2; 1463 u32 retry = 0; 1464 u16 swfw_mask = 0; 1465 1466 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1467 1468 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1469 swfw_mask = IXGBE_GSSR_PHY1_SM; 1470 else 1471 swfw_mask = IXGBE_GSSR_PHY0_SM; 1472 1473 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1474 status = IXGBE_ERR_SWFW_SYNC; 1475 goto write_byte_out; 1476 } 1477 1478 do { 1479 ixgbe_i2c_start(hw); 1480 1481 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1482 if (status != IXGBE_SUCCESS) 1483 goto fail; 1484 1485 status = ixgbe_get_i2c_ack(hw); 1486 if (status != IXGBE_SUCCESS) 1487 goto fail; 1488 1489 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1490 if (status != IXGBE_SUCCESS) 1491 goto fail; 1492 1493 status = ixgbe_get_i2c_ack(hw); 1494 if (status != IXGBE_SUCCESS) 1495 goto fail; 1496 1497 status = ixgbe_clock_out_i2c_byte(hw, data); 1498 if (status != IXGBE_SUCCESS) 1499 goto fail; 1500 1501 status = ixgbe_get_i2c_ack(hw); 1502 if (status != IXGBE_SUCCESS) 1503 goto fail; 1504 1505 ixgbe_i2c_stop(hw); 1506 break; 1507 1508 fail: 1509 ixgbe_i2c_bus_clear(hw); 1510 retry++; 1511 if (retry < max_retry) 1512 DEBUGOUT("I2C byte write error - Retrying.\n"); 1513 else 1514 DEBUGOUT("I2C byte write error.\n"); 1515 } while (retry < max_retry); 1516 1517 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1518 1519 write_byte_out: 1520 return status; 1521 } 1522 1523 /** 1524 * ixgbe_i2c_start - Sets I2C start condition 1525 * @hw: pointer to hardware structure 1526 * 1527 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1528 **/ 1529 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1530 { 1531 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1532 1533 DEBUGFUNC("ixgbe_i2c_start"); 1534 1535 /* Start condition must begin with data and clock high */ 1536 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1537 ixgbe_raise_i2c_clk(hw, &i2cctl); 1538 1539 /* Setup time for start condition (4.7us) */ 1540 usec_delay(IXGBE_I2C_T_SU_STA); 1541 1542 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1543 1544 /* Hold time for start condition (4us) */ 1545 usec_delay(IXGBE_I2C_T_HD_STA); 1546 1547 ixgbe_lower_i2c_clk(hw, &i2cctl); 1548 1549 /* Minimum low period of clock is 4.7 us */ 1550 usec_delay(IXGBE_I2C_T_LOW); 1551 1552 } 1553 1554 /** 1555 * ixgbe_i2c_stop - Sets I2C stop condition 1556 * @hw: pointer to hardware structure 1557 * 1558 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1559 **/ 1560 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1561 { 1562 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1563 1564 DEBUGFUNC("ixgbe_i2c_stop"); 1565 1566 /* Stop condition must begin with data low and clock high */ 1567 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1568 ixgbe_raise_i2c_clk(hw, &i2cctl); 1569 1570 /* Setup time for stop condition (4us) */ 1571 usec_delay(IXGBE_I2C_T_SU_STO); 1572 1573 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1574 1575 /* bus free time between stop and start (4.7us)*/ 1576 usec_delay(IXGBE_I2C_T_BUF); 1577 } 1578 1579 /** 1580 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1581 * @hw: pointer to hardware structure 1582 * @data: data byte to clock in 1583 * 1584 * Clocks in one byte data via I2C data/clock 1585 **/ 1586 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1587 { 1588 s32 i; 1589 bool bit = 0; 1590 1591 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1592 1593 for (i = 7; i >= 0; i--) { 1594 ixgbe_clock_in_i2c_bit(hw, &bit); 1595 *data |= bit << i; 1596 } 1597 1598 return IXGBE_SUCCESS; 1599 } 1600 1601 /** 1602 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1603 * @hw: pointer to hardware structure 1604 * @data: data byte clocked out 1605 * 1606 * Clocks out one byte data via I2C data/clock 1607 **/ 1608 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1609 { 1610 s32 status = IXGBE_SUCCESS; 1611 s32 i; 1612 u32 i2cctl; 1613 bool bit = 0; 1614 1615 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1616 1617 for (i = 7; i >= 0; i--) { 1618 bit = (data >> i) & 0x1; 1619 status = ixgbe_clock_out_i2c_bit(hw, bit); 1620 1621 if (status != IXGBE_SUCCESS) 1622 break; 1623 } 1624 1625 /* Release SDA line (set high) */ 1626 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1627 i2cctl |= IXGBE_I2C_DATA_OUT; 1628 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1629 IXGBE_WRITE_FLUSH(hw); 1630 1631 return status; 1632 } 1633 1634 /** 1635 * ixgbe_get_i2c_ack - Polls for I2C ACK 1636 * @hw: pointer to hardware structure 1637 * 1638 * Clocks in/out one bit via I2C data/clock 1639 **/ 1640 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1641 { 1642 s32 status = IXGBE_SUCCESS; 1643 u32 i = 0; 1644 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1645 u32 timeout = 10; 1646 bool ack = 1; 1647 1648 DEBUGFUNC("ixgbe_get_i2c_ack"); 1649 1650 ixgbe_raise_i2c_clk(hw, &i2cctl); 1651 1652 1653 /* Minimum high period of clock is 4us */ 1654 usec_delay(IXGBE_I2C_T_HIGH); 1655 1656 /* Poll for ACK. Note that ACK in I2C spec is 1657 * transition from 1 to 0 */ 1658 for (i = 0; i < timeout; i++) { 1659 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1660 ack = ixgbe_get_i2c_data(&i2cctl); 1661 1662 usec_delay(1); 1663 if (ack == 0) 1664 break; 1665 } 1666 1667 if (ack == 1) { 1668 DEBUGOUT("I2C ack was not received.\n"); 1669 status = IXGBE_ERR_I2C; 1670 } 1671 1672 ixgbe_lower_i2c_clk(hw, &i2cctl); 1673 1674 /* Minimum low period of clock is 4.7 us */ 1675 usec_delay(IXGBE_I2C_T_LOW); 1676 1677 return status; 1678 } 1679 1680 /** 1681 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1682 * @hw: pointer to hardware structure 1683 * @data: read data value 1684 * 1685 * Clocks in one bit via I2C data/clock 1686 **/ 1687 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1688 { 1689 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1690 1691 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1692 1693 ixgbe_raise_i2c_clk(hw, &i2cctl); 1694 1695 /* Minimum high period of clock is 4us */ 1696 usec_delay(IXGBE_I2C_T_HIGH); 1697 1698 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1699 *data = ixgbe_get_i2c_data(&i2cctl); 1700 1701 ixgbe_lower_i2c_clk(hw, &i2cctl); 1702 1703 /* Minimum low period of clock is 4.7 us */ 1704 usec_delay(IXGBE_I2C_T_LOW); 1705 1706 return IXGBE_SUCCESS; 1707 } 1708 1709 /** 1710 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1711 * @hw: pointer to hardware structure 1712 * @data: data value to write 1713 * 1714 * Clocks out one bit via I2C data/clock 1715 **/ 1716 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1717 { 1718 s32 status; 1719 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1720 1721 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1722 1723 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1724 if (status == IXGBE_SUCCESS) { 1725 ixgbe_raise_i2c_clk(hw, &i2cctl); 1726 1727 /* Minimum high period of clock is 4us */ 1728 usec_delay(IXGBE_I2C_T_HIGH); 1729 1730 ixgbe_lower_i2c_clk(hw, &i2cctl); 1731 1732 /* Minimum low period of clock is 4.7 us. 1733 * This also takes care of the data hold time. 1734 */ 1735 usec_delay(IXGBE_I2C_T_LOW); 1736 } else { 1737 status = IXGBE_ERR_I2C; 1738 DEBUGOUT1("I2C data was not set to %X\n", data); 1739 } 1740 1741 return status; 1742 } 1743 /** 1744 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1745 * @hw: pointer to hardware structure 1746 * @i2cctl: Current value of I2CCTL register 1747 * 1748 * Raises the I2C clock line '0'->'1' 1749 **/ 1750 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1751 { 1752 u32 i = 0; 1753 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 1754 u32 i2cctl_r = 0; 1755 1756 DEBUGFUNC("ixgbe_raise_i2c_clk"); 1757 1758 for (i = 0; i < timeout; i++) { 1759 *i2cctl |= IXGBE_I2C_CLK_OUT; 1760 1761 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1762 IXGBE_WRITE_FLUSH(hw); 1763 /* SCL rise time (1000ns) */ 1764 usec_delay(IXGBE_I2C_T_RISE); 1765 1766 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1767 if (i2cctl_r & IXGBE_I2C_CLK_IN) 1768 break; 1769 } 1770 } 1771 1772 /** 1773 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1774 * @hw: pointer to hardware structure 1775 * @i2cctl: Current value of I2CCTL register 1776 * 1777 * Lowers the I2C clock line '1'->'0' 1778 **/ 1779 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1780 { 1781 1782 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1783 1784 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1785 1786 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1787 IXGBE_WRITE_FLUSH(hw); 1788 1789 /* SCL fall time (300ns) */ 1790 usec_delay(IXGBE_I2C_T_FALL); 1791 } 1792 1793 /** 1794 * ixgbe_set_i2c_data - Sets the I2C data bit 1795 * @hw: pointer to hardware structure 1796 * @i2cctl: Current value of I2CCTL register 1797 * @data: I2C data value (0 or 1) to set 1798 * 1799 * Sets the I2C data bit 1800 **/ 1801 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1802 { 1803 s32 status = IXGBE_SUCCESS; 1804 1805 DEBUGFUNC("ixgbe_set_i2c_data"); 1806 1807 if (data) 1808 *i2cctl |= IXGBE_I2C_DATA_OUT; 1809 else 1810 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1811 1812 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1813 IXGBE_WRITE_FLUSH(hw); 1814 1815 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1816 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1817 1818 /* Verify data was set correctly */ 1819 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1820 if (data != ixgbe_get_i2c_data(i2cctl)) { 1821 status = IXGBE_ERR_I2C; 1822 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1823 } 1824 1825 return status; 1826 } 1827 1828 /** 1829 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1830 * @hw: pointer to hardware structure 1831 * @i2cctl: Current value of I2CCTL register 1832 * 1833 * Returns the I2C data bit value 1834 **/ 1835 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1836 { 1837 bool data; 1838 1839 DEBUGFUNC("ixgbe_get_i2c_data"); 1840 1841 if (*i2cctl & IXGBE_I2C_DATA_IN) 1842 data = 1; 1843 else 1844 data = 0; 1845 1846 return data; 1847 } 1848 1849 /** 1850 * ixgbe_i2c_bus_clear - Clears the I2C bus 1851 * @hw: pointer to hardware structure 1852 * 1853 * Clears the I2C bus by sending nine clock pulses. 1854 * Used when data line is stuck low. 1855 **/ 1856 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1857 { 1858 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1859 u32 i; 1860 1861 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1862 1863 ixgbe_i2c_start(hw); 1864 1865 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1866 1867 for (i = 0; i < 9; i++) { 1868 ixgbe_raise_i2c_clk(hw, &i2cctl); 1869 1870 /* Min high period of clock is 4us */ 1871 usec_delay(IXGBE_I2C_T_HIGH); 1872 1873 ixgbe_lower_i2c_clk(hw, &i2cctl); 1874 1875 /* Min low period of clock is 4.7us*/ 1876 usec_delay(IXGBE_I2C_T_LOW); 1877 } 1878 1879 ixgbe_i2c_start(hw); 1880 1881 /* Put the i2c bus back to default state */ 1882 ixgbe_i2c_stop(hw); 1883 } 1884 1885 /** 1886 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1887 * @hw: pointer to hardware structure 1888 * 1889 * Checks if the LASI temp alarm status was triggered due to overtemp 1890 **/ 1891 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1892 { 1893 s32 status = IXGBE_SUCCESS; 1894 u16 phy_data = 0; 1895 1896 DEBUGFUNC("ixgbe_tn_check_overtemp"); 1897 1898 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1899 goto out; 1900 1901 /* Check that the LASI temp alarm status was triggered */ 1902 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1903 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1904 1905 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1906 goto out; 1907 1908 status = IXGBE_ERR_OVERTEMP; 1909 out: 1910 return status; 1911 } 1912
Indexes created Wed Sep 24 22:09:59 GMT 2025