ixgbe_phy.c revision 1.6.2.2
1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 303032 2016-07-19 17:31:48Z sbruno $*/ 34 /*$NetBSD: ixgbe_phy.c,v 1.6.2.2 2017/03/20 06:57:37 pgoyette Exp $*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 52 u8 *sff8472_data); 53 54 /** 55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 56 * @hw: pointer to the hardware structure 57 * @byte: byte to send 58 * 59 * Returns an error code on error. 60 */ 61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 62 { 63 s32 status; 64 65 status = ixgbe_clock_out_i2c_byte(hw, byte); 66 if (status) 67 return status; 68 return ixgbe_get_i2c_ack(hw); 69 } 70 71 /** 72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 73 * @hw: pointer to the hardware structure 74 * @byte: pointer to a u8 to receive the byte 75 * 76 * Returns an error code on error. 77 */ 78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 79 { 80 s32 status; 81 82 status = ixgbe_clock_in_i2c_byte(hw, byte); 83 if (status) 84 return status; 85 /* ACK */ 86 return ixgbe_clock_out_i2c_bit(hw, FALSE); 87 } 88 89 /** 90 * ixgbe_ones_comp_byte_add - Perform one's complement addition 91 * @add1 - addend 1 92 * @add2 - addend 2 93 * 94 * Returns one's complement 8-bit sum. 95 */ 96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 97 { 98 u16 sum = add1 + add2; 99 100 sum = (sum & 0xFF) + (sum >> 8); 101 return sum & 0xFF; 102 } 103 104 /** 105 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 106 * @hw: pointer to the hardware structure 107 * @addr: I2C bus address to read from 108 * @reg: I2C device register to read from 109 * @val: pointer to location to receive read value 110 * @lock: TRUE if to take and release semaphore 111 * 112 * Returns an error code on error. 113 */ 114 static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 115 u16 reg, u16 *val, bool lock) 116 { 117 u32 swfw_mask = hw->phy.phy_semaphore_mask; 118 int max_retry = 10; 119 int retry = 0; 120 u8 csum_byte; 121 u8 high_bits; 122 u8 low_bits; 123 u8 reg_high; 124 u8 csum; 125 126 if (hw->mac.type >= ixgbe_mac_X550) 127 max_retry = 3; 128 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 129 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 130 csum = ~csum; 131 do { 132 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 133 return IXGBE_ERR_SWFW_SYNC; 134 ixgbe_i2c_start(hw); 135 /* Device Address and write indication */ 136 if (ixgbe_out_i2c_byte_ack(hw, addr)) 137 goto fail; 138 /* Write bits 14:8 */ 139 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 140 goto fail; 141 /* Write bits 7:0 */ 142 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 143 goto fail; 144 /* Write csum */ 145 if (ixgbe_out_i2c_byte_ack(hw, csum)) 146 goto fail; 147 /* Re-start condition */ 148 ixgbe_i2c_start(hw); 149 /* Device Address and read indication */ 150 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 151 goto fail; 152 /* Get upper bits */ 153 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 154 goto fail; 155 /* Get low bits */ 156 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 157 goto fail; 158 /* Get csum */ 159 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 160 goto fail; 161 /* NACK */ 162 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 163 goto fail; 164 ixgbe_i2c_stop(hw); 165 if (lock) 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 *val = (high_bits << 8) | low_bits; 168 return 0; 169 170 fail: 171 ixgbe_i2c_bus_clear(hw); 172 if (lock) 173 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 174 retry++; 175 if (retry < max_retry) 176 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 177 else 178 DEBUGOUT("I2C byte read combined error.\n"); 179 } while (retry < max_retry); 180 181 return IXGBE_ERR_I2C; 182 } 183 184 /** 185 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 186 * @hw: pointer to the hardware structure 187 * @addr: I2C bus address to read from 188 * @reg: I2C device register to read from 189 * @val: pointer to location to receive read value 190 * 191 * Returns an error code on error. 192 **/ 193 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 194 u16 reg, u16 *val) 195 { 196 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 197 } 198 199 /** 200 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 201 * @hw: pointer to the hardware structure 202 * @addr: I2C bus address to read from 203 * @reg: I2C device register to read from 204 * @val: pointer to location to receive read value 205 * 206 * Returns an error code on error. 207 **/ 208 static s32 209 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 210 u16 reg, u16 *val) 211 { 212 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 213 } 214 215 /** 216 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 217 * @hw: pointer to the hardware structure 218 * @addr: I2C bus address to write to 219 * @reg: I2C device register to write to 220 * @val: value to write 221 * @lock: TRUE if to take and release semaphore 222 * 223 * Returns an error code on error. 224 */ 225 static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 226 u16 reg, u16 val, bool lock) 227 { 228 u32 swfw_mask = hw->phy.phy_semaphore_mask; 229 int max_retry = 1; 230 int retry = 0; 231 u8 reg_high; 232 u8 csum; 233 234 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 235 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 236 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 237 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 238 csum = ~csum; 239 do { 240 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 241 return IXGBE_ERR_SWFW_SYNC; 242 ixgbe_i2c_start(hw); 243 /* Device Address and write indication */ 244 if (ixgbe_out_i2c_byte_ack(hw, addr)) 245 goto fail; 246 /* Write bits 14:8 */ 247 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 248 goto fail; 249 /* Write bits 7:0 */ 250 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 251 goto fail; 252 /* Write data 15:8 */ 253 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 254 goto fail; 255 /* Write data 7:0 */ 256 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 257 goto fail; 258 /* Write csum */ 259 if (ixgbe_out_i2c_byte_ack(hw, csum)) 260 goto fail; 261 ixgbe_i2c_stop(hw); 262 if (lock) 263 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 264 return 0; 265 266 fail: 267 ixgbe_i2c_bus_clear(hw); 268 if (lock) 269 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 270 retry++; 271 if (retry < max_retry) 272 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 273 else 274 DEBUGOUT("I2C byte write combined error.\n"); 275 } while (retry < max_retry); 276 277 return IXGBE_ERR_I2C; 278 } 279 280 /** 281 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 282 * @hw: pointer to the hardware structure 283 * @addr: I2C bus address to write to 284 * @reg: I2C device register to write to 285 * @val: value to write 286 * 287 * Returns an error code on error. 288 **/ 289 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 290 u8 addr, u16 reg, u16 val) 291 { 292 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 293 } 294 295 /** 296 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 297 * @hw: pointer to the hardware structure 298 * @addr: I2C bus address to write to 299 * @reg: I2C device register to write to 300 * @val: value to write 301 * 302 * Returns an error code on error. 303 **/ 304 static s32 305 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 306 u8 addr, u16 reg, u16 val) 307 { 308 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 309 } 310 311 /** 312 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 313 * @hw: pointer to the hardware structure 314 * 315 * Initialize the function pointers. 316 **/ 317 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 318 { 319 struct ixgbe_phy_info *phy = &hw->phy; 320 321 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 322 323 /* PHY */ 324 phy->ops.identify = ixgbe_identify_phy_generic; 325 phy->ops.reset = ixgbe_reset_phy_generic; 326 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 327 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 328 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 329 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 330 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 331 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 332 phy->ops.check_link = NULL; 333 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 334 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 335 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 336 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 337 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 338 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 339 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 340 phy->ops.identify_sfp = ixgbe_identify_module_generic; 341 phy->sfp_type = ixgbe_sfp_type_unknown; 342 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic; 343 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic; 344 phy->ops.read_i2c_combined_unlocked = 345 ixgbe_read_i2c_combined_generic_unlocked; 346 phy->ops.write_i2c_combined_unlocked = 347 ixgbe_write_i2c_combined_generic_unlocked; 348 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 349 phy->ops.write_i2c_byte_unlocked = 350 ixgbe_write_i2c_byte_generic_unlocked; 351 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 352 return IXGBE_SUCCESS; 353 } 354 355 /** 356 * ixgbe_identify_phy_generic - Get physical layer module 357 * @hw: pointer to hardware structure 358 * 359 * Determines the physical layer module found on the current adapter. 360 **/ 361 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 362 { 363 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 364 u32 phy_addr; 365 u16 ext_ability = 0; 366 367 DEBUGFUNC("ixgbe_identify_phy_generic"); 368 369 if (!hw->phy.phy_semaphore_mask) { 370 if (hw->bus.lan_id) 371 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 372 else 373 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 374 } 375 376 if (hw->phy.type == ixgbe_phy_unknown) { 377 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 378 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 379 hw->phy.addr = phy_addr; 380 ixgbe_get_phy_id(hw); 381 hw->phy.type = 382 ixgbe_get_phy_type_from_id(hw->phy.id); 383 384 if (hw->phy.type == ixgbe_phy_unknown) { 385 hw->phy.ops.read_reg(hw, 386 IXGBE_MDIO_PHY_EXT_ABILITY, 387 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 388 &ext_ability); 389 if (ext_ability & 390 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 391 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 392 hw->phy.type = 393 ixgbe_phy_cu_unknown; 394 else 395 hw->phy.type = 396 ixgbe_phy_generic; 397 } 398 399 status = IXGBE_SUCCESS; 400 break; 401 } 402 } 403 404 /* Certain media types do not have a phy so an address will not 405 * be found and the code will take this path. Caller has to 406 * decide if it is an error or not. 407 */ 408 if (status != IXGBE_SUCCESS) { 409 hw->phy.addr = 0; 410 } 411 } else { 412 status = IXGBE_SUCCESS; 413 } 414 415 return status; 416 } 417 418 /** 419 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 420 * @hw: pointer to the hardware structure 421 * 422 * This function checks the MMNGC.MNG_VETO bit to see if there are 423 * any constraints on link from manageability. For MAC's that don't 424 * have this bit just return faluse since the link can not be blocked 425 * via this method. 426 **/ 427 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 428 { 429 u32 mmngc; 430 431 DEBUGFUNC("ixgbe_check_reset_blocked"); 432 433 /* If we don't have this bit, it can't be blocking */ 434 if (hw->mac.type == ixgbe_mac_82598EB) 435 return FALSE; 436 437 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 438 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 439 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 440 "MNG_VETO bit detected.\n"); 441 return TRUE; 442 } 443 444 return FALSE; 445 } 446 447 /** 448 * ixgbe_validate_phy_addr - Determines phy address is valid 449 * @hw: pointer to hardware structure 450 * 451 **/ 452 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 453 { 454 u16 phy_id = 0; 455 bool valid = FALSE; 456 457 DEBUGFUNC("ixgbe_validate_phy_addr"); 458 459 hw->phy.addr = phy_addr; 460 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 461 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 462 463 if (phy_id != 0xFFFF && phy_id != 0x0) 464 valid = TRUE; 465 466 return valid; 467 } 468 469 /** 470 * ixgbe_get_phy_id - Get the phy type 471 * @hw: pointer to hardware structure 472 * 473 **/ 474 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 475 { 476 u32 status; 477 u16 phy_id_high = 0; 478 u16 phy_id_low = 0; 479 480 DEBUGFUNC("ixgbe_get_phy_id"); 481 482 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 483 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 484 &phy_id_high); 485 486 if (status == IXGBE_SUCCESS) { 487 hw->phy.id = (u32)(phy_id_high << 16); 488 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 489 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 490 &phy_id_low); 491 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 492 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 493 } 494 return status; 495 } 496 497 /** 498 * ixgbe_get_phy_type_from_id - Get the phy type 499 * @hw: pointer to hardware structure 500 * 501 **/ 502 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 503 { 504 enum ixgbe_phy_type phy_type; 505 506 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 507 508 switch (phy_id) { 509 case TN1010_PHY_ID: 510 phy_type = ixgbe_phy_tn; 511 break; 512 case X550_PHY_ID1: 513 case X550_PHY_ID2: 514 case X550_PHY_ID3: 515 case X540_PHY_ID: 516 phy_type = ixgbe_phy_aq; 517 break; 518 case QT2022_PHY_ID: 519 phy_type = ixgbe_phy_qt; 520 break; 521 case ATH_PHY_ID: 522 phy_type = ixgbe_phy_nl; 523 break; 524 case X557_PHY_ID: 525 phy_type = ixgbe_phy_x550em_ext_t; 526 break; 527 default: 528 phy_type = ixgbe_phy_unknown; 529 break; 530 } 531 532 DEBUGOUT1("phy type found is %d\n", phy_type); 533 return phy_type; 534 } 535 536 /** 537 * ixgbe_reset_phy_generic - Performs a PHY reset 538 * @hw: pointer to hardware structure 539 **/ 540 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 541 { 542 u32 i; 543 u16 ctrl = 0; 544 s32 status = IXGBE_SUCCESS; 545 546 DEBUGFUNC("ixgbe_reset_phy_generic"); 547 548 if (hw->phy.type == ixgbe_phy_unknown) 549 status = ixgbe_identify_phy_generic(hw); 550 551 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 552 goto out; 553 554 /* Don't reset PHY if it's shut down due to overtemp. */ 555 if (!hw->phy.reset_if_overtemp && 556 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 557 goto out; 558 559 /* Blocked by MNG FW so bail */ 560 if (ixgbe_check_reset_blocked(hw)) 561 goto out; 562 563 /* 564 * Perform soft PHY reset to the PHY_XS. 565 * This will cause a soft reset to the PHY 566 */ 567 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 568 IXGBE_MDIO_PHY_XS_DEV_TYPE, 569 IXGBE_MDIO_PHY_XS_RESET); 570 571 /* 572 * Poll for reset bit to self-clear indicating reset is complete. 573 * Some PHYs could take up to 3 seconds to complete and need about 574 * 1.7 usec delay after the reset is complete. 575 */ 576 for (i = 0; i < 30; i++) { 577 msec_delay(100); 578 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 579 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 580 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 581 usec_delay(2); 582 break; 583 } 584 } 585 586 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 587 status = IXGBE_ERR_RESET_FAILED; 588 ERROR_REPORT1(IXGBE_ERROR_POLLING, 589 "PHY reset polling failed to complete.\n"); 590 } 591 592 out: 593 return status; 594 } 595 596 /** 597 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 598 * the SWFW lock 599 * @hw: pointer to hardware structure 600 * @reg_addr: 32 bit address of PHY register to read 601 * @phy_data: Pointer to read data from PHY register 602 **/ 603 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 604 u16 *phy_data) 605 { 606 u32 i, data, command; 607 608 /* Setup and write the address cycle command */ 609 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 610 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 611 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 612 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 613 614 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 615 616 /* 617 * Check every 10 usec to see if the address cycle completed. 618 * The MDI Command bit will clear when the operation is 619 * complete 620 */ 621 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 622 usec_delay(10); 623 624 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 625 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 626 break; 627 } 628 629 630 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 631 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 632 return IXGBE_ERR_PHY; 633 } 634 635 /* 636 * Address cycle complete, setup and write the read 637 * command 638 */ 639 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 640 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 641 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 642 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 643 644 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 645 646 /* 647 * Check every 10 usec to see if the address cycle 648 * completed. The MDI Command bit will clear when the 649 * operation is complete 650 */ 651 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 652 usec_delay(10); 653 654 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 655 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 656 break; 657 } 658 659 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 660 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 661 return IXGBE_ERR_PHY; 662 } 663 664 /* 665 * Read operation is complete. Get the data 666 * from MSRWD 667 */ 668 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 669 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 670 *phy_data = (u16)(data); 671 672 return IXGBE_SUCCESS; 673 } 674 675 /** 676 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 677 * using the SWFW lock - this function is needed in most cases 678 * @hw: pointer to hardware structure 679 * @reg_addr: 32 bit address of PHY register to read 680 * @phy_data: Pointer to read data from PHY register 681 **/ 682 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 683 u32 device_type, u16 *phy_data) 684 { 685 s32 status; 686 u32 gssr = hw->phy.phy_semaphore_mask; 687 688 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 689 690 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 691 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 692 phy_data); 693 hw->mac.ops.release_swfw_sync(hw, gssr); 694 } else { 695 status = IXGBE_ERR_SWFW_SYNC; 696 } 697 698 return status; 699 } 700 701 /** 702 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 703 * without SWFW lock 704 * @hw: pointer to hardware structure 705 * @reg_addr: 32 bit PHY register to write 706 * @device_type: 5 bit device type 707 * @phy_data: Data to write to the PHY register 708 **/ 709 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 710 u32 device_type, u16 phy_data) 711 { 712 u32 i, command; 713 714 /* Put the data in the MDI single read and write data register*/ 715 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 716 717 /* Setup and write the address cycle command */ 718 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 719 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 720 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 721 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 722 723 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 724 725 /* 726 * Check every 10 usec to see if the address cycle completed. 727 * The MDI Command bit will clear when the operation is 728 * complete 729 */ 730 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 731 usec_delay(10); 732 733 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 734 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 735 break; 736 } 737 738 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 739 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 740 return IXGBE_ERR_PHY; 741 } 742 743 /* 744 * Address cycle complete, setup and write the write 745 * command 746 */ 747 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 748 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 749 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 750 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 751 752 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 753 754 /* 755 * Check every 10 usec to see if the address cycle 756 * completed. The MDI Command bit will clear when the 757 * operation is complete 758 */ 759 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 760 usec_delay(10); 761 762 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 763 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 764 break; 765 } 766 767 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 768 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 769 return IXGBE_ERR_PHY; 770 } 771 772 return IXGBE_SUCCESS; 773 } 774 775 /** 776 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 777 * using SWFW lock- this function is needed in most cases 778 * @hw: pointer to hardware structure 779 * @reg_addr: 32 bit PHY register to write 780 * @device_type: 5 bit device type 781 * @phy_data: Data to write to the PHY register 782 **/ 783 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 784 u32 device_type, u16 phy_data) 785 { 786 s32 status; 787 u32 gssr = hw->phy.phy_semaphore_mask; 788 789 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 790 791 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 792 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 793 phy_data); 794 hw->mac.ops.release_swfw_sync(hw, gssr); 795 } else { 796 status = IXGBE_ERR_SWFW_SYNC; 797 } 798 799 return status; 800 } 801 802 /** 803 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 804 * @hw: pointer to hardware structure 805 * 806 * Restart auto-negotiation and PHY and waits for completion. 807 **/ 808 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 809 { 810 s32 status = IXGBE_SUCCESS; 811 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 812 bool autoneg = FALSE; 813 ixgbe_link_speed speed; 814 815 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 816 817 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 818 819 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 820 /* Set or unset auto-negotiation 10G advertisement */ 821 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 822 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 823 &autoneg_reg); 824 825 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 826 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 827 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 828 829 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 830 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 831 autoneg_reg); 832 } 833 834 if (hw->mac.type == ixgbe_mac_X550) { 835 if (speed & IXGBE_LINK_SPEED_5GB_FULL) { 836 /* Set or unset auto-negotiation 5G advertisement */ 837 hw->phy.ops.read_reg(hw, 838 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 839 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 840 &autoneg_reg); 841 842 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 843 if (hw->phy.autoneg_advertised & 844 IXGBE_LINK_SPEED_5GB_FULL) 845 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 846 847 hw->phy.ops.write_reg(hw, 848 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 849 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 850 autoneg_reg); 851 } 852 853 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) { 854 /* Set or unset auto-negotiation 2.5G advertisement */ 855 hw->phy.ops.read_reg(hw, 856 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 858 &autoneg_reg); 859 860 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 861 if (hw->phy.autoneg_advertised & 862 IXGBE_LINK_SPEED_2_5GB_FULL) 863 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 864 865 hw->phy.ops.write_reg(hw, 866 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 867 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 868 autoneg_reg); 869 } 870 } 871 872 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 873 /* Set or unset auto-negotiation 1G advertisement */ 874 hw->phy.ops.read_reg(hw, 875 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 876 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 877 &autoneg_reg); 878 879 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 880 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 881 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 882 883 hw->phy.ops.write_reg(hw, 884 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 885 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 886 autoneg_reg); 887 } 888 889 if (speed & IXGBE_LINK_SPEED_100_FULL) { 890 /* Set or unset auto-negotiation 100M advertisement */ 891 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 892 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 893 &autoneg_reg); 894 895 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 896 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 897 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 898 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 899 900 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 901 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 902 autoneg_reg); 903 } 904 905 /* Blocked by MNG FW so don't reset PHY */ 906 if (ixgbe_check_reset_blocked(hw)) 907 return status; 908 909 /* Restart PHY auto-negotiation. */ 910 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 911 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 912 913 autoneg_reg |= IXGBE_MII_RESTART; 914 915 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 916 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 917 918 return status; 919 } 920 921 /** 922 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 923 * @hw: pointer to hardware structure 924 * @speed: new link speed 925 **/ 926 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 927 ixgbe_link_speed speed, 928 bool autoneg_wait_to_complete) 929 { 930 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 931 932 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 933 934 /* 935 * Clear autoneg_advertised and set new values based on input link 936 * speed. 937 */ 938 hw->phy.autoneg_advertised = 0; 939 940 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 941 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 942 943 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 944 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 945 946 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 947 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 948 949 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 950 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 951 952 if (speed & IXGBE_LINK_SPEED_100_FULL) 953 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 954 955 /* Setup link based on the new speed settings */ 956 ixgbe_setup_phy_link(hw); 957 958 return IXGBE_SUCCESS; 959 } 960 961 /** 962 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 963 * @hw: pointer to hardware structure 964 * 965 * Determines the supported link capabilities by reading the PHY auto 966 * negotiation register. 967 **/ 968 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 969 { 970 s32 status; 971 u16 speed_ability; 972 973 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 974 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 975 &speed_ability); 976 if (status) 977 return status; 978 979 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 980 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 981 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 982 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 983 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 984 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 985 986 switch (hw->mac.type) { 987 case ixgbe_mac_X550: 988 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 989 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 990 break; 991 case ixgbe_mac_X550EM_x: 992 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 993 break; 994 default: 995 break; 996 } 997 998 return status; 999 } 1000 1001 /** 1002 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 1003 * @hw: pointer to hardware structure 1004 * @speed: pointer to link speed 1005 * @autoneg: boolean auto-negotiation value 1006 **/ 1007 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 1008 ixgbe_link_speed *speed, 1009 bool *autoneg) 1010 { 1011 s32 status = IXGBE_SUCCESS; 1012 1013 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 1014 1015 *autoneg = TRUE; 1016 if (!hw->phy.speeds_supported) 1017 status = ixgbe_get_copper_speeds_supported(hw); 1018 1019 *speed = hw->phy.speeds_supported; 1020 return status; 1021 } 1022 1023 /** 1024 * ixgbe_check_phy_link_tnx - Determine link and speed status 1025 * @hw: pointer to hardware structure 1026 * 1027 * Reads the VS1 register to determine if link is up and the current speed for 1028 * the PHY. 1029 **/ 1030 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1031 bool *link_up) 1032 { 1033 s32 status = IXGBE_SUCCESS; 1034 u32 time_out; 1035 u32 max_time_out = 10; 1036 u16 phy_link = 0; 1037 u16 phy_speed = 0; 1038 u16 phy_data = 0; 1039 1040 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1041 1042 /* Initialize speed and link to default case */ 1043 *link_up = FALSE; 1044 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1045 1046 /* 1047 * Check current speed and link status of the PHY register. 1048 * This is a vendor specific register and may have to 1049 * be changed for other copper PHYs. 1050 */ 1051 for (time_out = 0; time_out < max_time_out; time_out++) { 1052 usec_delay(10); 1053 status = hw->phy.ops.read_reg(hw, 1054 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1055 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1056 &phy_data); 1057 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1058 phy_speed = phy_data & 1059 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1060 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1061 *link_up = TRUE; 1062 if (phy_speed == 1063 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1064 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1065 break; 1066 } 1067 } 1068 1069 return status; 1070 } 1071 1072 /** 1073 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1074 * @hw: pointer to hardware structure 1075 * 1076 * Restart auto-negotiation and PHY and waits for completion. 1077 **/ 1078 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1079 { 1080 s32 status = IXGBE_SUCCESS; 1081 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1082 bool autoneg = FALSE; 1083 ixgbe_link_speed speed; 1084 1085 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1086 1087 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1088 1089 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1090 /* Set or unset auto-negotiation 10G advertisement */ 1091 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1092 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1093 &autoneg_reg); 1094 1095 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1096 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1097 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1098 1099 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1100 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1101 autoneg_reg); 1102 } 1103 1104 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1105 /* Set or unset auto-negotiation 1G advertisement */ 1106 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1107 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1108 &autoneg_reg); 1109 1110 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1111 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1112 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1113 1114 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1115 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1116 autoneg_reg); 1117 } 1118 1119 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1120 /* Set or unset auto-negotiation 100M advertisement */ 1121 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1122 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1123 &autoneg_reg); 1124 1125 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1126 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1127 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1128 1129 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1130 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1131 autoneg_reg); 1132 } 1133 1134 /* Blocked by MNG FW so don't reset PHY */ 1135 if (ixgbe_check_reset_blocked(hw)) 1136 return status; 1137 1138 /* Restart PHY auto-negotiation. */ 1139 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1140 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1141 1142 autoneg_reg |= IXGBE_MII_RESTART; 1143 1144 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1145 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1146 1147 return status; 1148 } 1149 1150 /** 1151 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1152 * @hw: pointer to hardware structure 1153 * @firmware_version: pointer to the PHY Firmware Version 1154 **/ 1155 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1156 u16 *firmware_version) 1157 { 1158 s32 status; 1159 1160 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1161 1162 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1163 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1164 firmware_version); 1165 1166 return status; 1167 } 1168 1169 /** 1170 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1171 * @hw: pointer to hardware structure 1172 * @firmware_version: pointer to the PHY Firmware Version 1173 **/ 1174 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1175 u16 *firmware_version) 1176 { 1177 s32 status; 1178 1179 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1180 1181 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1182 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1183 firmware_version); 1184 1185 return status; 1186 } 1187 1188 /** 1189 * ixgbe_reset_phy_nl - Performs a PHY reset 1190 * @hw: pointer to hardware structure 1191 **/ 1192 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1193 { 1194 u16 phy_offset, control, eword, edata, block_crc; 1195 bool end_data = FALSE; 1196 u16 list_offset, data_offset; 1197 u16 phy_data = 0; 1198 s32 ret_val = IXGBE_SUCCESS; 1199 u32 i; 1200 1201 DEBUGFUNC("ixgbe_reset_phy_nl"); 1202 1203 /* Blocked by MNG FW so bail */ 1204 if (ixgbe_check_reset_blocked(hw)) 1205 goto out; 1206 1207 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1208 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1209 1210 /* reset the PHY and poll for completion */ 1211 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1212 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1213 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1214 1215 for (i = 0; i < 100; i++) { 1216 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1217 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1218 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1219 break; 1220 msec_delay(10); 1221 } 1222 1223 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1224 DEBUGOUT("PHY reset did not complete.\n"); 1225 ret_val = IXGBE_ERR_PHY; 1226 goto out; 1227 } 1228 1229 /* Get init offsets */ 1230 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1231 &data_offset); 1232 if (ret_val != IXGBE_SUCCESS) 1233 goto out; 1234 1235 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1236 data_offset++; 1237 while (!end_data) { 1238 /* 1239 * Read control word from PHY init contents offset 1240 */ 1241 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1242 if (ret_val) 1243 goto err_eeprom; 1244 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1245 IXGBE_CONTROL_SHIFT_NL; 1246 edata = eword & IXGBE_DATA_MASK_NL; 1247 switch (control) { 1248 case IXGBE_DELAY_NL: 1249 data_offset++; 1250 DEBUGOUT1("DELAY: %d MS\n", edata); 1251 msec_delay(edata); 1252 break; 1253 case IXGBE_DATA_NL: 1254 DEBUGOUT("DATA:\n"); 1255 data_offset++; 1256 ret_val = hw->eeprom.ops.read(hw, data_offset, 1257 &phy_offset); 1258 if (ret_val) 1259 goto err_eeprom; 1260 data_offset++; 1261 for (i = 0; i < edata; i++) { 1262 ret_val = hw->eeprom.ops.read(hw, data_offset, 1263 &eword); 1264 if (ret_val) 1265 goto err_eeprom; 1266 hw->phy.ops.write_reg(hw, phy_offset, 1267 IXGBE_TWINAX_DEV, eword); 1268 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1269 phy_offset); 1270 data_offset++; 1271 phy_offset++; 1272 } 1273 break; 1274 case IXGBE_CONTROL_NL: 1275 data_offset++; 1276 DEBUGOUT("CONTROL:\n"); 1277 if (edata == IXGBE_CONTROL_EOL_NL) { 1278 DEBUGOUT("EOL\n"); 1279 end_data = TRUE; 1280 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1281 DEBUGOUT("SOL\n"); 1282 } else { 1283 DEBUGOUT("Bad control value\n"); 1284 ret_val = IXGBE_ERR_PHY; 1285 goto out; 1286 } 1287 break; 1288 default: 1289 DEBUGOUT("Bad control type\n"); 1290 ret_val = IXGBE_ERR_PHY; 1291 goto out; 1292 } 1293 } 1294 1295 out: 1296 return ret_val; 1297 1298 err_eeprom: 1299 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1300 "eeprom read at offset %d failed", data_offset); 1301 return IXGBE_ERR_PHY; 1302 } 1303 1304 /** 1305 * ixgbe_identify_module_generic - Identifies module type 1306 * @hw: pointer to hardware structure 1307 * 1308 * Determines HW type and calls appropriate function. 1309 **/ 1310 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1311 { 1312 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1313 1314 DEBUGFUNC("ixgbe_identify_module_generic"); 1315 1316 switch (hw->mac.ops.get_media_type(hw)) { 1317 case ixgbe_media_type_fiber: 1318 status = ixgbe_identify_sfp_module_generic(hw); 1319 break; 1320 1321 case ixgbe_media_type_fiber_qsfp: 1322 status = ixgbe_identify_qsfp_module_generic(hw); 1323 break; 1324 1325 default: 1326 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1327 status = IXGBE_ERR_SFP_NOT_PRESENT; 1328 break; 1329 } 1330 1331 return status; 1332 } 1333 1334 /** 1335 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1336 * @hw: pointer to hardware structure 1337 * 1338 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1339 **/ 1340 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1341 { 1342 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1343 u32 vendor_oui = 0; 1344 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1345 u8 identifier = 0; 1346 u8 comp_codes_1g = 0; 1347 u8 comp_codes_10g = 0; 1348 u8 oui_bytes[3] = {0, 0, 0}; 1349 u8 cable_tech = 0; 1350 u8 cable_spec = 0; 1351 u16 enforce_sfp = 0; 1352 1353 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1354 1355 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1356 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1357 status = IXGBE_ERR_SFP_NOT_PRESENT; 1358 goto out; 1359 } 1360 1361 /* LAN ID is needed for I2C access */ 1362 hw->mac.ops.set_lan_id(hw); 1363 1364 status = hw->phy.ops.read_i2c_eeprom(hw, 1365 IXGBE_SFF_IDENTIFIER, 1366 &identifier); 1367 1368 if (status != IXGBE_SUCCESS) 1369 goto err_read_i2c_eeprom; 1370 1371 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1372 hw->phy.type = ixgbe_phy_sfp_unsupported; 1373 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1374 } else { 1375 status = hw->phy.ops.read_i2c_eeprom(hw, 1376 IXGBE_SFF_1GBE_COMP_CODES, 1377 &comp_codes_1g); 1378 1379 if (status != IXGBE_SUCCESS) 1380 goto err_read_i2c_eeprom; 1381 1382 status = hw->phy.ops.read_i2c_eeprom(hw, 1383 IXGBE_SFF_10GBE_COMP_CODES, 1384 &comp_codes_10g); 1385 1386 if (status != IXGBE_SUCCESS) 1387 goto err_read_i2c_eeprom; 1388 status = hw->phy.ops.read_i2c_eeprom(hw, 1389 IXGBE_SFF_CABLE_TECHNOLOGY, 1390 &cable_tech); 1391 1392 if (status != IXGBE_SUCCESS) 1393 goto err_read_i2c_eeprom; 1394 1395 /* ID Module 1396 * ========= 1397 * 0 SFP_DA_CU 1398 * 1 SFP_SR 1399 * 2 SFP_LR 1400 * 3 SFP_DA_CORE0 - 82599-specific 1401 * 4 SFP_DA_CORE1 - 82599-specific 1402 * 5 SFP_SR/LR_CORE0 - 82599-specific 1403 * 6 SFP_SR/LR_CORE1 - 82599-specific 1404 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1405 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1406 * 9 SFP_1g_cu_CORE0 - 82599-specific 1407 * 10 SFP_1g_cu_CORE1 - 82599-specific 1408 * 11 SFP_1g_sx_CORE0 - 82599-specific 1409 * 12 SFP_1g_sx_CORE1 - 82599-specific 1410 */ 1411 if (hw->mac.type == ixgbe_mac_82598EB) { 1412 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1413 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1414 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1415 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1416 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1417 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1418 else 1419 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1420 } else { 1421 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1422 if (hw->bus.lan_id == 0) 1423 hw->phy.sfp_type = 1424 ixgbe_sfp_type_da_cu_core0; 1425 else 1426 hw->phy.sfp_type = 1427 ixgbe_sfp_type_da_cu_core1; 1428 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1429 hw->phy.ops.read_i2c_eeprom( 1430 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1431 &cable_spec); 1432 if (cable_spec & 1433 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1434 if (hw->bus.lan_id == 0) 1435 hw->phy.sfp_type = 1436 ixgbe_sfp_type_da_act_lmt_core0; 1437 else 1438 hw->phy.sfp_type = 1439 ixgbe_sfp_type_da_act_lmt_core1; 1440 } else { 1441 hw->phy.sfp_type = 1442 ixgbe_sfp_type_unknown; 1443 } 1444 } else if (comp_codes_10g & 1445 (IXGBE_SFF_10GBASESR_CAPABLE | 1446 IXGBE_SFF_10GBASELR_CAPABLE)) { 1447 if (hw->bus.lan_id == 0) 1448 hw->phy.sfp_type = 1449 ixgbe_sfp_type_srlr_core0; 1450 else 1451 hw->phy.sfp_type = 1452 ixgbe_sfp_type_srlr_core1; 1453 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1454 if (hw->bus.lan_id == 0) 1455 hw->phy.sfp_type = 1456 ixgbe_sfp_type_1g_cu_core0; 1457 else 1458 hw->phy.sfp_type = 1459 ixgbe_sfp_type_1g_cu_core1; 1460 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1461 if (hw->bus.lan_id == 0) 1462 hw->phy.sfp_type = 1463 ixgbe_sfp_type_1g_sx_core0; 1464 else 1465 hw->phy.sfp_type = 1466 ixgbe_sfp_type_1g_sx_core1; 1467 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1468 if (hw->bus.lan_id == 0) 1469 hw->phy.sfp_type = 1470 ixgbe_sfp_type_1g_lx_core0; 1471 else 1472 hw->phy.sfp_type = 1473 ixgbe_sfp_type_1g_lx_core1; 1474 } else { 1475 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1476 } 1477 } 1478 1479 if (hw->phy.sfp_type != stored_sfp_type) 1480 hw->phy.sfp_setup_needed = TRUE; 1481 1482 /* Determine if the SFP+ PHY is dual speed or not. */ 1483 hw->phy.multispeed_fiber = FALSE; 1484 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1485 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1486 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1487 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1488 hw->phy.multispeed_fiber = TRUE; 1489 1490 /* Determine PHY vendor */ 1491 if (hw->phy.type != ixgbe_phy_nl) { 1492 hw->phy.id = identifier; 1493 status = hw->phy.ops.read_i2c_eeprom(hw, 1494 IXGBE_SFF_VENDOR_OUI_BYTE0, 1495 &oui_bytes[0]); 1496 1497 if (status != IXGBE_SUCCESS) 1498 goto err_read_i2c_eeprom; 1499 1500 status = hw->phy.ops.read_i2c_eeprom(hw, 1501 IXGBE_SFF_VENDOR_OUI_BYTE1, 1502 &oui_bytes[1]); 1503 1504 if (status != IXGBE_SUCCESS) 1505 goto err_read_i2c_eeprom; 1506 1507 status = hw->phy.ops.read_i2c_eeprom(hw, 1508 IXGBE_SFF_VENDOR_OUI_BYTE2, 1509 &oui_bytes[2]); 1510 1511 if (status != IXGBE_SUCCESS) 1512 goto err_read_i2c_eeprom; 1513 1514 vendor_oui = 1515 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1516 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1517 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1518 1519 switch (vendor_oui) { 1520 case IXGBE_SFF_VENDOR_OUI_TYCO: 1521 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1522 hw->phy.type = 1523 ixgbe_phy_sfp_passive_tyco; 1524 break; 1525 case IXGBE_SFF_VENDOR_OUI_FTL: 1526 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1527 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1528 else 1529 hw->phy.type = ixgbe_phy_sfp_ftl; 1530 break; 1531 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1532 hw->phy.type = ixgbe_phy_sfp_avago; 1533 break; 1534 case IXGBE_SFF_VENDOR_OUI_INTEL: 1535 hw->phy.type = ixgbe_phy_sfp_intel; 1536 break; 1537 default: 1538 hw->phy.type = ixgbe_phy_sfp_unknown; 1539 break; 1540 } 1541 } 1542 1543 /* Allow any DA cable vendor */ 1544 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1545 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1546 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1547 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1548 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1549 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1550 status = IXGBE_SUCCESS; 1551 goto out; 1552 } 1553 1554 /* Verify supported 1G SFP modules */ 1555 if (comp_codes_10g == 0 && 1556 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1557 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1558 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1559 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1561 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1562 hw->phy.type = ixgbe_phy_sfp_unsupported; 1563 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1564 goto out; 1565 } 1566 1567 /* Anything else 82598-based is supported */ 1568 if (hw->mac.type == ixgbe_mac_82598EB) { 1569 status = IXGBE_SUCCESS; 1570 goto out; 1571 } 1572 1573 ixgbe_get_device_caps(hw, &enforce_sfp); 1574 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1575 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1576 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1577 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1578 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1579 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1580 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1581 /* Make sure we're a supported PHY type */ 1582 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1583 status = IXGBE_SUCCESS; 1584 } else { 1585 if (hw->allow_unsupported_sfp == TRUE) { 1586 EWARN(hw, "WARNING: Intel (R) Network " 1587 "Connections are quality tested " 1588 "using Intel (R) Ethernet Optics." 1589 " Using untested modules is not " 1590 "supported and may cause unstable" 1591 " operation or damage to the " 1592 "module or the adapter. Intel " 1593 "Corporation is not responsible " 1594 "for any harm caused by using " 1595 "untested modules.\n", status); 1596 status = IXGBE_SUCCESS; 1597 } else { 1598 DEBUGOUT("SFP+ module not supported\n"); 1599 hw->phy.type = 1600 ixgbe_phy_sfp_unsupported; 1601 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1602 } 1603 } 1604 } else { 1605 status = IXGBE_SUCCESS; 1606 } 1607 } 1608 1609 out: 1610 return status; 1611 1612 err_read_i2c_eeprom: 1613 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1614 if (hw->phy.type != ixgbe_phy_nl) { 1615 hw->phy.id = 0; 1616 hw->phy.type = ixgbe_phy_unknown; 1617 } 1618 return IXGBE_ERR_SFP_NOT_PRESENT; 1619 } 1620 1621 /** 1622 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1623 * @hw: pointer to hardware structure 1624 * 1625 * Determines physical layer capabilities of the current SFP. 1626 */ 1627 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1628 { 1629 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1630 u8 comp_codes_10g = 0; 1631 u8 comp_codes_1g = 0; 1632 1633 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1634 1635 hw->phy.ops.identify_sfp(hw); 1636 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1637 return physical_layer; 1638 1639 switch (hw->phy.type) { 1640 case ixgbe_phy_sfp_passive_tyco: 1641 case ixgbe_phy_sfp_passive_unknown: 1642 case ixgbe_phy_qsfp_passive_unknown: 1643 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1644 break; 1645 case ixgbe_phy_sfp_ftl_active: 1646 case ixgbe_phy_sfp_active_unknown: 1647 case ixgbe_phy_qsfp_active_unknown: 1648 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1649 break; 1650 case ixgbe_phy_sfp_avago: 1651 case ixgbe_phy_sfp_ftl: 1652 case ixgbe_phy_sfp_intel: 1653 case ixgbe_phy_sfp_unknown: 1654 hw->phy.ops.read_i2c_eeprom(hw, 1655 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1656 hw->phy.ops.read_i2c_eeprom(hw, 1657 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1658 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1659 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1660 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1661 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1662 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1663 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1664 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1665 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1666 break; 1667 case ixgbe_phy_qsfp_intel: 1668 case ixgbe_phy_qsfp_unknown: 1669 hw->phy.ops.read_i2c_eeprom(hw, 1670 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1671 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1672 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1673 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1674 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1675 break; 1676 default: 1677 break; 1678 } 1679 1680 return physical_layer; 1681 } 1682 1683 /** 1684 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1685 * @hw: pointer to hardware structure 1686 * 1687 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1688 **/ 1689 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1690 { 1691 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1692 u32 vendor_oui = 0; 1693 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1694 u8 identifier = 0; 1695 u8 comp_codes_1g = 0; 1696 u8 comp_codes_10g = 0; 1697 u8 oui_bytes[3] = {0, 0, 0}; 1698 u16 enforce_sfp = 0; 1699 u8 connector = 0; 1700 u8 cable_length = 0; 1701 u8 device_tech = 0; 1702 bool active_cable = FALSE; 1703 1704 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1705 1706 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1707 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1708 status = IXGBE_ERR_SFP_NOT_PRESENT; 1709 goto out; 1710 } 1711 1712 /* LAN ID is needed for I2C access */ 1713 hw->mac.ops.set_lan_id(hw); 1714 1715 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1716 &identifier); 1717 1718 if (status != IXGBE_SUCCESS) 1719 goto err_read_i2c_eeprom; 1720 1721 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1722 hw->phy.type = ixgbe_phy_sfp_unsupported; 1723 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1724 goto out; 1725 } 1726 1727 hw->phy.id = identifier; 1728 1729 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1730 &comp_codes_10g); 1731 1732 if (status != IXGBE_SUCCESS) 1733 goto err_read_i2c_eeprom; 1734 1735 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1736 &comp_codes_1g); 1737 1738 if (status != IXGBE_SUCCESS) 1739 goto err_read_i2c_eeprom; 1740 1741 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1742 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1743 if (hw->bus.lan_id == 0) 1744 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1745 else 1746 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1747 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1748 IXGBE_SFF_10GBASELR_CAPABLE)) { 1749 if (hw->bus.lan_id == 0) 1750 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1751 else 1752 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1753 } else { 1754 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1755 active_cable = TRUE; 1756 1757 if (!active_cable) { 1758 /* check for active DA cables that pre-date 1759 * SFF-8436 v3.6 */ 1760 hw->phy.ops.read_i2c_eeprom(hw, 1761 IXGBE_SFF_QSFP_CONNECTOR, 1762 &connector); 1763 1764 hw->phy.ops.read_i2c_eeprom(hw, 1765 IXGBE_SFF_QSFP_CABLE_LENGTH, 1766 &cable_length); 1767 1768 hw->phy.ops.read_i2c_eeprom(hw, 1769 IXGBE_SFF_QSFP_DEVICE_TECH, 1770 &device_tech); 1771 1772 if ((connector == 1773 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1774 (cable_length > 0) && 1775 ((device_tech >> 4) == 1776 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1777 active_cable = TRUE; 1778 } 1779 1780 if (active_cable) { 1781 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1782 if (hw->bus.lan_id == 0) 1783 hw->phy.sfp_type = 1784 ixgbe_sfp_type_da_act_lmt_core0; 1785 else 1786 hw->phy.sfp_type = 1787 ixgbe_sfp_type_da_act_lmt_core1; 1788 } else { 1789 /* unsupported module type */ 1790 hw->phy.type = ixgbe_phy_sfp_unsupported; 1791 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1792 goto out; 1793 } 1794 } 1795 1796 if (hw->phy.sfp_type != stored_sfp_type) 1797 hw->phy.sfp_setup_needed = TRUE; 1798 1799 /* Determine if the QSFP+ PHY is dual speed or not. */ 1800 hw->phy.multispeed_fiber = FALSE; 1801 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1802 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1803 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1804 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1805 hw->phy.multispeed_fiber = TRUE; 1806 1807 /* Determine PHY vendor for optical modules */ 1808 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1809 IXGBE_SFF_10GBASELR_CAPABLE)) { 1810 status = hw->phy.ops.read_i2c_eeprom(hw, 1811 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1812 &oui_bytes[0]); 1813 1814 if (status != IXGBE_SUCCESS) 1815 goto err_read_i2c_eeprom; 1816 1817 status = hw->phy.ops.read_i2c_eeprom(hw, 1818 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1819 &oui_bytes[1]); 1820 1821 if (status != IXGBE_SUCCESS) 1822 goto err_read_i2c_eeprom; 1823 1824 status = hw->phy.ops.read_i2c_eeprom(hw, 1825 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1826 &oui_bytes[2]); 1827 1828 if (status != IXGBE_SUCCESS) 1829 goto err_read_i2c_eeprom; 1830 1831 vendor_oui = 1832 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1833 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1834 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1835 1836 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1837 hw->phy.type = ixgbe_phy_qsfp_intel; 1838 else 1839 hw->phy.type = ixgbe_phy_qsfp_unknown; 1840 1841 ixgbe_get_device_caps(hw, &enforce_sfp); 1842 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1843 /* Make sure we're a supported PHY type */ 1844 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1845 status = IXGBE_SUCCESS; 1846 } else { 1847 if (hw->allow_unsupported_sfp == TRUE) { 1848 EWARN(hw, "WARNING: Intel (R) Network " 1849 "Connections are quality tested " 1850 "using Intel (R) Ethernet Optics." 1851 " Using untested modules is not " 1852 "supported and may cause unstable" 1853 " operation or damage to the " 1854 "module or the adapter. Intel " 1855 "Corporation is not responsible " 1856 "for any harm caused by using " 1857 "untested modules.\n", status); 1858 status = IXGBE_SUCCESS; 1859 } else { 1860 DEBUGOUT("QSFP module not supported\n"); 1861 hw->phy.type = 1862 ixgbe_phy_sfp_unsupported; 1863 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1864 } 1865 } 1866 } else { 1867 status = IXGBE_SUCCESS; 1868 } 1869 } 1870 1871 out: 1872 return status; 1873 1874 err_read_i2c_eeprom: 1875 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1876 hw->phy.id = 0; 1877 hw->phy.type = ixgbe_phy_unknown; 1878 1879 return IXGBE_ERR_SFP_NOT_PRESENT; 1880 } 1881 1882 1883 /** 1884 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1885 * @hw: pointer to hardware structure 1886 * @list_offset: offset to the SFP ID list 1887 * @data_offset: offset to the SFP data block 1888 * 1889 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1890 * so it returns the offsets to the phy init sequence block. 1891 **/ 1892 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1893 u16 *list_offset, 1894 u16 *data_offset) 1895 { 1896 u16 sfp_id; 1897 u16 sfp_type = hw->phy.sfp_type; 1898 1899 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1900 1901 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1902 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1903 1904 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1905 return IXGBE_ERR_SFP_NOT_PRESENT; 1906 1907 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1908 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1909 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1910 1911 /* 1912 * Limiting active cables and 1G Phys must be initialized as 1913 * SR modules 1914 */ 1915 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1916 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1917 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1918 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1919 sfp_type = ixgbe_sfp_type_srlr_core0; 1920 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1921 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1922 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1923 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1924 sfp_type = ixgbe_sfp_type_srlr_core1; 1925 1926 /* Read offset to PHY init contents */ 1927 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1928 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1929 "eeprom read at offset %d failed", 1930 IXGBE_PHY_INIT_OFFSET_NL); 1931 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1932 } 1933 1934 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1935 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1936 1937 /* Shift offset to first ID word */ 1938 (*list_offset)++; 1939 1940 /* 1941 * Find the matching SFP ID in the EEPROM 1942 * and program the init sequence 1943 */ 1944 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1945 goto err_phy; 1946 1947 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1948 if (sfp_id == sfp_type) { 1949 (*list_offset)++; 1950 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1951 goto err_phy; 1952 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1953 DEBUGOUT("SFP+ module not supported\n"); 1954 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1955 } else { 1956 break; 1957 } 1958 } else { 1959 (*list_offset) += 2; 1960 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1961 goto err_phy; 1962 } 1963 } 1964 1965 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1966 DEBUGOUT("No matching SFP+ module found\n"); 1967 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1968 } 1969 1970 return IXGBE_SUCCESS; 1971 1972 err_phy: 1973 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1974 "eeprom read at offset %d failed", *list_offset); 1975 return IXGBE_ERR_PHY; 1976 } 1977 1978 /** 1979 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1980 * @hw: pointer to hardware structure 1981 * @byte_offset: EEPROM byte offset to read 1982 * @eeprom_data: value read 1983 * 1984 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1985 **/ 1986 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1987 u8 *eeprom_data) 1988 { 1989 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1990 1991 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1992 IXGBE_I2C_EEPROM_DEV_ADDR, 1993 eeprom_data); 1994 } 1995 1996 /** 1997 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1998 * @hw: pointer to hardware structure 1999 * @byte_offset: byte offset at address 0xA2 2000 * @eeprom_data: value read 2001 * 2002 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2003 **/ 2004 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2005 u8 *sff8472_data) 2006 { 2007 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2008 IXGBE_I2C_EEPROM_DEV_ADDR2, 2009 sff8472_data); 2010 } 2011 2012 /** 2013 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2014 * @hw: pointer to hardware structure 2015 * @byte_offset: EEPROM byte offset to write 2016 * @eeprom_data: value to write 2017 * 2018 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2019 **/ 2020 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2021 u8 eeprom_data) 2022 { 2023 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2024 2025 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2026 IXGBE_I2C_EEPROM_DEV_ADDR, 2027 eeprom_data); 2028 } 2029 2030 /** 2031 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2032 * @hw: pointer to hardware structure 2033 * @offset: eeprom offset to be read 2034 * @addr: I2C address to be read 2035 */ 2036 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2037 { 2038 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2039 offset == IXGBE_SFF_IDENTIFIER && 2040 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2041 return TRUE; 2042 return FALSE; 2043 } 2044 2045 /** 2046 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2047 * @hw: pointer to hardware structure 2048 * @byte_offset: byte offset to read 2049 * @data: value read 2050 * @lock: TRUE if to take and release semaphore 2051 * 2052 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2053 * a specified device address. 2054 **/ 2055 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2056 u8 dev_addr, u8 *data, bool lock) 2057 { 2058 s32 status; 2059 u32 max_retry = 10; 2060 u32 retry = 0; 2061 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2062 bool nack = 1; 2063 *data = 0; 2064 2065 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2066 2067 if (hw->mac.type >= ixgbe_mac_X550) 2068 max_retry = 3; 2069 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2070 max_retry = IXGBE_SFP_DETECT_RETRIES; 2071 2072 do { 2073 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2074 return IXGBE_ERR_SWFW_SYNC; 2075 2076 ixgbe_i2c_start(hw); 2077 2078 /* Device Address and write indication */ 2079 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2080 if (status != IXGBE_SUCCESS) 2081 goto fail; 2082 2083 status = ixgbe_get_i2c_ack(hw); 2084 if (status != IXGBE_SUCCESS) 2085 goto fail; 2086 2087 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2088 if (status != IXGBE_SUCCESS) 2089 goto fail; 2090 2091 status = ixgbe_get_i2c_ack(hw); 2092 if (status != IXGBE_SUCCESS) 2093 goto fail; 2094 2095 ixgbe_i2c_start(hw); 2096 2097 /* Device Address and read indication */ 2098 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2099 if (status != IXGBE_SUCCESS) 2100 goto fail; 2101 2102 status = ixgbe_get_i2c_ack(hw); 2103 if (status != IXGBE_SUCCESS) 2104 goto fail; 2105 2106 status = ixgbe_clock_in_i2c_byte(hw, data); 2107 if (status != IXGBE_SUCCESS) 2108 goto fail; 2109 2110 status = ixgbe_clock_out_i2c_bit(hw, nack); 2111 if (status != IXGBE_SUCCESS) 2112 goto fail; 2113 2114 ixgbe_i2c_stop(hw); 2115 if (lock) 2116 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2117 return IXGBE_SUCCESS; 2118 2119 fail: 2120 ixgbe_i2c_bus_clear(hw); 2121 if (lock) { 2122 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2123 msec_delay(100); 2124 } 2125 retry++; 2126 if (retry < max_retry) 2127 DEBUGOUT("I2C byte read error - Retrying.\n"); 2128 else 2129 DEBUGOUT("I2C byte read error.\n"); 2130 2131 } while (retry < max_retry); 2132 2133 return status; 2134 } 2135 2136 /** 2137 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2138 * @hw: pointer to hardware structure 2139 * @byte_offset: byte offset to read 2140 * @data: value read 2141 * 2142 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2143 * a specified device address. 2144 **/ 2145 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2146 u8 dev_addr, u8 *data) 2147 { 2148 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2149 data, TRUE); 2150 } 2151 2152 /** 2153 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2154 * @hw: pointer to hardware structure 2155 * @byte_offset: byte offset to read 2156 * @data: value read 2157 * 2158 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2159 * a specified device address. 2160 **/ 2161 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2162 u8 dev_addr, u8 *data) 2163 { 2164 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2165 data, FALSE); 2166 } 2167 2168 /** 2169 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2170 * @hw: pointer to hardware structure 2171 * @byte_offset: byte offset to write 2172 * @data: value to write 2173 * @lock: TRUE if to take and release semaphore 2174 * 2175 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2176 * a specified device address. 2177 **/ 2178 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2179 u8 dev_addr, u8 data, bool lock) 2180 { 2181 s32 status; 2182 u32 max_retry = 2; 2183 u32 retry = 0; 2184 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2185 2186 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2187 2188 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2189 IXGBE_SUCCESS) 2190 return IXGBE_ERR_SWFW_SYNC; 2191 2192 do { 2193 ixgbe_i2c_start(hw); 2194 2195 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2196 if (status != IXGBE_SUCCESS) 2197 goto fail; 2198 2199 status = ixgbe_get_i2c_ack(hw); 2200 if (status != IXGBE_SUCCESS) 2201 goto fail; 2202 2203 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2204 if (status != IXGBE_SUCCESS) 2205 goto fail; 2206 2207 status = ixgbe_get_i2c_ack(hw); 2208 if (status != IXGBE_SUCCESS) 2209 goto fail; 2210 2211 status = ixgbe_clock_out_i2c_byte(hw, data); 2212 if (status != IXGBE_SUCCESS) 2213 goto fail; 2214 2215 status = ixgbe_get_i2c_ack(hw); 2216 if (status != IXGBE_SUCCESS) 2217 goto fail; 2218 2219 ixgbe_i2c_stop(hw); 2220 if (lock) 2221 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2222 return IXGBE_SUCCESS; 2223 2224 fail: 2225 ixgbe_i2c_bus_clear(hw); 2226 retry++; 2227 if (retry < max_retry) 2228 DEBUGOUT("I2C byte write error - Retrying.\n"); 2229 else 2230 DEBUGOUT("I2C byte write error.\n"); 2231 } while (retry < max_retry); 2232 2233 if (lock) 2234 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2235 2236 return status; 2237 } 2238 2239 /** 2240 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2241 * @hw: pointer to hardware structure 2242 * @byte_offset: byte offset to write 2243 * @data: value to write 2244 * 2245 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2246 * a specified device address. 2247 **/ 2248 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2249 u8 dev_addr, u8 data) 2250 { 2251 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2252 data, TRUE); 2253 } 2254 2255 /** 2256 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2257 * @hw: pointer to hardware structure 2258 * @byte_offset: byte offset to write 2259 * @data: value to write 2260 * 2261 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2262 * a specified device address. 2263 **/ 2264 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2265 u8 dev_addr, u8 data) 2266 { 2267 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2268 data, FALSE); 2269 } 2270 2271 /** 2272 * ixgbe_i2c_start - Sets I2C start condition 2273 * @hw: pointer to hardware structure 2274 * 2275 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2276 * Set bit-bang mode on X550 hardware. 2277 **/ 2278 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2279 { 2280 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2281 2282 DEBUGFUNC("ixgbe_i2c_start"); 2283 2284 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2285 2286 /* Start condition must begin with data and clock high */ 2287 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2288 ixgbe_raise_i2c_clk(hw, &i2cctl); 2289 2290 /* Setup time for start condition (4.7us) */ 2291 usec_delay(IXGBE_I2C_T_SU_STA); 2292 2293 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2294 2295 /* Hold time for start condition (4us) */ 2296 usec_delay(IXGBE_I2C_T_HD_STA); 2297 2298 ixgbe_lower_i2c_clk(hw, &i2cctl); 2299 2300 /* Minimum low period of clock is 4.7 us */ 2301 usec_delay(IXGBE_I2C_T_LOW); 2302 2303 } 2304 2305 /** 2306 * ixgbe_i2c_stop - Sets I2C stop condition 2307 * @hw: pointer to hardware structure 2308 * 2309 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2310 * Disables bit-bang mode and negates data output enable on X550 2311 * hardware. 2312 **/ 2313 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2314 { 2315 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2316 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2317 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2318 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2319 2320 DEBUGFUNC("ixgbe_i2c_stop"); 2321 2322 /* Stop condition must begin with data low and clock high */ 2323 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2324 ixgbe_raise_i2c_clk(hw, &i2cctl); 2325 2326 /* Setup time for stop condition (4us) */ 2327 usec_delay(IXGBE_I2C_T_SU_STO); 2328 2329 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2330 2331 /* bus free time between stop and start (4.7us)*/ 2332 usec_delay(IXGBE_I2C_T_BUF); 2333 2334 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2335 i2cctl &= ~bb_en_bit; 2336 i2cctl |= data_oe_bit | clk_oe_bit; 2337 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2338 IXGBE_WRITE_FLUSH(hw); 2339 } 2340 } 2341 2342 /** 2343 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2344 * @hw: pointer to hardware structure 2345 * @data: data byte to clock in 2346 * 2347 * Clocks in one byte data via I2C data/clock 2348 **/ 2349 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2350 { 2351 s32 i; 2352 bool bit = 0; 2353 2354 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2355 2356 *data = 0; 2357 for (i = 7; i >= 0; i--) { 2358 ixgbe_clock_in_i2c_bit(hw, &bit); 2359 *data |= bit << i; 2360 } 2361 2362 return IXGBE_SUCCESS; 2363 } 2364 2365 /** 2366 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2367 * @hw: pointer to hardware structure 2368 * @data: data byte clocked out 2369 * 2370 * Clocks out one byte data via I2C data/clock 2371 **/ 2372 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2373 { 2374 s32 status = IXGBE_SUCCESS; 2375 s32 i; 2376 u32 i2cctl; 2377 bool bit; 2378 2379 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2380 2381 for (i = 7; i >= 0; i--) { 2382 bit = (data >> i) & 0x1; 2383 status = ixgbe_clock_out_i2c_bit(hw, bit); 2384 2385 if (status != IXGBE_SUCCESS) 2386 break; 2387 } 2388 2389 /* Release SDA line (set high) */ 2390 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2391 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2392 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2393 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2394 IXGBE_WRITE_FLUSH(hw); 2395 2396 return status; 2397 } 2398 2399 /** 2400 * ixgbe_get_i2c_ack - Polls for I2C ACK 2401 * @hw: pointer to hardware structure 2402 * 2403 * Clocks in/out one bit via I2C data/clock 2404 **/ 2405 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2406 { 2407 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2408 s32 status = IXGBE_SUCCESS; 2409 u32 i = 0; 2410 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2411 u32 timeout = 10; 2412 bool ack = 1; 2413 2414 DEBUGFUNC("ixgbe_get_i2c_ack"); 2415 2416 if (data_oe_bit) { 2417 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2418 i2cctl |= data_oe_bit; 2419 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2420 IXGBE_WRITE_FLUSH(hw); 2421 } 2422 ixgbe_raise_i2c_clk(hw, &i2cctl); 2423 2424 /* Minimum high period of clock is 4us */ 2425 usec_delay(IXGBE_I2C_T_HIGH); 2426 2427 /* Poll for ACK. Note that ACK in I2C spec is 2428 * transition from 1 to 0 */ 2429 for (i = 0; i < timeout; i++) { 2430 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2431 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2432 2433 usec_delay(1); 2434 if (!ack) 2435 break; 2436 } 2437 2438 if (ack) { 2439 DEBUGOUT("I2C ack was not received.\n"); 2440 status = IXGBE_ERR_I2C; 2441 } 2442 2443 ixgbe_lower_i2c_clk(hw, &i2cctl); 2444 2445 /* Minimum low period of clock is 4.7 us */ 2446 usec_delay(IXGBE_I2C_T_LOW); 2447 2448 return status; 2449 } 2450 2451 /** 2452 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2453 * @hw: pointer to hardware structure 2454 * @data: read data value 2455 * 2456 * Clocks in one bit via I2C data/clock 2457 **/ 2458 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2459 { 2460 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2461 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2462 2463 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2464 2465 if (data_oe_bit) { 2466 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2467 i2cctl |= data_oe_bit; 2468 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2469 IXGBE_WRITE_FLUSH(hw); 2470 } 2471 ixgbe_raise_i2c_clk(hw, &i2cctl); 2472 2473 /* Minimum high period of clock is 4us */ 2474 usec_delay(IXGBE_I2C_T_HIGH); 2475 2476 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2477 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2478 2479 ixgbe_lower_i2c_clk(hw, &i2cctl); 2480 2481 /* Minimum low period of clock is 4.7 us */ 2482 usec_delay(IXGBE_I2C_T_LOW); 2483 2484 return IXGBE_SUCCESS; 2485 } 2486 2487 /** 2488 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2489 * @hw: pointer to hardware structure 2490 * @data: data value to write 2491 * 2492 * Clocks out one bit via I2C data/clock 2493 **/ 2494 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2495 { 2496 s32 status; 2497 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2498 2499 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2500 2501 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2502 if (status == IXGBE_SUCCESS) { 2503 ixgbe_raise_i2c_clk(hw, &i2cctl); 2504 2505 /* Minimum high period of clock is 4us */ 2506 usec_delay(IXGBE_I2C_T_HIGH); 2507 2508 ixgbe_lower_i2c_clk(hw, &i2cctl); 2509 2510 /* Minimum low period of clock is 4.7 us. 2511 * This also takes care of the data hold time. 2512 */ 2513 usec_delay(IXGBE_I2C_T_LOW); 2514 } else { 2515 status = IXGBE_ERR_I2C; 2516 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2517 "I2C data was not set to %X\n", data); 2518 } 2519 2520 return status; 2521 } 2522 2523 /** 2524 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2525 * @hw: pointer to hardware structure 2526 * @i2cctl: Current value of I2CCTL register 2527 * 2528 * Raises the I2C clock line '0'->'1' 2529 * Negates the I2C clock output enable on X550 hardware. 2530 **/ 2531 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2532 { 2533 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2534 u32 i = 0; 2535 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2536 u32 i2cctl_r = 0; 2537 2538 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2539 2540 if (clk_oe_bit) { 2541 *i2cctl |= clk_oe_bit; 2542 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2543 } 2544 2545 for (i = 0; i < timeout; i++) { 2546 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2547 2548 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2549 IXGBE_WRITE_FLUSH(hw); 2550 /* SCL rise time (1000ns) */ 2551 usec_delay(IXGBE_I2C_T_RISE); 2552 2553 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2554 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2555 break; 2556 } 2557 } 2558 2559 /** 2560 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2561 * @hw: pointer to hardware structure 2562 * @i2cctl: Current value of I2CCTL register 2563 * 2564 * Lowers the I2C clock line '1'->'0' 2565 * Asserts the I2C clock output enable on X550 hardware. 2566 **/ 2567 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2568 { 2569 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2570 2571 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2572 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2573 2574 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2575 IXGBE_WRITE_FLUSH(hw); 2576 2577 /* SCL fall time (300ns) */ 2578 usec_delay(IXGBE_I2C_T_FALL); 2579 } 2580 2581 /** 2582 * ixgbe_set_i2c_data - Sets the I2C data bit 2583 * @hw: pointer to hardware structure 2584 * @i2cctl: Current value of I2CCTL register 2585 * @data: I2C data value (0 or 1) to set 2586 * 2587 * Sets the I2C data bit 2588 * Asserts the I2C data output enable on X550 hardware. 2589 **/ 2590 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2591 { 2592 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2593 s32 status = IXGBE_SUCCESS; 2594 2595 DEBUGFUNC("ixgbe_set_i2c_data"); 2596 2597 if (data) 2598 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2599 else 2600 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2601 *i2cctl &= ~data_oe_bit; 2602 2603 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2604 IXGBE_WRITE_FLUSH(hw); 2605 2606 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2607 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2608 2609 if (!data) /* Can't verify data in this case */ 2610 return IXGBE_SUCCESS; 2611 if (data_oe_bit) { 2612 *i2cctl |= data_oe_bit; 2613 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2614 IXGBE_WRITE_FLUSH(hw); 2615 } 2616 2617 /* Verify data was set correctly */ 2618 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2619 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2620 status = IXGBE_ERR_I2C; 2621 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2622 "Error - I2C data was not set to %X.\n", 2623 data); 2624 } 2625 2626 return status; 2627 } 2628 2629 /** 2630 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2631 * @hw: pointer to hardware structure 2632 * @i2cctl: Current value of I2CCTL register 2633 * 2634 * Returns the I2C data bit value 2635 * Negates the I2C data output enable on X550 hardware. 2636 **/ 2637 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2638 { 2639 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2640 bool data; 2641 2642 DEBUGFUNC("ixgbe_get_i2c_data"); 2643 2644 if (data_oe_bit) { 2645 *i2cctl |= data_oe_bit; 2646 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2647 IXGBE_WRITE_FLUSH(hw); 2648 usec_delay(IXGBE_I2C_T_FALL); 2649 } 2650 2651 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2652 data = 1; 2653 else 2654 data = 0; 2655 2656 return data; 2657 } 2658 2659 /** 2660 * ixgbe_i2c_bus_clear - Clears the I2C bus 2661 * @hw: pointer to hardware structure 2662 * 2663 * Clears the I2C bus by sending nine clock pulses. 2664 * Used when data line is stuck low. 2665 **/ 2666 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2667 { 2668 u32 i2cctl; 2669 u32 i; 2670 2671 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2672 2673 ixgbe_i2c_start(hw); 2674 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2675 2676 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2677 2678 for (i = 0; i < 9; i++) { 2679 ixgbe_raise_i2c_clk(hw, &i2cctl); 2680 2681 /* Min high period of clock is 4us */ 2682 usec_delay(IXGBE_I2C_T_HIGH); 2683 2684 ixgbe_lower_i2c_clk(hw, &i2cctl); 2685 2686 /* Min low period of clock is 4.7us*/ 2687 usec_delay(IXGBE_I2C_T_LOW); 2688 } 2689 2690 ixgbe_i2c_start(hw); 2691 2692 /* Put the i2c bus back to default state */ 2693 ixgbe_i2c_stop(hw); 2694 } 2695 2696 /** 2697 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2698 * @hw: pointer to hardware structure 2699 * 2700 * Checks if the LASI temp alarm status was triggered due to overtemp 2701 **/ 2702 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2703 { 2704 s32 status = IXGBE_SUCCESS; 2705 u16 phy_data = 0; 2706 2707 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2708 2709 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2710 goto out; 2711 2712 /* Check that the LASI temp alarm status was triggered */ 2713 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2714 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2715 2716 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2717 goto out; 2718 2719 status = IXGBE_ERR_OVERTEMP; 2720 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2721 out: 2722 return status; 2723 } 2724 2725 /** 2726 * ixgbe_set_copper_phy_power - Control power for copper phy 2727 * @hw: pointer to hardware structure 2728 * @on: TRUE for on, FALSE for off 2729 */ 2730 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2731 { 2732 u32 status; 2733 u16 reg; 2734 2735 if (!on && ixgbe_mng_present(hw)) 2736 return 0; 2737 2738 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2739 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2740 ®); 2741 if (status) 2742 return status; 2743 2744 if (on) { 2745 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2746 } else { 2747 if (ixgbe_check_reset_blocked(hw)) 2748 return 0; 2749 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2750 } 2751 2752 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2753 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2754 reg); 2755 return status; 2756 } 2757
Indexes created Wed Oct 15 07:09:58 GMT 2025