ixgbe_phy.c revision 1.7
1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 280182 2015-03-17 18:32:28Z jfv $*/ 34 /*$NetBSD: ixgbe_phy.c,v 1.7 2016/12/01 06:27:18 msaitoh Exp $*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 52 u8 *sff8472_data); 53 54 /** 55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 56 * @hw: pointer to the hardware structure 57 * @byte: byte to send 58 * 59 * Returns an error code on error. 60 */ 61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 62 { 63 s32 status; 64 65 status = ixgbe_clock_out_i2c_byte(hw, byte); 66 if (status) 67 return status; 68 return ixgbe_get_i2c_ack(hw); 69 } 70 71 /** 72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 73 * @hw: pointer to the hardware structure 74 * @byte: pointer to a u8 to receive the byte 75 * 76 * Returns an error code on error. 77 */ 78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 79 { 80 s32 status; 81 82 status = ixgbe_clock_in_i2c_byte(hw, byte); 83 if (status) 84 return status; 85 /* ACK */ 86 return ixgbe_clock_out_i2c_bit(hw, FALSE); 87 } 88 89 /** 90 * ixgbe_ones_comp_byte_add - Perform one's complement addition 91 * @add1 - addend 1 92 * @add2 - addend 2 93 * 94 * Returns one's complement 8-bit sum. 95 */ 96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 97 { 98 u16 sum = add1 + add2; 99 100 sum = (sum & 0xFF) + (sum >> 8); 101 return sum & 0xFF; 102 } 103 104 /** 105 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 106 * @hw: pointer to the hardware structure 107 * @addr: I2C bus address to read from 108 * @reg: I2C device register to read from 109 * @val: pointer to location to receive read value 110 * 111 * Returns an error code on error. 112 */ 113 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 114 u16 reg, u16 *val) 115 { 116 u32 swfw_mask = hw->phy.phy_semaphore_mask; 117 int max_retry = 10; 118 int retry = 0; 119 u8 csum_byte; 120 u8 high_bits; 121 u8 low_bits; 122 u8 reg_high; 123 u8 csum; 124 125 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 126 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 127 csum = ~csum; 128 do { 129 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 130 return IXGBE_ERR_SWFW_SYNC; 131 ixgbe_i2c_start(hw); 132 /* Device Address and write indication */ 133 if (ixgbe_out_i2c_byte_ack(hw, addr)) 134 goto fail; 135 /* Write bits 14:8 */ 136 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 137 goto fail; 138 /* Write bits 7:0 */ 139 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 140 goto fail; 141 /* Write csum */ 142 if (ixgbe_out_i2c_byte_ack(hw, csum)) 143 goto fail; 144 /* Re-start condition */ 145 ixgbe_i2c_start(hw); 146 /* Device Address and read indication */ 147 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 148 goto fail; 149 /* Get upper bits */ 150 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 151 goto fail; 152 /* Get low bits */ 153 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 154 goto fail; 155 /* Get csum */ 156 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 157 goto fail; 158 /* NACK */ 159 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 160 goto fail; 161 ixgbe_i2c_stop(hw); 162 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 163 *val = (high_bits << 8) | low_bits; 164 return 0; 165 166 fail: 167 ixgbe_i2c_bus_clear(hw); 168 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 169 retry++; 170 if (retry < max_retry) 171 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 172 else 173 DEBUGOUT("I2C byte read combined error.\n"); 174 } while (retry < max_retry); 175 176 return IXGBE_ERR_I2C; 177 } 178 179 /** 180 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 181 * @hw: pointer to the hardware structure 182 * @addr: I2C bus address to write to 183 * @reg: I2C device register to write to 184 * @val: value to write 185 * 186 * Returns an error code on error. 187 */ 188 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 189 u8 addr, u16 reg, u16 val) 190 { 191 int max_retry = 1; 192 int retry = 0; 193 u8 reg_high; 194 u8 csum; 195 196 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 197 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 198 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 199 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 200 csum = ~csum; 201 do { 202 ixgbe_i2c_start(hw); 203 /* Device Address and write indication */ 204 if (ixgbe_out_i2c_byte_ack(hw, addr)) 205 goto fail; 206 /* Write bits 14:8 */ 207 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 208 goto fail; 209 /* Write bits 7:0 */ 210 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 211 goto fail; 212 /* Write data 15:8 */ 213 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 214 goto fail; 215 /* Write data 7:0 */ 216 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 217 goto fail; 218 /* Write csum */ 219 if (ixgbe_out_i2c_byte_ack(hw, csum)) 220 goto fail; 221 ixgbe_i2c_stop(hw); 222 return 0; 223 224 fail: 225 ixgbe_i2c_bus_clear(hw); 226 retry++; 227 if (retry < max_retry) 228 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 229 else 230 DEBUGOUT("I2C byte write combined error.\n"); 231 } while (retry < max_retry); 232 233 return IXGBE_ERR_I2C; 234 } 235 236 /** 237 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 238 * @hw: pointer to the hardware structure 239 * 240 * Initialize the function pointers. 241 **/ 242 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 243 { 244 struct ixgbe_phy_info *phy = &hw->phy; 245 246 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 247 248 /* PHY */ 249 phy->ops.identify = ixgbe_identify_phy_generic; 250 phy->ops.reset = ixgbe_reset_phy_generic; 251 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 252 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 253 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 254 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 255 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 256 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 257 phy->ops.check_link = NULL; 258 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 259 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 260 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 261 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 262 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 263 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 264 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 265 phy->ops.identify_sfp = ixgbe_identify_module_generic; 266 phy->sfp_type = ixgbe_sfp_type_unknown; 267 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic; 268 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic; 269 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 270 return IXGBE_SUCCESS; 271 } 272 273 /** 274 * ixgbe_identify_phy_generic - Get physical layer module 275 * @hw: pointer to hardware structure 276 * 277 * Determines the physical layer module found on the current adapter. 278 **/ 279 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 280 { 281 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 282 u32 phy_addr; 283 u16 ext_ability = 0; 284 285 DEBUGFUNC("ixgbe_identify_phy_generic"); 286 287 if (!hw->phy.phy_semaphore_mask) { 288 if (hw->bus.lan_id) 289 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 290 else 291 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 292 } 293 294 if (hw->phy.type == ixgbe_phy_unknown) { 295 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 296 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 297 hw->phy.addr = phy_addr; 298 ixgbe_get_phy_id(hw); 299 hw->phy.type = 300 ixgbe_get_phy_type_from_id(hw->phy.id); 301 302 if (hw->phy.type == ixgbe_phy_unknown) { 303 hw->phy.ops.read_reg(hw, 304 IXGBE_MDIO_PHY_EXT_ABILITY, 305 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 306 &ext_ability); 307 if (ext_ability & 308 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 309 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 310 hw->phy.type = 311 ixgbe_phy_cu_unknown; 312 else 313 hw->phy.type = 314 ixgbe_phy_generic; 315 } 316 317 status = IXGBE_SUCCESS; 318 break; 319 } 320 } 321 322 /* Certain media types do not have a phy so an address will not 323 * be found and the code will take this path. Caller has to 324 * decide if it is an error or not. 325 */ 326 if (status != IXGBE_SUCCESS) { 327 hw->phy.addr = 0; 328 } 329 } else { 330 status = IXGBE_SUCCESS; 331 } 332 333 return status; 334 } 335 336 /** 337 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 338 * @hw: pointer to the hardware structure 339 * 340 * This function checks the MMNGC.MNG_VETO bit to see if there are 341 * any constraints on link from manageability. For MAC's that don't 342 * have this bit just return faluse since the link can not be blocked 343 * via this method. 344 **/ 345 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 346 { 347 u32 mmngc; 348 349 DEBUGFUNC("ixgbe_check_reset_blocked"); 350 351 /* If we don't have this bit, it can't be blocking */ 352 if (hw->mac.type == ixgbe_mac_82598EB) 353 return FALSE; 354 355 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 356 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 357 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 358 "MNG_VETO bit detected.\n"); 359 return TRUE; 360 } 361 362 return FALSE; 363 } 364 365 /** 366 * ixgbe_validate_phy_addr - Determines phy address is valid 367 * @hw: pointer to hardware structure 368 * 369 **/ 370 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 371 { 372 u16 phy_id = 0; 373 bool valid = FALSE; 374 375 DEBUGFUNC("ixgbe_validate_phy_addr"); 376 377 hw->phy.addr = phy_addr; 378 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 379 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 380 381 if (phy_id != 0xFFFF && phy_id != 0x0) 382 valid = TRUE; 383 384 return valid; 385 } 386 387 /** 388 * ixgbe_get_phy_id - Get the phy type 389 * @hw: pointer to hardware structure 390 * 391 **/ 392 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 393 { 394 u32 status; 395 u16 phy_id_high = 0; 396 u16 phy_id_low = 0; 397 398 DEBUGFUNC("ixgbe_get_phy_id"); 399 400 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 401 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 402 &phy_id_high); 403 404 if (status == IXGBE_SUCCESS) { 405 hw->phy.id = (u32)(phy_id_high << 16); 406 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 407 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 408 &phy_id_low); 409 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 410 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 411 } 412 return status; 413 } 414 415 /** 416 * ixgbe_get_phy_type_from_id - Get the phy type 417 * @hw: pointer to hardware structure 418 * 419 **/ 420 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 421 { 422 enum ixgbe_phy_type phy_type; 423 424 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 425 426 switch (phy_id) { 427 case TN1010_PHY_ID: 428 phy_type = ixgbe_phy_tn; 429 break; 430 case X550_PHY_ID: 431 case X540_PHY_ID: 432 phy_type = ixgbe_phy_aq; 433 break; 434 case QT2022_PHY_ID: 435 phy_type = ixgbe_phy_qt; 436 break; 437 case ATH_PHY_ID: 438 phy_type = ixgbe_phy_nl; 439 break; 440 case X557_PHY_ID: 441 phy_type = ixgbe_phy_x550em_ext_t; 442 break; 443 default: 444 phy_type = ixgbe_phy_unknown; 445 break; 446 } 447 448 DEBUGOUT1("phy type found is %d\n", phy_type); 449 return phy_type; 450 } 451 452 /** 453 * ixgbe_reset_phy_generic - Performs a PHY reset 454 * @hw: pointer to hardware structure 455 **/ 456 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 457 { 458 u32 i; 459 u16 ctrl = 0; 460 s32 status = IXGBE_SUCCESS; 461 462 DEBUGFUNC("ixgbe_reset_phy_generic"); 463 464 if (hw->phy.type == ixgbe_phy_unknown) 465 status = ixgbe_identify_phy_generic(hw); 466 467 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 468 goto out; 469 470 /* Don't reset PHY if it's shut down due to overtemp. */ 471 if (!hw->phy.reset_if_overtemp && 472 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 473 goto out; 474 475 /* Blocked by MNG FW so bail */ 476 if (ixgbe_check_reset_blocked(hw)) 477 goto out; 478 479 /* 480 * Perform soft PHY reset to the PHY_XS. 481 * This will cause a soft reset to the PHY 482 */ 483 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 484 IXGBE_MDIO_PHY_XS_DEV_TYPE, 485 IXGBE_MDIO_PHY_XS_RESET); 486 487 /* 488 * Poll for reset bit to self-clear indicating reset is complete. 489 * Some PHYs could take up to 3 seconds to complete and need about 490 * 1.7 usec delay after the reset is complete. 491 */ 492 for (i = 0; i < 30; i++) { 493 msec_delay(100); 494 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 495 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 496 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 497 usec_delay(2); 498 break; 499 } 500 } 501 502 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 503 status = IXGBE_ERR_RESET_FAILED; 504 ERROR_REPORT1(IXGBE_ERROR_POLLING, 505 "PHY reset polling failed to complete.\n"); 506 } 507 508 out: 509 return status; 510 } 511 512 /** 513 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 514 * the SWFW lock 515 * @hw: pointer to hardware structure 516 * @reg_addr: 32 bit address of PHY register to read 517 * @phy_data: Pointer to read data from PHY register 518 **/ 519 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 520 u16 *phy_data) 521 { 522 u32 i, data, command; 523 524 /* Setup and write the address cycle command */ 525 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 526 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 527 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 528 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 529 530 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 531 532 /* 533 * Check every 10 usec to see if the address cycle completed. 534 * The MDI Command bit will clear when the operation is 535 * complete 536 */ 537 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 538 usec_delay(10); 539 540 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 541 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 542 break; 543 } 544 545 546 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 547 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 548 return IXGBE_ERR_PHY; 549 } 550 551 /* 552 * Address cycle complete, setup and write the read 553 * command 554 */ 555 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 556 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 557 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 558 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 559 560 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 561 562 /* 563 * Check every 10 usec to see if the address cycle 564 * completed. The MDI Command bit will clear when the 565 * operation is complete 566 */ 567 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 568 usec_delay(10); 569 570 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 571 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 572 break; 573 } 574 575 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 576 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 577 return IXGBE_ERR_PHY; 578 } 579 580 /* 581 * Read operation is complete. Get the data 582 * from MSRWD 583 */ 584 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 585 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 586 *phy_data = (u16)(data); 587 588 return IXGBE_SUCCESS; 589 } 590 591 /** 592 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 593 * using the SWFW lock - this function is needed in most cases 594 * @hw: pointer to hardware structure 595 * @reg_addr: 32 bit address of PHY register to read 596 * @phy_data: Pointer to read data from PHY register 597 **/ 598 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 599 u32 device_type, u16 *phy_data) 600 { 601 s32 status; 602 u32 gssr = hw->phy.phy_semaphore_mask; 603 604 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 605 606 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 607 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 608 phy_data); 609 hw->mac.ops.release_swfw_sync(hw, gssr); 610 } else { 611 status = IXGBE_ERR_SWFW_SYNC; 612 } 613 614 return status; 615 } 616 617 /** 618 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 619 * without SWFW lock 620 * @hw: pointer to hardware structure 621 * @reg_addr: 32 bit PHY register to write 622 * @device_type: 5 bit device type 623 * @phy_data: Data to write to the PHY register 624 **/ 625 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 626 u32 device_type, u16 phy_data) 627 { 628 u32 i, command; 629 630 /* Put the data in the MDI single read and write data register*/ 631 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 632 633 /* Setup and write the address cycle command */ 634 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 635 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 636 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 637 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 638 639 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 640 641 /* 642 * Check every 10 usec to see if the address cycle completed. 643 * The MDI Command bit will clear when the operation is 644 * complete 645 */ 646 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 647 usec_delay(10); 648 649 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 650 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 651 break; 652 } 653 654 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 655 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 656 return IXGBE_ERR_PHY; 657 } 658 659 /* 660 * Address cycle complete, setup and write the write 661 * command 662 */ 663 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 664 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 665 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 666 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 667 668 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 669 670 /* 671 * Check every 10 usec to see if the address cycle 672 * completed. The MDI Command bit will clear when the 673 * operation is complete 674 */ 675 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 676 usec_delay(10); 677 678 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 679 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 680 break; 681 } 682 683 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 684 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 685 return IXGBE_ERR_PHY; 686 } 687 688 return IXGBE_SUCCESS; 689 } 690 691 /** 692 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 693 * using SWFW lock- this function is needed in most cases 694 * @hw: pointer to hardware structure 695 * @reg_addr: 32 bit PHY register to write 696 * @device_type: 5 bit device type 697 * @phy_data: Data to write to the PHY register 698 **/ 699 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 700 u32 device_type, u16 phy_data) 701 { 702 s32 status; 703 u32 gssr = hw->phy.phy_semaphore_mask; 704 705 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 706 707 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 708 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 709 phy_data); 710 hw->mac.ops.release_swfw_sync(hw, gssr); 711 } else { 712 status = IXGBE_ERR_SWFW_SYNC; 713 } 714 715 return status; 716 } 717 718 /** 719 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 720 * @hw: pointer to hardware structure 721 * 722 * Restart auto-negotiation and PHY and waits for completion. 723 **/ 724 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 725 { 726 s32 status = IXGBE_SUCCESS; 727 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 728 bool autoneg = FALSE; 729 ixgbe_link_speed speed; 730 731 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 732 733 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 734 735 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 736 /* Set or unset auto-negotiation 10G advertisement */ 737 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 738 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 739 &autoneg_reg); 740 741 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 742 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 743 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 744 745 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 746 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 747 autoneg_reg); 748 } 749 750 if (hw->mac.type == ixgbe_mac_X550) { 751 if (speed & IXGBE_LINK_SPEED_5GB_FULL) { 752 /* Set or unset auto-negotiation 1G advertisement */ 753 hw->phy.ops.read_reg(hw, 754 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 756 &autoneg_reg); 757 758 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 759 if (hw->phy.autoneg_advertised & 760 IXGBE_LINK_SPEED_5GB_FULL) 761 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 762 763 hw->phy.ops.write_reg(hw, 764 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 765 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 766 autoneg_reg); 767 } 768 769 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) { 770 /* Set or unset auto-negotiation 1G advertisement */ 771 hw->phy.ops.read_reg(hw, 772 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 773 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 774 &autoneg_reg); 775 776 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 777 if (hw->phy.autoneg_advertised & 778 IXGBE_LINK_SPEED_2_5GB_FULL) 779 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 780 781 hw->phy.ops.write_reg(hw, 782 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 783 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 784 autoneg_reg); 785 } 786 } 787 788 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 789 /* Set or unset auto-negotiation 1G advertisement */ 790 hw->phy.ops.read_reg(hw, 791 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 792 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 793 &autoneg_reg); 794 795 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 796 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 797 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 798 799 hw->phy.ops.write_reg(hw, 800 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 801 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 802 autoneg_reg); 803 } 804 805 if (speed & IXGBE_LINK_SPEED_100_FULL) { 806 /* Set or unset auto-negotiation 100M advertisement */ 807 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 808 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 809 &autoneg_reg); 810 811 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 812 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 813 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 814 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 815 816 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 817 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 818 autoneg_reg); 819 } 820 821 /* Blocked by MNG FW so don't reset PHY */ 822 if (ixgbe_check_reset_blocked(hw)) 823 return status; 824 825 /* Restart PHY auto-negotiation. */ 826 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 827 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 828 829 autoneg_reg |= IXGBE_MII_RESTART; 830 831 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 832 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 833 834 return status; 835 } 836 837 /** 838 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 839 * @hw: pointer to hardware structure 840 * @speed: new link speed 841 **/ 842 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 843 ixgbe_link_speed speed, 844 bool autoneg_wait_to_complete) 845 { 846 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 847 848 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 849 850 /* 851 * Clear autoneg_advertised and set new values based on input link 852 * speed. 853 */ 854 hw->phy.autoneg_advertised = 0; 855 856 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 857 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 858 859 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 860 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 861 862 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 863 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 864 865 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 866 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 867 868 if (speed & IXGBE_LINK_SPEED_100_FULL) 869 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 870 871 /* Setup link based on the new speed settings */ 872 hw->phy.ops.setup_link(hw); 873 874 return IXGBE_SUCCESS; 875 } 876 877 /** 878 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 879 * @hw: pointer to hardware structure 880 * @speed: pointer to link speed 881 * @autoneg: boolean auto-negotiation value 882 * 883 * Determines the supported link capabilities by reading the PHY auto 884 * negotiation register. 885 **/ 886 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 887 ixgbe_link_speed *speed, 888 bool *autoneg) 889 { 890 s32 status; 891 u16 speed_ability; 892 893 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 894 895 *speed = 0; 896 *autoneg = TRUE; 897 898 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 899 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 900 &speed_ability); 901 902 if (status == IXGBE_SUCCESS) { 903 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 904 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 905 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 906 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 907 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 908 *speed |= IXGBE_LINK_SPEED_100_FULL; 909 } 910 911 /* Internal PHY does not support 100 Mbps */ 912 if (hw->mac.type == ixgbe_mac_X550EM_x) 913 *speed &= ~IXGBE_LINK_SPEED_100_FULL; 914 915 if (hw->mac.type == ixgbe_mac_X550) { 916 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 917 *speed |= IXGBE_LINK_SPEED_5GB_FULL; 918 } 919 920 return status; 921 } 922 923 /** 924 * ixgbe_check_phy_link_tnx - Determine link and speed status 925 * @hw: pointer to hardware structure 926 * 927 * Reads the VS1 register to determine if link is up and the current speed for 928 * the PHY. 929 **/ 930 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 931 bool *link_up) 932 { 933 s32 status = IXGBE_SUCCESS; 934 u32 time_out; 935 u32 max_time_out = 10; 936 u16 phy_link = 0; 937 u16 phy_speed = 0; 938 u16 phy_data = 0; 939 940 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 941 942 /* Initialize speed and link to default case */ 943 *link_up = FALSE; 944 *speed = IXGBE_LINK_SPEED_10GB_FULL; 945 946 /* 947 * Check current speed and link status of the PHY register. 948 * This is a vendor specific register and may have to 949 * be changed for other copper PHYs. 950 */ 951 for (time_out = 0; time_out < max_time_out; time_out++) { 952 usec_delay(10); 953 status = hw->phy.ops.read_reg(hw, 954 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 955 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 956 &phy_data); 957 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 958 phy_speed = phy_data & 959 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 960 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 961 *link_up = TRUE; 962 if (phy_speed == 963 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 964 *speed = IXGBE_LINK_SPEED_1GB_FULL; 965 break; 966 } 967 } 968 969 return status; 970 } 971 972 /** 973 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 974 * @hw: pointer to hardware structure 975 * 976 * Restart auto-negotiation and PHY and waits for completion. 977 **/ 978 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 979 { 980 s32 status = IXGBE_SUCCESS; 981 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 982 bool autoneg = FALSE; 983 ixgbe_link_speed speed; 984 985 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 986 987 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 988 989 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 990 /* Set or unset auto-negotiation 10G advertisement */ 991 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 992 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 993 &autoneg_reg); 994 995 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 996 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 997 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 998 999 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1000 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1001 autoneg_reg); 1002 } 1003 1004 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1005 /* Set or unset auto-negotiation 1G advertisement */ 1006 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1007 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1008 &autoneg_reg); 1009 1010 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1011 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1012 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1013 1014 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1015 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1016 autoneg_reg); 1017 } 1018 1019 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1020 /* Set or unset auto-negotiation 100M advertisement */ 1021 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1022 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1023 &autoneg_reg); 1024 1025 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1026 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1027 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1028 1029 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1030 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1031 autoneg_reg); 1032 } 1033 1034 /* Blocked by MNG FW so don't reset PHY */ 1035 if (ixgbe_check_reset_blocked(hw)) 1036 return status; 1037 1038 /* Restart PHY auto-negotiation. */ 1039 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1040 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1041 1042 autoneg_reg |= IXGBE_MII_RESTART; 1043 1044 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1045 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1046 1047 return status; 1048 } 1049 1050 /** 1051 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1052 * @hw: pointer to hardware structure 1053 * @firmware_version: pointer to the PHY Firmware Version 1054 **/ 1055 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1056 u16 *firmware_version) 1057 { 1058 s32 status; 1059 1060 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1061 1062 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1063 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1064 firmware_version); 1065 1066 return status; 1067 } 1068 1069 /** 1070 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1071 * @hw: pointer to hardware structure 1072 * @firmware_version: pointer to the PHY Firmware Version 1073 **/ 1074 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1075 u16 *firmware_version) 1076 { 1077 s32 status; 1078 1079 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1080 1081 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1082 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1083 firmware_version); 1084 1085 return status; 1086 } 1087 1088 /** 1089 * ixgbe_reset_phy_nl - Performs a PHY reset 1090 * @hw: pointer to hardware structure 1091 **/ 1092 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1093 { 1094 u16 phy_offset, control, eword, edata, block_crc; 1095 bool end_data = FALSE; 1096 u16 list_offset, data_offset; 1097 u16 phy_data = 0; 1098 s32 ret_val = IXGBE_SUCCESS; 1099 u32 i; 1100 1101 DEBUGFUNC("ixgbe_reset_phy_nl"); 1102 1103 /* Blocked by MNG FW so bail */ 1104 if (ixgbe_check_reset_blocked(hw)) 1105 goto out; 1106 1107 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1108 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1109 1110 /* reset the PHY and poll for completion */ 1111 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1112 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1113 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1114 1115 for (i = 0; i < 100; i++) { 1116 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1117 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1118 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1119 break; 1120 msec_delay(10); 1121 } 1122 1123 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1124 DEBUGOUT("PHY reset did not complete.\n"); 1125 ret_val = IXGBE_ERR_PHY; 1126 goto out; 1127 } 1128 1129 /* Get init offsets */ 1130 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1131 &data_offset); 1132 if (ret_val != IXGBE_SUCCESS) 1133 goto out; 1134 1135 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1136 data_offset++; 1137 while (!end_data) { 1138 /* 1139 * Read control word from PHY init contents offset 1140 */ 1141 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1142 if (ret_val) 1143 goto err_eeprom; 1144 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1145 IXGBE_CONTROL_SHIFT_NL; 1146 edata = eword & IXGBE_DATA_MASK_NL; 1147 switch (control) { 1148 case IXGBE_DELAY_NL: 1149 data_offset++; 1150 DEBUGOUT1("DELAY: %d MS\n", edata); 1151 msec_delay(edata); 1152 break; 1153 case IXGBE_DATA_NL: 1154 DEBUGOUT("DATA:\n"); 1155 data_offset++; 1156 ret_val = hw->eeprom.ops.read(hw, data_offset, 1157 &phy_offset); 1158 if (ret_val) 1159 goto err_eeprom; 1160 data_offset++; 1161 for (i = 0; i < edata; i++) { 1162 ret_val = hw->eeprom.ops.read(hw, data_offset, 1163 &eword); 1164 if (ret_val) 1165 goto err_eeprom; 1166 hw->phy.ops.write_reg(hw, phy_offset, 1167 IXGBE_TWINAX_DEV, eword); 1168 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1169 phy_offset); 1170 data_offset++; 1171 phy_offset++; 1172 } 1173 break; 1174 case IXGBE_CONTROL_NL: 1175 data_offset++; 1176 DEBUGOUT("CONTROL:\n"); 1177 if (edata == IXGBE_CONTROL_EOL_NL) { 1178 DEBUGOUT("EOL\n"); 1179 end_data = TRUE; 1180 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1181 DEBUGOUT("SOL\n"); 1182 } else { 1183 DEBUGOUT("Bad control value\n"); 1184 ret_val = IXGBE_ERR_PHY; 1185 goto out; 1186 } 1187 break; 1188 default: 1189 DEBUGOUT("Bad control type\n"); 1190 ret_val = IXGBE_ERR_PHY; 1191 goto out; 1192 } 1193 } 1194 1195 out: 1196 return ret_val; 1197 1198 err_eeprom: 1199 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1200 "eeprom read at offset %d failed", data_offset); 1201 return IXGBE_ERR_PHY; 1202 } 1203 1204 /** 1205 * ixgbe_identify_module_generic - Identifies module type 1206 * @hw: pointer to hardware structure 1207 * 1208 * Determines HW type and calls appropriate function. 1209 **/ 1210 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1211 { 1212 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1213 1214 DEBUGFUNC("ixgbe_identify_module_generic"); 1215 1216 switch (hw->mac.ops.get_media_type(hw)) { 1217 case ixgbe_media_type_fiber: 1218 status = ixgbe_identify_sfp_module_generic(hw); 1219 break; 1220 1221 case ixgbe_media_type_fiber_qsfp: 1222 status = ixgbe_identify_qsfp_module_generic(hw); 1223 break; 1224 1225 default: 1226 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1227 status = IXGBE_ERR_SFP_NOT_PRESENT; 1228 break; 1229 } 1230 1231 return status; 1232 } 1233 1234 /** 1235 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1236 * @hw: pointer to hardware structure 1237 * 1238 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1239 **/ 1240 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1241 { 1242 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1243 u32 vendor_oui = 0; 1244 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1245 u8 identifier = 0; 1246 u8 comp_codes_1g = 0; 1247 u8 comp_codes_10g = 0; 1248 u8 oui_bytes[3] = {0, 0, 0}; 1249 u8 cable_tech = 0; 1250 u8 cable_spec = 0; 1251 u16 enforce_sfp = 0; 1252 1253 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1254 1255 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1256 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1257 status = IXGBE_ERR_SFP_NOT_PRESENT; 1258 goto out; 1259 } 1260 1261 /* LAN ID is needed for I2C access */ 1262 hw->mac.ops.set_lan_id(hw); 1263 1264 status = hw->phy.ops.read_i2c_eeprom(hw, 1265 IXGBE_SFF_IDENTIFIER, 1266 &identifier); 1267 1268 if (status != IXGBE_SUCCESS) 1269 goto err_read_i2c_eeprom; 1270 1271 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1272 hw->phy.type = ixgbe_phy_sfp_unsupported; 1273 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1274 } else { 1275 status = hw->phy.ops.read_i2c_eeprom(hw, 1276 IXGBE_SFF_1GBE_COMP_CODES, 1277 &comp_codes_1g); 1278 1279 if (status != IXGBE_SUCCESS) 1280 goto err_read_i2c_eeprom; 1281 1282 status = hw->phy.ops.read_i2c_eeprom(hw, 1283 IXGBE_SFF_10GBE_COMP_CODES, 1284 &comp_codes_10g); 1285 1286 if (status != IXGBE_SUCCESS) 1287 goto err_read_i2c_eeprom; 1288 status = hw->phy.ops.read_i2c_eeprom(hw, 1289 IXGBE_SFF_CABLE_TECHNOLOGY, 1290 &cable_tech); 1291 1292 if (status != IXGBE_SUCCESS) 1293 goto err_read_i2c_eeprom; 1294 1295 /* ID Module 1296 * ========= 1297 * 0 SFP_DA_CU 1298 * 1 SFP_SR 1299 * 2 SFP_LR 1300 * 3 SFP_DA_CORE0 - 82599-specific 1301 * 4 SFP_DA_CORE1 - 82599-specific 1302 * 5 SFP_SR/LR_CORE0 - 82599-specific 1303 * 6 SFP_SR/LR_CORE1 - 82599-specific 1304 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1305 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1306 * 9 SFP_1g_cu_CORE0 - 82599-specific 1307 * 10 SFP_1g_cu_CORE1 - 82599-specific 1308 * 11 SFP_1g_sx_CORE0 - 82599-specific 1309 * 12 SFP_1g_sx_CORE1 - 82599-specific 1310 */ 1311 if (hw->mac.type == ixgbe_mac_82598EB) { 1312 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1313 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1314 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1315 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1316 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1317 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1318 else 1319 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1320 } else { 1321 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1322 if (hw->bus.lan_id == 0) 1323 hw->phy.sfp_type = 1324 ixgbe_sfp_type_da_cu_core0; 1325 else 1326 hw->phy.sfp_type = 1327 ixgbe_sfp_type_da_cu_core1; 1328 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1329 hw->phy.ops.read_i2c_eeprom( 1330 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1331 &cable_spec); 1332 if (cable_spec & 1333 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1334 if (hw->bus.lan_id == 0) 1335 hw->phy.sfp_type = 1336 ixgbe_sfp_type_da_act_lmt_core0; 1337 else 1338 hw->phy.sfp_type = 1339 ixgbe_sfp_type_da_act_lmt_core1; 1340 } else { 1341 hw->phy.sfp_type = 1342 ixgbe_sfp_type_unknown; 1343 } 1344 } else if (comp_codes_10g & 1345 (IXGBE_SFF_10GBASESR_CAPABLE | 1346 IXGBE_SFF_10GBASELR_CAPABLE)) { 1347 if (hw->bus.lan_id == 0) 1348 hw->phy.sfp_type = 1349 ixgbe_sfp_type_srlr_core0; 1350 else 1351 hw->phy.sfp_type = 1352 ixgbe_sfp_type_srlr_core1; 1353 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1354 if (hw->bus.lan_id == 0) 1355 hw->phy.sfp_type = 1356 ixgbe_sfp_type_1g_cu_core0; 1357 else 1358 hw->phy.sfp_type = 1359 ixgbe_sfp_type_1g_cu_core1; 1360 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1361 if (hw->bus.lan_id == 0) 1362 hw->phy.sfp_type = 1363 ixgbe_sfp_type_1g_sx_core0; 1364 else 1365 hw->phy.sfp_type = 1366 ixgbe_sfp_type_1g_sx_core1; 1367 } else { 1368 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1369 } 1370 } 1371 1372 if (hw->phy.sfp_type != stored_sfp_type) 1373 hw->phy.sfp_setup_needed = TRUE; 1374 1375 /* Determine if the SFP+ PHY is dual speed or not. */ 1376 hw->phy.multispeed_fiber = FALSE; 1377 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1378 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1379 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1380 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1381 hw->phy.multispeed_fiber = TRUE; 1382 1383 /* Determine PHY vendor */ 1384 if (hw->phy.type != ixgbe_phy_nl) { 1385 hw->phy.id = identifier; 1386 status = hw->phy.ops.read_i2c_eeprom(hw, 1387 IXGBE_SFF_VENDOR_OUI_BYTE0, 1388 &oui_bytes[0]); 1389 1390 if (status != IXGBE_SUCCESS) 1391 goto err_read_i2c_eeprom; 1392 1393 status = hw->phy.ops.read_i2c_eeprom(hw, 1394 IXGBE_SFF_VENDOR_OUI_BYTE1, 1395 &oui_bytes[1]); 1396 1397 if (status != IXGBE_SUCCESS) 1398 goto err_read_i2c_eeprom; 1399 1400 status = hw->phy.ops.read_i2c_eeprom(hw, 1401 IXGBE_SFF_VENDOR_OUI_BYTE2, 1402 &oui_bytes[2]); 1403 1404 if (status != IXGBE_SUCCESS) 1405 goto err_read_i2c_eeprom; 1406 1407 vendor_oui = 1408 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1409 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1410 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1411 1412 switch (vendor_oui) { 1413 case IXGBE_SFF_VENDOR_OUI_TYCO: 1414 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1415 hw->phy.type = 1416 ixgbe_phy_sfp_passive_tyco; 1417 break; 1418 case IXGBE_SFF_VENDOR_OUI_FTL: 1419 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1420 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1421 else 1422 hw->phy.type = ixgbe_phy_sfp_ftl; 1423 break; 1424 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1425 hw->phy.type = ixgbe_phy_sfp_avago; 1426 break; 1427 case IXGBE_SFF_VENDOR_OUI_INTEL: 1428 hw->phy.type = ixgbe_phy_sfp_intel; 1429 break; 1430 default: 1431 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1432 hw->phy.type = 1433 ixgbe_phy_sfp_passive_unknown; 1434 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1435 hw->phy.type = 1436 ixgbe_phy_sfp_active_unknown; 1437 else 1438 hw->phy.type = ixgbe_phy_sfp_unknown; 1439 break; 1440 } 1441 } 1442 1443 /* Allow any DA cable vendor */ 1444 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1445 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1446 status = IXGBE_SUCCESS; 1447 goto out; 1448 } 1449 1450 /* Verify supported 1G SFP modules */ 1451 if (comp_codes_10g == 0 && 1452 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1453 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1454 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1455 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1456 hw->phy.type = ixgbe_phy_sfp_unsupported; 1457 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1458 goto out; 1459 } 1460 1461 /* Anything else 82598-based is supported */ 1462 if (hw->mac.type == ixgbe_mac_82598EB) { 1463 status = IXGBE_SUCCESS; 1464 goto out; 1465 } 1466 1467 ixgbe_get_device_caps(hw, &enforce_sfp); 1468 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1469 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1470 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1471 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1472 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1473 /* Make sure we're a supported PHY type */ 1474 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1475 status = IXGBE_SUCCESS; 1476 } else { 1477 if (hw->allow_unsupported_sfp == TRUE) { 1478 EWARN(hw, "WARNING: Intel (R) Network " 1479 "Connections are quality tested " 1480 "using Intel (R) Ethernet Optics." 1481 " Using untested modules is not " 1482 "supported and may cause unstable" 1483 " operation or damage to the " 1484 "module or the adapter. Intel " 1485 "Corporation is not responsible " 1486 "for any harm caused by using " 1487 "untested modules.\n", status); 1488 status = IXGBE_SUCCESS; 1489 } else { 1490 DEBUGOUT("SFP+ module not supported\n"); 1491 hw->phy.type = 1492 ixgbe_phy_sfp_unsupported; 1493 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1494 } 1495 } 1496 } else { 1497 status = IXGBE_SUCCESS; 1498 } 1499 } 1500 1501 out: 1502 return status; 1503 1504 err_read_i2c_eeprom: 1505 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1506 if (hw->phy.type != ixgbe_phy_nl) { 1507 hw->phy.id = 0; 1508 hw->phy.type = ixgbe_phy_unknown; 1509 } 1510 return IXGBE_ERR_SFP_NOT_PRESENT; 1511 } 1512 1513 /** 1514 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1515 * @hw: pointer to hardware structure 1516 * 1517 * Determines physical layer capabilities of the current SFP. 1518 */ 1519 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1520 { 1521 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1522 u8 comp_codes_10g = 0; 1523 u8 comp_codes_1g = 0; 1524 1525 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1526 1527 hw->phy.ops.identify_sfp(hw); 1528 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1529 return physical_layer; 1530 1531 switch (hw->phy.type) { 1532 case ixgbe_phy_sfp_passive_tyco: 1533 case ixgbe_phy_sfp_passive_unknown: 1534 case ixgbe_phy_qsfp_passive_unknown: 1535 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1536 break; 1537 case ixgbe_phy_sfp_ftl_active: 1538 case ixgbe_phy_sfp_active_unknown: 1539 case ixgbe_phy_qsfp_active_unknown: 1540 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1541 break; 1542 case ixgbe_phy_sfp_avago: 1543 case ixgbe_phy_sfp_ftl: 1544 case ixgbe_phy_sfp_intel: 1545 case ixgbe_phy_sfp_unknown: 1546 hw->phy.ops.read_i2c_eeprom(hw, 1547 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1548 hw->phy.ops.read_i2c_eeprom(hw, 1549 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1550 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1551 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1552 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1553 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1554 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1555 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1556 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1557 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1558 break; 1559 case ixgbe_phy_qsfp_intel: 1560 case ixgbe_phy_qsfp_unknown: 1561 hw->phy.ops.read_i2c_eeprom(hw, 1562 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1563 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1564 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1565 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1566 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1567 break; 1568 default: 1569 break; 1570 } 1571 1572 return physical_layer; 1573 } 1574 1575 /** 1576 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1577 * @hw: pointer to hardware structure 1578 * 1579 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1580 **/ 1581 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1582 { 1583 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1584 u32 vendor_oui = 0; 1585 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1586 u8 identifier = 0; 1587 u8 comp_codes_1g = 0; 1588 u8 comp_codes_10g = 0; 1589 u8 oui_bytes[3] = {0, 0, 0}; 1590 u16 enforce_sfp = 0; 1591 u8 connector = 0; 1592 u8 cable_length = 0; 1593 u8 device_tech = 0; 1594 bool active_cable = FALSE; 1595 1596 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1597 1598 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1599 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1600 status = IXGBE_ERR_SFP_NOT_PRESENT; 1601 goto out; 1602 } 1603 1604 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1605 &identifier); 1606 1607 if (status != IXGBE_SUCCESS) 1608 goto err_read_i2c_eeprom; 1609 1610 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1611 hw->phy.type = ixgbe_phy_sfp_unsupported; 1612 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1613 goto out; 1614 } 1615 1616 hw->phy.id = identifier; 1617 1618 /* LAN ID is needed for sfp_type determination */ 1619 hw->mac.ops.set_lan_id(hw); 1620 1621 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1622 &comp_codes_10g); 1623 1624 if (status != IXGBE_SUCCESS) 1625 goto err_read_i2c_eeprom; 1626 1627 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1628 &comp_codes_1g); 1629 1630 if (status != IXGBE_SUCCESS) 1631 goto err_read_i2c_eeprom; 1632 1633 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1634 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1635 if (hw->bus.lan_id == 0) 1636 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1637 else 1638 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1639 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1640 IXGBE_SFF_10GBASELR_CAPABLE)) { 1641 if (hw->bus.lan_id == 0) 1642 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1643 else 1644 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1645 } else { 1646 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1647 active_cable = TRUE; 1648 1649 if (!active_cable) { 1650 /* check for active DA cables that pre-date 1651 * SFF-8436 v3.6 */ 1652 hw->phy.ops.read_i2c_eeprom(hw, 1653 IXGBE_SFF_QSFP_CONNECTOR, 1654 &connector); 1655 1656 hw->phy.ops.read_i2c_eeprom(hw, 1657 IXGBE_SFF_QSFP_CABLE_LENGTH, 1658 &cable_length); 1659 1660 hw->phy.ops.read_i2c_eeprom(hw, 1661 IXGBE_SFF_QSFP_DEVICE_TECH, 1662 &device_tech); 1663 1664 if ((connector == 1665 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1666 (cable_length > 0) && 1667 ((device_tech >> 4) == 1668 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1669 active_cable = TRUE; 1670 } 1671 1672 if (active_cable) { 1673 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1674 if (hw->bus.lan_id == 0) 1675 hw->phy.sfp_type = 1676 ixgbe_sfp_type_da_act_lmt_core0; 1677 else 1678 hw->phy.sfp_type = 1679 ixgbe_sfp_type_da_act_lmt_core1; 1680 } else { 1681 /* unsupported module type */ 1682 hw->phy.type = ixgbe_phy_sfp_unsupported; 1683 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1684 goto out; 1685 } 1686 } 1687 1688 if (hw->phy.sfp_type != stored_sfp_type) 1689 hw->phy.sfp_setup_needed = TRUE; 1690 1691 /* Determine if the QSFP+ PHY is dual speed or not. */ 1692 hw->phy.multispeed_fiber = FALSE; 1693 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1694 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1695 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1696 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1697 hw->phy.multispeed_fiber = TRUE; 1698 1699 /* Determine PHY vendor for optical modules */ 1700 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1701 IXGBE_SFF_10GBASELR_CAPABLE)) { 1702 status = hw->phy.ops.read_i2c_eeprom(hw, 1703 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1704 &oui_bytes[0]); 1705 1706 if (status != IXGBE_SUCCESS) 1707 goto err_read_i2c_eeprom; 1708 1709 status = hw->phy.ops.read_i2c_eeprom(hw, 1710 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1711 &oui_bytes[1]); 1712 1713 if (status != IXGBE_SUCCESS) 1714 goto err_read_i2c_eeprom; 1715 1716 status = hw->phy.ops.read_i2c_eeprom(hw, 1717 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1718 &oui_bytes[2]); 1719 1720 if (status != IXGBE_SUCCESS) 1721 goto err_read_i2c_eeprom; 1722 1723 vendor_oui = 1724 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1725 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1726 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1727 1728 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1729 hw->phy.type = ixgbe_phy_qsfp_intel; 1730 else 1731 hw->phy.type = ixgbe_phy_qsfp_unknown; 1732 1733 ixgbe_get_device_caps(hw, &enforce_sfp); 1734 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1735 /* Make sure we're a supported PHY type */ 1736 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1737 status = IXGBE_SUCCESS; 1738 } else { 1739 if (hw->allow_unsupported_sfp == TRUE) { 1740 EWARN(hw, "WARNING: Intel (R) Network " 1741 "Connections are quality tested " 1742 "using Intel (R) Ethernet Optics." 1743 " Using untested modules is not " 1744 "supported and may cause unstable" 1745 " operation or damage to the " 1746 "module or the adapter. Intel " 1747 "Corporation is not responsible " 1748 "for any harm caused by using " 1749 "untested modules.\n", status); 1750 status = IXGBE_SUCCESS; 1751 } else { 1752 DEBUGOUT("QSFP module not supported\n"); 1753 hw->phy.type = 1754 ixgbe_phy_sfp_unsupported; 1755 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1756 } 1757 } 1758 } else { 1759 status = IXGBE_SUCCESS; 1760 } 1761 } 1762 1763 out: 1764 return status; 1765 1766 err_read_i2c_eeprom: 1767 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1768 hw->phy.id = 0; 1769 hw->phy.type = ixgbe_phy_unknown; 1770 1771 return IXGBE_ERR_SFP_NOT_PRESENT; 1772 } 1773 1774 1775 /** 1776 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1777 * @hw: pointer to hardware structure 1778 * @list_offset: offset to the SFP ID list 1779 * @data_offset: offset to the SFP data block 1780 * 1781 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1782 * so it returns the offsets to the phy init sequence block. 1783 **/ 1784 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1785 u16 *list_offset, 1786 u16 *data_offset) 1787 { 1788 u16 sfp_id; 1789 u16 sfp_type = hw->phy.sfp_type; 1790 1791 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1792 1793 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1794 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1795 1796 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1797 return IXGBE_ERR_SFP_NOT_PRESENT; 1798 1799 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1800 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1801 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1802 1803 /* 1804 * Limiting active cables and 1G Phys must be initialized as 1805 * SR modules 1806 */ 1807 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1808 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1809 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1810 sfp_type = ixgbe_sfp_type_srlr_core0; 1811 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1812 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1813 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1814 sfp_type = ixgbe_sfp_type_srlr_core1; 1815 1816 /* Read offset to PHY init contents */ 1817 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1818 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1819 "eeprom read at offset %d failed", 1820 IXGBE_PHY_INIT_OFFSET_NL); 1821 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1822 } 1823 1824 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1825 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1826 1827 /* Shift offset to first ID word */ 1828 (*list_offset)++; 1829 1830 /* 1831 * Find the matching SFP ID in the EEPROM 1832 * and program the init sequence 1833 */ 1834 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1835 goto err_phy; 1836 1837 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1838 if (sfp_id == sfp_type) { 1839 (*list_offset)++; 1840 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1841 goto err_phy; 1842 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1843 DEBUGOUT("SFP+ module not supported\n"); 1844 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1845 } else { 1846 break; 1847 } 1848 } else { 1849 (*list_offset) += 2; 1850 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1851 goto err_phy; 1852 } 1853 } 1854 1855 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1856 DEBUGOUT("No matching SFP+ module found\n"); 1857 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1858 } 1859 1860 return IXGBE_SUCCESS; 1861 1862 err_phy: 1863 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1864 "eeprom read at offset %d failed", *list_offset); 1865 return IXGBE_ERR_PHY; 1866 } 1867 1868 /** 1869 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1870 * @hw: pointer to hardware structure 1871 * @byte_offset: EEPROM byte offset to read 1872 * @eeprom_data: value read 1873 * 1874 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1875 **/ 1876 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1877 u8 *eeprom_data) 1878 { 1879 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1880 1881 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1882 IXGBE_I2C_EEPROM_DEV_ADDR, 1883 eeprom_data); 1884 } 1885 1886 /** 1887 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1888 * @hw: pointer to hardware structure 1889 * @byte_offset: byte offset at address 0xA2 1890 * @eeprom_data: value read 1891 * 1892 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1893 **/ 1894 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1895 u8 *sff8472_data) 1896 { 1897 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1898 IXGBE_I2C_EEPROM_DEV_ADDR2, 1899 sff8472_data); 1900 } 1901 1902 /** 1903 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1904 * @hw: pointer to hardware structure 1905 * @byte_offset: EEPROM byte offset to write 1906 * @eeprom_data: value to write 1907 * 1908 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1909 **/ 1910 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1911 u8 eeprom_data) 1912 { 1913 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1914 1915 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1916 IXGBE_I2C_EEPROM_DEV_ADDR, 1917 eeprom_data); 1918 } 1919 1920 /** 1921 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1922 * @hw: pointer to hardware structure 1923 * @offset: eeprom offset to be read 1924 * @addr: I2C address to be read 1925 */ 1926 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1927 { 1928 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1929 offset == IXGBE_SFF_IDENTIFIER && 1930 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1931 return TRUE; 1932 return FALSE; 1933 } 1934 1935 /** 1936 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1937 * @hw: pointer to hardware structure 1938 * @byte_offset: byte offset to read 1939 * @data: value read 1940 * 1941 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1942 * a specified device address. 1943 **/ 1944 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1945 u8 dev_addr, u8 *data) 1946 { 1947 s32 status; 1948 u32 max_retry = 10; 1949 u32 retry = 0; 1950 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1951 bool nack = 1; 1952 *data = 0; 1953 1954 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1955 1956 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 1957 max_retry = IXGBE_SFP_DETECT_RETRIES; 1958 1959 do { 1960 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1961 return IXGBE_ERR_SWFW_SYNC; 1962 1963 ixgbe_i2c_start(hw); 1964 1965 /* Device Address and write indication */ 1966 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1967 if (status != IXGBE_SUCCESS) 1968 goto fail; 1969 1970 status = ixgbe_get_i2c_ack(hw); 1971 if (status != IXGBE_SUCCESS) 1972 goto fail; 1973 1974 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1975 if (status != IXGBE_SUCCESS) 1976 goto fail; 1977 1978 status = ixgbe_get_i2c_ack(hw); 1979 if (status != IXGBE_SUCCESS) 1980 goto fail; 1981 1982 ixgbe_i2c_start(hw); 1983 1984 /* Device Address and read indication */ 1985 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1986 if (status != IXGBE_SUCCESS) 1987 goto fail; 1988 1989 status = ixgbe_get_i2c_ack(hw); 1990 if (status != IXGBE_SUCCESS) 1991 goto fail; 1992 1993 status = ixgbe_clock_in_i2c_byte(hw, data); 1994 if (status != IXGBE_SUCCESS) 1995 goto fail; 1996 1997 status = ixgbe_clock_out_i2c_bit(hw, nack); 1998 if (status != IXGBE_SUCCESS) 1999 goto fail; 2000 2001 ixgbe_i2c_stop(hw); 2002 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2003 return IXGBE_SUCCESS; 2004 2005 fail: 2006 ixgbe_i2c_bus_clear(hw); 2007 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2008 msec_delay(100); 2009 retry++; 2010 if (retry < max_retry) 2011 DEBUGOUT("I2C byte read error - Retrying.\n"); 2012 else 2013 DEBUGOUT("I2C byte read error.\n"); 2014 2015 } while (retry < max_retry); 2016 2017 return status; 2018 } 2019 2020 /** 2021 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2022 * @hw: pointer to hardware structure 2023 * @byte_offset: byte offset to write 2024 * @data: value to write 2025 * 2026 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2027 * a specified device address. 2028 **/ 2029 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2030 u8 dev_addr, u8 data) 2031 { 2032 s32 status = IXGBE_SUCCESS; 2033 u32 max_retry = 2; 2034 u32 retry = 0; 2035 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2036 2037 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2038 2039 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 2040 status = IXGBE_ERR_SWFW_SYNC; 2041 goto write_byte_out; 2042 } 2043 2044 do { 2045 ixgbe_i2c_start(hw); 2046 2047 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2048 if (status != IXGBE_SUCCESS) 2049 goto fail; 2050 2051 status = ixgbe_get_i2c_ack(hw); 2052 if (status != IXGBE_SUCCESS) 2053 goto fail; 2054 2055 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2056 if (status != IXGBE_SUCCESS) 2057 goto fail; 2058 2059 status = ixgbe_get_i2c_ack(hw); 2060 if (status != IXGBE_SUCCESS) 2061 goto fail; 2062 2063 status = ixgbe_clock_out_i2c_byte(hw, data); 2064 if (status != IXGBE_SUCCESS) 2065 goto fail; 2066 2067 status = ixgbe_get_i2c_ack(hw); 2068 if (status != IXGBE_SUCCESS) 2069 goto fail; 2070 2071 ixgbe_i2c_stop(hw); 2072 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2073 return IXGBE_SUCCESS; 2074 2075 fail: 2076 ixgbe_i2c_bus_clear(hw); 2077 retry++; 2078 if (retry < max_retry) 2079 DEBUGOUT("I2C byte write error - Retrying.\n"); 2080 else 2081 DEBUGOUT("I2C byte write error.\n"); 2082 } while (retry < max_retry); 2083 2084 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2085 2086 write_byte_out: 2087 return status; 2088 } 2089 2090 /** 2091 * ixgbe_i2c_start - Sets I2C start condition 2092 * @hw: pointer to hardware structure 2093 * 2094 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2095 * Set bit-bang mode on X550 hardware. 2096 **/ 2097 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2098 { 2099 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2100 2101 DEBUGFUNC("ixgbe_i2c_start"); 2102 2103 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2104 2105 /* Start condition must begin with data and clock high */ 2106 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2107 ixgbe_raise_i2c_clk(hw, &i2cctl); 2108 2109 /* Setup time for start condition (4.7us) */ 2110 usec_delay(IXGBE_I2C_T_SU_STA); 2111 2112 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2113 2114 /* Hold time for start condition (4us) */ 2115 usec_delay(IXGBE_I2C_T_HD_STA); 2116 2117 ixgbe_lower_i2c_clk(hw, &i2cctl); 2118 2119 /* Minimum low period of clock is 4.7 us */ 2120 usec_delay(IXGBE_I2C_T_LOW); 2121 2122 } 2123 2124 /** 2125 * ixgbe_i2c_stop - Sets I2C stop condition 2126 * @hw: pointer to hardware structure 2127 * 2128 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2129 * Disables bit-bang mode and negates data output enable on X550 2130 * hardware. 2131 **/ 2132 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2133 { 2134 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2135 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2136 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2137 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2138 2139 DEBUGFUNC("ixgbe_i2c_stop"); 2140 2141 /* Stop condition must begin with data low and clock high */ 2142 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2143 ixgbe_raise_i2c_clk(hw, &i2cctl); 2144 2145 /* Setup time for stop condition (4us) */ 2146 usec_delay(IXGBE_I2C_T_SU_STO); 2147 2148 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2149 2150 /* bus free time between stop and start (4.7us)*/ 2151 usec_delay(IXGBE_I2C_T_BUF); 2152 2153 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2154 i2cctl &= ~bb_en_bit; 2155 i2cctl |= data_oe_bit | clk_oe_bit; 2156 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2157 IXGBE_WRITE_FLUSH(hw); 2158 } 2159 } 2160 2161 /** 2162 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2163 * @hw: pointer to hardware structure 2164 * @data: data byte to clock in 2165 * 2166 * Clocks in one byte data via I2C data/clock 2167 **/ 2168 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2169 { 2170 s32 i; 2171 bool bit = 0; 2172 2173 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2174 2175 *data = 0; 2176 for (i = 7; i >= 0; i--) { 2177 ixgbe_clock_in_i2c_bit(hw, &bit); 2178 *data |= bit << i; 2179 } 2180 2181 return IXGBE_SUCCESS; 2182 } 2183 2184 /** 2185 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2186 * @hw: pointer to hardware structure 2187 * @data: data byte clocked out 2188 * 2189 * Clocks out one byte data via I2C data/clock 2190 **/ 2191 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2192 { 2193 s32 status = IXGBE_SUCCESS; 2194 s32 i; 2195 u32 i2cctl; 2196 bool bit; 2197 2198 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2199 2200 for (i = 7; i >= 0; i--) { 2201 bit = (data >> i) & 0x1; 2202 status = ixgbe_clock_out_i2c_bit(hw, bit); 2203 2204 if (status != IXGBE_SUCCESS) 2205 break; 2206 } 2207 2208 /* Release SDA line (set high) */ 2209 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2210 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2211 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2212 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2213 IXGBE_WRITE_FLUSH(hw); 2214 2215 return status; 2216 } 2217 2218 /** 2219 * ixgbe_get_i2c_ack - Polls for I2C ACK 2220 * @hw: pointer to hardware structure 2221 * 2222 * Clocks in/out one bit via I2C data/clock 2223 **/ 2224 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2225 { 2226 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2227 s32 status = IXGBE_SUCCESS; 2228 u32 i = 0; 2229 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2230 u32 timeout = 10; 2231 bool ack = 1; 2232 2233 DEBUGFUNC("ixgbe_get_i2c_ack"); 2234 2235 if (data_oe_bit) { 2236 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2237 i2cctl |= data_oe_bit; 2238 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2239 IXGBE_WRITE_FLUSH(hw); 2240 } 2241 ixgbe_raise_i2c_clk(hw, &i2cctl); 2242 2243 /* Minimum high period of clock is 4us */ 2244 usec_delay(IXGBE_I2C_T_HIGH); 2245 2246 /* Poll for ACK. Note that ACK in I2C spec is 2247 * transition from 1 to 0 */ 2248 for (i = 0; i < timeout; i++) { 2249 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2250 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2251 2252 usec_delay(1); 2253 if (!ack) 2254 break; 2255 } 2256 2257 if (ack) { 2258 DEBUGOUT("I2C ack was not received.\n"); 2259 status = IXGBE_ERR_I2C; 2260 } 2261 2262 ixgbe_lower_i2c_clk(hw, &i2cctl); 2263 2264 /* Minimum low period of clock is 4.7 us */ 2265 usec_delay(IXGBE_I2C_T_LOW); 2266 2267 return status; 2268 } 2269 2270 /** 2271 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2272 * @hw: pointer to hardware structure 2273 * @data: read data value 2274 * 2275 * Clocks in one bit via I2C data/clock 2276 **/ 2277 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2278 { 2279 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2280 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2281 2282 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2283 2284 if (data_oe_bit) { 2285 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2286 i2cctl |= data_oe_bit; 2287 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2288 IXGBE_WRITE_FLUSH(hw); 2289 } 2290 ixgbe_raise_i2c_clk(hw, &i2cctl); 2291 2292 /* Minimum high period of clock is 4us */ 2293 usec_delay(IXGBE_I2C_T_HIGH); 2294 2295 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2296 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2297 2298 ixgbe_lower_i2c_clk(hw, &i2cctl); 2299 2300 /* Minimum low period of clock is 4.7 us */ 2301 usec_delay(IXGBE_I2C_T_LOW); 2302 2303 return IXGBE_SUCCESS; 2304 } 2305 2306 /** 2307 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2308 * @hw: pointer to hardware structure 2309 * @data: data value to write 2310 * 2311 * Clocks out one bit via I2C data/clock 2312 **/ 2313 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2314 { 2315 s32 status; 2316 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2317 2318 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2319 2320 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2321 if (status == IXGBE_SUCCESS) { 2322 ixgbe_raise_i2c_clk(hw, &i2cctl); 2323 2324 /* Minimum high period of clock is 4us */ 2325 usec_delay(IXGBE_I2C_T_HIGH); 2326 2327 ixgbe_lower_i2c_clk(hw, &i2cctl); 2328 2329 /* Minimum low period of clock is 4.7 us. 2330 * This also takes care of the data hold time. 2331 */ 2332 usec_delay(IXGBE_I2C_T_LOW); 2333 } else { 2334 status = IXGBE_ERR_I2C; 2335 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2336 "I2C data was not set to %X\n", data); 2337 } 2338 2339 return status; 2340 } 2341 2342 /** 2343 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2344 * @hw: pointer to hardware structure 2345 * @i2cctl: Current value of I2CCTL register 2346 * 2347 * Raises the I2C clock line '0'->'1' 2348 * Negates the I2C clock output enable on X550 hardware. 2349 **/ 2350 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2351 { 2352 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2353 u32 i = 0; 2354 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2355 u32 i2cctl_r = 0; 2356 2357 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2358 2359 if (clk_oe_bit) { 2360 *i2cctl |= clk_oe_bit; 2361 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2362 } 2363 2364 for (i = 0; i < timeout; i++) { 2365 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2366 2367 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2368 IXGBE_WRITE_FLUSH(hw); 2369 /* SCL rise time (1000ns) */ 2370 usec_delay(IXGBE_I2C_T_RISE); 2371 2372 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2373 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2374 break; 2375 } 2376 } 2377 2378 /** 2379 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2380 * @hw: pointer to hardware structure 2381 * @i2cctl: Current value of I2CCTL register 2382 * 2383 * Lowers the I2C clock line '1'->'0' 2384 * Asserts the I2C clock output enable on X550 hardware. 2385 **/ 2386 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2387 { 2388 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2389 2390 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2391 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2392 2393 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2394 IXGBE_WRITE_FLUSH(hw); 2395 2396 /* SCL fall time (300ns) */ 2397 usec_delay(IXGBE_I2C_T_FALL); 2398 } 2399 2400 /** 2401 * ixgbe_set_i2c_data - Sets the I2C data bit 2402 * @hw: pointer to hardware structure 2403 * @i2cctl: Current value of I2CCTL register 2404 * @data: I2C data value (0 or 1) to set 2405 * 2406 * Sets the I2C data bit 2407 * Asserts the I2C data output enable on X550 hardware. 2408 **/ 2409 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2410 { 2411 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2412 s32 status = IXGBE_SUCCESS; 2413 2414 DEBUGFUNC("ixgbe_set_i2c_data"); 2415 2416 if (data) 2417 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2418 else 2419 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2420 *i2cctl &= ~data_oe_bit; 2421 2422 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2423 IXGBE_WRITE_FLUSH(hw); 2424 2425 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2426 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2427 2428 if (!data) /* Can't verify data in this case */ 2429 return IXGBE_SUCCESS; 2430 if (data_oe_bit) { 2431 *i2cctl |= data_oe_bit; 2432 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2433 IXGBE_WRITE_FLUSH(hw); 2434 } 2435 2436 /* Verify data was set correctly */ 2437 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2438 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2439 status = IXGBE_ERR_I2C; 2440 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2441 "Error - I2C data was not set to %X.\n", 2442 data); 2443 } 2444 2445 return status; 2446 } 2447 2448 /** 2449 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2450 * @hw: pointer to hardware structure 2451 * @i2cctl: Current value of I2CCTL register 2452 * 2453 * Returns the I2C data bit value 2454 * Negates the I2C data output enable on X550 hardware. 2455 **/ 2456 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2457 { 2458 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2459 bool data; 2460 2461 DEBUGFUNC("ixgbe_get_i2c_data"); 2462 2463 if (data_oe_bit) { 2464 *i2cctl |= data_oe_bit; 2465 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2466 IXGBE_WRITE_FLUSH(hw); 2467 usec_delay(IXGBE_I2C_T_FALL); 2468 } 2469 2470 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2471 data = 1; 2472 else 2473 data = 0; 2474 2475 return data; 2476 } 2477 2478 /** 2479 * ixgbe_i2c_bus_clear - Clears the I2C bus 2480 * @hw: pointer to hardware structure 2481 * 2482 * Clears the I2C bus by sending nine clock pulses. 2483 * Used when data line is stuck low. 2484 **/ 2485 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2486 { 2487 u32 i2cctl; 2488 u32 i; 2489 2490 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2491 2492 ixgbe_i2c_start(hw); 2493 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2494 2495 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2496 2497 for (i = 0; i < 9; i++) { 2498 ixgbe_raise_i2c_clk(hw, &i2cctl); 2499 2500 /* Min high period of clock is 4us */ 2501 usec_delay(IXGBE_I2C_T_HIGH); 2502 2503 ixgbe_lower_i2c_clk(hw, &i2cctl); 2504 2505 /* Min low period of clock is 4.7us*/ 2506 usec_delay(IXGBE_I2C_T_LOW); 2507 } 2508 2509 ixgbe_i2c_start(hw); 2510 2511 /* Put the i2c bus back to default state */ 2512 ixgbe_i2c_stop(hw); 2513 } 2514 2515 /** 2516 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2517 * @hw: pointer to hardware structure 2518 * 2519 * Checks if the LASI temp alarm status was triggered due to overtemp 2520 **/ 2521 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2522 { 2523 s32 status = IXGBE_SUCCESS; 2524 u16 phy_data = 0; 2525 2526 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2527 2528 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2529 goto out; 2530 2531 /* Check that the LASI temp alarm status was triggered */ 2532 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2533 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2534 2535 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2536 goto out; 2537 2538 status = IXGBE_ERR_OVERTEMP; 2539 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2540 out: 2541 return status; 2542 } 2543 2544 /** 2545 * ixgbe_set_copper_phy_power - Control power for copper phy 2546 * @hw: pointer to hardware structure 2547 * @on: TRUE for on, FALSE for off 2548 */ 2549 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2550 { 2551 u32 status; 2552 u16 reg; 2553 2554 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2555 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2556 ®); 2557 if (status) 2558 return status; 2559 2560 if (on) { 2561 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2562 } else { 2563 if (ixgbe_check_reset_blocked(hw)) 2564 return 0; 2565 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2566 } 2567 2568 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2569 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2570 reg); 2571 return status; 2572 } 2573
Indexes created Wed Sep 24 05:09:52 GMT 2025