ixgbe_phy.c revision 1.8
1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 282289 2015-04-30 22:53:27Z erj $*/ 34 /*$NetBSD: ixgbe_phy.c,v 1.8 2016/12/01 06:56:28 msaitoh Exp $*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 52 u8 *sff8472_data); 53 54 /** 55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 56 * @hw: pointer to the hardware structure 57 * @byte: byte to send 58 * 59 * Returns an error code on error. 60 */ 61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 62 { 63 s32 status; 64 65 status = ixgbe_clock_out_i2c_byte(hw, byte); 66 if (status) 67 return status; 68 return ixgbe_get_i2c_ack(hw); 69 } 70 71 /** 72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 73 * @hw: pointer to the hardware structure 74 * @byte: pointer to a u8 to receive the byte 75 * 76 * Returns an error code on error. 77 */ 78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 79 { 80 s32 status; 81 82 status = ixgbe_clock_in_i2c_byte(hw, byte); 83 if (status) 84 return status; 85 /* ACK */ 86 return ixgbe_clock_out_i2c_bit(hw, FALSE); 87 } 88 89 /** 90 * ixgbe_ones_comp_byte_add - Perform one's complement addition 91 * @add1 - addend 1 92 * @add2 - addend 2 93 * 94 * Returns one's complement 8-bit sum. 95 */ 96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 97 { 98 u16 sum = add1 + add2; 99 100 sum = (sum & 0xFF) + (sum >> 8); 101 return sum & 0xFF; 102 } 103 104 /** 105 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 106 * @hw: pointer to the hardware structure 107 * @addr: I2C bus address to read from 108 * @reg: I2C device register to read from 109 * @val: pointer to location to receive read value 110 * @lock: TRUE if to take and release semaphore 111 * 112 * Returns an error code on error. 113 */ 114 static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 115 u16 reg, u16 *val, bool lock) 116 { 117 u32 swfw_mask = hw->phy.phy_semaphore_mask; 118 int max_retry = 10; 119 int retry = 0; 120 u8 csum_byte; 121 u8 high_bits; 122 u8 low_bits; 123 u8 reg_high; 124 u8 csum; 125 126 if (hw->mac.type >= ixgbe_mac_X550) 127 max_retry = 3; 128 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 129 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 130 csum = ~csum; 131 do { 132 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 133 return IXGBE_ERR_SWFW_SYNC; 134 ixgbe_i2c_start(hw); 135 /* Device Address and write indication */ 136 if (ixgbe_out_i2c_byte_ack(hw, addr)) 137 goto fail; 138 /* Write bits 14:8 */ 139 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 140 goto fail; 141 /* Write bits 7:0 */ 142 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 143 goto fail; 144 /* Write csum */ 145 if (ixgbe_out_i2c_byte_ack(hw, csum)) 146 goto fail; 147 /* Re-start condition */ 148 ixgbe_i2c_start(hw); 149 /* Device Address and read indication */ 150 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 151 goto fail; 152 /* Get upper bits */ 153 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 154 goto fail; 155 /* Get low bits */ 156 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 157 goto fail; 158 /* Get csum */ 159 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 160 goto fail; 161 /* NACK */ 162 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 163 goto fail; 164 ixgbe_i2c_stop(hw); 165 if (lock) 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 *val = (high_bits << 8) | low_bits; 168 return 0; 169 170 fail: 171 ixgbe_i2c_bus_clear(hw); 172 if (lock) 173 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 174 retry++; 175 if (retry < max_retry) 176 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 177 else 178 DEBUGOUT("I2C byte read combined error.\n"); 179 } while (retry < max_retry); 180 181 return IXGBE_ERR_I2C; 182 } 183 184 /** 185 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 186 * @hw: pointer to the hardware structure 187 * @addr: I2C bus address to read from 188 * @reg: I2C device register to read from 189 * @val: pointer to location to receive read value 190 * 191 * Returns an error code on error. 192 **/ 193 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 194 u16 reg, u16 *val) 195 { 196 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 197 } 198 199 /** 200 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 201 * @hw: pointer to the hardware structure 202 * @addr: I2C bus address to read from 203 * @reg: I2C device register to read from 204 * @val: pointer to location to receive read value 205 * 206 * Returns an error code on error. 207 **/ 208 static s32 209 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 210 u16 reg, u16 *val) 211 { 212 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 213 } 214 215 /** 216 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 217 * @hw: pointer to the hardware structure 218 * @addr: I2C bus address to write to 219 * @reg: I2C device register to write to 220 * @val: value to write 221 * @lock: TRUE if to take and release semaphore 222 * 223 * Returns an error code on error. 224 */ 225 static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 226 u16 reg, u16 val, bool lock) 227 { 228 u32 swfw_mask = hw->phy.phy_semaphore_mask; 229 int max_retry = 1; 230 int retry = 0; 231 u8 reg_high; 232 u8 csum; 233 234 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 235 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 236 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 237 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 238 csum = ~csum; 239 do { 240 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 241 return IXGBE_ERR_SWFW_SYNC; 242 ixgbe_i2c_start(hw); 243 /* Device Address and write indication */ 244 if (ixgbe_out_i2c_byte_ack(hw, addr)) 245 goto fail; 246 /* Write bits 14:8 */ 247 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 248 goto fail; 249 /* Write bits 7:0 */ 250 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 251 goto fail; 252 /* Write data 15:8 */ 253 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 254 goto fail; 255 /* Write data 7:0 */ 256 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 257 goto fail; 258 /* Write csum */ 259 if (ixgbe_out_i2c_byte_ack(hw, csum)) 260 goto fail; 261 ixgbe_i2c_stop(hw); 262 if (lock) 263 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 264 return 0; 265 266 fail: 267 ixgbe_i2c_bus_clear(hw); 268 if (lock) 269 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 270 retry++; 271 if (retry < max_retry) 272 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 273 else 274 DEBUGOUT("I2C byte write combined error.\n"); 275 } while (retry < max_retry); 276 277 return IXGBE_ERR_I2C; 278 } 279 280 /** 281 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 282 * @hw: pointer to the hardware structure 283 * @addr: I2C bus address to write to 284 * @reg: I2C device register to write to 285 * @val: value to write 286 * 287 * Returns an error code on error. 288 **/ 289 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 290 u8 addr, u16 reg, u16 val) 291 { 292 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 293 } 294 295 /** 296 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 297 * @hw: pointer to the hardware structure 298 * @addr: I2C bus address to write to 299 * @reg: I2C device register to write to 300 * @val: value to write 301 * 302 * Returns an error code on error. 303 **/ 304 static s32 305 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 306 u8 addr, u16 reg, u16 val) 307 { 308 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 309 } 310 311 /** 312 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 313 * @hw: pointer to the hardware structure 314 * 315 * Initialize the function pointers. 316 **/ 317 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 318 { 319 struct ixgbe_phy_info *phy = &hw->phy; 320 321 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 322 323 /* PHY */ 324 phy->ops.identify = ixgbe_identify_phy_generic; 325 phy->ops.reset = ixgbe_reset_phy_generic; 326 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 327 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 328 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 329 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 330 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 331 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 332 phy->ops.check_link = NULL; 333 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 334 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 335 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 336 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 337 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 338 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 339 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 340 phy->ops.identify_sfp = ixgbe_identify_module_generic; 341 phy->sfp_type = ixgbe_sfp_type_unknown; 342 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic; 343 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic; 344 phy->ops.read_i2c_combined_unlocked = 345 ixgbe_read_i2c_combined_generic_unlocked; 346 phy->ops.write_i2c_combined_unlocked = 347 ixgbe_write_i2c_combined_generic_unlocked; 348 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 349 phy->ops.write_i2c_byte_unlocked = 350 ixgbe_write_i2c_byte_generic_unlocked; 351 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 352 return IXGBE_SUCCESS; 353 } 354 355 /** 356 * ixgbe_identify_phy_generic - Get physical layer module 357 * @hw: pointer to hardware structure 358 * 359 * Determines the physical layer module found on the current adapter. 360 **/ 361 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 362 { 363 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 364 u32 phy_addr; 365 u16 ext_ability = 0; 366 367 DEBUGFUNC("ixgbe_identify_phy_generic"); 368 369 if (!hw->phy.phy_semaphore_mask) { 370 if (hw->bus.lan_id) 371 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 372 else 373 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 374 } 375 376 if (hw->phy.type == ixgbe_phy_unknown) { 377 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 378 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 379 hw->phy.addr = phy_addr; 380 ixgbe_get_phy_id(hw); 381 hw->phy.type = 382 ixgbe_get_phy_type_from_id(hw->phy.id); 383 384 if (hw->phy.type == ixgbe_phy_unknown) { 385 hw->phy.ops.read_reg(hw, 386 IXGBE_MDIO_PHY_EXT_ABILITY, 387 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 388 &ext_ability); 389 if (ext_ability & 390 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 391 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 392 hw->phy.type = 393 ixgbe_phy_cu_unknown; 394 else 395 hw->phy.type = 396 ixgbe_phy_generic; 397 } 398 399 status = IXGBE_SUCCESS; 400 break; 401 } 402 } 403 404 /* Certain media types do not have a phy so an address will not 405 * be found and the code will take this path. Caller has to 406 * decide if it is an error or not. 407 */ 408 if (status != IXGBE_SUCCESS) { 409 hw->phy.addr = 0; 410 } 411 } else { 412 status = IXGBE_SUCCESS; 413 } 414 415 return status; 416 } 417 418 /** 419 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 420 * @hw: pointer to the hardware structure 421 * 422 * This function checks the MMNGC.MNG_VETO bit to see if there are 423 * any constraints on link from manageability. For MAC's that don't 424 * have this bit just return faluse since the link can not be blocked 425 * via this method. 426 **/ 427 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 428 { 429 u32 mmngc; 430 431 DEBUGFUNC("ixgbe_check_reset_blocked"); 432 433 /* If we don't have this bit, it can't be blocking */ 434 if (hw->mac.type == ixgbe_mac_82598EB) 435 return FALSE; 436 437 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 438 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 439 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 440 "MNG_VETO bit detected.\n"); 441 return TRUE; 442 } 443 444 return FALSE; 445 } 446 447 /** 448 * ixgbe_validate_phy_addr - Determines phy address is valid 449 * @hw: pointer to hardware structure 450 * 451 **/ 452 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 453 { 454 u16 phy_id = 0; 455 bool valid = FALSE; 456 457 DEBUGFUNC("ixgbe_validate_phy_addr"); 458 459 hw->phy.addr = phy_addr; 460 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 461 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 462 463 if (phy_id != 0xFFFF && phy_id != 0x0) 464 valid = TRUE; 465 466 return valid; 467 } 468 469 /** 470 * ixgbe_get_phy_id - Get the phy type 471 * @hw: pointer to hardware structure 472 * 473 **/ 474 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 475 { 476 u32 status; 477 u16 phy_id_high = 0; 478 u16 phy_id_low = 0; 479 480 DEBUGFUNC("ixgbe_get_phy_id"); 481 482 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 483 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 484 &phy_id_high); 485 486 if (status == IXGBE_SUCCESS) { 487 hw->phy.id = (u32)(phy_id_high << 16); 488 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 489 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 490 &phy_id_low); 491 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 492 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 493 } 494 return status; 495 } 496 497 /** 498 * ixgbe_get_phy_type_from_id - Get the phy type 499 * @hw: pointer to hardware structure 500 * 501 **/ 502 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 503 { 504 enum ixgbe_phy_type phy_type; 505 506 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 507 508 switch (phy_id) { 509 case TN1010_PHY_ID: 510 phy_type = ixgbe_phy_tn; 511 break; 512 case X550_PHY_ID: 513 case X540_PHY_ID: 514 phy_type = ixgbe_phy_aq; 515 break; 516 case QT2022_PHY_ID: 517 phy_type = ixgbe_phy_qt; 518 break; 519 case ATH_PHY_ID: 520 phy_type = ixgbe_phy_nl; 521 break; 522 case X557_PHY_ID: 523 phy_type = ixgbe_phy_x550em_ext_t; 524 break; 525 default: 526 phy_type = ixgbe_phy_unknown; 527 break; 528 } 529 530 DEBUGOUT1("phy type found is %d\n", phy_type); 531 return phy_type; 532 } 533 534 /** 535 * ixgbe_reset_phy_generic - Performs a PHY reset 536 * @hw: pointer to hardware structure 537 **/ 538 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 539 { 540 u32 i; 541 u16 ctrl = 0; 542 s32 status = IXGBE_SUCCESS; 543 544 DEBUGFUNC("ixgbe_reset_phy_generic"); 545 546 if (hw->phy.type == ixgbe_phy_unknown) 547 status = ixgbe_identify_phy_generic(hw); 548 549 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 550 goto out; 551 552 /* Don't reset PHY if it's shut down due to overtemp. */ 553 if (!hw->phy.reset_if_overtemp && 554 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 555 goto out; 556 557 /* Blocked by MNG FW so bail */ 558 if (ixgbe_check_reset_blocked(hw)) 559 goto out; 560 561 /* 562 * Perform soft PHY reset to the PHY_XS. 563 * This will cause a soft reset to the PHY 564 */ 565 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 566 IXGBE_MDIO_PHY_XS_DEV_TYPE, 567 IXGBE_MDIO_PHY_XS_RESET); 568 569 /* 570 * Poll for reset bit to self-clear indicating reset is complete. 571 * Some PHYs could take up to 3 seconds to complete and need about 572 * 1.7 usec delay after the reset is complete. 573 */ 574 for (i = 0; i < 30; i++) { 575 msec_delay(100); 576 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 577 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 578 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 579 usec_delay(2); 580 break; 581 } 582 } 583 584 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 585 status = IXGBE_ERR_RESET_FAILED; 586 ERROR_REPORT1(IXGBE_ERROR_POLLING, 587 "PHY reset polling failed to complete.\n"); 588 } 589 590 out: 591 return status; 592 } 593 594 /** 595 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 596 * the SWFW lock 597 * @hw: pointer to hardware structure 598 * @reg_addr: 32 bit address of PHY register to read 599 * @phy_data: Pointer to read data from PHY register 600 **/ 601 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 602 u16 *phy_data) 603 { 604 u32 i, data, command; 605 606 /* Setup and write the address cycle command */ 607 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 608 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 609 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 610 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 611 612 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 613 614 /* 615 * Check every 10 usec to see if the address cycle completed. 616 * The MDI Command bit will clear when the operation is 617 * complete 618 */ 619 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 620 usec_delay(10); 621 622 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 623 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 624 break; 625 } 626 627 628 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 629 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 630 return IXGBE_ERR_PHY; 631 } 632 633 /* 634 * Address cycle complete, setup and write the read 635 * command 636 */ 637 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 638 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 639 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 640 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 641 642 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 643 644 /* 645 * Check every 10 usec to see if the address cycle 646 * completed. The MDI Command bit will clear when the 647 * operation is complete 648 */ 649 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 650 usec_delay(10); 651 652 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 653 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 654 break; 655 } 656 657 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 658 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 659 return IXGBE_ERR_PHY; 660 } 661 662 /* 663 * Read operation is complete. Get the data 664 * from MSRWD 665 */ 666 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 667 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 668 *phy_data = (u16)(data); 669 670 return IXGBE_SUCCESS; 671 } 672 673 /** 674 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 675 * using the SWFW lock - this function is needed in most cases 676 * @hw: pointer to hardware structure 677 * @reg_addr: 32 bit address of PHY register to read 678 * @phy_data: Pointer to read data from PHY register 679 **/ 680 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 681 u32 device_type, u16 *phy_data) 682 { 683 s32 status; 684 u32 gssr = hw->phy.phy_semaphore_mask; 685 686 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 687 688 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 689 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 690 phy_data); 691 hw->mac.ops.release_swfw_sync(hw, gssr); 692 } else { 693 status = IXGBE_ERR_SWFW_SYNC; 694 } 695 696 return status; 697 } 698 699 /** 700 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 701 * without SWFW lock 702 * @hw: pointer to hardware structure 703 * @reg_addr: 32 bit PHY register to write 704 * @device_type: 5 bit device type 705 * @phy_data: Data to write to the PHY register 706 **/ 707 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 708 u32 device_type, u16 phy_data) 709 { 710 u32 i, command; 711 712 /* Put the data in the MDI single read and write data register*/ 713 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 714 715 /* Setup and write the address cycle command */ 716 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 717 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 718 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 719 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 720 721 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 722 723 /* 724 * Check every 10 usec to see if the address cycle completed. 725 * The MDI Command bit will clear when the operation is 726 * complete 727 */ 728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 729 usec_delay(10); 730 731 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 732 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 733 break; 734 } 735 736 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 737 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 738 return IXGBE_ERR_PHY; 739 } 740 741 /* 742 * Address cycle complete, setup and write the write 743 * command 744 */ 745 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 746 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 747 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 748 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 749 750 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 751 752 /* 753 * Check every 10 usec to see if the address cycle 754 * completed. The MDI Command bit will clear when the 755 * operation is complete 756 */ 757 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 758 usec_delay(10); 759 760 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 761 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 762 break; 763 } 764 765 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 766 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 767 return IXGBE_ERR_PHY; 768 } 769 770 return IXGBE_SUCCESS; 771 } 772 773 /** 774 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 775 * using SWFW lock- this function is needed in most cases 776 * @hw: pointer to hardware structure 777 * @reg_addr: 32 bit PHY register to write 778 * @device_type: 5 bit device type 779 * @phy_data: Data to write to the PHY register 780 **/ 781 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 782 u32 device_type, u16 phy_data) 783 { 784 s32 status; 785 u32 gssr = hw->phy.phy_semaphore_mask; 786 787 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 788 789 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 790 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 791 phy_data); 792 hw->mac.ops.release_swfw_sync(hw, gssr); 793 } else { 794 status = IXGBE_ERR_SWFW_SYNC; 795 } 796 797 return status; 798 } 799 800 /** 801 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 802 * @hw: pointer to hardware structure 803 * 804 * Restart auto-negotiation and PHY and waits for completion. 805 **/ 806 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 807 { 808 s32 status = IXGBE_SUCCESS; 809 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 810 bool autoneg = FALSE; 811 ixgbe_link_speed speed; 812 813 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 814 815 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 816 817 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 818 /* Set or unset auto-negotiation 10G advertisement */ 819 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 820 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 821 &autoneg_reg); 822 823 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 824 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 825 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 826 827 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 829 autoneg_reg); 830 } 831 832 if (hw->mac.type == ixgbe_mac_X550) { 833 if (speed & IXGBE_LINK_SPEED_5GB_FULL) { 834 /* Set or unset auto-negotiation 1G advertisement */ 835 hw->phy.ops.read_reg(hw, 836 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 837 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 838 &autoneg_reg); 839 840 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 841 if (hw->phy.autoneg_advertised & 842 IXGBE_LINK_SPEED_5GB_FULL) 843 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 844 845 hw->phy.ops.write_reg(hw, 846 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 847 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 848 autoneg_reg); 849 } 850 851 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) { 852 /* Set or unset auto-negotiation 1G advertisement */ 853 hw->phy.ops.read_reg(hw, 854 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 855 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 856 &autoneg_reg); 857 858 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 859 if (hw->phy.autoneg_advertised & 860 IXGBE_LINK_SPEED_2_5GB_FULL) 861 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 862 863 hw->phy.ops.write_reg(hw, 864 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 865 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 866 autoneg_reg); 867 } 868 } 869 870 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 871 /* Set or unset auto-negotiation 1G advertisement */ 872 hw->phy.ops.read_reg(hw, 873 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 874 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 875 &autoneg_reg); 876 877 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 878 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 879 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 880 881 hw->phy.ops.write_reg(hw, 882 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 883 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 884 autoneg_reg); 885 } 886 887 if (speed & IXGBE_LINK_SPEED_100_FULL) { 888 /* Set or unset auto-negotiation 100M advertisement */ 889 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 890 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 891 &autoneg_reg); 892 893 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 894 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 895 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 896 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 897 898 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 899 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 900 autoneg_reg); 901 } 902 903 /* Blocked by MNG FW so don't reset PHY */ 904 if (ixgbe_check_reset_blocked(hw)) 905 return status; 906 907 /* Restart PHY auto-negotiation. */ 908 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 909 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 910 911 autoneg_reg |= IXGBE_MII_RESTART; 912 913 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 914 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 915 916 return status; 917 } 918 919 /** 920 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 921 * @hw: pointer to hardware structure 922 * @speed: new link speed 923 **/ 924 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 925 ixgbe_link_speed speed, 926 bool autoneg_wait_to_complete) 927 { 928 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 929 930 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 931 932 /* 933 * Clear autoneg_advertised and set new values based on input link 934 * speed. 935 */ 936 hw->phy.autoneg_advertised = 0; 937 938 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 939 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 940 941 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 942 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 943 944 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 945 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 946 947 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 948 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 949 950 if (speed & IXGBE_LINK_SPEED_100_FULL) 951 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 952 953 /* Setup link based on the new speed settings */ 954 hw->phy.ops.setup_link(hw); 955 956 return IXGBE_SUCCESS; 957 } 958 959 /** 960 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 961 * @hw: pointer to hardware structure 962 * @speed: pointer to link speed 963 * @autoneg: boolean auto-negotiation value 964 * 965 * Determines the supported link capabilities by reading the PHY auto 966 * negotiation register. 967 **/ 968 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 969 ixgbe_link_speed *speed, 970 bool *autoneg) 971 { 972 s32 status; 973 u16 speed_ability; 974 975 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 976 977 *speed = 0; 978 *autoneg = TRUE; 979 980 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 981 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 982 &speed_ability); 983 984 if (status == IXGBE_SUCCESS) { 985 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 986 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 987 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 988 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 989 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 990 *speed |= IXGBE_LINK_SPEED_100_FULL; 991 } 992 993 /* Internal PHY does not support 100 Mbps */ 994 if (hw->mac.type == ixgbe_mac_X550EM_x) 995 *speed &= ~IXGBE_LINK_SPEED_100_FULL; 996 997 if (hw->mac.type == ixgbe_mac_X550) { 998 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 999 *speed |= IXGBE_LINK_SPEED_5GB_FULL; 1000 } 1001 1002 return status; 1003 } 1004 1005 /** 1006 * ixgbe_check_phy_link_tnx - Determine link and speed status 1007 * @hw: pointer to hardware structure 1008 * 1009 * Reads the VS1 register to determine if link is up and the current speed for 1010 * the PHY. 1011 **/ 1012 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1013 bool *link_up) 1014 { 1015 s32 status = IXGBE_SUCCESS; 1016 u32 time_out; 1017 u32 max_time_out = 10; 1018 u16 phy_link = 0; 1019 u16 phy_speed = 0; 1020 u16 phy_data = 0; 1021 1022 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1023 1024 /* Initialize speed and link to default case */ 1025 *link_up = FALSE; 1026 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1027 1028 /* 1029 * Check current speed and link status of the PHY register. 1030 * This is a vendor specific register and may have to 1031 * be changed for other copper PHYs. 1032 */ 1033 for (time_out = 0; time_out < max_time_out; time_out++) { 1034 usec_delay(10); 1035 status = hw->phy.ops.read_reg(hw, 1036 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1037 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1038 &phy_data); 1039 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1040 phy_speed = phy_data & 1041 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1042 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1043 *link_up = TRUE; 1044 if (phy_speed == 1045 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1046 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1047 break; 1048 } 1049 } 1050 1051 return status; 1052 } 1053 1054 /** 1055 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1056 * @hw: pointer to hardware structure 1057 * 1058 * Restart auto-negotiation and PHY and waits for completion. 1059 **/ 1060 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1061 { 1062 s32 status = IXGBE_SUCCESS; 1063 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1064 bool autoneg = FALSE; 1065 ixgbe_link_speed speed; 1066 1067 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1068 1069 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1070 1071 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1072 /* Set or unset auto-negotiation 10G advertisement */ 1073 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1074 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1075 &autoneg_reg); 1076 1077 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1078 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1079 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1080 1081 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1082 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1083 autoneg_reg); 1084 } 1085 1086 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1087 /* Set or unset auto-negotiation 1G advertisement */ 1088 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1089 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1090 &autoneg_reg); 1091 1092 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1093 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1094 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1095 1096 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1097 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1098 autoneg_reg); 1099 } 1100 1101 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1102 /* Set or unset auto-negotiation 100M advertisement */ 1103 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1104 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1105 &autoneg_reg); 1106 1107 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1108 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1109 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1110 1111 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1112 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1113 autoneg_reg); 1114 } 1115 1116 /* Blocked by MNG FW so don't reset PHY */ 1117 if (ixgbe_check_reset_blocked(hw)) 1118 return status; 1119 1120 /* Restart PHY auto-negotiation. */ 1121 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1122 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1123 1124 autoneg_reg |= IXGBE_MII_RESTART; 1125 1126 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1127 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1128 1129 return status; 1130 } 1131 1132 /** 1133 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1134 * @hw: pointer to hardware structure 1135 * @firmware_version: pointer to the PHY Firmware Version 1136 **/ 1137 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1138 u16 *firmware_version) 1139 { 1140 s32 status; 1141 1142 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1143 1144 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1145 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1146 firmware_version); 1147 1148 return status; 1149 } 1150 1151 /** 1152 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1153 * @hw: pointer to hardware structure 1154 * @firmware_version: pointer to the PHY Firmware Version 1155 **/ 1156 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1157 u16 *firmware_version) 1158 { 1159 s32 status; 1160 1161 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1162 1163 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1164 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1165 firmware_version); 1166 1167 return status; 1168 } 1169 1170 /** 1171 * ixgbe_reset_phy_nl - Performs a PHY reset 1172 * @hw: pointer to hardware structure 1173 **/ 1174 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1175 { 1176 u16 phy_offset, control, eword, edata, block_crc; 1177 bool end_data = FALSE; 1178 u16 list_offset, data_offset; 1179 u16 phy_data = 0; 1180 s32 ret_val = IXGBE_SUCCESS; 1181 u32 i; 1182 1183 DEBUGFUNC("ixgbe_reset_phy_nl"); 1184 1185 /* Blocked by MNG FW so bail */ 1186 if (ixgbe_check_reset_blocked(hw)) 1187 goto out; 1188 1189 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1190 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1191 1192 /* reset the PHY and poll for completion */ 1193 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1194 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1195 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1196 1197 for (i = 0; i < 100; i++) { 1198 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1199 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1200 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1201 break; 1202 msec_delay(10); 1203 } 1204 1205 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1206 DEBUGOUT("PHY reset did not complete.\n"); 1207 ret_val = IXGBE_ERR_PHY; 1208 goto out; 1209 } 1210 1211 /* Get init offsets */ 1212 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1213 &data_offset); 1214 if (ret_val != IXGBE_SUCCESS) 1215 goto out; 1216 1217 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1218 data_offset++; 1219 while (!end_data) { 1220 /* 1221 * Read control word from PHY init contents offset 1222 */ 1223 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1224 if (ret_val) 1225 goto err_eeprom; 1226 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1227 IXGBE_CONTROL_SHIFT_NL; 1228 edata = eword & IXGBE_DATA_MASK_NL; 1229 switch (control) { 1230 case IXGBE_DELAY_NL: 1231 data_offset++; 1232 DEBUGOUT1("DELAY: %d MS\n", edata); 1233 msec_delay(edata); 1234 break; 1235 case IXGBE_DATA_NL: 1236 DEBUGOUT("DATA:\n"); 1237 data_offset++; 1238 ret_val = hw->eeprom.ops.read(hw, data_offset, 1239 &phy_offset); 1240 if (ret_val) 1241 goto err_eeprom; 1242 data_offset++; 1243 for (i = 0; i < edata; i++) { 1244 ret_val = hw->eeprom.ops.read(hw, data_offset, 1245 &eword); 1246 if (ret_val) 1247 goto err_eeprom; 1248 hw->phy.ops.write_reg(hw, phy_offset, 1249 IXGBE_TWINAX_DEV, eword); 1250 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1251 phy_offset); 1252 data_offset++; 1253 phy_offset++; 1254 } 1255 break; 1256 case IXGBE_CONTROL_NL: 1257 data_offset++; 1258 DEBUGOUT("CONTROL:\n"); 1259 if (edata == IXGBE_CONTROL_EOL_NL) { 1260 DEBUGOUT("EOL\n"); 1261 end_data = TRUE; 1262 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1263 DEBUGOUT("SOL\n"); 1264 } else { 1265 DEBUGOUT("Bad control value\n"); 1266 ret_val = IXGBE_ERR_PHY; 1267 goto out; 1268 } 1269 break; 1270 default: 1271 DEBUGOUT("Bad control type\n"); 1272 ret_val = IXGBE_ERR_PHY; 1273 goto out; 1274 } 1275 } 1276 1277 out: 1278 return ret_val; 1279 1280 err_eeprom: 1281 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1282 "eeprom read at offset %d failed", data_offset); 1283 return IXGBE_ERR_PHY; 1284 } 1285 1286 /** 1287 * ixgbe_identify_module_generic - Identifies module type 1288 * @hw: pointer to hardware structure 1289 * 1290 * Determines HW type and calls appropriate function. 1291 **/ 1292 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1293 { 1294 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1295 1296 DEBUGFUNC("ixgbe_identify_module_generic"); 1297 1298 switch (hw->mac.ops.get_media_type(hw)) { 1299 case ixgbe_media_type_fiber: 1300 status = ixgbe_identify_sfp_module_generic(hw); 1301 break; 1302 1303 case ixgbe_media_type_fiber_qsfp: 1304 status = ixgbe_identify_qsfp_module_generic(hw); 1305 break; 1306 1307 default: 1308 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1309 status = IXGBE_ERR_SFP_NOT_PRESENT; 1310 break; 1311 } 1312 1313 return status; 1314 } 1315 1316 /** 1317 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1318 * @hw: pointer to hardware structure 1319 * 1320 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1321 **/ 1322 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1323 { 1324 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1325 u32 vendor_oui = 0; 1326 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1327 u8 identifier = 0; 1328 u8 comp_codes_1g = 0; 1329 u8 comp_codes_10g = 0; 1330 u8 oui_bytes[3] = {0, 0, 0}; 1331 u8 cable_tech = 0; 1332 u8 cable_spec = 0; 1333 u16 enforce_sfp = 0; 1334 1335 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1336 1337 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1338 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1339 status = IXGBE_ERR_SFP_NOT_PRESENT; 1340 goto out; 1341 } 1342 1343 /* LAN ID is needed for I2C access */ 1344 hw->mac.ops.set_lan_id(hw); 1345 1346 status = hw->phy.ops.read_i2c_eeprom(hw, 1347 IXGBE_SFF_IDENTIFIER, 1348 &identifier); 1349 1350 if (status != IXGBE_SUCCESS) 1351 goto err_read_i2c_eeprom; 1352 1353 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1354 hw->phy.type = ixgbe_phy_sfp_unsupported; 1355 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1356 } else { 1357 status = hw->phy.ops.read_i2c_eeprom(hw, 1358 IXGBE_SFF_1GBE_COMP_CODES, 1359 &comp_codes_1g); 1360 1361 if (status != IXGBE_SUCCESS) 1362 goto err_read_i2c_eeprom; 1363 1364 status = hw->phy.ops.read_i2c_eeprom(hw, 1365 IXGBE_SFF_10GBE_COMP_CODES, 1366 &comp_codes_10g); 1367 1368 if (status != IXGBE_SUCCESS) 1369 goto err_read_i2c_eeprom; 1370 status = hw->phy.ops.read_i2c_eeprom(hw, 1371 IXGBE_SFF_CABLE_TECHNOLOGY, 1372 &cable_tech); 1373 1374 if (status != IXGBE_SUCCESS) 1375 goto err_read_i2c_eeprom; 1376 1377 /* ID Module 1378 * ========= 1379 * 0 SFP_DA_CU 1380 * 1 SFP_SR 1381 * 2 SFP_LR 1382 * 3 SFP_DA_CORE0 - 82599-specific 1383 * 4 SFP_DA_CORE1 - 82599-specific 1384 * 5 SFP_SR/LR_CORE0 - 82599-specific 1385 * 6 SFP_SR/LR_CORE1 - 82599-specific 1386 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1387 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1388 * 9 SFP_1g_cu_CORE0 - 82599-specific 1389 * 10 SFP_1g_cu_CORE1 - 82599-specific 1390 * 11 SFP_1g_sx_CORE0 - 82599-specific 1391 * 12 SFP_1g_sx_CORE1 - 82599-specific 1392 */ 1393 if (hw->mac.type == ixgbe_mac_82598EB) { 1394 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1395 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1396 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1397 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1398 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1399 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1400 else 1401 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1402 } else { 1403 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1404 if (hw->bus.lan_id == 0) 1405 hw->phy.sfp_type = 1406 ixgbe_sfp_type_da_cu_core0; 1407 else 1408 hw->phy.sfp_type = 1409 ixgbe_sfp_type_da_cu_core1; 1410 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1411 hw->phy.ops.read_i2c_eeprom( 1412 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1413 &cable_spec); 1414 if (cable_spec & 1415 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1416 if (hw->bus.lan_id == 0) 1417 hw->phy.sfp_type = 1418 ixgbe_sfp_type_da_act_lmt_core0; 1419 else 1420 hw->phy.sfp_type = 1421 ixgbe_sfp_type_da_act_lmt_core1; 1422 } else { 1423 hw->phy.sfp_type = 1424 ixgbe_sfp_type_unknown; 1425 } 1426 } else if (comp_codes_10g & 1427 (IXGBE_SFF_10GBASESR_CAPABLE | 1428 IXGBE_SFF_10GBASELR_CAPABLE)) { 1429 if (hw->bus.lan_id == 0) 1430 hw->phy.sfp_type = 1431 ixgbe_sfp_type_srlr_core0; 1432 else 1433 hw->phy.sfp_type = 1434 ixgbe_sfp_type_srlr_core1; 1435 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1436 if (hw->bus.lan_id == 0) 1437 hw->phy.sfp_type = 1438 ixgbe_sfp_type_1g_cu_core0; 1439 else 1440 hw->phy.sfp_type = 1441 ixgbe_sfp_type_1g_cu_core1; 1442 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1443 if (hw->bus.lan_id == 0) 1444 hw->phy.sfp_type = 1445 ixgbe_sfp_type_1g_sx_core0; 1446 else 1447 hw->phy.sfp_type = 1448 ixgbe_sfp_type_1g_sx_core1; 1449 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1450 if (hw->bus.lan_id == 0) 1451 hw->phy.sfp_type = 1452 ixgbe_sfp_type_1g_lx_core0; 1453 else 1454 hw->phy.sfp_type = 1455 ixgbe_sfp_type_1g_lx_core1; 1456 } else { 1457 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1458 } 1459 } 1460 1461 if (hw->phy.sfp_type != stored_sfp_type) 1462 hw->phy.sfp_setup_needed = TRUE; 1463 1464 /* Determine if the SFP+ PHY is dual speed or not. */ 1465 hw->phy.multispeed_fiber = FALSE; 1466 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1467 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1468 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1469 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1470 hw->phy.multispeed_fiber = TRUE; 1471 1472 /* Determine PHY vendor */ 1473 if (hw->phy.type != ixgbe_phy_nl) { 1474 hw->phy.id = identifier; 1475 status = hw->phy.ops.read_i2c_eeprom(hw, 1476 IXGBE_SFF_VENDOR_OUI_BYTE0, 1477 &oui_bytes[0]); 1478 1479 if (status != IXGBE_SUCCESS) 1480 goto err_read_i2c_eeprom; 1481 1482 status = hw->phy.ops.read_i2c_eeprom(hw, 1483 IXGBE_SFF_VENDOR_OUI_BYTE1, 1484 &oui_bytes[1]); 1485 1486 if (status != IXGBE_SUCCESS) 1487 goto err_read_i2c_eeprom; 1488 1489 status = hw->phy.ops.read_i2c_eeprom(hw, 1490 IXGBE_SFF_VENDOR_OUI_BYTE2, 1491 &oui_bytes[2]); 1492 1493 if (status != IXGBE_SUCCESS) 1494 goto err_read_i2c_eeprom; 1495 1496 vendor_oui = 1497 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1498 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1499 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1500 1501 switch (vendor_oui) { 1502 case IXGBE_SFF_VENDOR_OUI_TYCO: 1503 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1504 hw->phy.type = 1505 ixgbe_phy_sfp_passive_tyco; 1506 break; 1507 case IXGBE_SFF_VENDOR_OUI_FTL: 1508 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1509 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1510 else 1511 hw->phy.type = ixgbe_phy_sfp_ftl; 1512 break; 1513 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1514 hw->phy.type = ixgbe_phy_sfp_avago; 1515 break; 1516 case IXGBE_SFF_VENDOR_OUI_INTEL: 1517 hw->phy.type = ixgbe_phy_sfp_intel; 1518 break; 1519 default: 1520 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1521 hw->phy.type = 1522 ixgbe_phy_sfp_passive_unknown; 1523 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1524 hw->phy.type = 1525 ixgbe_phy_sfp_active_unknown; 1526 else 1527 hw->phy.type = ixgbe_phy_sfp_unknown; 1528 break; 1529 } 1530 } 1531 1532 /* Allow any DA cable vendor */ 1533 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1534 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1535 status = IXGBE_SUCCESS; 1536 goto out; 1537 } 1538 1539 /* Verify supported 1G SFP modules */ 1540 if (comp_codes_10g == 0 && 1541 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1543 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1544 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1545 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1546 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1547 hw->phy.type = ixgbe_phy_sfp_unsupported; 1548 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1549 goto out; 1550 } 1551 1552 /* Anything else 82598-based is supported */ 1553 if (hw->mac.type == ixgbe_mac_82598EB) { 1554 status = IXGBE_SUCCESS; 1555 goto out; 1556 } 1557 1558 ixgbe_get_device_caps(hw, &enforce_sfp); 1559 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1560 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1561 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1562 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1563 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1564 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1565 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1566 /* Make sure we're a supported PHY type */ 1567 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1568 status = IXGBE_SUCCESS; 1569 } else { 1570 if (hw->allow_unsupported_sfp == TRUE) { 1571 EWARN(hw, "WARNING: Intel (R) Network " 1572 "Connections are quality tested " 1573 "using Intel (R) Ethernet Optics." 1574 " Using untested modules is not " 1575 "supported and may cause unstable" 1576 " operation or damage to the " 1577 "module or the adapter. Intel " 1578 "Corporation is not responsible " 1579 "for any harm caused by using " 1580 "untested modules.\n", status); 1581 status = IXGBE_SUCCESS; 1582 } else { 1583 DEBUGOUT("SFP+ module not supported\n"); 1584 hw->phy.type = 1585 ixgbe_phy_sfp_unsupported; 1586 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1587 } 1588 } 1589 } else { 1590 status = IXGBE_SUCCESS; 1591 } 1592 } 1593 1594 out: 1595 return status; 1596 1597 err_read_i2c_eeprom: 1598 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1599 if (hw->phy.type != ixgbe_phy_nl) { 1600 hw->phy.id = 0; 1601 hw->phy.type = ixgbe_phy_unknown; 1602 } 1603 return IXGBE_ERR_SFP_NOT_PRESENT; 1604 } 1605 1606 /** 1607 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1608 * @hw: pointer to hardware structure 1609 * 1610 * Determines physical layer capabilities of the current SFP. 1611 */ 1612 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1613 { 1614 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1615 u8 comp_codes_10g = 0; 1616 u8 comp_codes_1g = 0; 1617 1618 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1619 1620 hw->phy.ops.identify_sfp(hw); 1621 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1622 return physical_layer; 1623 1624 switch (hw->phy.type) { 1625 case ixgbe_phy_sfp_passive_tyco: 1626 case ixgbe_phy_sfp_passive_unknown: 1627 case ixgbe_phy_qsfp_passive_unknown: 1628 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1629 break; 1630 case ixgbe_phy_sfp_ftl_active: 1631 case ixgbe_phy_sfp_active_unknown: 1632 case ixgbe_phy_qsfp_active_unknown: 1633 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1634 break; 1635 case ixgbe_phy_sfp_avago: 1636 case ixgbe_phy_sfp_ftl: 1637 case ixgbe_phy_sfp_intel: 1638 case ixgbe_phy_sfp_unknown: 1639 hw->phy.ops.read_i2c_eeprom(hw, 1640 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1641 hw->phy.ops.read_i2c_eeprom(hw, 1642 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1643 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1644 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1645 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1646 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1647 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1648 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1649 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1650 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1651 break; 1652 case ixgbe_phy_qsfp_intel: 1653 case ixgbe_phy_qsfp_unknown: 1654 hw->phy.ops.read_i2c_eeprom(hw, 1655 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1656 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1657 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1658 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1659 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1660 break; 1661 default: 1662 break; 1663 } 1664 1665 return physical_layer; 1666 } 1667 1668 /** 1669 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1670 * @hw: pointer to hardware structure 1671 * 1672 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1673 **/ 1674 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1675 { 1676 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1677 u32 vendor_oui = 0; 1678 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1679 u8 identifier = 0; 1680 u8 comp_codes_1g = 0; 1681 u8 comp_codes_10g = 0; 1682 u8 oui_bytes[3] = {0, 0, 0}; 1683 u16 enforce_sfp = 0; 1684 u8 connector = 0; 1685 u8 cable_length = 0; 1686 u8 device_tech = 0; 1687 bool active_cable = FALSE; 1688 1689 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1690 1691 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1692 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1693 status = IXGBE_ERR_SFP_NOT_PRESENT; 1694 goto out; 1695 } 1696 1697 /* LAN ID is needed for I2C access */ 1698 hw->mac.ops.set_lan_id(hw); 1699 1700 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1701 &identifier); 1702 1703 if (status != IXGBE_SUCCESS) 1704 goto err_read_i2c_eeprom; 1705 1706 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1707 hw->phy.type = ixgbe_phy_sfp_unsupported; 1708 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1709 goto out; 1710 } 1711 1712 hw->phy.id = identifier; 1713 1714 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1715 &comp_codes_10g); 1716 1717 if (status != IXGBE_SUCCESS) 1718 goto err_read_i2c_eeprom; 1719 1720 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1721 &comp_codes_1g); 1722 1723 if (status != IXGBE_SUCCESS) 1724 goto err_read_i2c_eeprom; 1725 1726 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1727 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1728 if (hw->bus.lan_id == 0) 1729 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1730 else 1731 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1732 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1733 IXGBE_SFF_10GBASELR_CAPABLE)) { 1734 if (hw->bus.lan_id == 0) 1735 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1736 else 1737 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1738 } else { 1739 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1740 active_cable = TRUE; 1741 1742 if (!active_cable) { 1743 /* check for active DA cables that pre-date 1744 * SFF-8436 v3.6 */ 1745 hw->phy.ops.read_i2c_eeprom(hw, 1746 IXGBE_SFF_QSFP_CONNECTOR, 1747 &connector); 1748 1749 hw->phy.ops.read_i2c_eeprom(hw, 1750 IXGBE_SFF_QSFP_CABLE_LENGTH, 1751 &cable_length); 1752 1753 hw->phy.ops.read_i2c_eeprom(hw, 1754 IXGBE_SFF_QSFP_DEVICE_TECH, 1755 &device_tech); 1756 1757 if ((connector == 1758 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1759 (cable_length > 0) && 1760 ((device_tech >> 4) == 1761 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1762 active_cable = TRUE; 1763 } 1764 1765 if (active_cable) { 1766 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1767 if (hw->bus.lan_id == 0) 1768 hw->phy.sfp_type = 1769 ixgbe_sfp_type_da_act_lmt_core0; 1770 else 1771 hw->phy.sfp_type = 1772 ixgbe_sfp_type_da_act_lmt_core1; 1773 } else { 1774 /* unsupported module type */ 1775 hw->phy.type = ixgbe_phy_sfp_unsupported; 1776 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1777 goto out; 1778 } 1779 } 1780 1781 if (hw->phy.sfp_type != stored_sfp_type) 1782 hw->phy.sfp_setup_needed = TRUE; 1783 1784 /* Determine if the QSFP+ PHY is dual speed or not. */ 1785 hw->phy.multispeed_fiber = FALSE; 1786 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1787 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1788 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1789 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1790 hw->phy.multispeed_fiber = TRUE; 1791 1792 /* Determine PHY vendor for optical modules */ 1793 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1794 IXGBE_SFF_10GBASELR_CAPABLE)) { 1795 status = hw->phy.ops.read_i2c_eeprom(hw, 1796 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1797 &oui_bytes[0]); 1798 1799 if (status != IXGBE_SUCCESS) 1800 goto err_read_i2c_eeprom; 1801 1802 status = hw->phy.ops.read_i2c_eeprom(hw, 1803 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1804 &oui_bytes[1]); 1805 1806 if (status != IXGBE_SUCCESS) 1807 goto err_read_i2c_eeprom; 1808 1809 status = hw->phy.ops.read_i2c_eeprom(hw, 1810 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1811 &oui_bytes[2]); 1812 1813 if (status != IXGBE_SUCCESS) 1814 goto err_read_i2c_eeprom; 1815 1816 vendor_oui = 1817 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1818 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1819 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1820 1821 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1822 hw->phy.type = ixgbe_phy_qsfp_intel; 1823 else 1824 hw->phy.type = ixgbe_phy_qsfp_unknown; 1825 1826 ixgbe_get_device_caps(hw, &enforce_sfp); 1827 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1828 /* Make sure we're a supported PHY type */ 1829 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1830 status = IXGBE_SUCCESS; 1831 } else { 1832 if (hw->allow_unsupported_sfp == TRUE) { 1833 EWARN(hw, "WARNING: Intel (R) Network " 1834 "Connections are quality tested " 1835 "using Intel (R) Ethernet Optics." 1836 " Using untested modules is not " 1837 "supported and may cause unstable" 1838 " operation or damage to the " 1839 "module or the adapter. Intel " 1840 "Corporation is not responsible " 1841 "for any harm caused by using " 1842 "untested modules.\n", status); 1843 status = IXGBE_SUCCESS; 1844 } else { 1845 DEBUGOUT("QSFP module not supported\n"); 1846 hw->phy.type = 1847 ixgbe_phy_sfp_unsupported; 1848 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1849 } 1850 } 1851 } else { 1852 status = IXGBE_SUCCESS; 1853 } 1854 } 1855 1856 out: 1857 return status; 1858 1859 err_read_i2c_eeprom: 1860 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1861 hw->phy.id = 0; 1862 hw->phy.type = ixgbe_phy_unknown; 1863 1864 return IXGBE_ERR_SFP_NOT_PRESENT; 1865 } 1866 1867 1868 /** 1869 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1870 * @hw: pointer to hardware structure 1871 * @list_offset: offset to the SFP ID list 1872 * @data_offset: offset to the SFP data block 1873 * 1874 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1875 * so it returns the offsets to the phy init sequence block. 1876 **/ 1877 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1878 u16 *list_offset, 1879 u16 *data_offset) 1880 { 1881 u16 sfp_id; 1882 u16 sfp_type = hw->phy.sfp_type; 1883 1884 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1885 1886 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1887 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1888 1889 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1890 return IXGBE_ERR_SFP_NOT_PRESENT; 1891 1892 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1893 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1894 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1895 1896 /* 1897 * Limiting active cables and 1G Phys must be initialized as 1898 * SR modules 1899 */ 1900 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1901 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1902 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1903 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1904 sfp_type = ixgbe_sfp_type_srlr_core0; 1905 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1906 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1907 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1908 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1909 sfp_type = ixgbe_sfp_type_srlr_core1; 1910 1911 /* Read offset to PHY init contents */ 1912 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1913 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1914 "eeprom read at offset %d failed", 1915 IXGBE_PHY_INIT_OFFSET_NL); 1916 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1917 } 1918 1919 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1920 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1921 1922 /* Shift offset to first ID word */ 1923 (*list_offset)++; 1924 1925 /* 1926 * Find the matching SFP ID in the EEPROM 1927 * and program the init sequence 1928 */ 1929 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1930 goto err_phy; 1931 1932 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1933 if (sfp_id == sfp_type) { 1934 (*list_offset)++; 1935 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1936 goto err_phy; 1937 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1938 DEBUGOUT("SFP+ module not supported\n"); 1939 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1940 } else { 1941 break; 1942 } 1943 } else { 1944 (*list_offset) += 2; 1945 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1946 goto err_phy; 1947 } 1948 } 1949 1950 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1951 DEBUGOUT("No matching SFP+ module found\n"); 1952 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1953 } 1954 1955 return IXGBE_SUCCESS; 1956 1957 err_phy: 1958 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1959 "eeprom read at offset %d failed", *list_offset); 1960 return IXGBE_ERR_PHY; 1961 } 1962 1963 /** 1964 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1965 * @hw: pointer to hardware structure 1966 * @byte_offset: EEPROM byte offset to read 1967 * @eeprom_data: value read 1968 * 1969 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1970 **/ 1971 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1972 u8 *eeprom_data) 1973 { 1974 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1975 1976 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1977 IXGBE_I2C_EEPROM_DEV_ADDR, 1978 eeprom_data); 1979 } 1980 1981 /** 1982 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1983 * @hw: pointer to hardware structure 1984 * @byte_offset: byte offset at address 0xA2 1985 * @eeprom_data: value read 1986 * 1987 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1988 **/ 1989 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1990 u8 *sff8472_data) 1991 { 1992 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1993 IXGBE_I2C_EEPROM_DEV_ADDR2, 1994 sff8472_data); 1995 } 1996 1997 /** 1998 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1999 * @hw: pointer to hardware structure 2000 * @byte_offset: EEPROM byte offset to write 2001 * @eeprom_data: value to write 2002 * 2003 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2004 **/ 2005 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2006 u8 eeprom_data) 2007 { 2008 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2009 2010 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2011 IXGBE_I2C_EEPROM_DEV_ADDR, 2012 eeprom_data); 2013 } 2014 2015 /** 2016 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2017 * @hw: pointer to hardware structure 2018 * @offset: eeprom offset to be read 2019 * @addr: I2C address to be read 2020 */ 2021 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2022 { 2023 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2024 offset == IXGBE_SFF_IDENTIFIER && 2025 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2026 return TRUE; 2027 return FALSE; 2028 } 2029 2030 /** 2031 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2032 * @hw: pointer to hardware structure 2033 * @byte_offset: byte offset to read 2034 * @data: value read 2035 * @lock: TRUE if to take and release semaphore 2036 * 2037 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2038 * a specified device address. 2039 **/ 2040 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2041 u8 dev_addr, u8 *data, bool lock) 2042 { 2043 s32 status; 2044 u32 max_retry = 10; 2045 u32 retry = 0; 2046 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2047 bool nack = 1; 2048 *data = 0; 2049 2050 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2051 2052 if (hw->mac.type >= ixgbe_mac_X550) 2053 max_retry = 3; 2054 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2055 max_retry = IXGBE_SFP_DETECT_RETRIES; 2056 2057 do { 2058 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2059 return IXGBE_ERR_SWFW_SYNC; 2060 2061 ixgbe_i2c_start(hw); 2062 2063 /* Device Address and write indication */ 2064 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2065 if (status != IXGBE_SUCCESS) 2066 goto fail; 2067 2068 status = ixgbe_get_i2c_ack(hw); 2069 if (status != IXGBE_SUCCESS) 2070 goto fail; 2071 2072 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2073 if (status != IXGBE_SUCCESS) 2074 goto fail; 2075 2076 status = ixgbe_get_i2c_ack(hw); 2077 if (status != IXGBE_SUCCESS) 2078 goto fail; 2079 2080 ixgbe_i2c_start(hw); 2081 2082 /* Device Address and read indication */ 2083 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2084 if (status != IXGBE_SUCCESS) 2085 goto fail; 2086 2087 status = ixgbe_get_i2c_ack(hw); 2088 if (status != IXGBE_SUCCESS) 2089 goto fail; 2090 2091 status = ixgbe_clock_in_i2c_byte(hw, data); 2092 if (status != IXGBE_SUCCESS) 2093 goto fail; 2094 2095 status = ixgbe_clock_out_i2c_bit(hw, nack); 2096 if (status != IXGBE_SUCCESS) 2097 goto fail; 2098 2099 ixgbe_i2c_stop(hw); 2100 if (lock) 2101 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2102 return IXGBE_SUCCESS; 2103 2104 fail: 2105 ixgbe_i2c_bus_clear(hw); 2106 if (lock) { 2107 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2108 msec_delay(100); 2109 } 2110 retry++; 2111 if (retry < max_retry) 2112 DEBUGOUT("I2C byte read error - Retrying.\n"); 2113 else 2114 DEBUGOUT("I2C byte read error.\n"); 2115 2116 } while (retry < max_retry); 2117 2118 return status; 2119 } 2120 2121 /** 2122 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2123 * @hw: pointer to hardware structure 2124 * @byte_offset: byte offset to read 2125 * @data: value read 2126 * 2127 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2128 * a specified device address. 2129 **/ 2130 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2131 u8 dev_addr, u8 *data) 2132 { 2133 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2134 data, TRUE); 2135 } 2136 2137 /** 2138 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2139 * @hw: pointer to hardware structure 2140 * @byte_offset: byte offset to read 2141 * @data: value read 2142 * 2143 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2144 * a specified device address. 2145 **/ 2146 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2147 u8 dev_addr, u8 *data) 2148 { 2149 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2150 data, FALSE); 2151 } 2152 2153 /** 2154 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2155 * @hw: pointer to hardware structure 2156 * @byte_offset: byte offset to write 2157 * @data: value to write 2158 * @lock: TRUE if to take and release semaphore 2159 * 2160 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2161 * a specified device address. 2162 **/ 2163 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2164 u8 dev_addr, u8 data, bool lock) 2165 { 2166 s32 status; 2167 u32 max_retry = 2; 2168 u32 retry = 0; 2169 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2170 2171 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2172 2173 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2174 IXGBE_SUCCESS) 2175 return IXGBE_ERR_SWFW_SYNC; 2176 2177 do { 2178 ixgbe_i2c_start(hw); 2179 2180 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2181 if (status != IXGBE_SUCCESS) 2182 goto fail; 2183 2184 status = ixgbe_get_i2c_ack(hw); 2185 if (status != IXGBE_SUCCESS) 2186 goto fail; 2187 2188 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2189 if (status != IXGBE_SUCCESS) 2190 goto fail; 2191 2192 status = ixgbe_get_i2c_ack(hw); 2193 if (status != IXGBE_SUCCESS) 2194 goto fail; 2195 2196 status = ixgbe_clock_out_i2c_byte(hw, data); 2197 if (status != IXGBE_SUCCESS) 2198 goto fail; 2199 2200 status = ixgbe_get_i2c_ack(hw); 2201 if (status != IXGBE_SUCCESS) 2202 goto fail; 2203 2204 ixgbe_i2c_stop(hw); 2205 if (lock) 2206 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2207 return IXGBE_SUCCESS; 2208 2209 fail: 2210 ixgbe_i2c_bus_clear(hw); 2211 retry++; 2212 if (retry < max_retry) 2213 DEBUGOUT("I2C byte write error - Retrying.\n"); 2214 else 2215 DEBUGOUT("I2C byte write error.\n"); 2216 } while (retry < max_retry); 2217 2218 if (lock) 2219 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2220 2221 return status; 2222 } 2223 2224 /** 2225 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2226 * @hw: pointer to hardware structure 2227 * @byte_offset: byte offset to write 2228 * @data: value to write 2229 * 2230 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2231 * a specified device address. 2232 **/ 2233 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2234 u8 dev_addr, u8 data) 2235 { 2236 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2237 data, TRUE); 2238 } 2239 2240 /** 2241 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2242 * @hw: pointer to hardware structure 2243 * @byte_offset: byte offset to write 2244 * @data: value to write 2245 * 2246 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2247 * a specified device address. 2248 **/ 2249 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2250 u8 dev_addr, u8 data) 2251 { 2252 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2253 data, FALSE); 2254 } 2255 2256 /** 2257 * ixgbe_i2c_start - Sets I2C start condition 2258 * @hw: pointer to hardware structure 2259 * 2260 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2261 * Set bit-bang mode on X550 hardware. 2262 **/ 2263 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2264 { 2265 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2266 2267 DEBUGFUNC("ixgbe_i2c_start"); 2268 2269 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2270 2271 /* Start condition must begin with data and clock high */ 2272 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2273 ixgbe_raise_i2c_clk(hw, &i2cctl); 2274 2275 /* Setup time for start condition (4.7us) */ 2276 usec_delay(IXGBE_I2C_T_SU_STA); 2277 2278 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2279 2280 /* Hold time for start condition (4us) */ 2281 usec_delay(IXGBE_I2C_T_HD_STA); 2282 2283 ixgbe_lower_i2c_clk(hw, &i2cctl); 2284 2285 /* Minimum low period of clock is 4.7 us */ 2286 usec_delay(IXGBE_I2C_T_LOW); 2287 2288 } 2289 2290 /** 2291 * ixgbe_i2c_stop - Sets I2C stop condition 2292 * @hw: pointer to hardware structure 2293 * 2294 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2295 * Disables bit-bang mode and negates data output enable on X550 2296 * hardware. 2297 **/ 2298 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2299 { 2300 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2301 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2302 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2303 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2304 2305 DEBUGFUNC("ixgbe_i2c_stop"); 2306 2307 /* Stop condition must begin with data low and clock high */ 2308 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2309 ixgbe_raise_i2c_clk(hw, &i2cctl); 2310 2311 /* Setup time for stop condition (4us) */ 2312 usec_delay(IXGBE_I2C_T_SU_STO); 2313 2314 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2315 2316 /* bus free time between stop and start (4.7us)*/ 2317 usec_delay(IXGBE_I2C_T_BUF); 2318 2319 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2320 i2cctl &= ~bb_en_bit; 2321 i2cctl |= data_oe_bit | clk_oe_bit; 2322 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2323 IXGBE_WRITE_FLUSH(hw); 2324 } 2325 } 2326 2327 /** 2328 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2329 * @hw: pointer to hardware structure 2330 * @data: data byte to clock in 2331 * 2332 * Clocks in one byte data via I2C data/clock 2333 **/ 2334 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2335 { 2336 s32 i; 2337 bool bit = 0; 2338 2339 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2340 2341 *data = 0; 2342 for (i = 7; i >= 0; i--) { 2343 ixgbe_clock_in_i2c_bit(hw, &bit); 2344 *data |= bit << i; 2345 } 2346 2347 return IXGBE_SUCCESS; 2348 } 2349 2350 /** 2351 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2352 * @hw: pointer to hardware structure 2353 * @data: data byte clocked out 2354 * 2355 * Clocks out one byte data via I2C data/clock 2356 **/ 2357 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2358 { 2359 s32 status = IXGBE_SUCCESS; 2360 s32 i; 2361 u32 i2cctl; 2362 bool bit; 2363 2364 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2365 2366 for (i = 7; i >= 0; i--) { 2367 bit = (data >> i) & 0x1; 2368 status = ixgbe_clock_out_i2c_bit(hw, bit); 2369 2370 if (status != IXGBE_SUCCESS) 2371 break; 2372 } 2373 2374 /* Release SDA line (set high) */ 2375 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2376 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2377 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2378 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2379 IXGBE_WRITE_FLUSH(hw); 2380 2381 return status; 2382 } 2383 2384 /** 2385 * ixgbe_get_i2c_ack - Polls for I2C ACK 2386 * @hw: pointer to hardware structure 2387 * 2388 * Clocks in/out one bit via I2C data/clock 2389 **/ 2390 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2391 { 2392 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2393 s32 status = IXGBE_SUCCESS; 2394 u32 i = 0; 2395 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2396 u32 timeout = 10; 2397 bool ack = 1; 2398 2399 DEBUGFUNC("ixgbe_get_i2c_ack"); 2400 2401 if (data_oe_bit) { 2402 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2403 i2cctl |= data_oe_bit; 2404 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2405 IXGBE_WRITE_FLUSH(hw); 2406 } 2407 ixgbe_raise_i2c_clk(hw, &i2cctl); 2408 2409 /* Minimum high period of clock is 4us */ 2410 usec_delay(IXGBE_I2C_T_HIGH); 2411 2412 /* Poll for ACK. Note that ACK in I2C spec is 2413 * transition from 1 to 0 */ 2414 for (i = 0; i < timeout; i++) { 2415 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2416 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2417 2418 usec_delay(1); 2419 if (!ack) 2420 break; 2421 } 2422 2423 if (ack) { 2424 DEBUGOUT("I2C ack was not received.\n"); 2425 status = IXGBE_ERR_I2C; 2426 } 2427 2428 ixgbe_lower_i2c_clk(hw, &i2cctl); 2429 2430 /* Minimum low period of clock is 4.7 us */ 2431 usec_delay(IXGBE_I2C_T_LOW); 2432 2433 return status; 2434 } 2435 2436 /** 2437 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2438 * @hw: pointer to hardware structure 2439 * @data: read data value 2440 * 2441 * Clocks in one bit via I2C data/clock 2442 **/ 2443 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2444 { 2445 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2446 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2447 2448 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2449 2450 if (data_oe_bit) { 2451 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2452 i2cctl |= data_oe_bit; 2453 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2454 IXGBE_WRITE_FLUSH(hw); 2455 } 2456 ixgbe_raise_i2c_clk(hw, &i2cctl); 2457 2458 /* Minimum high period of clock is 4us */ 2459 usec_delay(IXGBE_I2C_T_HIGH); 2460 2461 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2462 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2463 2464 ixgbe_lower_i2c_clk(hw, &i2cctl); 2465 2466 /* Minimum low period of clock is 4.7 us */ 2467 usec_delay(IXGBE_I2C_T_LOW); 2468 2469 return IXGBE_SUCCESS; 2470 } 2471 2472 /** 2473 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2474 * @hw: pointer to hardware structure 2475 * @data: data value to write 2476 * 2477 * Clocks out one bit via I2C data/clock 2478 **/ 2479 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2480 { 2481 s32 status; 2482 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2483 2484 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2485 2486 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2487 if (status == IXGBE_SUCCESS) { 2488 ixgbe_raise_i2c_clk(hw, &i2cctl); 2489 2490 /* Minimum high period of clock is 4us */ 2491 usec_delay(IXGBE_I2C_T_HIGH); 2492 2493 ixgbe_lower_i2c_clk(hw, &i2cctl); 2494 2495 /* Minimum low period of clock is 4.7 us. 2496 * This also takes care of the data hold time. 2497 */ 2498 usec_delay(IXGBE_I2C_T_LOW); 2499 } else { 2500 status = IXGBE_ERR_I2C; 2501 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2502 "I2C data was not set to %X\n", data); 2503 } 2504 2505 return status; 2506 } 2507 2508 /** 2509 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2510 * @hw: pointer to hardware structure 2511 * @i2cctl: Current value of I2CCTL register 2512 * 2513 * Raises the I2C clock line '0'->'1' 2514 * Negates the I2C clock output enable on X550 hardware. 2515 **/ 2516 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2517 { 2518 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2519 u32 i = 0; 2520 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2521 u32 i2cctl_r = 0; 2522 2523 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2524 2525 if (clk_oe_bit) { 2526 *i2cctl |= clk_oe_bit; 2527 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2528 } 2529 2530 for (i = 0; i < timeout; i++) { 2531 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2532 2533 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2534 IXGBE_WRITE_FLUSH(hw); 2535 /* SCL rise time (1000ns) */ 2536 usec_delay(IXGBE_I2C_T_RISE); 2537 2538 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2539 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2540 break; 2541 } 2542 } 2543 2544 /** 2545 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2546 * @hw: pointer to hardware structure 2547 * @i2cctl: Current value of I2CCTL register 2548 * 2549 * Lowers the I2C clock line '1'->'0' 2550 * Asserts the I2C clock output enable on X550 hardware. 2551 **/ 2552 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2553 { 2554 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2555 2556 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2557 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2558 2559 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2560 IXGBE_WRITE_FLUSH(hw); 2561 2562 /* SCL fall time (300ns) */ 2563 usec_delay(IXGBE_I2C_T_FALL); 2564 } 2565 2566 /** 2567 * ixgbe_set_i2c_data - Sets the I2C data bit 2568 * @hw: pointer to hardware structure 2569 * @i2cctl: Current value of I2CCTL register 2570 * @data: I2C data value (0 or 1) to set 2571 * 2572 * Sets the I2C data bit 2573 * Asserts the I2C data output enable on X550 hardware. 2574 **/ 2575 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2576 { 2577 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2578 s32 status = IXGBE_SUCCESS; 2579 2580 DEBUGFUNC("ixgbe_set_i2c_data"); 2581 2582 if (data) 2583 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2584 else 2585 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2586 *i2cctl &= ~data_oe_bit; 2587 2588 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2589 IXGBE_WRITE_FLUSH(hw); 2590 2591 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2592 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2593 2594 if (!data) /* Can't verify data in this case */ 2595 return IXGBE_SUCCESS; 2596 if (data_oe_bit) { 2597 *i2cctl |= data_oe_bit; 2598 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2599 IXGBE_WRITE_FLUSH(hw); 2600 } 2601 2602 /* Verify data was set correctly */ 2603 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2604 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2605 status = IXGBE_ERR_I2C; 2606 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2607 "Error - I2C data was not set to %X.\n", 2608 data); 2609 } 2610 2611 return status; 2612 } 2613 2614 /** 2615 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2616 * @hw: pointer to hardware structure 2617 * @i2cctl: Current value of I2CCTL register 2618 * 2619 * Returns the I2C data bit value 2620 * Negates the I2C data output enable on X550 hardware. 2621 **/ 2622 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2623 { 2624 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2625 bool data; 2626 2627 DEBUGFUNC("ixgbe_get_i2c_data"); 2628 2629 if (data_oe_bit) { 2630 *i2cctl |= data_oe_bit; 2631 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2632 IXGBE_WRITE_FLUSH(hw); 2633 usec_delay(IXGBE_I2C_T_FALL); 2634 } 2635 2636 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2637 data = 1; 2638 else 2639 data = 0; 2640 2641 return data; 2642 } 2643 2644 /** 2645 * ixgbe_i2c_bus_clear - Clears the I2C bus 2646 * @hw: pointer to hardware structure 2647 * 2648 * Clears the I2C bus by sending nine clock pulses. 2649 * Used when data line is stuck low. 2650 **/ 2651 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2652 { 2653 u32 i2cctl; 2654 u32 i; 2655 2656 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2657 2658 ixgbe_i2c_start(hw); 2659 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2660 2661 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2662 2663 for (i = 0; i < 9; i++) { 2664 ixgbe_raise_i2c_clk(hw, &i2cctl); 2665 2666 /* Min high period of clock is 4us */ 2667 usec_delay(IXGBE_I2C_T_HIGH); 2668 2669 ixgbe_lower_i2c_clk(hw, &i2cctl); 2670 2671 /* Min low period of clock is 4.7us*/ 2672 usec_delay(IXGBE_I2C_T_LOW); 2673 } 2674 2675 ixgbe_i2c_start(hw); 2676 2677 /* Put the i2c bus back to default state */ 2678 ixgbe_i2c_stop(hw); 2679 } 2680 2681 /** 2682 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2683 * @hw: pointer to hardware structure 2684 * 2685 * Checks if the LASI temp alarm status was triggered due to overtemp 2686 **/ 2687 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2688 { 2689 s32 status = IXGBE_SUCCESS; 2690 u16 phy_data = 0; 2691 2692 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2693 2694 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2695 goto out; 2696 2697 /* Check that the LASI temp alarm status was triggered */ 2698 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2699 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2700 2701 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2702 goto out; 2703 2704 status = IXGBE_ERR_OVERTEMP; 2705 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2706 out: 2707 return status; 2708 } 2709 2710 /** 2711 * ixgbe_set_copper_phy_power - Control power for copper phy 2712 * @hw: pointer to hardware structure 2713 * @on: TRUE for on, FALSE for off 2714 */ 2715 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2716 { 2717 u32 status; 2718 u16 reg; 2719 2720 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2721 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2722 ®); 2723 if (status) 2724 return status; 2725 2726 if (on) { 2727 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2728 } else { 2729 if (ixgbe_check_reset_blocked(hw)) 2730 return 0; 2731 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2732 } 2733 2734 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2735 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2736 reg); 2737 return status; 2738 } 2739
Indexes created Thu Sep 25 16:09:42 GMT 2025