ixgbe_phy.h revision 1.6
1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 280182 2015-03-17 18:32:28Z jfv $*/ 34 /*$NetBSD: ixgbe_phy.h,v 1.6 2016/12/01 06:27:18 msaitoh Exp $*/ 35 36 #ifndef _IXGBE_PHY_H_ 37 #define _IXGBE_PHY_H_ 38 39 #include "ixgbe_type.h" 40 #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 41 #define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2 42 #define IXGBE_I2C_EEPROM_BANK_LEN 0xFF 43 44 /* EEPROM byte offsets */ 45 #define IXGBE_SFF_IDENTIFIER 0x0 46 #define IXGBE_SFF_IDENTIFIER_SFP 0x3 47 #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 48 #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 49 #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 50 #define IXGBE_SFF_1GBE_COMP_CODES 0x6 51 #define IXGBE_SFF_10GBE_COMP_CODES 0x3 52 #define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 53 #define IXGBE_SFF_CABLE_SPEC_COMP 0x3C 54 #define IXGBE_SFF_SFF_8472_SWAP 0x5C 55 #define IXGBE_SFF_SFF_8472_COMP 0x5E 56 #define IXGBE_SFF_SFF_8472_OSCB 0x6E 57 #define IXGBE_SFF_SFF_8472_ESCB 0x76 58 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD 59 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5 60 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6 61 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7 62 #define IXGBE_SFF_QSFP_CONNECTOR 0x82 63 #define IXGBE_SFF_QSFP_10GBE_COMP 0x83 64 #define IXGBE_SFF_QSFP_1GBE_COMP 0x86 65 #define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92 66 #define IXGBE_SFF_QSFP_DEVICE_TECH 0x93 67 68 /* Bitmasks */ 69 #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 70 #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 71 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 72 #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 73 #define IXGBE_SFF_1GBASELX_CAPABLE 0x2 74 #define IXGBE_SFF_1GBASET_CAPABLE 0x8 75 #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 76 #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 77 #define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 78 #define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8 79 #define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0 80 #define IXGBE_SFF_ADDRESSING_MODE 0x4 81 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1 82 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8 83 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23 84 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0 85 #define IXGBE_I2C_EEPROM_READ_MASK 0x100 86 #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 87 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 88 #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 89 #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 90 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 91 92 #define IXGBE_CS4227 0xBE /* CS4227 address */ 93 #define IXGBE_CS4227_SPARE24_LSB 0x12B0 /* Reg to program EDC */ 94 #define IXGBE_CS4227_EDC_MODE_CX1 0x0002 95 #define IXGBE_CS4227_EDC_MODE_SR 0x0004 96 97 /* Flow control defines */ 98 #define IXGBE_TAF_SYM_PAUSE 0x400 99 #define IXGBE_TAF_ASM_PAUSE 0x800 100 101 /* Bit-shift macros */ 102 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24 103 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16 104 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8 105 106 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 107 #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 108 #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 109 #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 110 #define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100 111 112 /* I2C SDA and SCL timing parameters for standard mode */ 113 #define IXGBE_I2C_T_HD_STA 4 114 #define IXGBE_I2C_T_LOW 5 115 #define IXGBE_I2C_T_HIGH 4 116 #define IXGBE_I2C_T_SU_STA 5 117 #define IXGBE_I2C_T_HD_DATA 5 118 #define IXGBE_I2C_T_SU_DATA 1 119 #define IXGBE_I2C_T_RISE 1 120 #define IXGBE_I2C_T_FALL 1 121 #define IXGBE_I2C_T_SU_STO 4 122 #define IXGBE_I2C_T_BUF 5 123 124 #ifndef IXGBE_SFP_DETECT_RETRIES 125 #define IXGBE_SFP_DETECT_RETRIES 10 126 127 #endif /* IXGBE_SFP_DETECT_RETRIES */ 128 #define IXGBE_TN_LASI_STATUS_REG 0x9005 129 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 130 131 /* SFP+ SFF-8472 Compliance */ 132 #define IXGBE_SFF_SFF_8472_UNSUP 0x00 133 134 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 135 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 136 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 137 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 138 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 139 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 140 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 141 u16 *phy_data); 142 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 143 u16 phy_data); 144 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 145 u32 device_type, u16 *phy_data); 146 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 147 u32 device_type, u16 phy_data); 148 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); 149 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 150 ixgbe_link_speed speed, 151 bool autoneg_wait_to_complete); 152 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 153 ixgbe_link_speed *speed, 154 bool *autoneg); 155 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw); 156 157 /* PHY specific */ 158 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 159 ixgbe_link_speed *speed, 160 bool *link_up); 161 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw); 162 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 163 u16 *firmware_version); 164 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 165 u16 *firmware_version); 166 167 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 168 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on); 169 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw); 170 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 171 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw); 172 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 173 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 174 u16 *list_offset, 175 u16 *data_offset); 176 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); 177 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 178 u8 dev_addr, u8 *data); 179 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 180 u8 dev_addr, u8 data); 181 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 182 u8 *eeprom_data); 183 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 184 u8 eeprom_data); 185 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 186 #endif /* _IXGBE_PHY_H_ */ 187
Indexes created Mon Sep 29 15:09:53 GMT 2025