ixgbe_phy.h revision 1.9
1 /* $NetBSD: ixgbe_phy.h,v 1.9 2017/08/30 08:49:18 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2017, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 320688 2017-07-05 17:27:03Z erj $*/ 36 37 #ifndef _IXGBE_PHY_H_ 38 #define _IXGBE_PHY_H_ 39 40 #include "ixgbe_type.h" 41 #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 42 #define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2 43 #define IXGBE_I2C_EEPROM_BANK_LEN 0xFF 44 45 /* EEPROM byte offsets */ 46 #define IXGBE_SFF_IDENTIFIER 0x0 47 #define IXGBE_SFF_IDENTIFIER_SFP 0x3 48 #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 49 #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 50 #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 51 #define IXGBE_SFF_1GBE_COMP_CODES 0x6 52 #define IXGBE_SFF_10GBE_COMP_CODES 0x3 53 #define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 54 #define IXGBE_SFF_CABLE_SPEC_COMP 0x3C 55 #define IXGBE_SFF_SFF_8472_SWAP 0x5C 56 #define IXGBE_SFF_SFF_8472_COMP 0x5E 57 #define IXGBE_SFF_SFF_8472_OSCB 0x6E 58 #define IXGBE_SFF_SFF_8472_ESCB 0x76 59 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD 60 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5 61 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6 62 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7 63 #define IXGBE_SFF_QSFP_CONNECTOR 0x82 64 #define IXGBE_SFF_QSFP_10GBE_COMP 0x83 65 #define IXGBE_SFF_QSFP_1GBE_COMP 0x86 66 #define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92 67 #define IXGBE_SFF_QSFP_DEVICE_TECH 0x93 68 69 /* Bitmasks */ 70 #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 71 #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 72 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 73 #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 74 #define IXGBE_SFF_1GBASELX_CAPABLE 0x2 75 #define IXGBE_SFF_1GBASET_CAPABLE 0x8 76 #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 77 #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 78 #define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 79 #define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8 80 #define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0 81 #define IXGBE_SFF_ADDRESSING_MODE 0x4 82 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1 83 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8 84 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23 85 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0 86 #define IXGBE_I2C_EEPROM_READ_MASK 0x100 87 #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 88 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 89 #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 90 #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 91 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 92 93 #define IXGBE_CS4227 0xBE /* CS4227 address */ 94 #define IXGBE_CS4227_GLOBAL_ID_LSB 0 95 #define IXGBE_CS4227_GLOBAL_ID_MSB 1 96 #define IXGBE_CS4227_SCRATCH 2 97 #define IXGBE_CS4227_GLOBAL_ID_VALUE 0x03E5 98 #define IXGBE_CS4227_EFUSE_PDF_SKU 0x19F 99 #define IXGBE_CS4223_SKU_ID 0x0010 /* Quad port */ 100 #define IXGBE_CS4227_SKU_ID 0x0014 /* Dual port */ 101 #define IXGBE_CS4227_RESET_PENDING 0x1357 102 #define IXGBE_CS4227_RESET_COMPLETE 0x5AA5 103 #define IXGBE_CS4227_RETRIES 15 104 #define IXGBE_CS4227_EFUSE_STATUS 0x0181 105 #define IXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to program speed */ 106 #define IXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to program EDC */ 107 #define IXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to program speed */ 108 #define IXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */ 109 #define IXGBE_CS4227_EEPROM_STATUS 0x5001 110 #define IXGBE_CS4227_EEPROM_LOAD_OK 0x0001 111 #define IXGBE_CS4227_SPEED_1G 0x8000 112 #define IXGBE_CS4227_SPEED_10G 0 113 #define IXGBE_CS4227_EDC_MODE_CX1 0x0002 114 #define IXGBE_CS4227_EDC_MODE_SR 0x0004 115 #define IXGBE_CS4227_EDC_MODE_DIAG 0x0008 116 #define IXGBE_CS4227_RESET_HOLD 500 /* microseconds */ 117 #define IXGBE_CS4227_RESET_DELAY 450 /* milliseconds */ 118 #define IXGBE_CS4227_CHECK_DELAY 30 /* milliseconds */ 119 #define IXGBE_PE 0xE0 /* Port expander address */ 120 #define IXGBE_PE_OUTPUT 1 /* Output register offset */ 121 #define IXGBE_PE_CONFIG 3 /* Config register offset */ 122 #define IXGBE_PE_BIT1 (1 << 1) 123 124 /* Flow control defines */ 125 #define IXGBE_TAF_SYM_PAUSE 0x400 126 #define IXGBE_TAF_ASM_PAUSE 0x800 127 128 /* Bit-shift macros */ 129 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24 130 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16 131 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8 132 133 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 134 #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 135 #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 136 #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 137 #define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100 138 139 /* I2C SDA and SCL timing parameters for standard mode */ 140 #define IXGBE_I2C_T_HD_STA 4 141 #define IXGBE_I2C_T_LOW 5 142 #define IXGBE_I2C_T_HIGH 4 143 #define IXGBE_I2C_T_SU_STA 5 144 #define IXGBE_I2C_T_HD_DATA 5 145 #define IXGBE_I2C_T_SU_DATA 1 146 #define IXGBE_I2C_T_RISE 1 147 #define IXGBE_I2C_T_FALL 1 148 #define IXGBE_I2C_T_SU_STO 4 149 #define IXGBE_I2C_T_BUF 5 150 151 #ifndef IXGBE_SFP_DETECT_RETRIES 152 #define IXGBE_SFP_DETECT_RETRIES 10 153 154 #endif /* IXGBE_SFP_DETECT_RETRIES */ 155 #define IXGBE_TN_LASI_STATUS_REG 0x9005 156 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 157 158 /* SFP+ SFF-8472 Compliance */ 159 #define IXGBE_SFF_SFF_8472_UNSUP 0x00 160 161 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 162 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 163 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 164 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 165 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 166 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 167 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 168 u16 *phy_data); 169 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 170 u16 phy_data); 171 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 172 u32 device_type, u16 *phy_data); 173 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 174 u32 device_type, u16 phy_data); 175 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); 176 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 177 ixgbe_link_speed speed, 178 bool autoneg_wait_to_complete); 179 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 180 ixgbe_link_speed *speed, 181 bool *autoneg); 182 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw); 183 184 /* PHY specific */ 185 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 186 ixgbe_link_speed *speed, 187 bool *link_up); 188 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw); 189 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 190 u16 *firmware_version); 191 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 192 u16 *firmware_version); 193 194 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 195 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on); 196 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw); 197 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 198 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw); 199 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 200 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 201 u16 *list_offset, 202 u16 *data_offset); 203 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); 204 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 205 u8 dev_addr, u8 *data); 206 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 207 u8 dev_addr, u8 *data); 208 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 209 u8 dev_addr, u8 data); 210 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 211 u8 dev_addr, u8 data); 212 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 213 u8 *eeprom_data); 214 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 215 u8 eeprom_data); 216 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 217 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, 218 u16 *val, bool lock); 219 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, 220 u16 val, bool lock); 221 #endif /* _IXGBE_PHY_H_ */ 222
Indexes created Sun Sep 28 07:09:56 GMT 2025