ixgbe_x540.c revision 1.2.2.2
1 1.2.2.2 skrll /****************************************************************************** 2 1.2.2.2 skrll 3 1.2.2.2 skrll Copyright (c) 2001-2012, Intel Corporation 4 1.2.2.2 skrll All rights reserved. 5 1.2.2.2 skrll 6 1.2.2.2 skrll Redistribution and use in source and binary forms, with or without 7 1.2.2.2 skrll modification, are permitted provided that the following conditions are met: 8 1.2.2.2 skrll 9 1.2.2.2 skrll 1. Redistributions of source code must retain the above copyright notice, 10 1.2.2.2 skrll this list of conditions and the following disclaimer. 11 1.2.2.2 skrll 12 1.2.2.2 skrll 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll 16 1.2.2.2 skrll 3. Neither the name of the Intel Corporation nor the names of its 17 1.2.2.2 skrll contributors may be used to endorse or promote products derived from 18 1.2.2.2 skrll this software without specific prior written permission. 19 1.2.2.2 skrll 20 1.2.2.2 skrll THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.2.2.2 skrll AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.2.2.2 skrll IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.2.2.2 skrll ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.2.2.2 skrll LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.2.2.2 skrll CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.2.2.2 skrll SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.2.2.2 skrll INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.2.2.2 skrll CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.2.2.2 skrll ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.2.2.2 skrll POSSIBILITY OF SUCH DAMAGE. 31 1.2.2.2 skrll 32 1.2.2.2 skrll ******************************************************************************/ 33 1.2.2.2 skrll /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 238149 2012-07-05 20:51:44Z jfv $*/ 34 1.2.2.2 skrll 35 1.2.2.2 skrll #include "ixgbe_x540.h" 36 1.2.2.2 skrll #include "ixgbe_type.h" 37 1.2.2.2 skrll #include "ixgbe_api.h" 38 1.2.2.2 skrll #include "ixgbe_common.h" 39 1.2.2.2 skrll #include "ixgbe_phy.h" 40 1.2.2.2 skrll 41 1.2.2.2 skrll static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 42 1.2.2.2 skrll static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 43 1.2.2.2 skrll static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 44 1.2.2.2 skrll static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 45 1.2.2.2 skrll 46 1.2.2.2 skrll /** 47 1.2.2.2 skrll * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 48 1.2.2.2 skrll * @hw: pointer to hardware structure 49 1.2.2.2 skrll * 50 1.2.2.2 skrll * Initialize the function pointers and assign the MAC type for X540. 51 1.2.2.2 skrll * Does not touch the hardware. 52 1.2.2.2 skrll **/ 53 1.2.2.2 skrll s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 54 1.2.2.2 skrll { 55 1.2.2.2 skrll struct ixgbe_mac_info *mac = &hw->mac; 56 1.2.2.2 skrll struct ixgbe_phy_info *phy = &hw->phy; 57 1.2.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 58 1.2.2.2 skrll s32 ret_val; 59 1.2.2.2 skrll 60 1.2.2.2 skrll DEBUGFUNC("ixgbe_init_ops_X540"); 61 1.2.2.2 skrll 62 1.2.2.2 skrll ret_val = ixgbe_init_phy_ops_generic(hw); 63 1.2.2.2 skrll ret_val = ixgbe_init_ops_generic(hw); 64 1.2.2.2 skrll 65 1.2.2.2 skrll 66 1.2.2.2 skrll /* EEPROM */ 67 1.2.2.2 skrll eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540; 68 1.2.2.2 skrll eeprom->ops.read = &ixgbe_read_eerd_X540; 69 1.2.2.2 skrll eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540; 70 1.2.2.2 skrll eeprom->ops.write = &ixgbe_write_eewr_X540; 71 1.2.2.2 skrll eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540; 72 1.2.2.2 skrll eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540; 73 1.2.2.2 skrll eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540; 74 1.2.2.2 skrll eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540; 75 1.2.2.2 skrll 76 1.2.2.2 skrll /* PHY */ 77 1.2.2.2 skrll phy->ops.init = &ixgbe_init_phy_ops_generic; 78 1.2.2.2 skrll phy->ops.reset = NULL; 79 1.2.2.2 skrll 80 1.2.2.2 skrll /* MAC */ 81 1.2.2.2 skrll mac->ops.reset_hw = &ixgbe_reset_hw_X540; 82 1.2.2.2 skrll mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 83 1.2.2.2 skrll mac->ops.get_media_type = &ixgbe_get_media_type_X540; 84 1.2.2.2 skrll mac->ops.get_supported_physical_layer = 85 1.2.2.2 skrll &ixgbe_get_supported_physical_layer_X540; 86 1.2.2.2 skrll mac->ops.read_analog_reg8 = NULL; 87 1.2.2.2 skrll mac->ops.write_analog_reg8 = NULL; 88 1.2.2.2 skrll mac->ops.start_hw = &ixgbe_start_hw_X540; 89 1.2.2.2 skrll mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 90 1.2.2.2 skrll mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 91 1.2.2.2 skrll mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 92 1.2.2.2 skrll mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 93 1.2.2.2 skrll mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 94 1.2.2.2 skrll mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540; 95 1.2.2.2 skrll mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540; 96 1.2.2.2 skrll mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 97 1.2.2.2 skrll mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 98 1.2.2.2 skrll 99 1.2.2.2 skrll /* RAR, Multicast, VLAN */ 100 1.2.2.2 skrll mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 101 1.2.2.2 skrll mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic; 102 1.2.2.2 skrll mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 103 1.2.2.2 skrll mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 104 1.2.2.2 skrll mac->rar_highwater = 1; 105 1.2.2.2 skrll mac->ops.set_vfta = &ixgbe_set_vfta_generic; 106 1.2.2.2 skrll mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; 107 1.2.2.2 skrll mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 108 1.2.2.2 skrll mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 109 1.2.2.2 skrll mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 110 1.2.2.2 skrll mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 111 1.2.2.2 skrll 112 1.2.2.2 skrll /* Link */ 113 1.2.2.2 skrll mac->ops.get_link_capabilities = 114 1.2.2.2 skrll &ixgbe_get_copper_link_capabilities_generic; 115 1.2.2.2 skrll mac->ops.setup_link = &ixgbe_setup_mac_link_X540; 116 1.2.2.2 skrll mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; 117 1.2.2.2 skrll mac->ops.check_link = &ixgbe_check_mac_link_generic; 118 1.2.2.2 skrll 119 1.2.2.2 skrll mac->mcft_size = 128; 120 1.2.2.2 skrll mac->vft_size = 128; 121 1.2.2.2 skrll mac->num_rar_entries = 128; 122 1.2.2.2 skrll mac->rx_pb_size = 384; 123 1.2.2.2 skrll mac->max_tx_queues = 128; 124 1.2.2.2 skrll mac->max_rx_queues = 128; 125 1.2.2.2 skrll mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 126 1.2.2.2 skrll 127 1.2.2.2 skrll /* 128 1.2.2.2 skrll * FWSM register 129 1.2.2.2 skrll * ARC supported; valid only if manageability features are 130 1.2.2.2 skrll * enabled. 131 1.2.2.2 skrll */ 132 1.2.2.2 skrll mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & 133 1.2.2.2 skrll IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; 134 1.2.2.2 skrll 135 1.2.2.2 skrll hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 136 1.2.2.2 skrll 137 1.2.2.2 skrll /* LEDs */ 138 1.2.2.2 skrll mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 139 1.2.2.2 skrll mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 140 1.2.2.2 skrll 141 1.2.2.2 skrll /* Manageability interface */ 142 1.2.2.2 skrll mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; 143 1.2.2.2 skrll 144 1.2.2.2 skrll return ret_val; 145 1.2.2.2 skrll } 146 1.2.2.2 skrll 147 1.2.2.2 skrll /** 148 1.2.2.2 skrll * ixgbe_get_link_capabilities_X540 - Determines link capabilities 149 1.2.2.2 skrll * @hw: pointer to hardware structure 150 1.2.2.2 skrll * @speed: pointer to link speed 151 1.2.2.2 skrll * @autoneg: TRUE when autoneg or autotry is enabled 152 1.2.2.2 skrll * 153 1.2.2.2 skrll * Determines the link capabilities by reading the AUTOC register. 154 1.2.2.2 skrll **/ 155 1.2.2.2 skrll s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 156 1.2.2.2 skrll ixgbe_link_speed *speed, 157 1.2.2.2 skrll bool *autoneg) 158 1.2.2.2 skrll { 159 1.2.2.2 skrll ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 160 1.2.2.2 skrll 161 1.2.2.2 skrll return IXGBE_SUCCESS; 162 1.2.2.2 skrll } 163 1.2.2.2 skrll 164 1.2.2.2 skrll /** 165 1.2.2.2 skrll * ixgbe_get_media_type_X540 - Get media type 166 1.2.2.2 skrll * @hw: pointer to hardware structure 167 1.2.2.2 skrll * 168 1.2.2.2 skrll * Returns the media type (fiber, copper, backplane) 169 1.2.2.2 skrll **/ 170 1.2.2.2 skrll enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 171 1.2.2.2 skrll { 172 1.2.2.2 skrll UNREFERENCED_1PARAMETER(hw); 173 1.2.2.2 skrll return ixgbe_media_type_copper; 174 1.2.2.2 skrll } 175 1.2.2.2 skrll 176 1.2.2.2 skrll /** 177 1.2.2.2 skrll * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 178 1.2.2.2 skrll * @hw: pointer to hardware structure 179 1.2.2.2 skrll * @speed: new link speed 180 1.2.2.2 skrll * @autoneg: TRUE if autonegotiation enabled 181 1.2.2.2 skrll * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 182 1.2.2.2 skrll **/ 183 1.2.2.2 skrll s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 184 1.2.2.2 skrll ixgbe_link_speed speed, bool autoneg, 185 1.2.2.2 skrll bool autoneg_wait_to_complete) 186 1.2.2.2 skrll { 187 1.2.2.2 skrll DEBUGFUNC("ixgbe_setup_mac_link_X540"); 188 1.2.2.2 skrll return hw->phy.ops.setup_link_speed(hw, speed, autoneg, 189 1.2.2.2 skrll autoneg_wait_to_complete); 190 1.2.2.2 skrll } 191 1.2.2.2 skrll 192 1.2.2.2 skrll /** 193 1.2.2.2 skrll * ixgbe_reset_hw_X540 - Perform hardware reset 194 1.2.2.2 skrll * @hw: pointer to hardware structure 195 1.2.2.2 skrll * 196 1.2.2.2 skrll * Resets the hardware by resetting the transmit and receive units, masks 197 1.2.2.2 skrll * and clears all interrupts, and perform a reset. 198 1.2.2.2 skrll **/ 199 1.2.2.2 skrll s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 200 1.2.2.2 skrll { 201 1.2.2.2 skrll s32 status; 202 1.2.2.2 skrll u32 ctrl, i; 203 1.2.2.2 skrll 204 1.2.2.2 skrll DEBUGFUNC("ixgbe_reset_hw_X540"); 205 1.2.2.2 skrll 206 1.2.2.2 skrll /* Call adapter stop to disable tx/rx and clear interrupts */ 207 1.2.2.2 skrll status = hw->mac.ops.stop_adapter(hw); 208 1.2.2.2 skrll if (status != IXGBE_SUCCESS) 209 1.2.2.2 skrll goto reset_hw_out; 210 1.2.2.2 skrll 211 1.2.2.2 skrll /* flush pending Tx transactions */ 212 1.2.2.2 skrll ixgbe_clear_tx_pending(hw); 213 1.2.2.2 skrll 214 1.2.2.2 skrll mac_reset_top: 215 1.2.2.2 skrll ctrl = IXGBE_CTRL_RST; 216 1.2.2.2 skrll ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 217 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 218 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 219 1.2.2.2 skrll 220 1.2.2.2 skrll /* Poll for reset bit to self-clear indicating reset is complete */ 221 1.2.2.2 skrll for (i = 0; i < 10; i++) { 222 1.2.2.2 skrll usec_delay(1); 223 1.2.2.2 skrll ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 224 1.2.2.2 skrll if (!(ctrl & IXGBE_CTRL_RST_MASK)) 225 1.2.2.2 skrll break; 226 1.2.2.2 skrll } 227 1.2.2.2 skrll 228 1.2.2.2 skrll if (ctrl & IXGBE_CTRL_RST_MASK) { 229 1.2.2.2 skrll status = IXGBE_ERR_RESET_FAILED; 230 1.2.2.2 skrll DEBUGOUT("Reset polling failed to complete.\n"); 231 1.2.2.2 skrll } 232 1.2.2.2 skrll msec_delay(100); 233 1.2.2.2 skrll 234 1.2.2.2 skrll /* 235 1.2.2.2 skrll * Double resets are required for recovery from certain error 236 1.2.2.2 skrll * conditions. Between resets, it is necessary to stall to allow time 237 1.2.2.2 skrll * for any pending HW events to complete. 238 1.2.2.2 skrll */ 239 1.2.2.2 skrll if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 240 1.2.2.2 skrll hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 241 1.2.2.2 skrll goto mac_reset_top; 242 1.2.2.2 skrll } 243 1.2.2.2 skrll 244 1.2.2.2 skrll /* Set the Rx packet buffer size. */ 245 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 246 1.2.2.2 skrll 247 1.2.2.2 skrll /* Store the permanent mac address */ 248 1.2.2.2 skrll hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 249 1.2.2.2 skrll 250 1.2.2.2 skrll /* 251 1.2.2.2 skrll * Store MAC address from RAR0, clear receive address registers, and 252 1.2.2.2 skrll * clear the multicast table. Also reset num_rar_entries to 128, 253 1.2.2.2 skrll * since we modify this value when programming the SAN MAC address. 254 1.2.2.2 skrll */ 255 1.2.2.2 skrll hw->mac.num_rar_entries = 128; 256 1.2.2.2 skrll hw->mac.ops.init_rx_addrs(hw); 257 1.2.2.2 skrll 258 1.2.2.2 skrll /* Store the permanent SAN mac address */ 259 1.2.2.2 skrll hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 260 1.2.2.2 skrll 261 1.2.2.2 skrll /* Add the SAN MAC address to the RAR only if it's a valid address */ 262 1.2.2.2 skrll if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 263 1.2.2.2 skrll hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 264 1.2.2.2 skrll hw->mac.san_addr, 0, IXGBE_RAH_AV); 265 1.2.2.2 skrll 266 1.2.2.2 skrll /* Save the SAN MAC RAR index */ 267 1.2.2.2 skrll hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 268 1.2.2.2 skrll 269 1.2.2.2 skrll /* Reserve the last RAR for the SAN MAC address */ 270 1.2.2.2 skrll hw->mac.num_rar_entries--; 271 1.2.2.2 skrll } 272 1.2.2.2 skrll 273 1.2.2.2 skrll /* Store the alternative WWNN/WWPN prefix */ 274 1.2.2.2 skrll hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 275 1.2.2.2 skrll &hw->mac.wwpn_prefix); 276 1.2.2.2 skrll 277 1.2.2.2 skrll reset_hw_out: 278 1.2.2.2 skrll return status; 279 1.2.2.2 skrll } 280 1.2.2.2 skrll 281 1.2.2.2 skrll /** 282 1.2.2.2 skrll * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 283 1.2.2.2 skrll * @hw: pointer to hardware structure 284 1.2.2.2 skrll * 285 1.2.2.2 skrll * Starts the hardware using the generic start_hw function 286 1.2.2.2 skrll * and the generation start_hw function. 287 1.2.2.2 skrll * Then performs revision-specific operations, if any. 288 1.2.2.2 skrll **/ 289 1.2.2.2 skrll s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 290 1.2.2.2 skrll { 291 1.2.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 292 1.2.2.2 skrll 293 1.2.2.2 skrll DEBUGFUNC("ixgbe_start_hw_X540"); 294 1.2.2.2 skrll 295 1.2.2.2 skrll ret_val = ixgbe_start_hw_generic(hw); 296 1.2.2.2 skrll if (ret_val != IXGBE_SUCCESS) 297 1.2.2.2 skrll goto out; 298 1.2.2.2 skrll 299 1.2.2.2 skrll ret_val = ixgbe_start_hw_gen2(hw); 300 1.2.2.2 skrll 301 1.2.2.2 skrll out: 302 1.2.2.2 skrll return ret_val; 303 1.2.2.2 skrll } 304 1.2.2.2 skrll 305 1.2.2.2 skrll /** 306 1.2.2.2 skrll * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 307 1.2.2.2 skrll * @hw: pointer to hardware structure 308 1.2.2.2 skrll * 309 1.2.2.2 skrll * Determines physical layer capabilities of the current configuration. 310 1.2.2.2 skrll **/ 311 1.2.2.2 skrll u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 312 1.2.2.2 skrll { 313 1.2.2.2 skrll u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 314 1.2.2.2 skrll u16 ext_ability = 0; 315 1.2.2.2 skrll 316 1.2.2.2 skrll DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 317 1.2.2.2 skrll 318 1.2.2.2 skrll hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 319 1.2.2.2 skrll IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 320 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 321 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 322 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 323 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 324 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 325 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 326 1.2.2.2 skrll 327 1.2.2.2 skrll return physical_layer; 328 1.2.2.2 skrll } 329 1.2.2.2 skrll 330 1.2.2.2 skrll /** 331 1.2.2.2 skrll * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 332 1.2.2.2 skrll * @hw: pointer to hardware structure 333 1.2.2.2 skrll * 334 1.2.2.2 skrll * Initializes the EEPROM parameters ixgbe_eeprom_info within the 335 1.2.2.2 skrll * ixgbe_hw struct in order to set up EEPROM access. 336 1.2.2.2 skrll **/ 337 1.2.2.2 skrll s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 338 1.2.2.2 skrll { 339 1.2.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 340 1.2.2.2 skrll u32 eec; 341 1.2.2.2 skrll u16 eeprom_size; 342 1.2.2.2 skrll 343 1.2.2.2 skrll DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 344 1.2.2.2 skrll 345 1.2.2.2 skrll if (eeprom->type == ixgbe_eeprom_uninitialized) { 346 1.2.2.2 skrll eeprom->semaphore_delay = 10; 347 1.2.2.2 skrll eeprom->type = ixgbe_flash; 348 1.2.2.2 skrll 349 1.2.2.2 skrll eec = IXGBE_READ_REG(hw, IXGBE_EEC); 350 1.2.2.2 skrll eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 351 1.2.2.2 skrll IXGBE_EEC_SIZE_SHIFT); 352 1.2.2.2 skrll eeprom->word_size = 1 << (eeprom_size + 353 1.2.2.2 skrll IXGBE_EEPROM_WORD_SIZE_SHIFT); 354 1.2.2.2 skrll 355 1.2.2.2 skrll DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 356 1.2.2.2 skrll eeprom->type, eeprom->word_size); 357 1.2.2.2 skrll } 358 1.2.2.2 skrll 359 1.2.2.2 skrll return IXGBE_SUCCESS; 360 1.2.2.2 skrll } 361 1.2.2.2 skrll 362 1.2.2.2 skrll /** 363 1.2.2.2 skrll * ixgbe_read_eerd_X540- Read EEPROM word using EERD 364 1.2.2.2 skrll * @hw: pointer to hardware structure 365 1.2.2.2 skrll * @offset: offset of word in the EEPROM to read 366 1.2.2.2 skrll * @data: word read from the EEPROM 367 1.2.2.2 skrll * 368 1.2.2.2 skrll * Reads a 16 bit word from the EEPROM using the EERD register. 369 1.2.2.2 skrll **/ 370 1.2.2.2 skrll s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 371 1.2.2.2 skrll { 372 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 373 1.2.2.2 skrll 374 1.2.2.2 skrll DEBUGFUNC("ixgbe_read_eerd_X540"); 375 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 376 1.2.2.2 skrll IXGBE_SUCCESS) 377 1.2.2.2 skrll status = ixgbe_read_eerd_generic(hw, offset, data); 378 1.2.2.2 skrll else 379 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 380 1.2.2.2 skrll 381 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 382 1.2.2.2 skrll return status; 383 1.2.2.2 skrll } 384 1.2.2.2 skrll 385 1.2.2.2 skrll /** 386 1.2.2.2 skrll * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 387 1.2.2.2 skrll * @hw: pointer to hardware structure 388 1.2.2.2 skrll * @offset: offset of word in the EEPROM to read 389 1.2.2.2 skrll * @words: number of words 390 1.2.2.2 skrll * @data: word(s) read from the EEPROM 391 1.2.2.2 skrll * 392 1.2.2.2 skrll * Reads a 16 bit word(s) from the EEPROM using the EERD register. 393 1.2.2.2 skrll **/ 394 1.2.2.2 skrll s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 395 1.2.2.2 skrll u16 offset, u16 words, u16 *data) 396 1.2.2.2 skrll { 397 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 398 1.2.2.2 skrll 399 1.2.2.2 skrll DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 400 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 401 1.2.2.2 skrll IXGBE_SUCCESS) 402 1.2.2.2 skrll status = ixgbe_read_eerd_buffer_generic(hw, offset, 403 1.2.2.2 skrll words, data); 404 1.2.2.2 skrll else 405 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 406 1.2.2.2 skrll 407 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 408 1.2.2.2 skrll return status; 409 1.2.2.2 skrll } 410 1.2.2.2 skrll 411 1.2.2.2 skrll /** 412 1.2.2.2 skrll * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 413 1.2.2.2 skrll * @hw: pointer to hardware structure 414 1.2.2.2 skrll * @offset: offset of word in the EEPROM to write 415 1.2.2.2 skrll * @data: word write to the EEPROM 416 1.2.2.2 skrll * 417 1.2.2.2 skrll * Write a 16 bit word to the EEPROM using the EEWR register. 418 1.2.2.2 skrll **/ 419 1.2.2.2 skrll s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 420 1.2.2.2 skrll { 421 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 422 1.2.2.2 skrll 423 1.2.2.2 skrll DEBUGFUNC("ixgbe_write_eewr_X540"); 424 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 425 1.2.2.2 skrll IXGBE_SUCCESS) 426 1.2.2.2 skrll status = ixgbe_write_eewr_generic(hw, offset, data); 427 1.2.2.2 skrll else 428 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 429 1.2.2.2 skrll 430 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 431 1.2.2.2 skrll return status; 432 1.2.2.2 skrll } 433 1.2.2.2 skrll 434 1.2.2.2 skrll /** 435 1.2.2.2 skrll * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 436 1.2.2.2 skrll * @hw: pointer to hardware structure 437 1.2.2.2 skrll * @offset: offset of word in the EEPROM to write 438 1.2.2.2 skrll * @words: number of words 439 1.2.2.2 skrll * @data: word(s) write to the EEPROM 440 1.2.2.2 skrll * 441 1.2.2.2 skrll * Write a 16 bit word(s) to the EEPROM using the EEWR register. 442 1.2.2.2 skrll **/ 443 1.2.2.2 skrll s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 444 1.2.2.2 skrll u16 offset, u16 words, u16 *data) 445 1.2.2.2 skrll { 446 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 447 1.2.2.2 skrll 448 1.2.2.2 skrll DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 449 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 450 1.2.2.2 skrll IXGBE_SUCCESS) 451 1.2.2.2 skrll status = ixgbe_write_eewr_buffer_generic(hw, offset, 452 1.2.2.2 skrll words, data); 453 1.2.2.2 skrll else 454 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 455 1.2.2.2 skrll 456 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 457 1.2.2.2 skrll return status; 458 1.2.2.2 skrll } 459 1.2.2.2 skrll 460 1.2.2.2 skrll /** 461 1.2.2.2 skrll * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 462 1.2.2.2 skrll * 463 1.2.2.2 skrll * This function does not use synchronization for EERD and EEWR. It can 464 1.2.2.2 skrll * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 465 1.2.2.2 skrll * 466 1.2.2.2 skrll * @hw: pointer to hardware structure 467 1.2.2.2 skrll **/ 468 1.2.2.2 skrll u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 469 1.2.2.2 skrll { 470 1.2.2.2 skrll u16 i; 471 1.2.2.2 skrll u16 j; 472 1.2.2.2 skrll u16 checksum = 0; 473 1.2.2.2 skrll u16 length = 0; 474 1.2.2.2 skrll u16 pointer = 0; 475 1.2.2.2 skrll u16 word = 0; 476 1.2.2.2 skrll 477 1.2.2.2 skrll /* 478 1.2.2.2 skrll * Do not use hw->eeprom.ops.read because we do not want to take 479 1.2.2.2 skrll * the synchronization semaphores here. Instead use 480 1.2.2.2 skrll * ixgbe_read_eerd_generic 481 1.2.2.2 skrll */ 482 1.2.2.2 skrll 483 1.2.2.2 skrll DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 484 1.2.2.2 skrll 485 1.2.2.2 skrll /* Include 0x0-0x3F in the checksum */ 486 1.2.2.2 skrll for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 487 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) { 488 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 489 1.2.2.2 skrll break; 490 1.2.2.2 skrll } 491 1.2.2.2 skrll checksum += word; 492 1.2.2.2 skrll } 493 1.2.2.2 skrll 494 1.2.2.2 skrll /* 495 1.2.2.2 skrll * Include all data from pointers 0x3, 0x6-0xE. This excludes the 496 1.2.2.2 skrll * FW, PHY module, and PCIe Expansion/Option ROM pointers. 497 1.2.2.2 skrll */ 498 1.2.2.2 skrll for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 499 1.2.2.2 skrll if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 500 1.2.2.2 skrll continue; 501 1.2.2.2 skrll 502 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) { 503 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 504 1.2.2.2 skrll break; 505 1.2.2.2 skrll } 506 1.2.2.2 skrll 507 1.2.2.2 skrll /* Skip pointer section if the pointer is invalid. */ 508 1.2.2.2 skrll if (pointer == 0xFFFF || pointer == 0 || 509 1.2.2.2 skrll pointer >= hw->eeprom.word_size) 510 1.2.2.2 skrll continue; 511 1.2.2.2 skrll 512 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, pointer, &length) != 513 1.2.2.2 skrll IXGBE_SUCCESS) { 514 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 515 1.2.2.2 skrll break; 516 1.2.2.2 skrll } 517 1.2.2.2 skrll 518 1.2.2.2 skrll /* Skip pointer section if length is invalid. */ 519 1.2.2.2 skrll if (length == 0xFFFF || length == 0 || 520 1.2.2.2 skrll (pointer + length) >= hw->eeprom.word_size) 521 1.2.2.2 skrll continue; 522 1.2.2.2 skrll 523 1.2.2.2 skrll for (j = pointer+1; j <= pointer+length; j++) { 524 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, j, &word) != 525 1.2.2.2 skrll IXGBE_SUCCESS) { 526 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 527 1.2.2.2 skrll break; 528 1.2.2.2 skrll } 529 1.2.2.2 skrll checksum += word; 530 1.2.2.2 skrll } 531 1.2.2.2 skrll } 532 1.2.2.2 skrll 533 1.2.2.2 skrll checksum = (u16)IXGBE_EEPROM_SUM - checksum; 534 1.2.2.2 skrll 535 1.2.2.2 skrll return checksum; 536 1.2.2.2 skrll } 537 1.2.2.2 skrll 538 1.2.2.2 skrll /** 539 1.2.2.2 skrll * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 540 1.2.2.2 skrll * @hw: pointer to hardware structure 541 1.2.2.2 skrll * @checksum_val: calculated checksum 542 1.2.2.2 skrll * 543 1.2.2.2 skrll * Performs checksum calculation and validates the EEPROM checksum. If the 544 1.2.2.2 skrll * caller does not need checksum_val, the value can be NULL. 545 1.2.2.2 skrll **/ 546 1.2.2.2 skrll s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 547 1.2.2.2 skrll u16 *checksum_val) 548 1.2.2.2 skrll { 549 1.2.2.2 skrll s32 status; 550 1.2.2.2 skrll u16 checksum; 551 1.2.2.2 skrll u16 read_checksum = 0; 552 1.2.2.2 skrll 553 1.2.2.2 skrll DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 554 1.2.2.2 skrll 555 1.2.2.2 skrll /* 556 1.2.2.2 skrll * Read the first word from the EEPROM. If this times out or fails, do 557 1.2.2.2 skrll * not continue or we could be in for a very long wait while every 558 1.2.2.2 skrll * EEPROM read fails 559 1.2.2.2 skrll */ 560 1.2.2.2 skrll status = hw->eeprom.ops.read(hw, 0, &checksum); 561 1.2.2.2 skrll 562 1.2.2.2 skrll if (status != IXGBE_SUCCESS) { 563 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 564 1.2.2.2 skrll goto out; 565 1.2.2.2 skrll } 566 1.2.2.2 skrll 567 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 568 1.2.2.2 skrll IXGBE_SUCCESS) { 569 1.2.2.2 skrll checksum = hw->eeprom.ops.calc_checksum(hw); 570 1.2.2.2 skrll 571 1.2.2.2 skrll /* 572 1.2.2.2 skrll * Do not use hw->eeprom.ops.read because we do not want to take 573 1.2.2.2 skrll * the synchronization semaphores twice here. 574 1.2.2.2 skrll */ 575 1.2.2.2 skrll ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 576 1.2.2.2 skrll &read_checksum); 577 1.2.2.2 skrll 578 1.2.2.2 skrll /* 579 1.2.2.2 skrll * Verify read checksum from EEPROM is the same as 580 1.2.2.2 skrll * calculated checksum 581 1.2.2.2 skrll */ 582 1.2.2.2 skrll if (read_checksum != checksum) 583 1.2.2.2 skrll status = IXGBE_ERR_EEPROM_CHECKSUM; 584 1.2.2.2 skrll 585 1.2.2.2 skrll /* If the user cares, return the calculated checksum */ 586 1.2.2.2 skrll if (checksum_val) 587 1.2.2.2 skrll *checksum_val = checksum; 588 1.2.2.2 skrll } else { 589 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 590 1.2.2.2 skrll } 591 1.2.2.2 skrll 592 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 593 1.2.2.2 skrll out: 594 1.2.2.2 skrll return status; 595 1.2.2.2 skrll } 596 1.2.2.2 skrll 597 1.2.2.2 skrll /** 598 1.2.2.2 skrll * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 599 1.2.2.2 skrll * @hw: pointer to hardware structure 600 1.2.2.2 skrll * 601 1.2.2.2 skrll * After writing EEPROM to shadow RAM using EEWR register, software calculates 602 1.2.2.2 skrll * checksum and updates the EEPROM and instructs the hardware to update 603 1.2.2.2 skrll * the flash. 604 1.2.2.2 skrll **/ 605 1.2.2.2 skrll s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 606 1.2.2.2 skrll { 607 1.2.2.2 skrll s32 status; 608 1.2.2.2 skrll u16 checksum; 609 1.2.2.2 skrll 610 1.2.2.2 skrll DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 611 1.2.2.2 skrll 612 1.2.2.2 skrll /* 613 1.2.2.2 skrll * Read the first word from the EEPROM. If this times out or fails, do 614 1.2.2.2 skrll * not continue or we could be in for a very long wait while every 615 1.2.2.2 skrll * EEPROM read fails 616 1.2.2.2 skrll */ 617 1.2.2.2 skrll status = hw->eeprom.ops.read(hw, 0, &checksum); 618 1.2.2.2 skrll 619 1.2.2.2 skrll if (status != IXGBE_SUCCESS) 620 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 621 1.2.2.2 skrll 622 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 623 1.2.2.2 skrll IXGBE_SUCCESS) { 624 1.2.2.2 skrll checksum = hw->eeprom.ops.calc_checksum(hw); 625 1.2.2.2 skrll 626 1.2.2.2 skrll /* 627 1.2.2.2 skrll * Do not use hw->eeprom.ops.write because we do not want to 628 1.2.2.2 skrll * take the synchronization semaphores twice here. 629 1.2.2.2 skrll */ 630 1.2.2.2 skrll status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, 631 1.2.2.2 skrll checksum); 632 1.2.2.2 skrll 633 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 634 1.2.2.2 skrll status = ixgbe_update_flash_X540(hw); 635 1.2.2.2 skrll else 636 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 637 1.2.2.2 skrll } 638 1.2.2.2 skrll 639 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 640 1.2.2.2 skrll 641 1.2.2.2 skrll return status; 642 1.2.2.2 skrll } 643 1.2.2.2 skrll 644 1.2.2.2 skrll /** 645 1.2.2.2 skrll * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 646 1.2.2.2 skrll * @hw: pointer to hardware structure 647 1.2.2.2 skrll * 648 1.2.2.2 skrll * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 649 1.2.2.2 skrll * EEPROM from shadow RAM to the flash device. 650 1.2.2.2 skrll **/ 651 1.2.2.2 skrll static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 652 1.2.2.2 skrll { 653 1.2.2.2 skrll u32 flup; 654 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 655 1.2.2.2 skrll 656 1.2.2.2 skrll DEBUGFUNC("ixgbe_update_flash_X540"); 657 1.2.2.2 skrll 658 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 659 1.2.2.2 skrll if (status == IXGBE_ERR_EEPROM) { 660 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 661 1.2.2.2 skrll goto out; 662 1.2.2.2 skrll } 663 1.2.2.2 skrll 664 1.2.2.2 skrll flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 665 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 666 1.2.2.2 skrll 667 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 668 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 669 1.2.2.2 skrll DEBUGOUT("Flash update complete\n"); 670 1.2.2.2 skrll else 671 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 672 1.2.2.2 skrll 673 1.2.2.2 skrll if (hw->revision_id == 0) { 674 1.2.2.2 skrll flup = IXGBE_READ_REG(hw, IXGBE_EEC); 675 1.2.2.2 skrll 676 1.2.2.2 skrll if (flup & IXGBE_EEC_SEC1VAL) { 677 1.2.2.2 skrll flup |= IXGBE_EEC_FLUP; 678 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 679 1.2.2.2 skrll } 680 1.2.2.2 skrll 681 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 682 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 683 1.2.2.2 skrll DEBUGOUT("Flash update complete\n"); 684 1.2.2.2 skrll else 685 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 686 1.2.2.2 skrll } 687 1.2.2.2 skrll out: 688 1.2.2.2 skrll return status; 689 1.2.2.2 skrll } 690 1.2.2.2 skrll 691 1.2.2.2 skrll /** 692 1.2.2.2 skrll * ixgbe_poll_flash_update_done_X540 - Poll flash update status 693 1.2.2.2 skrll * @hw: pointer to hardware structure 694 1.2.2.2 skrll * 695 1.2.2.2 skrll * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 696 1.2.2.2 skrll * flash update is done. 697 1.2.2.2 skrll **/ 698 1.2.2.2 skrll static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 699 1.2.2.2 skrll { 700 1.2.2.2 skrll u32 i; 701 1.2.2.2 skrll u32 reg; 702 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 703 1.2.2.2 skrll 704 1.2.2.2 skrll DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 705 1.2.2.2 skrll 706 1.2.2.2 skrll for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 707 1.2.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_EEC); 708 1.2.2.2 skrll if (reg & IXGBE_EEC_FLUDONE) { 709 1.2.2.2 skrll status = IXGBE_SUCCESS; 710 1.2.2.2 skrll break; 711 1.2.2.2 skrll } 712 1.2.2.2 skrll usec_delay(5); 713 1.2.2.2 skrll } 714 1.2.2.2 skrll return status; 715 1.2.2.2 skrll } 716 1.2.2.2 skrll 717 1.2.2.2 skrll /** 718 1.2.2.2 skrll * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 719 1.2.2.2 skrll * @hw: pointer to hardware structure 720 1.2.2.2 skrll * @mask: Mask to specify which semaphore to acquire 721 1.2.2.2 skrll * 722 1.2.2.2 skrll * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 723 1.2.2.2 skrll * the specified function (CSR, PHY0, PHY1, NVM, Flash) 724 1.2.2.2 skrll **/ 725 1.2.2.2 skrll s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 726 1.2.2.2 skrll { 727 1.2.2.2 skrll u32 swfw_sync; 728 1.2.2.2 skrll u32 swmask = mask; 729 1.2.2.2 skrll u32 fwmask = mask << 5; 730 1.2.2.2 skrll u32 hwmask = 0; 731 1.2.2.2 skrll u32 timeout = 200; 732 1.2.2.2 skrll u32 i; 733 1.2.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 734 1.2.2.2 skrll 735 1.2.2.2 skrll DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 736 1.2.2.2 skrll 737 1.2.2.2 skrll if (swmask == IXGBE_GSSR_EEP_SM) 738 1.2.2.2 skrll hwmask = IXGBE_GSSR_FLASH_SM; 739 1.2.2.2 skrll 740 1.2.2.2 skrll /* SW only mask doesn't have FW bit pair */ 741 1.2.2.2 skrll if (swmask == IXGBE_GSSR_SW_MNG_SM) 742 1.2.2.2 skrll fwmask = 0; 743 1.2.2.2 skrll 744 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 745 1.2.2.2 skrll /* 746 1.2.2.2 skrll * SW NVM semaphore bit is used for access to all 747 1.2.2.2 skrll * SW_FW_SYNC bits (not just NVM) 748 1.2.2.2 skrll */ 749 1.2.2.2 skrll if (ixgbe_get_swfw_sync_semaphore(hw)) { 750 1.2.2.2 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 751 1.2.2.2 skrll goto out; 752 1.2.2.2 skrll } 753 1.2.2.2 skrll 754 1.2.2.2 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 755 1.2.2.2 skrll if (!(swfw_sync & (fwmask | swmask | hwmask))) { 756 1.2.2.2 skrll swfw_sync |= swmask; 757 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 758 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 759 1.2.2.2 skrll msec_delay(5); 760 1.2.2.2 skrll goto out; 761 1.2.2.2 skrll } else { 762 1.2.2.2 skrll /* 763 1.2.2.2 skrll * Firmware currently using resource (fwmask), hardware 764 1.2.2.2 skrll * currently using resource (hwmask), or other software 765 1.2.2.2 skrll * thread currently using resource (swmask) 766 1.2.2.2 skrll */ 767 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 768 1.2.2.2 skrll msec_delay(5); 769 1.2.2.2 skrll } 770 1.2.2.2 skrll } 771 1.2.2.2 skrll 772 1.2.2.2 skrll /* Failed to get SW only semaphore */ 773 1.2.2.2 skrll if (swmask == IXGBE_GSSR_SW_MNG_SM) { 774 1.2.2.2 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 775 1.2.2.2 skrll goto out; 776 1.2.2.2 skrll } 777 1.2.2.2 skrll 778 1.2.2.2 skrll /* If the resource is not released by the FW/HW the SW can assume that 779 1.2.2.2 skrll * the FW/HW malfunctions. In that case the SW should sets the SW bit(s) 780 1.2.2.2 skrll * of the requested resource(s) while ignoring the corresponding FW/HW 781 1.2.2.2 skrll * bits in the SW_FW_SYNC register. 782 1.2.2.2 skrll */ 783 1.2.2.2 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 784 1.2.2.2 skrll if (swfw_sync & (fwmask | hwmask)) { 785 1.2.2.2 skrll if (ixgbe_get_swfw_sync_semaphore(hw)) { 786 1.2.2.2 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 787 1.2.2.2 skrll goto out; 788 1.2.2.2 skrll } 789 1.2.2.2 skrll 790 1.2.2.2 skrll swfw_sync |= swmask; 791 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 792 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 793 1.2.2.2 skrll msec_delay(5); 794 1.2.2.2 skrll } 795 1.2.2.2 skrll 796 1.2.2.2 skrll out: 797 1.2.2.2 skrll return ret_val; 798 1.2.2.2 skrll } 799 1.2.2.2 skrll 800 1.2.2.2 skrll /** 801 1.2.2.2 skrll * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 802 1.2.2.2 skrll * @hw: pointer to hardware structure 803 1.2.2.2 skrll * @mask: Mask to specify which semaphore to release 804 1.2.2.2 skrll * 805 1.2.2.2 skrll * Releases the SWFW semaphore through the SW_FW_SYNC register 806 1.2.2.2 skrll * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 807 1.2.2.2 skrll **/ 808 1.2.2.2 skrll void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 809 1.2.2.2 skrll { 810 1.2.2.2 skrll u32 swfw_sync; 811 1.2.2.2 skrll u32 swmask = mask; 812 1.2.2.2 skrll 813 1.2.2.2 skrll DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 814 1.2.2.2 skrll 815 1.2.2.2 skrll ixgbe_get_swfw_sync_semaphore(hw); 816 1.2.2.2 skrll 817 1.2.2.2 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 818 1.2.2.2 skrll swfw_sync &= ~swmask; 819 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 820 1.2.2.2 skrll 821 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 822 1.2.2.2 skrll msec_delay(5); 823 1.2.2.2 skrll } 824 1.2.2.2 skrll 825 1.2.2.2 skrll /** 826 1.2.2.2 skrll * ixgbe_get_nvm_semaphore - Get hardware semaphore 827 1.2.2.2 skrll * @hw: pointer to hardware structure 828 1.2.2.2 skrll * 829 1.2.2.2 skrll * Sets the hardware semaphores so SW/FW can gain control of shared resources 830 1.2.2.2 skrll **/ 831 1.2.2.2 skrll static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 832 1.2.2.2 skrll { 833 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 834 1.2.2.2 skrll u32 timeout = 2000; 835 1.2.2.2 skrll u32 i; 836 1.2.2.2 skrll u32 swsm; 837 1.2.2.2 skrll 838 1.2.2.2 skrll DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 839 1.2.2.2 skrll 840 1.2.2.2 skrll /* Get SMBI software semaphore between device drivers first */ 841 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 842 1.2.2.2 skrll /* 843 1.2.2.2 skrll * If the SMBI bit is 0 when we read it, then the bit will be 844 1.2.2.2 skrll * set and we have the semaphore 845 1.2.2.2 skrll */ 846 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 847 1.2.2.2 skrll if (!(swsm & IXGBE_SWSM_SMBI)) { 848 1.2.2.2 skrll status = IXGBE_SUCCESS; 849 1.2.2.2 skrll break; 850 1.2.2.2 skrll } 851 1.2.2.2 skrll usec_delay(50); 852 1.2.2.2 skrll } 853 1.2.2.2 skrll 854 1.2.2.2 skrll /* Now get the semaphore between SW/FW through the REGSMP bit */ 855 1.2.2.2 skrll if (status == IXGBE_SUCCESS) { 856 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 857 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 858 1.2.2.2 skrll if (!(swsm & IXGBE_SWFW_REGSMP)) 859 1.2.2.2 skrll break; 860 1.2.2.2 skrll 861 1.2.2.2 skrll usec_delay(50); 862 1.2.2.2 skrll } 863 1.2.2.2 skrll 864 1.2.2.2 skrll /* 865 1.2.2.2 skrll * Release semaphores and return error if SW NVM semaphore 866 1.2.2.2 skrll * was not granted because we don't have access to the EEPROM 867 1.2.2.2 skrll */ 868 1.2.2.2 skrll if (i >= timeout) { 869 1.2.2.2 skrll DEBUGOUT("REGSMP Software NVM semaphore not " 870 1.2.2.2 skrll "granted.\n"); 871 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 872 1.2.2.2 skrll status = IXGBE_ERR_EEPROM; 873 1.2.2.2 skrll } 874 1.2.2.2 skrll } else { 875 1.2.2.2 skrll DEBUGOUT("Software semaphore SMBI between device drivers " 876 1.2.2.2 skrll "not granted.\n"); 877 1.2.2.2 skrll } 878 1.2.2.2 skrll 879 1.2.2.2 skrll return status; 880 1.2.2.2 skrll } 881 1.2.2.2 skrll 882 1.2.2.2 skrll /** 883 1.2.2.2 skrll * ixgbe_release_nvm_semaphore - Release hardware semaphore 884 1.2.2.2 skrll * @hw: pointer to hardware structure 885 1.2.2.2 skrll * 886 1.2.2.2 skrll * This function clears hardware semaphore bits. 887 1.2.2.2 skrll **/ 888 1.2.2.2 skrll static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 889 1.2.2.2 skrll { 890 1.2.2.2 skrll u32 swsm; 891 1.2.2.2 skrll 892 1.2.2.2 skrll DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 893 1.2.2.2 skrll 894 1.2.2.2 skrll /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 895 1.2.2.2 skrll 896 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 897 1.2.2.2 skrll swsm &= ~IXGBE_SWSM_SMBI; 898 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 899 1.2.2.2 skrll 900 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 901 1.2.2.2 skrll swsm &= ~IXGBE_SWFW_REGSMP; 902 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 903 1.2.2.2 skrll 904 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 905 1.2.2.2 skrll } 906 1.2.2.2 skrll 907 1.2.2.2 skrll /** 908 1.2.2.2 skrll * ixgbe_blink_led_start_X540 - Blink LED based on index. 909 1.2.2.2 skrll * @hw: pointer to hardware structure 910 1.2.2.2 skrll * @index: led number to blink 911 1.2.2.2 skrll * 912 1.2.2.2 skrll * Devices that implement the version 2 interface: 913 1.2.2.2 skrll * X540 914 1.2.2.2 skrll **/ 915 1.2.2.2 skrll s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 916 1.2.2.2 skrll { 917 1.2.2.2 skrll u32 macc_reg; 918 1.2.2.2 skrll u32 ledctl_reg; 919 1.2.2.2 skrll ixgbe_link_speed speed; 920 1.2.2.2 skrll bool link_up; 921 1.2.2.2 skrll 922 1.2.2.2 skrll DEBUGFUNC("ixgbe_blink_led_start_X540"); 923 1.2.2.2 skrll 924 1.2.2.2 skrll /* 925 1.2.2.2 skrll * Link should be up in order for the blink bit in the LED control 926 1.2.2.2 skrll * register to work. Force link and speed in the MAC if link is down. 927 1.2.2.2 skrll * This will be reversed when we stop the blinking. 928 1.2.2.2 skrll */ 929 1.2.2.2 skrll hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 930 1.2.2.2 skrll if (link_up == FALSE) { 931 1.2.2.2 skrll macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 932 1.2.2.2 skrll macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 933 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 934 1.2.2.2 skrll } 935 1.2.2.2 skrll /* Set the LED to LINK_UP + BLINK. */ 936 1.2.2.2 skrll ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 937 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 938 1.2.2.2 skrll ledctl_reg |= IXGBE_LED_BLINK(index); 939 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 940 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 941 1.2.2.2 skrll 942 1.2.2.2 skrll return IXGBE_SUCCESS; 943 1.2.2.2 skrll } 944 1.2.2.2 skrll 945 1.2.2.2 skrll /** 946 1.2.2.2 skrll * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 947 1.2.2.2 skrll * @hw: pointer to hardware structure 948 1.2.2.2 skrll * @index: led number to stop blinking 949 1.2.2.2 skrll * 950 1.2.2.2 skrll * Devices that implement the version 2 interface: 951 1.2.2.2 skrll * X540 952 1.2.2.2 skrll **/ 953 1.2.2.2 skrll s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 954 1.2.2.2 skrll { 955 1.2.2.2 skrll u32 macc_reg; 956 1.2.2.2 skrll u32 ledctl_reg; 957 1.2.2.2 skrll 958 1.2.2.2 skrll DEBUGFUNC("ixgbe_blink_led_stop_X540"); 959 1.2.2.2 skrll 960 1.2.2.2 skrll /* Restore the LED to its default value. */ 961 1.2.2.2 skrll ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 962 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 963 1.2.2.2 skrll ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 964 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_BLINK(index); 965 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 966 1.2.2.2 skrll 967 1.2.2.2 skrll /* Unforce link and speed in the MAC. */ 968 1.2.2.2 skrll macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 969 1.2.2.2 skrll macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 970 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 971 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 972 1.2.2.2 skrll 973 1.2.2.2 skrll return IXGBE_SUCCESS; 974 1.2.2.2 skrll } 975 1.2.2.2 skrll 976
Indexes created Tue Oct 21 08:09:48 GMT 2025