ixgbe_x540.c revision 1.2.2.3
1 1.2.2.2 skrll /****************************************************************************** 2 1.2.2.2 skrll 3 1.2.2.3 skrll Copyright (c) 2001-2013, Intel Corporation 4 1.2.2.2 skrll All rights reserved. 5 1.2.2.2 skrll 6 1.2.2.2 skrll Redistribution and use in source and binary forms, with or without 7 1.2.2.2 skrll modification, are permitted provided that the following conditions are met: 8 1.2.2.2 skrll 9 1.2.2.2 skrll 1. Redistributions of source code must retain the above copyright notice, 10 1.2.2.2 skrll this list of conditions and the following disclaimer. 11 1.2.2.2 skrll 12 1.2.2.2 skrll 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll 16 1.2.2.2 skrll 3. Neither the name of the Intel Corporation nor the names of its 17 1.2.2.2 skrll contributors may be used to endorse or promote products derived from 18 1.2.2.2 skrll this software without specific prior written permission. 19 1.2.2.2 skrll 20 1.2.2.2 skrll THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.2.2.2 skrll AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.2.2.2 skrll IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.2.2.2 skrll ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.2.2.2 skrll LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.2.2.2 skrll CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.2.2.2 skrll SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.2.2.2 skrll INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.2.2.2 skrll CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.2.2.2 skrll ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.2.2.2 skrll POSSIBILITY OF SUCH DAMAGE. 31 1.2.2.2 skrll 32 1.2.2.2 skrll ******************************************************************************/ 33 1.2.2.3 skrll /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 247822 2013-03-04 23:07:40Z jfv $*/ 34 1.2.2.2 skrll 35 1.2.2.2 skrll #include "ixgbe_x540.h" 36 1.2.2.2 skrll #include "ixgbe_type.h" 37 1.2.2.2 skrll #include "ixgbe_api.h" 38 1.2.2.2 skrll #include "ixgbe_common.h" 39 1.2.2.2 skrll #include "ixgbe_phy.h" 40 1.2.2.2 skrll 41 1.2.2.2 skrll static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 42 1.2.2.2 skrll static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 43 1.2.2.2 skrll static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 44 1.2.2.2 skrll static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 45 1.2.2.2 skrll 46 1.2.2.2 skrll /** 47 1.2.2.2 skrll * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 48 1.2.2.2 skrll * @hw: pointer to hardware structure 49 1.2.2.2 skrll * 50 1.2.2.2 skrll * Initialize the function pointers and assign the MAC type for X540. 51 1.2.2.2 skrll * Does not touch the hardware. 52 1.2.2.2 skrll **/ 53 1.2.2.2 skrll s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 54 1.2.2.2 skrll { 55 1.2.2.2 skrll struct ixgbe_mac_info *mac = &hw->mac; 56 1.2.2.2 skrll struct ixgbe_phy_info *phy = &hw->phy; 57 1.2.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 58 1.2.2.2 skrll s32 ret_val; 59 1.2.2.2 skrll 60 1.2.2.2 skrll DEBUGFUNC("ixgbe_init_ops_X540"); 61 1.2.2.2 skrll 62 1.2.2.2 skrll ret_val = ixgbe_init_phy_ops_generic(hw); 63 1.2.2.2 skrll ret_val = ixgbe_init_ops_generic(hw); 64 1.2.2.2 skrll 65 1.2.2.2 skrll 66 1.2.2.2 skrll /* EEPROM */ 67 1.2.2.2 skrll eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540; 68 1.2.2.2 skrll eeprom->ops.read = &ixgbe_read_eerd_X540; 69 1.2.2.2 skrll eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540; 70 1.2.2.2 skrll eeprom->ops.write = &ixgbe_write_eewr_X540; 71 1.2.2.2 skrll eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540; 72 1.2.2.2 skrll eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540; 73 1.2.2.2 skrll eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540; 74 1.2.2.2 skrll eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540; 75 1.2.2.2 skrll 76 1.2.2.2 skrll /* PHY */ 77 1.2.2.2 skrll phy->ops.init = &ixgbe_init_phy_ops_generic; 78 1.2.2.2 skrll phy->ops.reset = NULL; 79 1.2.2.2 skrll 80 1.2.2.2 skrll /* MAC */ 81 1.2.2.2 skrll mac->ops.reset_hw = &ixgbe_reset_hw_X540; 82 1.2.2.2 skrll mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 83 1.2.2.2 skrll mac->ops.get_media_type = &ixgbe_get_media_type_X540; 84 1.2.2.2 skrll mac->ops.get_supported_physical_layer = 85 1.2.2.2 skrll &ixgbe_get_supported_physical_layer_X540; 86 1.2.2.2 skrll mac->ops.read_analog_reg8 = NULL; 87 1.2.2.2 skrll mac->ops.write_analog_reg8 = NULL; 88 1.2.2.2 skrll mac->ops.start_hw = &ixgbe_start_hw_X540; 89 1.2.2.2 skrll mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 90 1.2.2.2 skrll mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 91 1.2.2.2 skrll mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 92 1.2.2.2 skrll mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 93 1.2.2.2 skrll mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 94 1.2.2.2 skrll mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540; 95 1.2.2.2 skrll mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540; 96 1.2.2.2 skrll mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 97 1.2.2.2 skrll mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 98 1.2.2.2 skrll 99 1.2.2.2 skrll /* RAR, Multicast, VLAN */ 100 1.2.2.2 skrll mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 101 1.2.2.2 skrll mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic; 102 1.2.2.2 skrll mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 103 1.2.2.2 skrll mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 104 1.2.2.2 skrll mac->rar_highwater = 1; 105 1.2.2.2 skrll mac->ops.set_vfta = &ixgbe_set_vfta_generic; 106 1.2.2.2 skrll mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; 107 1.2.2.2 skrll mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 108 1.2.2.2 skrll mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 109 1.2.2.2 skrll mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 110 1.2.2.2 skrll mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 111 1.2.2.2 skrll 112 1.2.2.2 skrll /* Link */ 113 1.2.2.2 skrll mac->ops.get_link_capabilities = 114 1.2.2.2 skrll &ixgbe_get_copper_link_capabilities_generic; 115 1.2.2.2 skrll mac->ops.setup_link = &ixgbe_setup_mac_link_X540; 116 1.2.2.2 skrll mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; 117 1.2.2.2 skrll mac->ops.check_link = &ixgbe_check_mac_link_generic; 118 1.2.2.2 skrll 119 1.2.2.3 skrll 120 1.2.2.2 skrll mac->mcft_size = 128; 121 1.2.2.2 skrll mac->vft_size = 128; 122 1.2.2.2 skrll mac->num_rar_entries = 128; 123 1.2.2.2 skrll mac->rx_pb_size = 384; 124 1.2.2.2 skrll mac->max_tx_queues = 128; 125 1.2.2.2 skrll mac->max_rx_queues = 128; 126 1.2.2.2 skrll mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 127 1.2.2.2 skrll 128 1.2.2.2 skrll /* 129 1.2.2.2 skrll * FWSM register 130 1.2.2.2 skrll * ARC supported; valid only if manageability features are 131 1.2.2.2 skrll * enabled. 132 1.2.2.2 skrll */ 133 1.2.2.2 skrll mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & 134 1.2.2.2 skrll IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; 135 1.2.2.2 skrll 136 1.2.2.2 skrll hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 137 1.2.2.2 skrll 138 1.2.2.2 skrll /* LEDs */ 139 1.2.2.2 skrll mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 140 1.2.2.2 skrll mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 141 1.2.2.2 skrll 142 1.2.2.2 skrll /* Manageability interface */ 143 1.2.2.2 skrll mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; 144 1.2.2.2 skrll 145 1.2.2.2 skrll return ret_val; 146 1.2.2.2 skrll } 147 1.2.2.2 skrll 148 1.2.2.2 skrll /** 149 1.2.2.2 skrll * ixgbe_get_link_capabilities_X540 - Determines link capabilities 150 1.2.2.2 skrll * @hw: pointer to hardware structure 151 1.2.2.2 skrll * @speed: pointer to link speed 152 1.2.2.2 skrll * @autoneg: TRUE when autoneg or autotry is enabled 153 1.2.2.2 skrll * 154 1.2.2.2 skrll * Determines the link capabilities by reading the AUTOC register. 155 1.2.2.2 skrll **/ 156 1.2.2.2 skrll s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 157 1.2.2.2 skrll ixgbe_link_speed *speed, 158 1.2.2.2 skrll bool *autoneg) 159 1.2.2.2 skrll { 160 1.2.2.2 skrll ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 161 1.2.2.2 skrll 162 1.2.2.2 skrll return IXGBE_SUCCESS; 163 1.2.2.2 skrll } 164 1.2.2.2 skrll 165 1.2.2.2 skrll /** 166 1.2.2.2 skrll * ixgbe_get_media_type_X540 - Get media type 167 1.2.2.2 skrll * @hw: pointer to hardware structure 168 1.2.2.2 skrll * 169 1.2.2.2 skrll * Returns the media type (fiber, copper, backplane) 170 1.2.2.2 skrll **/ 171 1.2.2.2 skrll enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 172 1.2.2.2 skrll { 173 1.2.2.2 skrll UNREFERENCED_1PARAMETER(hw); 174 1.2.2.2 skrll return ixgbe_media_type_copper; 175 1.2.2.2 skrll } 176 1.2.2.2 skrll 177 1.2.2.2 skrll /** 178 1.2.2.2 skrll * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 179 1.2.2.2 skrll * @hw: pointer to hardware structure 180 1.2.2.2 skrll * @speed: new link speed 181 1.2.2.2 skrll * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 182 1.2.2.2 skrll **/ 183 1.2.2.2 skrll s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 184 1.2.2.3 skrll ixgbe_link_speed speed, 185 1.2.2.2 skrll bool autoneg_wait_to_complete) 186 1.2.2.2 skrll { 187 1.2.2.2 skrll DEBUGFUNC("ixgbe_setup_mac_link_X540"); 188 1.2.2.3 skrll return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 189 1.2.2.2 skrll } 190 1.2.2.2 skrll 191 1.2.2.2 skrll /** 192 1.2.2.2 skrll * ixgbe_reset_hw_X540 - Perform hardware reset 193 1.2.2.2 skrll * @hw: pointer to hardware structure 194 1.2.2.2 skrll * 195 1.2.2.2 skrll * Resets the hardware by resetting the transmit and receive units, masks 196 1.2.2.2 skrll * and clears all interrupts, and perform a reset. 197 1.2.2.2 skrll **/ 198 1.2.2.2 skrll s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 199 1.2.2.2 skrll { 200 1.2.2.2 skrll s32 status; 201 1.2.2.2 skrll u32 ctrl, i; 202 1.2.2.2 skrll 203 1.2.2.2 skrll DEBUGFUNC("ixgbe_reset_hw_X540"); 204 1.2.2.2 skrll 205 1.2.2.2 skrll /* Call adapter stop to disable tx/rx and clear interrupts */ 206 1.2.2.2 skrll status = hw->mac.ops.stop_adapter(hw); 207 1.2.2.2 skrll if (status != IXGBE_SUCCESS) 208 1.2.2.2 skrll goto reset_hw_out; 209 1.2.2.2 skrll 210 1.2.2.2 skrll /* flush pending Tx transactions */ 211 1.2.2.2 skrll ixgbe_clear_tx_pending(hw); 212 1.2.2.2 skrll 213 1.2.2.2 skrll mac_reset_top: 214 1.2.2.2 skrll ctrl = IXGBE_CTRL_RST; 215 1.2.2.2 skrll ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 216 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 217 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 218 1.2.2.2 skrll 219 1.2.2.2 skrll /* Poll for reset bit to self-clear indicating reset is complete */ 220 1.2.2.2 skrll for (i = 0; i < 10; i++) { 221 1.2.2.2 skrll usec_delay(1); 222 1.2.2.2 skrll ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 223 1.2.2.2 skrll if (!(ctrl & IXGBE_CTRL_RST_MASK)) 224 1.2.2.2 skrll break; 225 1.2.2.2 skrll } 226 1.2.2.2 skrll 227 1.2.2.2 skrll if (ctrl & IXGBE_CTRL_RST_MASK) { 228 1.2.2.2 skrll status = IXGBE_ERR_RESET_FAILED; 229 1.2.2.2 skrll DEBUGOUT("Reset polling failed to complete.\n"); 230 1.2.2.2 skrll } 231 1.2.2.2 skrll msec_delay(100); 232 1.2.2.2 skrll 233 1.2.2.2 skrll /* 234 1.2.2.2 skrll * Double resets are required for recovery from certain error 235 1.2.2.2 skrll * conditions. Between resets, it is necessary to stall to allow time 236 1.2.2.2 skrll * for any pending HW events to complete. 237 1.2.2.2 skrll */ 238 1.2.2.2 skrll if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 239 1.2.2.2 skrll hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 240 1.2.2.2 skrll goto mac_reset_top; 241 1.2.2.2 skrll } 242 1.2.2.2 skrll 243 1.2.2.2 skrll /* Set the Rx packet buffer size. */ 244 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 245 1.2.2.2 skrll 246 1.2.2.2 skrll /* Store the permanent mac address */ 247 1.2.2.2 skrll hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 248 1.2.2.2 skrll 249 1.2.2.2 skrll /* 250 1.2.2.2 skrll * Store MAC address from RAR0, clear receive address registers, and 251 1.2.2.2 skrll * clear the multicast table. Also reset num_rar_entries to 128, 252 1.2.2.2 skrll * since we modify this value when programming the SAN MAC address. 253 1.2.2.2 skrll */ 254 1.2.2.2 skrll hw->mac.num_rar_entries = 128; 255 1.2.2.2 skrll hw->mac.ops.init_rx_addrs(hw); 256 1.2.2.2 skrll 257 1.2.2.2 skrll /* Store the permanent SAN mac address */ 258 1.2.2.2 skrll hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 259 1.2.2.2 skrll 260 1.2.2.2 skrll /* Add the SAN MAC address to the RAR only if it's a valid address */ 261 1.2.2.2 skrll if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 262 1.2.2.2 skrll hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 263 1.2.2.2 skrll hw->mac.san_addr, 0, IXGBE_RAH_AV); 264 1.2.2.2 skrll 265 1.2.2.2 skrll /* Save the SAN MAC RAR index */ 266 1.2.2.2 skrll hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 267 1.2.2.2 skrll 268 1.2.2.2 skrll /* Reserve the last RAR for the SAN MAC address */ 269 1.2.2.2 skrll hw->mac.num_rar_entries--; 270 1.2.2.2 skrll } 271 1.2.2.2 skrll 272 1.2.2.2 skrll /* Store the alternative WWNN/WWPN prefix */ 273 1.2.2.2 skrll hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 274 1.2.2.2 skrll &hw->mac.wwpn_prefix); 275 1.2.2.2 skrll 276 1.2.2.2 skrll reset_hw_out: 277 1.2.2.2 skrll return status; 278 1.2.2.2 skrll } 279 1.2.2.2 skrll 280 1.2.2.2 skrll /** 281 1.2.2.2 skrll * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 282 1.2.2.2 skrll * @hw: pointer to hardware structure 283 1.2.2.2 skrll * 284 1.2.2.2 skrll * Starts the hardware using the generic start_hw function 285 1.2.2.2 skrll * and the generation start_hw function. 286 1.2.2.2 skrll * Then performs revision-specific operations, if any. 287 1.2.2.2 skrll **/ 288 1.2.2.2 skrll s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 289 1.2.2.2 skrll { 290 1.2.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 291 1.2.2.2 skrll 292 1.2.2.2 skrll DEBUGFUNC("ixgbe_start_hw_X540"); 293 1.2.2.2 skrll 294 1.2.2.2 skrll ret_val = ixgbe_start_hw_generic(hw); 295 1.2.2.2 skrll if (ret_val != IXGBE_SUCCESS) 296 1.2.2.2 skrll goto out; 297 1.2.2.2 skrll 298 1.2.2.2 skrll ret_val = ixgbe_start_hw_gen2(hw); 299 1.2.2.2 skrll 300 1.2.2.2 skrll out: 301 1.2.2.2 skrll return ret_val; 302 1.2.2.2 skrll } 303 1.2.2.2 skrll 304 1.2.2.2 skrll /** 305 1.2.2.2 skrll * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 306 1.2.2.2 skrll * @hw: pointer to hardware structure 307 1.2.2.2 skrll * 308 1.2.2.2 skrll * Determines physical layer capabilities of the current configuration. 309 1.2.2.2 skrll **/ 310 1.2.2.2 skrll u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 311 1.2.2.2 skrll { 312 1.2.2.2 skrll u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 313 1.2.2.2 skrll u16 ext_ability = 0; 314 1.2.2.2 skrll 315 1.2.2.2 skrll DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 316 1.2.2.2 skrll 317 1.2.2.2 skrll hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 318 1.2.2.2 skrll IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 319 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 320 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 321 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 322 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 323 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 324 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 325 1.2.2.2 skrll 326 1.2.2.2 skrll return physical_layer; 327 1.2.2.2 skrll } 328 1.2.2.2 skrll 329 1.2.2.2 skrll /** 330 1.2.2.2 skrll * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 331 1.2.2.2 skrll * @hw: pointer to hardware structure 332 1.2.2.2 skrll * 333 1.2.2.2 skrll * Initializes the EEPROM parameters ixgbe_eeprom_info within the 334 1.2.2.2 skrll * ixgbe_hw struct in order to set up EEPROM access. 335 1.2.2.2 skrll **/ 336 1.2.2.2 skrll s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 337 1.2.2.2 skrll { 338 1.2.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 339 1.2.2.2 skrll u32 eec; 340 1.2.2.2 skrll u16 eeprom_size; 341 1.2.2.2 skrll 342 1.2.2.2 skrll DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 343 1.2.2.2 skrll 344 1.2.2.2 skrll if (eeprom->type == ixgbe_eeprom_uninitialized) { 345 1.2.2.2 skrll eeprom->semaphore_delay = 10; 346 1.2.2.2 skrll eeprom->type = ixgbe_flash; 347 1.2.2.2 skrll 348 1.2.2.2 skrll eec = IXGBE_READ_REG(hw, IXGBE_EEC); 349 1.2.2.2 skrll eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 350 1.2.2.2 skrll IXGBE_EEC_SIZE_SHIFT); 351 1.2.2.2 skrll eeprom->word_size = 1 << (eeprom_size + 352 1.2.2.2 skrll IXGBE_EEPROM_WORD_SIZE_SHIFT); 353 1.2.2.2 skrll 354 1.2.2.2 skrll DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 355 1.2.2.2 skrll eeprom->type, eeprom->word_size); 356 1.2.2.2 skrll } 357 1.2.2.2 skrll 358 1.2.2.2 skrll return IXGBE_SUCCESS; 359 1.2.2.2 skrll } 360 1.2.2.2 skrll 361 1.2.2.2 skrll /** 362 1.2.2.2 skrll * ixgbe_read_eerd_X540- Read EEPROM word using EERD 363 1.2.2.2 skrll * @hw: pointer to hardware structure 364 1.2.2.2 skrll * @offset: offset of word in the EEPROM to read 365 1.2.2.2 skrll * @data: word read from the EEPROM 366 1.2.2.2 skrll * 367 1.2.2.2 skrll * Reads a 16 bit word from the EEPROM using the EERD register. 368 1.2.2.2 skrll **/ 369 1.2.2.2 skrll s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 370 1.2.2.2 skrll { 371 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 372 1.2.2.2 skrll 373 1.2.2.2 skrll DEBUGFUNC("ixgbe_read_eerd_X540"); 374 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 375 1.2.2.2 skrll IXGBE_SUCCESS) 376 1.2.2.2 skrll status = ixgbe_read_eerd_generic(hw, offset, data); 377 1.2.2.2 skrll else 378 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 379 1.2.2.2 skrll 380 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 381 1.2.2.2 skrll return status; 382 1.2.2.2 skrll } 383 1.2.2.2 skrll 384 1.2.2.2 skrll /** 385 1.2.2.2 skrll * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 386 1.2.2.2 skrll * @hw: pointer to hardware structure 387 1.2.2.2 skrll * @offset: offset of word in the EEPROM to read 388 1.2.2.2 skrll * @words: number of words 389 1.2.2.2 skrll * @data: word(s) read from the EEPROM 390 1.2.2.2 skrll * 391 1.2.2.2 skrll * Reads a 16 bit word(s) from the EEPROM using the EERD register. 392 1.2.2.2 skrll **/ 393 1.2.2.2 skrll s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 394 1.2.2.2 skrll u16 offset, u16 words, u16 *data) 395 1.2.2.2 skrll { 396 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 397 1.2.2.2 skrll 398 1.2.2.2 skrll DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 399 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 400 1.2.2.2 skrll IXGBE_SUCCESS) 401 1.2.2.2 skrll status = ixgbe_read_eerd_buffer_generic(hw, offset, 402 1.2.2.2 skrll words, data); 403 1.2.2.2 skrll else 404 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 405 1.2.2.2 skrll 406 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 407 1.2.2.2 skrll return status; 408 1.2.2.2 skrll } 409 1.2.2.2 skrll 410 1.2.2.2 skrll /** 411 1.2.2.2 skrll * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 412 1.2.2.2 skrll * @hw: pointer to hardware structure 413 1.2.2.2 skrll * @offset: offset of word in the EEPROM to write 414 1.2.2.2 skrll * @data: word write to the EEPROM 415 1.2.2.2 skrll * 416 1.2.2.2 skrll * Write a 16 bit word to the EEPROM using the EEWR register. 417 1.2.2.2 skrll **/ 418 1.2.2.2 skrll s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 419 1.2.2.2 skrll { 420 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 421 1.2.2.2 skrll 422 1.2.2.2 skrll DEBUGFUNC("ixgbe_write_eewr_X540"); 423 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 424 1.2.2.2 skrll IXGBE_SUCCESS) 425 1.2.2.2 skrll status = ixgbe_write_eewr_generic(hw, offset, data); 426 1.2.2.2 skrll else 427 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 428 1.2.2.2 skrll 429 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 430 1.2.2.2 skrll return status; 431 1.2.2.2 skrll } 432 1.2.2.2 skrll 433 1.2.2.2 skrll /** 434 1.2.2.2 skrll * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 435 1.2.2.2 skrll * @hw: pointer to hardware structure 436 1.2.2.2 skrll * @offset: offset of word in the EEPROM to write 437 1.2.2.2 skrll * @words: number of words 438 1.2.2.2 skrll * @data: word(s) write to the EEPROM 439 1.2.2.2 skrll * 440 1.2.2.2 skrll * Write a 16 bit word(s) to the EEPROM using the EEWR register. 441 1.2.2.2 skrll **/ 442 1.2.2.2 skrll s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 443 1.2.2.2 skrll u16 offset, u16 words, u16 *data) 444 1.2.2.2 skrll { 445 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 446 1.2.2.2 skrll 447 1.2.2.2 skrll DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 448 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 449 1.2.2.2 skrll IXGBE_SUCCESS) 450 1.2.2.2 skrll status = ixgbe_write_eewr_buffer_generic(hw, offset, 451 1.2.2.2 skrll words, data); 452 1.2.2.2 skrll else 453 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 454 1.2.2.2 skrll 455 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 456 1.2.2.2 skrll return status; 457 1.2.2.2 skrll } 458 1.2.2.2 skrll 459 1.2.2.2 skrll /** 460 1.2.2.2 skrll * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 461 1.2.2.2 skrll * 462 1.2.2.2 skrll * This function does not use synchronization for EERD and EEWR. It can 463 1.2.2.2 skrll * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 464 1.2.2.2 skrll * 465 1.2.2.2 skrll * @hw: pointer to hardware structure 466 1.2.2.2 skrll **/ 467 1.2.2.2 skrll u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 468 1.2.2.2 skrll { 469 1.2.2.2 skrll u16 i; 470 1.2.2.2 skrll u16 j; 471 1.2.2.2 skrll u16 checksum = 0; 472 1.2.2.2 skrll u16 length = 0; 473 1.2.2.2 skrll u16 pointer = 0; 474 1.2.2.2 skrll u16 word = 0; 475 1.2.2.2 skrll 476 1.2.2.2 skrll /* 477 1.2.2.2 skrll * Do not use hw->eeprom.ops.read because we do not want to take 478 1.2.2.2 skrll * the synchronization semaphores here. Instead use 479 1.2.2.2 skrll * ixgbe_read_eerd_generic 480 1.2.2.2 skrll */ 481 1.2.2.2 skrll 482 1.2.2.2 skrll DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 483 1.2.2.2 skrll 484 1.2.2.2 skrll /* Include 0x0-0x3F in the checksum */ 485 1.2.2.2 skrll for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 486 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) { 487 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 488 1.2.2.2 skrll break; 489 1.2.2.2 skrll } 490 1.2.2.2 skrll checksum += word; 491 1.2.2.2 skrll } 492 1.2.2.2 skrll 493 1.2.2.2 skrll /* 494 1.2.2.2 skrll * Include all data from pointers 0x3, 0x6-0xE. This excludes the 495 1.2.2.2 skrll * FW, PHY module, and PCIe Expansion/Option ROM pointers. 496 1.2.2.2 skrll */ 497 1.2.2.2 skrll for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 498 1.2.2.2 skrll if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 499 1.2.2.2 skrll continue; 500 1.2.2.2 skrll 501 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) { 502 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 503 1.2.2.2 skrll break; 504 1.2.2.2 skrll } 505 1.2.2.2 skrll 506 1.2.2.2 skrll /* Skip pointer section if the pointer is invalid. */ 507 1.2.2.2 skrll if (pointer == 0xFFFF || pointer == 0 || 508 1.2.2.2 skrll pointer >= hw->eeprom.word_size) 509 1.2.2.2 skrll continue; 510 1.2.2.2 skrll 511 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, pointer, &length) != 512 1.2.2.2 skrll IXGBE_SUCCESS) { 513 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 514 1.2.2.2 skrll break; 515 1.2.2.2 skrll } 516 1.2.2.2 skrll 517 1.2.2.2 skrll /* Skip pointer section if length is invalid. */ 518 1.2.2.2 skrll if (length == 0xFFFF || length == 0 || 519 1.2.2.2 skrll (pointer + length) >= hw->eeprom.word_size) 520 1.2.2.2 skrll continue; 521 1.2.2.2 skrll 522 1.2.2.2 skrll for (j = pointer+1; j <= pointer+length; j++) { 523 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, j, &word) != 524 1.2.2.2 skrll IXGBE_SUCCESS) { 525 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 526 1.2.2.2 skrll break; 527 1.2.2.2 skrll } 528 1.2.2.2 skrll checksum += word; 529 1.2.2.2 skrll } 530 1.2.2.2 skrll } 531 1.2.2.2 skrll 532 1.2.2.2 skrll checksum = (u16)IXGBE_EEPROM_SUM - checksum; 533 1.2.2.2 skrll 534 1.2.2.2 skrll return checksum; 535 1.2.2.2 skrll } 536 1.2.2.2 skrll 537 1.2.2.2 skrll /** 538 1.2.2.2 skrll * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 539 1.2.2.2 skrll * @hw: pointer to hardware structure 540 1.2.2.2 skrll * @checksum_val: calculated checksum 541 1.2.2.2 skrll * 542 1.2.2.2 skrll * Performs checksum calculation and validates the EEPROM checksum. If the 543 1.2.2.2 skrll * caller does not need checksum_val, the value can be NULL. 544 1.2.2.2 skrll **/ 545 1.2.2.2 skrll s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 546 1.2.2.2 skrll u16 *checksum_val) 547 1.2.2.2 skrll { 548 1.2.2.2 skrll s32 status; 549 1.2.2.2 skrll u16 checksum; 550 1.2.2.2 skrll u16 read_checksum = 0; 551 1.2.2.2 skrll 552 1.2.2.2 skrll DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 553 1.2.2.2 skrll 554 1.2.2.2 skrll /* 555 1.2.2.2 skrll * Read the first word from the EEPROM. If this times out or fails, do 556 1.2.2.2 skrll * not continue or we could be in for a very long wait while every 557 1.2.2.2 skrll * EEPROM read fails 558 1.2.2.2 skrll */ 559 1.2.2.2 skrll status = hw->eeprom.ops.read(hw, 0, &checksum); 560 1.2.2.2 skrll 561 1.2.2.2 skrll if (status != IXGBE_SUCCESS) { 562 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 563 1.2.2.2 skrll goto out; 564 1.2.2.2 skrll } 565 1.2.2.2 skrll 566 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 567 1.2.2.2 skrll IXGBE_SUCCESS) { 568 1.2.2.2 skrll checksum = hw->eeprom.ops.calc_checksum(hw); 569 1.2.2.2 skrll 570 1.2.2.2 skrll /* 571 1.2.2.2 skrll * Do not use hw->eeprom.ops.read because we do not want to take 572 1.2.2.2 skrll * the synchronization semaphores twice here. 573 1.2.2.2 skrll */ 574 1.2.2.2 skrll ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 575 1.2.2.2 skrll &read_checksum); 576 1.2.2.2 skrll 577 1.2.2.2 skrll /* 578 1.2.2.2 skrll * Verify read checksum from EEPROM is the same as 579 1.2.2.2 skrll * calculated checksum 580 1.2.2.2 skrll */ 581 1.2.2.2 skrll if (read_checksum != checksum) 582 1.2.2.2 skrll status = IXGBE_ERR_EEPROM_CHECKSUM; 583 1.2.2.2 skrll 584 1.2.2.2 skrll /* If the user cares, return the calculated checksum */ 585 1.2.2.2 skrll if (checksum_val) 586 1.2.2.2 skrll *checksum_val = checksum; 587 1.2.2.2 skrll } else { 588 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 589 1.2.2.2 skrll } 590 1.2.2.2 skrll 591 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 592 1.2.2.2 skrll out: 593 1.2.2.2 skrll return status; 594 1.2.2.2 skrll } 595 1.2.2.2 skrll 596 1.2.2.2 skrll /** 597 1.2.2.2 skrll * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 598 1.2.2.2 skrll * @hw: pointer to hardware structure 599 1.2.2.2 skrll * 600 1.2.2.2 skrll * After writing EEPROM to shadow RAM using EEWR register, software calculates 601 1.2.2.2 skrll * checksum and updates the EEPROM and instructs the hardware to update 602 1.2.2.2 skrll * the flash. 603 1.2.2.2 skrll **/ 604 1.2.2.2 skrll s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 605 1.2.2.2 skrll { 606 1.2.2.2 skrll s32 status; 607 1.2.2.2 skrll u16 checksum; 608 1.2.2.2 skrll 609 1.2.2.2 skrll DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 610 1.2.2.2 skrll 611 1.2.2.2 skrll /* 612 1.2.2.2 skrll * Read the first word from the EEPROM. If this times out or fails, do 613 1.2.2.2 skrll * not continue or we could be in for a very long wait while every 614 1.2.2.2 skrll * EEPROM read fails 615 1.2.2.2 skrll */ 616 1.2.2.2 skrll status = hw->eeprom.ops.read(hw, 0, &checksum); 617 1.2.2.2 skrll 618 1.2.2.2 skrll if (status != IXGBE_SUCCESS) 619 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 620 1.2.2.2 skrll 621 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 622 1.2.2.2 skrll IXGBE_SUCCESS) { 623 1.2.2.2 skrll checksum = hw->eeprom.ops.calc_checksum(hw); 624 1.2.2.2 skrll 625 1.2.2.2 skrll /* 626 1.2.2.2 skrll * Do not use hw->eeprom.ops.write because we do not want to 627 1.2.2.2 skrll * take the synchronization semaphores twice here. 628 1.2.2.2 skrll */ 629 1.2.2.2 skrll status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, 630 1.2.2.2 skrll checksum); 631 1.2.2.2 skrll 632 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 633 1.2.2.2 skrll status = ixgbe_update_flash_X540(hw); 634 1.2.2.2 skrll else 635 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 636 1.2.2.2 skrll } 637 1.2.2.2 skrll 638 1.2.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 639 1.2.2.2 skrll 640 1.2.2.2 skrll return status; 641 1.2.2.2 skrll } 642 1.2.2.2 skrll 643 1.2.2.2 skrll /** 644 1.2.2.2 skrll * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 645 1.2.2.2 skrll * @hw: pointer to hardware structure 646 1.2.2.2 skrll * 647 1.2.2.2 skrll * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 648 1.2.2.2 skrll * EEPROM from shadow RAM to the flash device. 649 1.2.2.2 skrll **/ 650 1.2.2.2 skrll static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 651 1.2.2.2 skrll { 652 1.2.2.2 skrll u32 flup; 653 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 654 1.2.2.2 skrll 655 1.2.2.2 skrll DEBUGFUNC("ixgbe_update_flash_X540"); 656 1.2.2.2 skrll 657 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 658 1.2.2.2 skrll if (status == IXGBE_ERR_EEPROM) { 659 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 660 1.2.2.2 skrll goto out; 661 1.2.2.2 skrll } 662 1.2.2.2 skrll 663 1.2.2.2 skrll flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 664 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 665 1.2.2.2 skrll 666 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 667 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 668 1.2.2.2 skrll DEBUGOUT("Flash update complete\n"); 669 1.2.2.2 skrll else 670 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 671 1.2.2.2 skrll 672 1.2.2.2 skrll if (hw->revision_id == 0) { 673 1.2.2.2 skrll flup = IXGBE_READ_REG(hw, IXGBE_EEC); 674 1.2.2.2 skrll 675 1.2.2.2 skrll if (flup & IXGBE_EEC_SEC1VAL) { 676 1.2.2.2 skrll flup |= IXGBE_EEC_FLUP; 677 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 678 1.2.2.2 skrll } 679 1.2.2.2 skrll 680 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 681 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 682 1.2.2.2 skrll DEBUGOUT("Flash update complete\n"); 683 1.2.2.2 skrll else 684 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 685 1.2.2.2 skrll } 686 1.2.2.2 skrll out: 687 1.2.2.2 skrll return status; 688 1.2.2.2 skrll } 689 1.2.2.2 skrll 690 1.2.2.2 skrll /** 691 1.2.2.2 skrll * ixgbe_poll_flash_update_done_X540 - Poll flash update status 692 1.2.2.2 skrll * @hw: pointer to hardware structure 693 1.2.2.2 skrll * 694 1.2.2.2 skrll * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 695 1.2.2.2 skrll * flash update is done. 696 1.2.2.2 skrll **/ 697 1.2.2.2 skrll static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 698 1.2.2.2 skrll { 699 1.2.2.2 skrll u32 i; 700 1.2.2.2 skrll u32 reg; 701 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 702 1.2.2.2 skrll 703 1.2.2.2 skrll DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 704 1.2.2.2 skrll 705 1.2.2.2 skrll for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 706 1.2.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_EEC); 707 1.2.2.2 skrll if (reg & IXGBE_EEC_FLUDONE) { 708 1.2.2.2 skrll status = IXGBE_SUCCESS; 709 1.2.2.2 skrll break; 710 1.2.2.2 skrll } 711 1.2.2.2 skrll usec_delay(5); 712 1.2.2.2 skrll } 713 1.2.2.2 skrll return status; 714 1.2.2.2 skrll } 715 1.2.2.2 skrll 716 1.2.2.2 skrll /** 717 1.2.2.2 skrll * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 718 1.2.2.2 skrll * @hw: pointer to hardware structure 719 1.2.2.2 skrll * @mask: Mask to specify which semaphore to acquire 720 1.2.2.2 skrll * 721 1.2.2.2 skrll * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 722 1.2.2.2 skrll * the specified function (CSR, PHY0, PHY1, NVM, Flash) 723 1.2.2.2 skrll **/ 724 1.2.2.2 skrll s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 725 1.2.2.2 skrll { 726 1.2.2.2 skrll u32 swfw_sync; 727 1.2.2.2 skrll u32 swmask = mask; 728 1.2.2.2 skrll u32 fwmask = mask << 5; 729 1.2.2.2 skrll u32 hwmask = 0; 730 1.2.2.2 skrll u32 timeout = 200; 731 1.2.2.2 skrll u32 i; 732 1.2.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 733 1.2.2.2 skrll 734 1.2.2.2 skrll DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 735 1.2.2.2 skrll 736 1.2.2.2 skrll if (swmask == IXGBE_GSSR_EEP_SM) 737 1.2.2.2 skrll hwmask = IXGBE_GSSR_FLASH_SM; 738 1.2.2.2 skrll 739 1.2.2.2 skrll /* SW only mask doesn't have FW bit pair */ 740 1.2.2.2 skrll if (swmask == IXGBE_GSSR_SW_MNG_SM) 741 1.2.2.2 skrll fwmask = 0; 742 1.2.2.2 skrll 743 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 744 1.2.2.2 skrll /* 745 1.2.2.2 skrll * SW NVM semaphore bit is used for access to all 746 1.2.2.2 skrll * SW_FW_SYNC bits (not just NVM) 747 1.2.2.2 skrll */ 748 1.2.2.2 skrll if (ixgbe_get_swfw_sync_semaphore(hw)) { 749 1.2.2.2 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 750 1.2.2.2 skrll goto out; 751 1.2.2.2 skrll } 752 1.2.2.2 skrll 753 1.2.2.2 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 754 1.2.2.2 skrll if (!(swfw_sync & (fwmask | swmask | hwmask))) { 755 1.2.2.2 skrll swfw_sync |= swmask; 756 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 757 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 758 1.2.2.2 skrll msec_delay(5); 759 1.2.2.2 skrll goto out; 760 1.2.2.2 skrll } else { 761 1.2.2.2 skrll /* 762 1.2.2.2 skrll * Firmware currently using resource (fwmask), hardware 763 1.2.2.2 skrll * currently using resource (hwmask), or other software 764 1.2.2.2 skrll * thread currently using resource (swmask) 765 1.2.2.2 skrll */ 766 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 767 1.2.2.2 skrll msec_delay(5); 768 1.2.2.2 skrll } 769 1.2.2.2 skrll } 770 1.2.2.2 skrll 771 1.2.2.2 skrll /* Failed to get SW only semaphore */ 772 1.2.2.2 skrll if (swmask == IXGBE_GSSR_SW_MNG_SM) { 773 1.2.2.2 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 774 1.2.2.2 skrll goto out; 775 1.2.2.2 skrll } 776 1.2.2.2 skrll 777 1.2.2.2 skrll /* If the resource is not released by the FW/HW the SW can assume that 778 1.2.2.2 skrll * the FW/HW malfunctions. In that case the SW should sets the SW bit(s) 779 1.2.2.2 skrll * of the requested resource(s) while ignoring the corresponding FW/HW 780 1.2.2.2 skrll * bits in the SW_FW_SYNC register. 781 1.2.2.2 skrll */ 782 1.2.2.2 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 783 1.2.2.2 skrll if (swfw_sync & (fwmask | hwmask)) { 784 1.2.2.2 skrll if (ixgbe_get_swfw_sync_semaphore(hw)) { 785 1.2.2.2 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 786 1.2.2.2 skrll goto out; 787 1.2.2.2 skrll } 788 1.2.2.2 skrll 789 1.2.2.2 skrll swfw_sync |= swmask; 790 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 791 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 792 1.2.2.2 skrll msec_delay(5); 793 1.2.2.2 skrll } 794 1.2.2.2 skrll 795 1.2.2.2 skrll out: 796 1.2.2.2 skrll return ret_val; 797 1.2.2.2 skrll } 798 1.2.2.2 skrll 799 1.2.2.2 skrll /** 800 1.2.2.2 skrll * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 801 1.2.2.2 skrll * @hw: pointer to hardware structure 802 1.2.2.2 skrll * @mask: Mask to specify which semaphore to release 803 1.2.2.2 skrll * 804 1.2.2.2 skrll * Releases the SWFW semaphore through the SW_FW_SYNC register 805 1.2.2.2 skrll * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 806 1.2.2.2 skrll **/ 807 1.2.2.2 skrll void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 808 1.2.2.2 skrll { 809 1.2.2.2 skrll u32 swfw_sync; 810 1.2.2.2 skrll u32 swmask = mask; 811 1.2.2.2 skrll 812 1.2.2.2 skrll DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 813 1.2.2.2 skrll 814 1.2.2.2 skrll ixgbe_get_swfw_sync_semaphore(hw); 815 1.2.2.2 skrll 816 1.2.2.2 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 817 1.2.2.2 skrll swfw_sync &= ~swmask; 818 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 819 1.2.2.2 skrll 820 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 821 1.2.2.2 skrll msec_delay(5); 822 1.2.2.2 skrll } 823 1.2.2.2 skrll 824 1.2.2.2 skrll /** 825 1.2.2.2 skrll * ixgbe_get_nvm_semaphore - Get hardware semaphore 826 1.2.2.2 skrll * @hw: pointer to hardware structure 827 1.2.2.2 skrll * 828 1.2.2.2 skrll * Sets the hardware semaphores so SW/FW can gain control of shared resources 829 1.2.2.2 skrll **/ 830 1.2.2.2 skrll static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 831 1.2.2.2 skrll { 832 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 833 1.2.2.2 skrll u32 timeout = 2000; 834 1.2.2.2 skrll u32 i; 835 1.2.2.2 skrll u32 swsm; 836 1.2.2.2 skrll 837 1.2.2.2 skrll DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 838 1.2.2.2 skrll 839 1.2.2.2 skrll /* Get SMBI software semaphore between device drivers first */ 840 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 841 1.2.2.2 skrll /* 842 1.2.2.2 skrll * If the SMBI bit is 0 when we read it, then the bit will be 843 1.2.2.2 skrll * set and we have the semaphore 844 1.2.2.2 skrll */ 845 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 846 1.2.2.2 skrll if (!(swsm & IXGBE_SWSM_SMBI)) { 847 1.2.2.2 skrll status = IXGBE_SUCCESS; 848 1.2.2.2 skrll break; 849 1.2.2.2 skrll } 850 1.2.2.2 skrll usec_delay(50); 851 1.2.2.2 skrll } 852 1.2.2.2 skrll 853 1.2.2.2 skrll /* Now get the semaphore between SW/FW through the REGSMP bit */ 854 1.2.2.2 skrll if (status == IXGBE_SUCCESS) { 855 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 856 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 857 1.2.2.2 skrll if (!(swsm & IXGBE_SWFW_REGSMP)) 858 1.2.2.2 skrll break; 859 1.2.2.2 skrll 860 1.2.2.2 skrll usec_delay(50); 861 1.2.2.2 skrll } 862 1.2.2.2 skrll 863 1.2.2.2 skrll /* 864 1.2.2.2 skrll * Release semaphores and return error if SW NVM semaphore 865 1.2.2.2 skrll * was not granted because we don't have access to the EEPROM 866 1.2.2.2 skrll */ 867 1.2.2.2 skrll if (i >= timeout) { 868 1.2.2.2 skrll DEBUGOUT("REGSMP Software NVM semaphore not " 869 1.2.2.2 skrll "granted.\n"); 870 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 871 1.2.2.2 skrll status = IXGBE_ERR_EEPROM; 872 1.2.2.2 skrll } 873 1.2.2.2 skrll } else { 874 1.2.2.2 skrll DEBUGOUT("Software semaphore SMBI between device drivers " 875 1.2.2.2 skrll "not granted.\n"); 876 1.2.2.2 skrll } 877 1.2.2.2 skrll 878 1.2.2.2 skrll return status; 879 1.2.2.2 skrll } 880 1.2.2.2 skrll 881 1.2.2.2 skrll /** 882 1.2.2.2 skrll * ixgbe_release_nvm_semaphore - Release hardware semaphore 883 1.2.2.2 skrll * @hw: pointer to hardware structure 884 1.2.2.2 skrll * 885 1.2.2.2 skrll * This function clears hardware semaphore bits. 886 1.2.2.2 skrll **/ 887 1.2.2.2 skrll static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 888 1.2.2.2 skrll { 889 1.2.2.2 skrll u32 swsm; 890 1.2.2.2 skrll 891 1.2.2.2 skrll DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 892 1.2.2.2 skrll 893 1.2.2.2 skrll /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 894 1.2.2.2 skrll 895 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 896 1.2.2.2 skrll swsm &= ~IXGBE_SWSM_SMBI; 897 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 898 1.2.2.2 skrll 899 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 900 1.2.2.2 skrll swsm &= ~IXGBE_SWFW_REGSMP; 901 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 902 1.2.2.2 skrll 903 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 904 1.2.2.2 skrll } 905 1.2.2.2 skrll 906 1.2.2.2 skrll /** 907 1.2.2.2 skrll * ixgbe_blink_led_start_X540 - Blink LED based on index. 908 1.2.2.2 skrll * @hw: pointer to hardware structure 909 1.2.2.2 skrll * @index: led number to blink 910 1.2.2.2 skrll * 911 1.2.2.2 skrll * Devices that implement the version 2 interface: 912 1.2.2.2 skrll * X540 913 1.2.2.2 skrll **/ 914 1.2.2.2 skrll s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 915 1.2.2.2 skrll { 916 1.2.2.2 skrll u32 macc_reg; 917 1.2.2.2 skrll u32 ledctl_reg; 918 1.2.2.2 skrll ixgbe_link_speed speed; 919 1.2.2.2 skrll bool link_up; 920 1.2.2.2 skrll 921 1.2.2.2 skrll DEBUGFUNC("ixgbe_blink_led_start_X540"); 922 1.2.2.2 skrll 923 1.2.2.2 skrll /* 924 1.2.2.2 skrll * Link should be up in order for the blink bit in the LED control 925 1.2.2.2 skrll * register to work. Force link and speed in the MAC if link is down. 926 1.2.2.2 skrll * This will be reversed when we stop the blinking. 927 1.2.2.2 skrll */ 928 1.2.2.2 skrll hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 929 1.2.2.2 skrll if (link_up == FALSE) { 930 1.2.2.2 skrll macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 931 1.2.2.2 skrll macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 932 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 933 1.2.2.2 skrll } 934 1.2.2.2 skrll /* Set the LED to LINK_UP + BLINK. */ 935 1.2.2.2 skrll ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 936 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 937 1.2.2.2 skrll ledctl_reg |= IXGBE_LED_BLINK(index); 938 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 939 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 940 1.2.2.2 skrll 941 1.2.2.2 skrll return IXGBE_SUCCESS; 942 1.2.2.2 skrll } 943 1.2.2.2 skrll 944 1.2.2.2 skrll /** 945 1.2.2.2 skrll * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 946 1.2.2.2 skrll * @hw: pointer to hardware structure 947 1.2.2.2 skrll * @index: led number to stop blinking 948 1.2.2.2 skrll * 949 1.2.2.2 skrll * Devices that implement the version 2 interface: 950 1.2.2.2 skrll * X540 951 1.2.2.2 skrll **/ 952 1.2.2.2 skrll s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 953 1.2.2.2 skrll { 954 1.2.2.2 skrll u32 macc_reg; 955 1.2.2.2 skrll u32 ledctl_reg; 956 1.2.2.2 skrll 957 1.2.2.2 skrll DEBUGFUNC("ixgbe_blink_led_stop_X540"); 958 1.2.2.2 skrll 959 1.2.2.2 skrll /* Restore the LED to its default value. */ 960 1.2.2.2 skrll ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 961 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 962 1.2.2.2 skrll ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 963 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_BLINK(index); 964 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 965 1.2.2.2 skrll 966 1.2.2.2 skrll /* Unforce link and speed in the MAC. */ 967 1.2.2.2 skrll macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 968 1.2.2.2 skrll macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 969 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 970 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 971 1.2.2.2 skrll 972 1.2.2.2 skrll return IXGBE_SUCCESS; 973 1.2.2.2 skrll } 974 1.2.2.2 skrll 975 1.2.2.3 skrll 976
Indexes created Tue Oct 21 08:09:48 GMT 2025