ixgbe_x540.c revision 1.2.2.4
1 1.2.2.2 skrll /****************************************************************************** 2 1.2.2.2 skrll 3 1.2.2.3 skrll Copyright (c) 2001-2013, Intel Corporation 4 1.2.2.2 skrll All rights reserved. 5 1.2.2.2 skrll 6 1.2.2.2 skrll Redistribution and use in source and binary forms, with or without 7 1.2.2.2 skrll modification, are permitted provided that the following conditions are met: 8 1.2.2.2 skrll 9 1.2.2.2 skrll 1. Redistributions of source code must retain the above copyright notice, 10 1.2.2.2 skrll this list of conditions and the following disclaimer. 11 1.2.2.2 skrll 12 1.2.2.2 skrll 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll 16 1.2.2.2 skrll 3. Neither the name of the Intel Corporation nor the names of its 17 1.2.2.2 skrll contributors may be used to endorse or promote products derived from 18 1.2.2.2 skrll this software without specific prior written permission. 19 1.2.2.2 skrll 20 1.2.2.2 skrll THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.2.2.2 skrll AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.2.2.2 skrll IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.2.2.2 skrll ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.2.2.2 skrll LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.2.2.2 skrll CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.2.2.2 skrll SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.2.2.2 skrll INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.2.2.2 skrll CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.2.2.2 skrll ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.2.2.2 skrll POSSIBILITY OF SUCH DAMAGE. 31 1.2.2.2 skrll 32 1.2.2.2 skrll ******************************************************************************/ 33 1.2.2.4 skrll /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 251964 2013-06-18 21:28:19Z jfv $*/ 34 1.2.2.2 skrll 35 1.2.2.2 skrll #include "ixgbe_x540.h" 36 1.2.2.2 skrll #include "ixgbe_type.h" 37 1.2.2.2 skrll #include "ixgbe_api.h" 38 1.2.2.2 skrll #include "ixgbe_common.h" 39 1.2.2.2 skrll #include "ixgbe_phy.h" 40 1.2.2.2 skrll 41 1.2.2.2 skrll static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 42 1.2.2.2 skrll static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 43 1.2.2.2 skrll static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 44 1.2.2.2 skrll 45 1.2.2.2 skrll /** 46 1.2.2.2 skrll * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 47 1.2.2.2 skrll * @hw: pointer to hardware structure 48 1.2.2.2 skrll * 49 1.2.2.2 skrll * Initialize the function pointers and assign the MAC type for X540. 50 1.2.2.2 skrll * Does not touch the hardware. 51 1.2.2.2 skrll **/ 52 1.2.2.2 skrll s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 53 1.2.2.2 skrll { 54 1.2.2.2 skrll struct ixgbe_mac_info *mac = &hw->mac; 55 1.2.2.2 skrll struct ixgbe_phy_info *phy = &hw->phy; 56 1.2.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 57 1.2.2.2 skrll s32 ret_val; 58 1.2.2.2 skrll 59 1.2.2.2 skrll DEBUGFUNC("ixgbe_init_ops_X540"); 60 1.2.2.2 skrll 61 1.2.2.2 skrll ret_val = ixgbe_init_phy_ops_generic(hw); 62 1.2.2.2 skrll ret_val = ixgbe_init_ops_generic(hw); 63 1.2.2.2 skrll 64 1.2.2.2 skrll 65 1.2.2.2 skrll /* EEPROM */ 66 1.2.2.2 skrll eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540; 67 1.2.2.2 skrll eeprom->ops.read = &ixgbe_read_eerd_X540; 68 1.2.2.2 skrll eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540; 69 1.2.2.2 skrll eeprom->ops.write = &ixgbe_write_eewr_X540; 70 1.2.2.2 skrll eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540; 71 1.2.2.2 skrll eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540; 72 1.2.2.2 skrll eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540; 73 1.2.2.2 skrll eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540; 74 1.2.2.2 skrll 75 1.2.2.2 skrll /* PHY */ 76 1.2.2.2 skrll phy->ops.init = &ixgbe_init_phy_ops_generic; 77 1.2.2.2 skrll phy->ops.reset = NULL; 78 1.2.2.2 skrll 79 1.2.2.2 skrll /* MAC */ 80 1.2.2.2 skrll mac->ops.reset_hw = &ixgbe_reset_hw_X540; 81 1.2.2.2 skrll mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 82 1.2.2.2 skrll mac->ops.get_media_type = &ixgbe_get_media_type_X540; 83 1.2.2.2 skrll mac->ops.get_supported_physical_layer = 84 1.2.2.2 skrll &ixgbe_get_supported_physical_layer_X540; 85 1.2.2.2 skrll mac->ops.read_analog_reg8 = NULL; 86 1.2.2.2 skrll mac->ops.write_analog_reg8 = NULL; 87 1.2.2.2 skrll mac->ops.start_hw = &ixgbe_start_hw_X540; 88 1.2.2.2 skrll mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 89 1.2.2.2 skrll mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 90 1.2.2.2 skrll mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 91 1.2.2.2 skrll mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 92 1.2.2.2 skrll mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 93 1.2.2.2 skrll mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540; 94 1.2.2.2 skrll mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540; 95 1.2.2.2 skrll mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 96 1.2.2.2 skrll mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 97 1.2.2.2 skrll 98 1.2.2.2 skrll /* RAR, Multicast, VLAN */ 99 1.2.2.2 skrll mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 100 1.2.2.2 skrll mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic; 101 1.2.2.2 skrll mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 102 1.2.2.2 skrll mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 103 1.2.2.2 skrll mac->rar_highwater = 1; 104 1.2.2.2 skrll mac->ops.set_vfta = &ixgbe_set_vfta_generic; 105 1.2.2.2 skrll mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; 106 1.2.2.2 skrll mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 107 1.2.2.2 skrll mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 108 1.2.2.2 skrll mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 109 1.2.2.2 skrll mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 110 1.2.2.2 skrll 111 1.2.2.2 skrll /* Link */ 112 1.2.2.2 skrll mac->ops.get_link_capabilities = 113 1.2.2.2 skrll &ixgbe_get_copper_link_capabilities_generic; 114 1.2.2.2 skrll mac->ops.setup_link = &ixgbe_setup_mac_link_X540; 115 1.2.2.2 skrll mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; 116 1.2.2.2 skrll mac->ops.check_link = &ixgbe_check_mac_link_generic; 117 1.2.2.2 skrll 118 1.2.2.3 skrll 119 1.2.2.2 skrll mac->mcft_size = 128; 120 1.2.2.2 skrll mac->vft_size = 128; 121 1.2.2.2 skrll mac->num_rar_entries = 128; 122 1.2.2.2 skrll mac->rx_pb_size = 384; 123 1.2.2.2 skrll mac->max_tx_queues = 128; 124 1.2.2.2 skrll mac->max_rx_queues = 128; 125 1.2.2.2 skrll mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 126 1.2.2.2 skrll 127 1.2.2.2 skrll /* 128 1.2.2.2 skrll * FWSM register 129 1.2.2.2 skrll * ARC supported; valid only if manageability features are 130 1.2.2.2 skrll * enabled. 131 1.2.2.2 skrll */ 132 1.2.2.2 skrll mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & 133 1.2.2.2 skrll IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; 134 1.2.2.2 skrll 135 1.2.2.2 skrll hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 136 1.2.2.2 skrll 137 1.2.2.2 skrll /* LEDs */ 138 1.2.2.2 skrll mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 139 1.2.2.2 skrll mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 140 1.2.2.2 skrll 141 1.2.2.2 skrll /* Manageability interface */ 142 1.2.2.2 skrll mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; 143 1.2.2.2 skrll 144 1.2.2.4 skrll mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic; 145 1.2.2.4 skrll 146 1.2.2.2 skrll return ret_val; 147 1.2.2.2 skrll } 148 1.2.2.2 skrll 149 1.2.2.2 skrll /** 150 1.2.2.2 skrll * ixgbe_get_link_capabilities_X540 - Determines link capabilities 151 1.2.2.2 skrll * @hw: pointer to hardware structure 152 1.2.2.2 skrll * @speed: pointer to link speed 153 1.2.2.2 skrll * @autoneg: TRUE when autoneg or autotry is enabled 154 1.2.2.2 skrll * 155 1.2.2.2 skrll * Determines the link capabilities by reading the AUTOC register. 156 1.2.2.2 skrll **/ 157 1.2.2.2 skrll s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 158 1.2.2.2 skrll ixgbe_link_speed *speed, 159 1.2.2.2 skrll bool *autoneg) 160 1.2.2.2 skrll { 161 1.2.2.2 skrll ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 162 1.2.2.2 skrll 163 1.2.2.2 skrll return IXGBE_SUCCESS; 164 1.2.2.2 skrll } 165 1.2.2.2 skrll 166 1.2.2.2 skrll /** 167 1.2.2.2 skrll * ixgbe_get_media_type_X540 - Get media type 168 1.2.2.2 skrll * @hw: pointer to hardware structure 169 1.2.2.2 skrll * 170 1.2.2.2 skrll * Returns the media type (fiber, copper, backplane) 171 1.2.2.2 skrll **/ 172 1.2.2.2 skrll enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 173 1.2.2.2 skrll { 174 1.2.2.2 skrll UNREFERENCED_1PARAMETER(hw); 175 1.2.2.2 skrll return ixgbe_media_type_copper; 176 1.2.2.2 skrll } 177 1.2.2.2 skrll 178 1.2.2.2 skrll /** 179 1.2.2.2 skrll * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 180 1.2.2.2 skrll * @hw: pointer to hardware structure 181 1.2.2.2 skrll * @speed: new link speed 182 1.2.2.2 skrll * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 183 1.2.2.2 skrll **/ 184 1.2.2.2 skrll s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 185 1.2.2.3 skrll ixgbe_link_speed speed, 186 1.2.2.2 skrll bool autoneg_wait_to_complete) 187 1.2.2.2 skrll { 188 1.2.2.2 skrll DEBUGFUNC("ixgbe_setup_mac_link_X540"); 189 1.2.2.3 skrll return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 190 1.2.2.2 skrll } 191 1.2.2.2 skrll 192 1.2.2.2 skrll /** 193 1.2.2.2 skrll * ixgbe_reset_hw_X540 - Perform hardware reset 194 1.2.2.2 skrll * @hw: pointer to hardware structure 195 1.2.2.2 skrll * 196 1.2.2.2 skrll * Resets the hardware by resetting the transmit and receive units, masks 197 1.2.2.2 skrll * and clears all interrupts, and perform a reset. 198 1.2.2.2 skrll **/ 199 1.2.2.2 skrll s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 200 1.2.2.2 skrll { 201 1.2.2.2 skrll s32 status; 202 1.2.2.2 skrll u32 ctrl, i; 203 1.2.2.2 skrll 204 1.2.2.2 skrll DEBUGFUNC("ixgbe_reset_hw_X540"); 205 1.2.2.2 skrll 206 1.2.2.2 skrll /* Call adapter stop to disable tx/rx and clear interrupts */ 207 1.2.2.2 skrll status = hw->mac.ops.stop_adapter(hw); 208 1.2.2.2 skrll if (status != IXGBE_SUCCESS) 209 1.2.2.2 skrll goto reset_hw_out; 210 1.2.2.2 skrll 211 1.2.2.2 skrll /* flush pending Tx transactions */ 212 1.2.2.2 skrll ixgbe_clear_tx_pending(hw); 213 1.2.2.2 skrll 214 1.2.2.2 skrll mac_reset_top: 215 1.2.2.2 skrll ctrl = IXGBE_CTRL_RST; 216 1.2.2.2 skrll ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 217 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 218 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 219 1.2.2.2 skrll 220 1.2.2.2 skrll /* Poll for reset bit to self-clear indicating reset is complete */ 221 1.2.2.2 skrll for (i = 0; i < 10; i++) { 222 1.2.2.2 skrll usec_delay(1); 223 1.2.2.2 skrll ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 224 1.2.2.2 skrll if (!(ctrl & IXGBE_CTRL_RST_MASK)) 225 1.2.2.2 skrll break; 226 1.2.2.2 skrll } 227 1.2.2.2 skrll 228 1.2.2.2 skrll if (ctrl & IXGBE_CTRL_RST_MASK) { 229 1.2.2.2 skrll status = IXGBE_ERR_RESET_FAILED; 230 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 231 1.2.2.4 skrll "Reset polling failed to complete.\n"); 232 1.2.2.2 skrll } 233 1.2.2.2 skrll msec_delay(100); 234 1.2.2.2 skrll 235 1.2.2.2 skrll /* 236 1.2.2.2 skrll * Double resets are required for recovery from certain error 237 1.2.2.2 skrll * conditions. Between resets, it is necessary to stall to allow time 238 1.2.2.2 skrll * for any pending HW events to complete. 239 1.2.2.2 skrll */ 240 1.2.2.2 skrll if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 241 1.2.2.2 skrll hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 242 1.2.2.2 skrll goto mac_reset_top; 243 1.2.2.2 skrll } 244 1.2.2.2 skrll 245 1.2.2.2 skrll /* Set the Rx packet buffer size. */ 246 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 247 1.2.2.2 skrll 248 1.2.2.2 skrll /* Store the permanent mac address */ 249 1.2.2.2 skrll hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 250 1.2.2.2 skrll 251 1.2.2.2 skrll /* 252 1.2.2.2 skrll * Store MAC address from RAR0, clear receive address registers, and 253 1.2.2.2 skrll * clear the multicast table. Also reset num_rar_entries to 128, 254 1.2.2.2 skrll * since we modify this value when programming the SAN MAC address. 255 1.2.2.2 skrll */ 256 1.2.2.2 skrll hw->mac.num_rar_entries = 128; 257 1.2.2.2 skrll hw->mac.ops.init_rx_addrs(hw); 258 1.2.2.2 skrll 259 1.2.2.2 skrll /* Store the permanent SAN mac address */ 260 1.2.2.2 skrll hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 261 1.2.2.2 skrll 262 1.2.2.2 skrll /* Add the SAN MAC address to the RAR only if it's a valid address */ 263 1.2.2.2 skrll if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 264 1.2.2.2 skrll hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 265 1.2.2.2 skrll hw->mac.san_addr, 0, IXGBE_RAH_AV); 266 1.2.2.2 skrll 267 1.2.2.2 skrll /* Save the SAN MAC RAR index */ 268 1.2.2.2 skrll hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 269 1.2.2.2 skrll 270 1.2.2.2 skrll /* Reserve the last RAR for the SAN MAC address */ 271 1.2.2.2 skrll hw->mac.num_rar_entries--; 272 1.2.2.2 skrll } 273 1.2.2.2 skrll 274 1.2.2.2 skrll /* Store the alternative WWNN/WWPN prefix */ 275 1.2.2.2 skrll hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 276 1.2.2.2 skrll &hw->mac.wwpn_prefix); 277 1.2.2.2 skrll 278 1.2.2.2 skrll reset_hw_out: 279 1.2.2.2 skrll return status; 280 1.2.2.2 skrll } 281 1.2.2.2 skrll 282 1.2.2.2 skrll /** 283 1.2.2.2 skrll * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 284 1.2.2.2 skrll * @hw: pointer to hardware structure 285 1.2.2.2 skrll * 286 1.2.2.2 skrll * Starts the hardware using the generic start_hw function 287 1.2.2.2 skrll * and the generation start_hw function. 288 1.2.2.2 skrll * Then performs revision-specific operations, if any. 289 1.2.2.2 skrll **/ 290 1.2.2.2 skrll s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 291 1.2.2.2 skrll { 292 1.2.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 293 1.2.2.2 skrll 294 1.2.2.2 skrll DEBUGFUNC("ixgbe_start_hw_X540"); 295 1.2.2.2 skrll 296 1.2.2.2 skrll ret_val = ixgbe_start_hw_generic(hw); 297 1.2.2.2 skrll if (ret_val != IXGBE_SUCCESS) 298 1.2.2.2 skrll goto out; 299 1.2.2.2 skrll 300 1.2.2.2 skrll ret_val = ixgbe_start_hw_gen2(hw); 301 1.2.2.2 skrll 302 1.2.2.2 skrll out: 303 1.2.2.2 skrll return ret_val; 304 1.2.2.2 skrll } 305 1.2.2.2 skrll 306 1.2.2.2 skrll /** 307 1.2.2.2 skrll * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 308 1.2.2.2 skrll * @hw: pointer to hardware structure 309 1.2.2.2 skrll * 310 1.2.2.2 skrll * Determines physical layer capabilities of the current configuration. 311 1.2.2.2 skrll **/ 312 1.2.2.2 skrll u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 313 1.2.2.2 skrll { 314 1.2.2.2 skrll u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 315 1.2.2.2 skrll u16 ext_ability = 0; 316 1.2.2.2 skrll 317 1.2.2.2 skrll DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 318 1.2.2.2 skrll 319 1.2.2.2 skrll hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 320 1.2.2.2 skrll IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 321 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 322 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 323 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 324 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 325 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 326 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 327 1.2.2.2 skrll 328 1.2.2.2 skrll return physical_layer; 329 1.2.2.2 skrll } 330 1.2.2.2 skrll 331 1.2.2.2 skrll /** 332 1.2.2.2 skrll * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 333 1.2.2.2 skrll * @hw: pointer to hardware structure 334 1.2.2.2 skrll * 335 1.2.2.2 skrll * Initializes the EEPROM parameters ixgbe_eeprom_info within the 336 1.2.2.2 skrll * ixgbe_hw struct in order to set up EEPROM access. 337 1.2.2.2 skrll **/ 338 1.2.2.2 skrll s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 339 1.2.2.2 skrll { 340 1.2.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 341 1.2.2.2 skrll u32 eec; 342 1.2.2.2 skrll u16 eeprom_size; 343 1.2.2.2 skrll 344 1.2.2.2 skrll DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 345 1.2.2.2 skrll 346 1.2.2.2 skrll if (eeprom->type == ixgbe_eeprom_uninitialized) { 347 1.2.2.2 skrll eeprom->semaphore_delay = 10; 348 1.2.2.2 skrll eeprom->type = ixgbe_flash; 349 1.2.2.2 skrll 350 1.2.2.2 skrll eec = IXGBE_READ_REG(hw, IXGBE_EEC); 351 1.2.2.2 skrll eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 352 1.2.2.2 skrll IXGBE_EEC_SIZE_SHIFT); 353 1.2.2.2 skrll eeprom->word_size = 1 << (eeprom_size + 354 1.2.2.2 skrll IXGBE_EEPROM_WORD_SIZE_SHIFT); 355 1.2.2.2 skrll 356 1.2.2.2 skrll DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 357 1.2.2.2 skrll eeprom->type, eeprom->word_size); 358 1.2.2.2 skrll } 359 1.2.2.2 skrll 360 1.2.2.2 skrll return IXGBE_SUCCESS; 361 1.2.2.2 skrll } 362 1.2.2.2 skrll 363 1.2.2.2 skrll /** 364 1.2.2.2 skrll * ixgbe_read_eerd_X540- Read EEPROM word using EERD 365 1.2.2.2 skrll * @hw: pointer to hardware structure 366 1.2.2.2 skrll * @offset: offset of word in the EEPROM to read 367 1.2.2.2 skrll * @data: word read from the EEPROM 368 1.2.2.2 skrll * 369 1.2.2.2 skrll * Reads a 16 bit word from the EEPROM using the EERD register. 370 1.2.2.2 skrll **/ 371 1.2.2.2 skrll s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 372 1.2.2.2 skrll { 373 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 374 1.2.2.2 skrll 375 1.2.2.2 skrll DEBUGFUNC("ixgbe_read_eerd_X540"); 376 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 377 1.2.2.4 skrll IXGBE_SUCCESS) { 378 1.2.2.2 skrll status = ixgbe_read_eerd_generic(hw, offset, data); 379 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 380 1.2.2.4 skrll } else { 381 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 382 1.2.2.4 skrll } 383 1.2.2.2 skrll 384 1.2.2.2 skrll return status; 385 1.2.2.2 skrll } 386 1.2.2.2 skrll 387 1.2.2.2 skrll /** 388 1.2.2.2 skrll * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 389 1.2.2.2 skrll * @hw: pointer to hardware structure 390 1.2.2.2 skrll * @offset: offset of word in the EEPROM to read 391 1.2.2.2 skrll * @words: number of words 392 1.2.2.2 skrll * @data: word(s) read from the EEPROM 393 1.2.2.2 skrll * 394 1.2.2.2 skrll * Reads a 16 bit word(s) from the EEPROM using the EERD register. 395 1.2.2.2 skrll **/ 396 1.2.2.2 skrll s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 397 1.2.2.2 skrll u16 offset, u16 words, u16 *data) 398 1.2.2.2 skrll { 399 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 400 1.2.2.2 skrll 401 1.2.2.2 skrll DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 402 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 403 1.2.2.4 skrll IXGBE_SUCCESS) { 404 1.2.2.2 skrll status = ixgbe_read_eerd_buffer_generic(hw, offset, 405 1.2.2.2 skrll words, data); 406 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 407 1.2.2.4 skrll } else { 408 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 409 1.2.2.4 skrll } 410 1.2.2.2 skrll 411 1.2.2.2 skrll return status; 412 1.2.2.2 skrll } 413 1.2.2.2 skrll 414 1.2.2.2 skrll /** 415 1.2.2.2 skrll * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 416 1.2.2.2 skrll * @hw: pointer to hardware structure 417 1.2.2.2 skrll * @offset: offset of word in the EEPROM to write 418 1.2.2.2 skrll * @data: word write to the EEPROM 419 1.2.2.2 skrll * 420 1.2.2.2 skrll * Write a 16 bit word to the EEPROM using the EEWR register. 421 1.2.2.2 skrll **/ 422 1.2.2.2 skrll s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 423 1.2.2.2 skrll { 424 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 425 1.2.2.2 skrll 426 1.2.2.2 skrll DEBUGFUNC("ixgbe_write_eewr_X540"); 427 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 428 1.2.2.4 skrll IXGBE_SUCCESS) { 429 1.2.2.2 skrll status = ixgbe_write_eewr_generic(hw, offset, data); 430 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 431 1.2.2.4 skrll } else { 432 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 433 1.2.2.4 skrll } 434 1.2.2.2 skrll 435 1.2.2.2 skrll return status; 436 1.2.2.2 skrll } 437 1.2.2.2 skrll 438 1.2.2.2 skrll /** 439 1.2.2.2 skrll * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 440 1.2.2.2 skrll * @hw: pointer to hardware structure 441 1.2.2.2 skrll * @offset: offset of word in the EEPROM to write 442 1.2.2.2 skrll * @words: number of words 443 1.2.2.2 skrll * @data: word(s) write to the EEPROM 444 1.2.2.2 skrll * 445 1.2.2.2 skrll * Write a 16 bit word(s) to the EEPROM using the EEWR register. 446 1.2.2.2 skrll **/ 447 1.2.2.2 skrll s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 448 1.2.2.2 skrll u16 offset, u16 words, u16 *data) 449 1.2.2.2 skrll { 450 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 451 1.2.2.2 skrll 452 1.2.2.2 skrll DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 453 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 454 1.2.2.4 skrll IXGBE_SUCCESS) { 455 1.2.2.2 skrll status = ixgbe_write_eewr_buffer_generic(hw, offset, 456 1.2.2.2 skrll words, data); 457 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 458 1.2.2.4 skrll } else { 459 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 460 1.2.2.4 skrll } 461 1.2.2.2 skrll 462 1.2.2.2 skrll return status; 463 1.2.2.2 skrll } 464 1.2.2.2 skrll 465 1.2.2.2 skrll /** 466 1.2.2.2 skrll * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 467 1.2.2.2 skrll * 468 1.2.2.2 skrll * This function does not use synchronization for EERD and EEWR. It can 469 1.2.2.2 skrll * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 470 1.2.2.2 skrll * 471 1.2.2.2 skrll * @hw: pointer to hardware structure 472 1.2.2.2 skrll **/ 473 1.2.2.2 skrll u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 474 1.2.2.2 skrll { 475 1.2.2.2 skrll u16 i; 476 1.2.2.2 skrll u16 j; 477 1.2.2.2 skrll u16 checksum = 0; 478 1.2.2.2 skrll u16 length = 0; 479 1.2.2.2 skrll u16 pointer = 0; 480 1.2.2.2 skrll u16 word = 0; 481 1.2.2.2 skrll 482 1.2.2.2 skrll /* 483 1.2.2.2 skrll * Do not use hw->eeprom.ops.read because we do not want to take 484 1.2.2.2 skrll * the synchronization semaphores here. Instead use 485 1.2.2.2 skrll * ixgbe_read_eerd_generic 486 1.2.2.2 skrll */ 487 1.2.2.2 skrll 488 1.2.2.2 skrll DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 489 1.2.2.2 skrll 490 1.2.2.2 skrll /* Include 0x0-0x3F in the checksum */ 491 1.2.2.2 skrll for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 492 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) { 493 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 494 1.2.2.2 skrll break; 495 1.2.2.2 skrll } 496 1.2.2.2 skrll checksum += word; 497 1.2.2.2 skrll } 498 1.2.2.2 skrll 499 1.2.2.2 skrll /* 500 1.2.2.2 skrll * Include all data from pointers 0x3, 0x6-0xE. This excludes the 501 1.2.2.2 skrll * FW, PHY module, and PCIe Expansion/Option ROM pointers. 502 1.2.2.2 skrll */ 503 1.2.2.2 skrll for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 504 1.2.2.2 skrll if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 505 1.2.2.2 skrll continue; 506 1.2.2.2 skrll 507 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) { 508 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 509 1.2.2.2 skrll break; 510 1.2.2.2 skrll } 511 1.2.2.2 skrll 512 1.2.2.2 skrll /* Skip pointer section if the pointer is invalid. */ 513 1.2.2.2 skrll if (pointer == 0xFFFF || pointer == 0 || 514 1.2.2.2 skrll pointer >= hw->eeprom.word_size) 515 1.2.2.2 skrll continue; 516 1.2.2.2 skrll 517 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, pointer, &length) != 518 1.2.2.2 skrll IXGBE_SUCCESS) { 519 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 520 1.2.2.2 skrll break; 521 1.2.2.2 skrll } 522 1.2.2.2 skrll 523 1.2.2.2 skrll /* Skip pointer section if length is invalid. */ 524 1.2.2.2 skrll if (length == 0xFFFF || length == 0 || 525 1.2.2.2 skrll (pointer + length) >= hw->eeprom.word_size) 526 1.2.2.2 skrll continue; 527 1.2.2.2 skrll 528 1.2.2.2 skrll for (j = pointer+1; j <= pointer+length; j++) { 529 1.2.2.2 skrll if (ixgbe_read_eerd_generic(hw, j, &word) != 530 1.2.2.2 skrll IXGBE_SUCCESS) { 531 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 532 1.2.2.2 skrll break; 533 1.2.2.2 skrll } 534 1.2.2.2 skrll checksum += word; 535 1.2.2.2 skrll } 536 1.2.2.2 skrll } 537 1.2.2.2 skrll 538 1.2.2.2 skrll checksum = (u16)IXGBE_EEPROM_SUM - checksum; 539 1.2.2.2 skrll 540 1.2.2.2 skrll return checksum; 541 1.2.2.2 skrll } 542 1.2.2.2 skrll 543 1.2.2.2 skrll /** 544 1.2.2.2 skrll * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 545 1.2.2.2 skrll * @hw: pointer to hardware structure 546 1.2.2.2 skrll * @checksum_val: calculated checksum 547 1.2.2.2 skrll * 548 1.2.2.2 skrll * Performs checksum calculation and validates the EEPROM checksum. If the 549 1.2.2.2 skrll * caller does not need checksum_val, the value can be NULL. 550 1.2.2.2 skrll **/ 551 1.2.2.2 skrll s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 552 1.2.2.2 skrll u16 *checksum_val) 553 1.2.2.2 skrll { 554 1.2.2.2 skrll s32 status; 555 1.2.2.2 skrll u16 checksum; 556 1.2.2.2 skrll u16 read_checksum = 0; 557 1.2.2.2 skrll 558 1.2.2.2 skrll DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 559 1.2.2.2 skrll 560 1.2.2.2 skrll /* 561 1.2.2.2 skrll * Read the first word from the EEPROM. If this times out or fails, do 562 1.2.2.2 skrll * not continue or we could be in for a very long wait while every 563 1.2.2.2 skrll * EEPROM read fails 564 1.2.2.2 skrll */ 565 1.2.2.2 skrll status = hw->eeprom.ops.read(hw, 0, &checksum); 566 1.2.2.2 skrll 567 1.2.2.2 skrll if (status != IXGBE_SUCCESS) { 568 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 569 1.2.2.2 skrll goto out; 570 1.2.2.2 skrll } 571 1.2.2.2 skrll 572 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 573 1.2.2.2 skrll IXGBE_SUCCESS) { 574 1.2.2.2 skrll checksum = hw->eeprom.ops.calc_checksum(hw); 575 1.2.2.2 skrll 576 1.2.2.2 skrll /* 577 1.2.2.2 skrll * Do not use hw->eeprom.ops.read because we do not want to take 578 1.2.2.2 skrll * the synchronization semaphores twice here. 579 1.2.2.2 skrll */ 580 1.2.2.2 skrll ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 581 1.2.2.2 skrll &read_checksum); 582 1.2.2.2 skrll 583 1.2.2.2 skrll /* 584 1.2.2.2 skrll * Verify read checksum from EEPROM is the same as 585 1.2.2.2 skrll * calculated checksum 586 1.2.2.2 skrll */ 587 1.2.2.4 skrll if (read_checksum != checksum) { 588 1.2.2.2 skrll status = IXGBE_ERR_EEPROM_CHECKSUM; 589 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 590 1.2.2.4 skrll "Invalid EEPROM checksum"); 591 1.2.2.4 skrll } 592 1.2.2.2 skrll 593 1.2.2.2 skrll /* If the user cares, return the calculated checksum */ 594 1.2.2.2 skrll if (checksum_val) 595 1.2.2.2 skrll *checksum_val = checksum; 596 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 597 1.2.2.2 skrll } else { 598 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 599 1.2.2.2 skrll } 600 1.2.2.2 skrll 601 1.2.2.2 skrll out: 602 1.2.2.2 skrll return status; 603 1.2.2.2 skrll } 604 1.2.2.2 skrll 605 1.2.2.2 skrll /** 606 1.2.2.2 skrll * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 607 1.2.2.2 skrll * @hw: pointer to hardware structure 608 1.2.2.2 skrll * 609 1.2.2.2 skrll * After writing EEPROM to shadow RAM using EEWR register, software calculates 610 1.2.2.2 skrll * checksum and updates the EEPROM and instructs the hardware to update 611 1.2.2.2 skrll * the flash. 612 1.2.2.2 skrll **/ 613 1.2.2.2 skrll s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 614 1.2.2.2 skrll { 615 1.2.2.2 skrll s32 status; 616 1.2.2.2 skrll u16 checksum; 617 1.2.2.2 skrll 618 1.2.2.2 skrll DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 619 1.2.2.2 skrll 620 1.2.2.2 skrll /* 621 1.2.2.2 skrll * Read the first word from the EEPROM. If this times out or fails, do 622 1.2.2.2 skrll * not continue or we could be in for a very long wait while every 623 1.2.2.2 skrll * EEPROM read fails 624 1.2.2.2 skrll */ 625 1.2.2.2 skrll status = hw->eeprom.ops.read(hw, 0, &checksum); 626 1.2.2.2 skrll 627 1.2.2.2 skrll if (status != IXGBE_SUCCESS) 628 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 629 1.2.2.2 skrll 630 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 631 1.2.2.2 skrll IXGBE_SUCCESS) { 632 1.2.2.2 skrll checksum = hw->eeprom.ops.calc_checksum(hw); 633 1.2.2.2 skrll 634 1.2.2.2 skrll /* 635 1.2.2.2 skrll * Do not use hw->eeprom.ops.write because we do not want to 636 1.2.2.2 skrll * take the synchronization semaphores twice here. 637 1.2.2.2 skrll */ 638 1.2.2.2 skrll status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, 639 1.2.2.2 skrll checksum); 640 1.2.2.2 skrll 641 1.2.2.4 skrll if (status == IXGBE_SUCCESS) 642 1.2.2.4 skrll status = ixgbe_update_flash_X540(hw); 643 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 644 1.2.2.4 skrll } else { 645 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 646 1.2.2.2 skrll } 647 1.2.2.2 skrll 648 1.2.2.2 skrll return status; 649 1.2.2.2 skrll } 650 1.2.2.2 skrll 651 1.2.2.2 skrll /** 652 1.2.2.2 skrll * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 653 1.2.2.2 skrll * @hw: pointer to hardware structure 654 1.2.2.2 skrll * 655 1.2.2.2 skrll * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 656 1.2.2.2 skrll * EEPROM from shadow RAM to the flash device. 657 1.2.2.2 skrll **/ 658 1.2.2.4 skrll s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 659 1.2.2.2 skrll { 660 1.2.2.2 skrll u32 flup; 661 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 662 1.2.2.2 skrll 663 1.2.2.2 skrll DEBUGFUNC("ixgbe_update_flash_X540"); 664 1.2.2.2 skrll 665 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 666 1.2.2.2 skrll if (status == IXGBE_ERR_EEPROM) { 667 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 668 1.2.2.2 skrll goto out; 669 1.2.2.2 skrll } 670 1.2.2.2 skrll 671 1.2.2.2 skrll flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 672 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 673 1.2.2.2 skrll 674 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 675 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 676 1.2.2.2 skrll DEBUGOUT("Flash update complete\n"); 677 1.2.2.2 skrll else 678 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 679 1.2.2.2 skrll 680 1.2.2.4 skrll if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 681 1.2.2.2 skrll flup = IXGBE_READ_REG(hw, IXGBE_EEC); 682 1.2.2.2 skrll 683 1.2.2.2 skrll if (flup & IXGBE_EEC_SEC1VAL) { 684 1.2.2.2 skrll flup |= IXGBE_EEC_FLUP; 685 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 686 1.2.2.2 skrll } 687 1.2.2.2 skrll 688 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 689 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 690 1.2.2.2 skrll DEBUGOUT("Flash update complete\n"); 691 1.2.2.2 skrll else 692 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 693 1.2.2.2 skrll } 694 1.2.2.2 skrll out: 695 1.2.2.2 skrll return status; 696 1.2.2.2 skrll } 697 1.2.2.2 skrll 698 1.2.2.2 skrll /** 699 1.2.2.2 skrll * ixgbe_poll_flash_update_done_X540 - Poll flash update status 700 1.2.2.2 skrll * @hw: pointer to hardware structure 701 1.2.2.2 skrll * 702 1.2.2.2 skrll * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 703 1.2.2.2 skrll * flash update is done. 704 1.2.2.2 skrll **/ 705 1.2.2.2 skrll static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 706 1.2.2.2 skrll { 707 1.2.2.2 skrll u32 i; 708 1.2.2.2 skrll u32 reg; 709 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 710 1.2.2.2 skrll 711 1.2.2.2 skrll DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 712 1.2.2.2 skrll 713 1.2.2.2 skrll for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 714 1.2.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_EEC); 715 1.2.2.2 skrll if (reg & IXGBE_EEC_FLUDONE) { 716 1.2.2.2 skrll status = IXGBE_SUCCESS; 717 1.2.2.2 skrll break; 718 1.2.2.2 skrll } 719 1.2.2.2 skrll usec_delay(5); 720 1.2.2.2 skrll } 721 1.2.2.4 skrll 722 1.2.2.4 skrll if (i == IXGBE_FLUDONE_ATTEMPTS) 723 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 724 1.2.2.4 skrll "Flash update status polling timed out"); 725 1.2.2.4 skrll 726 1.2.2.2 skrll return status; 727 1.2.2.2 skrll } 728 1.2.2.2 skrll 729 1.2.2.2 skrll /** 730 1.2.2.2 skrll * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 731 1.2.2.2 skrll * @hw: pointer to hardware structure 732 1.2.2.2 skrll * @mask: Mask to specify which semaphore to acquire 733 1.2.2.2 skrll * 734 1.2.2.2 skrll * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 735 1.2.2.2 skrll * the specified function (CSR, PHY0, PHY1, NVM, Flash) 736 1.2.2.2 skrll **/ 737 1.2.2.2 skrll s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 738 1.2.2.2 skrll { 739 1.2.2.2 skrll u32 swfw_sync; 740 1.2.2.2 skrll u32 swmask = mask; 741 1.2.2.2 skrll u32 fwmask = mask << 5; 742 1.2.2.2 skrll u32 hwmask = 0; 743 1.2.2.2 skrll u32 timeout = 200; 744 1.2.2.2 skrll u32 i; 745 1.2.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 746 1.2.2.2 skrll 747 1.2.2.2 skrll DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 748 1.2.2.2 skrll 749 1.2.2.2 skrll if (swmask == IXGBE_GSSR_EEP_SM) 750 1.2.2.2 skrll hwmask = IXGBE_GSSR_FLASH_SM; 751 1.2.2.2 skrll 752 1.2.2.2 skrll /* SW only mask doesn't have FW bit pair */ 753 1.2.2.2 skrll if (swmask == IXGBE_GSSR_SW_MNG_SM) 754 1.2.2.2 skrll fwmask = 0; 755 1.2.2.2 skrll 756 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 757 1.2.2.2 skrll /* 758 1.2.2.2 skrll * SW NVM semaphore bit is used for access to all 759 1.2.2.2 skrll * SW_FW_SYNC bits (not just NVM) 760 1.2.2.2 skrll */ 761 1.2.2.2 skrll if (ixgbe_get_swfw_sync_semaphore(hw)) { 762 1.2.2.2 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 763 1.2.2.2 skrll goto out; 764 1.2.2.2 skrll } 765 1.2.2.2 skrll 766 1.2.2.2 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 767 1.2.2.2 skrll if (!(swfw_sync & (fwmask | swmask | hwmask))) { 768 1.2.2.2 skrll swfw_sync |= swmask; 769 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 770 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 771 1.2.2.2 skrll goto out; 772 1.2.2.2 skrll } else { 773 1.2.2.2 skrll /* 774 1.2.2.2 skrll * Firmware currently using resource (fwmask), hardware 775 1.2.2.2 skrll * currently using resource (hwmask), or other software 776 1.2.2.2 skrll * thread currently using resource (swmask) 777 1.2.2.2 skrll */ 778 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 779 1.2.2.2 skrll msec_delay(5); 780 1.2.2.2 skrll } 781 1.2.2.2 skrll } 782 1.2.2.2 skrll 783 1.2.2.2 skrll /* Failed to get SW only semaphore */ 784 1.2.2.2 skrll if (swmask == IXGBE_GSSR_SW_MNG_SM) { 785 1.2.2.2 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 786 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 787 1.2.2.4 skrll "Failed to get SW only semaphore"); 788 1.2.2.2 skrll goto out; 789 1.2.2.2 skrll } 790 1.2.2.2 skrll 791 1.2.2.2 skrll /* If the resource is not released by the FW/HW the SW can assume that 792 1.2.2.4 skrll * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 793 1.2.2.2 skrll * of the requested resource(s) while ignoring the corresponding FW/HW 794 1.2.2.2 skrll * bits in the SW_FW_SYNC register. 795 1.2.2.2 skrll */ 796 1.2.2.2 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 797 1.2.2.2 skrll if (swfw_sync & (fwmask | hwmask)) { 798 1.2.2.2 skrll if (ixgbe_get_swfw_sync_semaphore(hw)) { 799 1.2.2.2 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 800 1.2.2.2 skrll goto out; 801 1.2.2.2 skrll } 802 1.2.2.2 skrll 803 1.2.2.2 skrll swfw_sync |= swmask; 804 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 805 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 806 1.2.2.2 skrll msec_delay(5); 807 1.2.2.2 skrll } 808 1.2.2.4 skrll /* If the resource is not released by other SW the SW can assume that 809 1.2.2.4 skrll * the other SW malfunctions. In that case the SW should clear all SW 810 1.2.2.4 skrll * flags that it does not own and then repeat the whole process once 811 1.2.2.4 skrll * again. 812 1.2.2.4 skrll */ 813 1.2.2.4 skrll else if (swfw_sync & swmask) { 814 1.2.2.4 skrll ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM | 815 1.2.2.4 skrll IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM | 816 1.2.2.4 skrll IXGBE_GSSR_MAC_CSR_SM); 817 1.2.2.4 skrll ret_val = IXGBE_ERR_SWFW_SYNC; 818 1.2.2.4 skrll } 819 1.2.2.2 skrll 820 1.2.2.2 skrll out: 821 1.2.2.2 skrll return ret_val; 822 1.2.2.2 skrll } 823 1.2.2.2 skrll 824 1.2.2.2 skrll /** 825 1.2.2.2 skrll * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 826 1.2.2.2 skrll * @hw: pointer to hardware structure 827 1.2.2.2 skrll * @mask: Mask to specify which semaphore to release 828 1.2.2.2 skrll * 829 1.2.2.2 skrll * Releases the SWFW semaphore through the SW_FW_SYNC register 830 1.2.2.2 skrll * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 831 1.2.2.2 skrll **/ 832 1.2.2.2 skrll void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 833 1.2.2.2 skrll { 834 1.2.2.2 skrll u32 swfw_sync; 835 1.2.2.2 skrll u32 swmask = mask; 836 1.2.2.2 skrll 837 1.2.2.2 skrll DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 838 1.2.2.2 skrll 839 1.2.2.2 skrll ixgbe_get_swfw_sync_semaphore(hw); 840 1.2.2.2 skrll 841 1.2.2.2 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 842 1.2.2.2 skrll swfw_sync &= ~swmask; 843 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 844 1.2.2.2 skrll 845 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 846 1.2.2.2 skrll } 847 1.2.2.2 skrll 848 1.2.2.2 skrll /** 849 1.2.2.2 skrll * ixgbe_get_nvm_semaphore - Get hardware semaphore 850 1.2.2.2 skrll * @hw: pointer to hardware structure 851 1.2.2.2 skrll * 852 1.2.2.2 skrll * Sets the hardware semaphores so SW/FW can gain control of shared resources 853 1.2.2.2 skrll **/ 854 1.2.2.2 skrll static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 855 1.2.2.2 skrll { 856 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 857 1.2.2.2 skrll u32 timeout = 2000; 858 1.2.2.2 skrll u32 i; 859 1.2.2.2 skrll u32 swsm; 860 1.2.2.2 skrll 861 1.2.2.2 skrll DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 862 1.2.2.2 skrll 863 1.2.2.2 skrll /* Get SMBI software semaphore between device drivers first */ 864 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 865 1.2.2.2 skrll /* 866 1.2.2.2 skrll * If the SMBI bit is 0 when we read it, then the bit will be 867 1.2.2.2 skrll * set and we have the semaphore 868 1.2.2.2 skrll */ 869 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 870 1.2.2.2 skrll if (!(swsm & IXGBE_SWSM_SMBI)) { 871 1.2.2.2 skrll status = IXGBE_SUCCESS; 872 1.2.2.2 skrll break; 873 1.2.2.2 skrll } 874 1.2.2.2 skrll usec_delay(50); 875 1.2.2.2 skrll } 876 1.2.2.2 skrll 877 1.2.2.2 skrll /* Now get the semaphore between SW/FW through the REGSMP bit */ 878 1.2.2.2 skrll if (status == IXGBE_SUCCESS) { 879 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 880 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 881 1.2.2.2 skrll if (!(swsm & IXGBE_SWFW_REGSMP)) 882 1.2.2.2 skrll break; 883 1.2.2.2 skrll 884 1.2.2.2 skrll usec_delay(50); 885 1.2.2.2 skrll } 886 1.2.2.2 skrll 887 1.2.2.2 skrll /* 888 1.2.2.2 skrll * Release semaphores and return error if SW NVM semaphore 889 1.2.2.2 skrll * was not granted because we don't have access to the EEPROM 890 1.2.2.2 skrll */ 891 1.2.2.2 skrll if (i >= timeout) { 892 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 893 1.2.2.4 skrll "REGSMP Software NVM semaphore not granted.\n"); 894 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 895 1.2.2.2 skrll status = IXGBE_ERR_EEPROM; 896 1.2.2.2 skrll } 897 1.2.2.2 skrll } else { 898 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 899 1.2.2.4 skrll "Software semaphore SMBI between device drivers " 900 1.2.2.4 skrll "not granted.\n"); 901 1.2.2.2 skrll } 902 1.2.2.2 skrll 903 1.2.2.2 skrll return status; 904 1.2.2.2 skrll } 905 1.2.2.2 skrll 906 1.2.2.2 skrll /** 907 1.2.2.2 skrll * ixgbe_release_nvm_semaphore - Release hardware semaphore 908 1.2.2.2 skrll * @hw: pointer to hardware structure 909 1.2.2.2 skrll * 910 1.2.2.2 skrll * This function clears hardware semaphore bits. 911 1.2.2.2 skrll **/ 912 1.2.2.2 skrll static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 913 1.2.2.2 skrll { 914 1.2.2.2 skrll u32 swsm; 915 1.2.2.2 skrll 916 1.2.2.2 skrll DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 917 1.2.2.2 skrll 918 1.2.2.2 skrll /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 919 1.2.2.2 skrll 920 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 921 1.2.2.2 skrll swsm &= ~IXGBE_SWSM_SMBI; 922 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 923 1.2.2.2 skrll 924 1.2.2.2 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 925 1.2.2.2 skrll swsm &= ~IXGBE_SWFW_REGSMP; 926 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 927 1.2.2.2 skrll 928 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 929 1.2.2.2 skrll } 930 1.2.2.2 skrll 931 1.2.2.2 skrll /** 932 1.2.2.2 skrll * ixgbe_blink_led_start_X540 - Blink LED based on index. 933 1.2.2.2 skrll * @hw: pointer to hardware structure 934 1.2.2.2 skrll * @index: led number to blink 935 1.2.2.2 skrll * 936 1.2.2.2 skrll * Devices that implement the version 2 interface: 937 1.2.2.2 skrll * X540 938 1.2.2.2 skrll **/ 939 1.2.2.2 skrll s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 940 1.2.2.2 skrll { 941 1.2.2.2 skrll u32 macc_reg; 942 1.2.2.2 skrll u32 ledctl_reg; 943 1.2.2.2 skrll ixgbe_link_speed speed; 944 1.2.2.2 skrll bool link_up; 945 1.2.2.2 skrll 946 1.2.2.2 skrll DEBUGFUNC("ixgbe_blink_led_start_X540"); 947 1.2.2.2 skrll 948 1.2.2.2 skrll /* 949 1.2.2.2 skrll * Link should be up in order for the blink bit in the LED control 950 1.2.2.2 skrll * register to work. Force link and speed in the MAC if link is down. 951 1.2.2.2 skrll * This will be reversed when we stop the blinking. 952 1.2.2.2 skrll */ 953 1.2.2.2 skrll hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 954 1.2.2.2 skrll if (link_up == FALSE) { 955 1.2.2.2 skrll macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 956 1.2.2.2 skrll macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 957 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 958 1.2.2.2 skrll } 959 1.2.2.2 skrll /* Set the LED to LINK_UP + BLINK. */ 960 1.2.2.2 skrll ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 961 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 962 1.2.2.2 skrll ledctl_reg |= IXGBE_LED_BLINK(index); 963 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 964 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 965 1.2.2.2 skrll 966 1.2.2.2 skrll return IXGBE_SUCCESS; 967 1.2.2.2 skrll } 968 1.2.2.2 skrll 969 1.2.2.2 skrll /** 970 1.2.2.2 skrll * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 971 1.2.2.2 skrll * @hw: pointer to hardware structure 972 1.2.2.2 skrll * @index: led number to stop blinking 973 1.2.2.2 skrll * 974 1.2.2.2 skrll * Devices that implement the version 2 interface: 975 1.2.2.2 skrll * X540 976 1.2.2.2 skrll **/ 977 1.2.2.2 skrll s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 978 1.2.2.2 skrll { 979 1.2.2.2 skrll u32 macc_reg; 980 1.2.2.2 skrll u32 ledctl_reg; 981 1.2.2.2 skrll 982 1.2.2.2 skrll DEBUGFUNC("ixgbe_blink_led_stop_X540"); 983 1.2.2.2 skrll 984 1.2.2.2 skrll /* Restore the LED to its default value. */ 985 1.2.2.2 skrll ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 986 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 987 1.2.2.2 skrll ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 988 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_BLINK(index); 989 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 990 1.2.2.2 skrll 991 1.2.2.2 skrll /* Unforce link and speed in the MAC. */ 992 1.2.2.2 skrll macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 993 1.2.2.2 skrll macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 994 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 995 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 996 1.2.2.2 skrll 997 1.2.2.2 skrll return IXGBE_SUCCESS; 998 1.2.2.2 skrll } 999 1.2.2.2 skrll 1000 1.2.2.3 skrll 1001
Indexes created Sun Oct 26 21:10:03 GMT 2025