ixgbe_x540.c revision 1.2.2.5
1 1.2.2.2 skrll /****************************************************************************** 2 1.2.2.2 skrll 3 1.2.2.5 skrll Copyright (c) 2001-2015, Intel Corporation 4 1.2.2.2 skrll All rights reserved. 5 1.2.2.2 skrll 6 1.2.2.2 skrll Redistribution and use in source and binary forms, with or without 7 1.2.2.2 skrll modification, are permitted provided that the following conditions are met: 8 1.2.2.2 skrll 9 1.2.2.2 skrll 1. Redistributions of source code must retain the above copyright notice, 10 1.2.2.2 skrll this list of conditions and the following disclaimer. 11 1.2.2.2 skrll 12 1.2.2.2 skrll 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll 16 1.2.2.2 skrll 3. Neither the name of the Intel Corporation nor the names of its 17 1.2.2.2 skrll contributors may be used to endorse or promote products derived from 18 1.2.2.2 skrll this software without specific prior written permission. 19 1.2.2.2 skrll 20 1.2.2.2 skrll THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.2.2.2 skrll AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.2.2.2 skrll IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.2.2.2 skrll ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.2.2.2 skrll LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.2.2.2 skrll CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.2.2.2 skrll SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.2.2.2 skrll INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.2.2.2 skrll CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.2.2.2 skrll ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.2.2.2 skrll POSSIBILITY OF SUCH DAMAGE. 31 1.2.2.2 skrll 32 1.2.2.2 skrll ******************************************************************************/ 33 1.2.2.5 skrll /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 292674 2015-12-23 22:45:17Z sbruno $*/ 34 1.2.2.2 skrll 35 1.2.2.2 skrll #include "ixgbe_x540.h" 36 1.2.2.2 skrll #include "ixgbe_type.h" 37 1.2.2.2 skrll #include "ixgbe_api.h" 38 1.2.2.2 skrll #include "ixgbe_common.h" 39 1.2.2.2 skrll #include "ixgbe_phy.h" 40 1.2.2.2 skrll 41 1.2.2.5 skrll #define IXGBE_X540_MAX_TX_QUEUES 128 42 1.2.2.5 skrll #define IXGBE_X540_MAX_RX_QUEUES 128 43 1.2.2.5 skrll #define IXGBE_X540_RAR_ENTRIES 128 44 1.2.2.5 skrll #define IXGBE_X540_MC_TBL_SIZE 128 45 1.2.2.5 skrll #define IXGBE_X540_VFT_TBL_SIZE 128 46 1.2.2.5 skrll #define IXGBE_X540_RX_PB_SIZE 384 47 1.2.2.5 skrll 48 1.2.2.2 skrll static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 49 1.2.2.2 skrll static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 50 1.2.2.2 skrll static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 51 1.2.2.2 skrll 52 1.2.2.2 skrll /** 53 1.2.2.2 skrll * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 54 1.2.2.2 skrll * @hw: pointer to hardware structure 55 1.2.2.2 skrll * 56 1.2.2.2 skrll * Initialize the function pointers and assign the MAC type for X540. 57 1.2.2.2 skrll * Does not touch the hardware. 58 1.2.2.2 skrll **/ 59 1.2.2.2 skrll s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 60 1.2.2.2 skrll { 61 1.2.2.2 skrll struct ixgbe_mac_info *mac = &hw->mac; 62 1.2.2.2 skrll struct ixgbe_phy_info *phy = &hw->phy; 63 1.2.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 64 1.2.2.2 skrll s32 ret_val; 65 1.2.2.2 skrll 66 1.2.2.2 skrll DEBUGFUNC("ixgbe_init_ops_X540"); 67 1.2.2.2 skrll 68 1.2.2.2 skrll ret_val = ixgbe_init_phy_ops_generic(hw); 69 1.2.2.2 skrll ret_val = ixgbe_init_ops_generic(hw); 70 1.2.2.2 skrll 71 1.2.2.2 skrll 72 1.2.2.2 skrll /* EEPROM */ 73 1.2.2.5 skrll eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 74 1.2.2.5 skrll eeprom->ops.read = ixgbe_read_eerd_X540; 75 1.2.2.5 skrll eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; 76 1.2.2.5 skrll eeprom->ops.write = ixgbe_write_eewr_X540; 77 1.2.2.5 skrll eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540; 78 1.2.2.5 skrll eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540; 79 1.2.2.5 skrll eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540; 80 1.2.2.5 skrll eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540; 81 1.2.2.2 skrll 82 1.2.2.2 skrll /* PHY */ 83 1.2.2.5 skrll phy->ops.init = ixgbe_init_phy_ops_generic; 84 1.2.2.2 skrll phy->ops.reset = NULL; 85 1.2.2.5 skrll if (!ixgbe_mng_present(hw)) 86 1.2.2.5 skrll phy->ops.set_phy_power = ixgbe_set_copper_phy_power; 87 1.2.2.2 skrll 88 1.2.2.2 skrll /* MAC */ 89 1.2.2.5 skrll mac->ops.reset_hw = ixgbe_reset_hw_X540; 90 1.2.2.5 skrll mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 91 1.2.2.5 skrll mac->ops.get_media_type = ixgbe_get_media_type_X540; 92 1.2.2.2 skrll mac->ops.get_supported_physical_layer = 93 1.2.2.5 skrll ixgbe_get_supported_physical_layer_X540; 94 1.2.2.2 skrll mac->ops.read_analog_reg8 = NULL; 95 1.2.2.2 skrll mac->ops.write_analog_reg8 = NULL; 96 1.2.2.5 skrll mac->ops.start_hw = ixgbe_start_hw_X540; 97 1.2.2.5 skrll mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 98 1.2.2.5 skrll mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 99 1.2.2.5 skrll mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 100 1.2.2.5 skrll mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 101 1.2.2.5 skrll mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 102 1.2.2.5 skrll mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; 103 1.2.2.5 skrll mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; 104 1.2.2.5 skrll mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 105 1.2.2.5 skrll mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 106 1.2.2.2 skrll 107 1.2.2.2 skrll /* RAR, Multicast, VLAN */ 108 1.2.2.5 skrll mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 109 1.2.2.5 skrll mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 110 1.2.2.5 skrll mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 111 1.2.2.5 skrll mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 112 1.2.2.2 skrll mac->rar_highwater = 1; 113 1.2.2.5 skrll mac->ops.set_vfta = ixgbe_set_vfta_generic; 114 1.2.2.5 skrll mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 115 1.2.2.5 skrll mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 116 1.2.2.5 skrll mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 117 1.2.2.5 skrll mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 118 1.2.2.5 skrll mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 119 1.2.2.2 skrll 120 1.2.2.2 skrll /* Link */ 121 1.2.2.2 skrll mac->ops.get_link_capabilities = 122 1.2.2.5 skrll ixgbe_get_copper_link_capabilities_generic; 123 1.2.2.5 skrll mac->ops.setup_link = ixgbe_setup_mac_link_X540; 124 1.2.2.5 skrll mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 125 1.2.2.5 skrll mac->ops.check_link = ixgbe_check_mac_link_generic; 126 1.2.2.2 skrll 127 1.2.2.3 skrll 128 1.2.2.5 skrll mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 129 1.2.2.5 skrll mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 130 1.2.2.5 skrll mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 131 1.2.2.5 skrll mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 132 1.2.2.5 skrll mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 133 1.2.2.5 skrll mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 134 1.2.2.2 skrll mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 135 1.2.2.2 skrll 136 1.2.2.2 skrll /* 137 1.2.2.2 skrll * FWSM register 138 1.2.2.2 skrll * ARC supported; valid only if manageability features are 139 1.2.2.2 skrll * enabled. 140 1.2.2.2 skrll */ 141 1.2.2.5 skrll mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 142 1.2.2.5 skrll & IXGBE_FWSM_MODE_MASK); 143 1.2.2.2 skrll 144 1.2.2.2 skrll hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 145 1.2.2.2 skrll 146 1.2.2.2 skrll /* LEDs */ 147 1.2.2.2 skrll mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 148 1.2.2.2 skrll mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 149 1.2.2.2 skrll 150 1.2.2.2 skrll /* Manageability interface */ 151 1.2.2.5 skrll mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 152 1.2.2.2 skrll 153 1.2.2.5 skrll mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 154 1.2.2.4 skrll 155 1.2.2.2 skrll return ret_val; 156 1.2.2.2 skrll } 157 1.2.2.2 skrll 158 1.2.2.2 skrll /** 159 1.2.2.2 skrll * ixgbe_get_link_capabilities_X540 - Determines link capabilities 160 1.2.2.2 skrll * @hw: pointer to hardware structure 161 1.2.2.2 skrll * @speed: pointer to link speed 162 1.2.2.2 skrll * @autoneg: TRUE when autoneg or autotry is enabled 163 1.2.2.2 skrll * 164 1.2.2.2 skrll * Determines the link capabilities by reading the AUTOC register. 165 1.2.2.2 skrll **/ 166 1.2.2.2 skrll s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 167 1.2.2.2 skrll ixgbe_link_speed *speed, 168 1.2.2.2 skrll bool *autoneg) 169 1.2.2.2 skrll { 170 1.2.2.2 skrll ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 171 1.2.2.2 skrll 172 1.2.2.2 skrll return IXGBE_SUCCESS; 173 1.2.2.2 skrll } 174 1.2.2.2 skrll 175 1.2.2.2 skrll /** 176 1.2.2.2 skrll * ixgbe_get_media_type_X540 - Get media type 177 1.2.2.2 skrll * @hw: pointer to hardware structure 178 1.2.2.2 skrll * 179 1.2.2.2 skrll * Returns the media type (fiber, copper, backplane) 180 1.2.2.2 skrll **/ 181 1.2.2.2 skrll enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 182 1.2.2.2 skrll { 183 1.2.2.2 skrll UNREFERENCED_1PARAMETER(hw); 184 1.2.2.2 skrll return ixgbe_media_type_copper; 185 1.2.2.2 skrll } 186 1.2.2.2 skrll 187 1.2.2.2 skrll /** 188 1.2.2.2 skrll * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 189 1.2.2.2 skrll * @hw: pointer to hardware structure 190 1.2.2.2 skrll * @speed: new link speed 191 1.2.2.2 skrll * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 192 1.2.2.2 skrll **/ 193 1.2.2.2 skrll s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 194 1.2.2.3 skrll ixgbe_link_speed speed, 195 1.2.2.2 skrll bool autoneg_wait_to_complete) 196 1.2.2.2 skrll { 197 1.2.2.2 skrll DEBUGFUNC("ixgbe_setup_mac_link_X540"); 198 1.2.2.3 skrll return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 199 1.2.2.2 skrll } 200 1.2.2.2 skrll 201 1.2.2.2 skrll /** 202 1.2.2.2 skrll * ixgbe_reset_hw_X540 - Perform hardware reset 203 1.2.2.2 skrll * @hw: pointer to hardware structure 204 1.2.2.2 skrll * 205 1.2.2.2 skrll * Resets the hardware by resetting the transmit and receive units, masks 206 1.2.2.2 skrll * and clears all interrupts, and perform a reset. 207 1.2.2.2 skrll **/ 208 1.2.2.2 skrll s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 209 1.2.2.2 skrll { 210 1.2.2.2 skrll s32 status; 211 1.2.2.2 skrll u32 ctrl, i; 212 1.2.2.2 skrll 213 1.2.2.2 skrll DEBUGFUNC("ixgbe_reset_hw_X540"); 214 1.2.2.2 skrll 215 1.2.2.2 skrll /* Call adapter stop to disable tx/rx and clear interrupts */ 216 1.2.2.2 skrll status = hw->mac.ops.stop_adapter(hw); 217 1.2.2.2 skrll if (status != IXGBE_SUCCESS) 218 1.2.2.2 skrll goto reset_hw_out; 219 1.2.2.2 skrll 220 1.2.2.2 skrll /* flush pending Tx transactions */ 221 1.2.2.2 skrll ixgbe_clear_tx_pending(hw); 222 1.2.2.2 skrll 223 1.2.2.2 skrll mac_reset_top: 224 1.2.2.2 skrll ctrl = IXGBE_CTRL_RST; 225 1.2.2.2 skrll ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 226 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 227 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 228 1.2.2.2 skrll 229 1.2.2.2 skrll /* Poll for reset bit to self-clear indicating reset is complete */ 230 1.2.2.2 skrll for (i = 0; i < 10; i++) { 231 1.2.2.2 skrll usec_delay(1); 232 1.2.2.2 skrll ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 233 1.2.2.2 skrll if (!(ctrl & IXGBE_CTRL_RST_MASK)) 234 1.2.2.2 skrll break; 235 1.2.2.2 skrll } 236 1.2.2.2 skrll 237 1.2.2.2 skrll if (ctrl & IXGBE_CTRL_RST_MASK) { 238 1.2.2.2 skrll status = IXGBE_ERR_RESET_FAILED; 239 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 240 1.2.2.4 skrll "Reset polling failed to complete.\n"); 241 1.2.2.2 skrll } 242 1.2.2.2 skrll msec_delay(100); 243 1.2.2.2 skrll 244 1.2.2.2 skrll /* 245 1.2.2.2 skrll * Double resets are required for recovery from certain error 246 1.2.2.2 skrll * conditions. Between resets, it is necessary to stall to allow time 247 1.2.2.2 skrll * for any pending HW events to complete. 248 1.2.2.2 skrll */ 249 1.2.2.2 skrll if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 250 1.2.2.2 skrll hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 251 1.2.2.2 skrll goto mac_reset_top; 252 1.2.2.2 skrll } 253 1.2.2.2 skrll 254 1.2.2.2 skrll /* Set the Rx packet buffer size. */ 255 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 256 1.2.2.2 skrll 257 1.2.2.2 skrll /* Store the permanent mac address */ 258 1.2.2.2 skrll hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 259 1.2.2.2 skrll 260 1.2.2.2 skrll /* 261 1.2.2.2 skrll * Store MAC address from RAR0, clear receive address registers, and 262 1.2.2.2 skrll * clear the multicast table. Also reset num_rar_entries to 128, 263 1.2.2.2 skrll * since we modify this value when programming the SAN MAC address. 264 1.2.2.2 skrll */ 265 1.2.2.2 skrll hw->mac.num_rar_entries = 128; 266 1.2.2.2 skrll hw->mac.ops.init_rx_addrs(hw); 267 1.2.2.2 skrll 268 1.2.2.2 skrll /* Store the permanent SAN mac address */ 269 1.2.2.2 skrll hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 270 1.2.2.2 skrll 271 1.2.2.2 skrll /* Add the SAN MAC address to the RAR only if it's a valid address */ 272 1.2.2.2 skrll if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 273 1.2.2.2 skrll hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 274 1.2.2.2 skrll hw->mac.san_addr, 0, IXGBE_RAH_AV); 275 1.2.2.2 skrll 276 1.2.2.2 skrll /* Save the SAN MAC RAR index */ 277 1.2.2.2 skrll hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 278 1.2.2.2 skrll 279 1.2.2.2 skrll /* Reserve the last RAR for the SAN MAC address */ 280 1.2.2.2 skrll hw->mac.num_rar_entries--; 281 1.2.2.2 skrll } 282 1.2.2.2 skrll 283 1.2.2.2 skrll /* Store the alternative WWNN/WWPN prefix */ 284 1.2.2.2 skrll hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 285 1.2.2.2 skrll &hw->mac.wwpn_prefix); 286 1.2.2.2 skrll 287 1.2.2.2 skrll reset_hw_out: 288 1.2.2.2 skrll return status; 289 1.2.2.2 skrll } 290 1.2.2.2 skrll 291 1.2.2.2 skrll /** 292 1.2.2.2 skrll * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 293 1.2.2.2 skrll * @hw: pointer to hardware structure 294 1.2.2.2 skrll * 295 1.2.2.2 skrll * Starts the hardware using the generic start_hw function 296 1.2.2.2 skrll * and the generation start_hw function. 297 1.2.2.2 skrll * Then performs revision-specific operations, if any. 298 1.2.2.2 skrll **/ 299 1.2.2.2 skrll s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 300 1.2.2.2 skrll { 301 1.2.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 302 1.2.2.2 skrll 303 1.2.2.2 skrll DEBUGFUNC("ixgbe_start_hw_X540"); 304 1.2.2.2 skrll 305 1.2.2.2 skrll ret_val = ixgbe_start_hw_generic(hw); 306 1.2.2.2 skrll if (ret_val != IXGBE_SUCCESS) 307 1.2.2.2 skrll goto out; 308 1.2.2.2 skrll 309 1.2.2.2 skrll ret_val = ixgbe_start_hw_gen2(hw); 310 1.2.2.2 skrll 311 1.2.2.2 skrll out: 312 1.2.2.2 skrll return ret_val; 313 1.2.2.2 skrll } 314 1.2.2.2 skrll 315 1.2.2.2 skrll /** 316 1.2.2.2 skrll * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 317 1.2.2.2 skrll * @hw: pointer to hardware structure 318 1.2.2.2 skrll * 319 1.2.2.2 skrll * Determines physical layer capabilities of the current configuration. 320 1.2.2.2 skrll **/ 321 1.2.2.2 skrll u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 322 1.2.2.2 skrll { 323 1.2.2.2 skrll u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 324 1.2.2.2 skrll u16 ext_ability = 0; 325 1.2.2.2 skrll 326 1.2.2.2 skrll DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 327 1.2.2.2 skrll 328 1.2.2.2 skrll hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 329 1.2.2.2 skrll IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 330 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 331 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 332 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 333 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 334 1.2.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 335 1.2.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 336 1.2.2.2 skrll 337 1.2.2.2 skrll return physical_layer; 338 1.2.2.2 skrll } 339 1.2.2.2 skrll 340 1.2.2.2 skrll /** 341 1.2.2.2 skrll * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 342 1.2.2.2 skrll * @hw: pointer to hardware structure 343 1.2.2.2 skrll * 344 1.2.2.2 skrll * Initializes the EEPROM parameters ixgbe_eeprom_info within the 345 1.2.2.2 skrll * ixgbe_hw struct in order to set up EEPROM access. 346 1.2.2.2 skrll **/ 347 1.2.2.2 skrll s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 348 1.2.2.2 skrll { 349 1.2.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 350 1.2.2.2 skrll u32 eec; 351 1.2.2.2 skrll u16 eeprom_size; 352 1.2.2.2 skrll 353 1.2.2.2 skrll DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 354 1.2.2.2 skrll 355 1.2.2.2 skrll if (eeprom->type == ixgbe_eeprom_uninitialized) { 356 1.2.2.2 skrll eeprom->semaphore_delay = 10; 357 1.2.2.2 skrll eeprom->type = ixgbe_flash; 358 1.2.2.2 skrll 359 1.2.2.5 skrll eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 360 1.2.2.2 skrll eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 361 1.2.2.2 skrll IXGBE_EEC_SIZE_SHIFT); 362 1.2.2.2 skrll eeprom->word_size = 1 << (eeprom_size + 363 1.2.2.2 skrll IXGBE_EEPROM_WORD_SIZE_SHIFT); 364 1.2.2.2 skrll 365 1.2.2.2 skrll DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 366 1.2.2.2 skrll eeprom->type, eeprom->word_size); 367 1.2.2.2 skrll } 368 1.2.2.2 skrll 369 1.2.2.2 skrll return IXGBE_SUCCESS; 370 1.2.2.2 skrll } 371 1.2.2.2 skrll 372 1.2.2.2 skrll /** 373 1.2.2.2 skrll * ixgbe_read_eerd_X540- Read EEPROM word using EERD 374 1.2.2.2 skrll * @hw: pointer to hardware structure 375 1.2.2.2 skrll * @offset: offset of word in the EEPROM to read 376 1.2.2.2 skrll * @data: word read from the EEPROM 377 1.2.2.2 skrll * 378 1.2.2.2 skrll * Reads a 16 bit word from the EEPROM using the EERD register. 379 1.2.2.2 skrll **/ 380 1.2.2.2 skrll s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 381 1.2.2.2 skrll { 382 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 383 1.2.2.2 skrll 384 1.2.2.2 skrll DEBUGFUNC("ixgbe_read_eerd_X540"); 385 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 386 1.2.2.4 skrll IXGBE_SUCCESS) { 387 1.2.2.2 skrll status = ixgbe_read_eerd_generic(hw, offset, data); 388 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 389 1.2.2.4 skrll } else { 390 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 391 1.2.2.4 skrll } 392 1.2.2.2 skrll 393 1.2.2.2 skrll return status; 394 1.2.2.2 skrll } 395 1.2.2.2 skrll 396 1.2.2.2 skrll /** 397 1.2.2.2 skrll * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 398 1.2.2.2 skrll * @hw: pointer to hardware structure 399 1.2.2.2 skrll * @offset: offset of word in the EEPROM to read 400 1.2.2.2 skrll * @words: number of words 401 1.2.2.2 skrll * @data: word(s) read from the EEPROM 402 1.2.2.2 skrll * 403 1.2.2.2 skrll * Reads a 16 bit word(s) from the EEPROM using the EERD register. 404 1.2.2.2 skrll **/ 405 1.2.2.2 skrll s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 406 1.2.2.2 skrll u16 offset, u16 words, u16 *data) 407 1.2.2.2 skrll { 408 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 409 1.2.2.2 skrll 410 1.2.2.2 skrll DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 411 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 412 1.2.2.4 skrll IXGBE_SUCCESS) { 413 1.2.2.2 skrll status = ixgbe_read_eerd_buffer_generic(hw, offset, 414 1.2.2.2 skrll words, data); 415 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 416 1.2.2.4 skrll } else { 417 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 418 1.2.2.4 skrll } 419 1.2.2.2 skrll 420 1.2.2.2 skrll return status; 421 1.2.2.2 skrll } 422 1.2.2.2 skrll 423 1.2.2.2 skrll /** 424 1.2.2.2 skrll * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 425 1.2.2.2 skrll * @hw: pointer to hardware structure 426 1.2.2.2 skrll * @offset: offset of word in the EEPROM to write 427 1.2.2.2 skrll * @data: word write to the EEPROM 428 1.2.2.2 skrll * 429 1.2.2.2 skrll * Write a 16 bit word to the EEPROM using the EEWR register. 430 1.2.2.2 skrll **/ 431 1.2.2.2 skrll s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 432 1.2.2.2 skrll { 433 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 434 1.2.2.2 skrll 435 1.2.2.2 skrll DEBUGFUNC("ixgbe_write_eewr_X540"); 436 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 437 1.2.2.4 skrll IXGBE_SUCCESS) { 438 1.2.2.2 skrll status = ixgbe_write_eewr_generic(hw, offset, data); 439 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 440 1.2.2.4 skrll } else { 441 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 442 1.2.2.4 skrll } 443 1.2.2.2 skrll 444 1.2.2.2 skrll return status; 445 1.2.2.2 skrll } 446 1.2.2.2 skrll 447 1.2.2.2 skrll /** 448 1.2.2.2 skrll * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 449 1.2.2.2 skrll * @hw: pointer to hardware structure 450 1.2.2.2 skrll * @offset: offset of word in the EEPROM to write 451 1.2.2.2 skrll * @words: number of words 452 1.2.2.2 skrll * @data: word(s) write to the EEPROM 453 1.2.2.2 skrll * 454 1.2.2.2 skrll * Write a 16 bit word(s) to the EEPROM using the EEWR register. 455 1.2.2.2 skrll **/ 456 1.2.2.2 skrll s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 457 1.2.2.2 skrll u16 offset, u16 words, u16 *data) 458 1.2.2.2 skrll { 459 1.2.2.2 skrll s32 status = IXGBE_SUCCESS; 460 1.2.2.2 skrll 461 1.2.2.2 skrll DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 462 1.2.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 463 1.2.2.4 skrll IXGBE_SUCCESS) { 464 1.2.2.2 skrll status = ixgbe_write_eewr_buffer_generic(hw, offset, 465 1.2.2.2 skrll words, data); 466 1.2.2.4 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 467 1.2.2.4 skrll } else { 468 1.2.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 469 1.2.2.4 skrll } 470 1.2.2.2 skrll 471 1.2.2.2 skrll return status; 472 1.2.2.2 skrll } 473 1.2.2.2 skrll 474 1.2.2.2 skrll /** 475 1.2.2.2 skrll * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 476 1.2.2.2 skrll * 477 1.2.2.2 skrll * This function does not use synchronization for EERD and EEWR. It can 478 1.2.2.2 skrll * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 479 1.2.2.2 skrll * 480 1.2.2.2 skrll * @hw: pointer to hardware structure 481 1.2.2.5 skrll * 482 1.2.2.5 skrll * Returns a negative error code on error, or the 16-bit checksum 483 1.2.2.2 skrll **/ 484 1.2.2.5 skrll s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 485 1.2.2.2 skrll { 486 1.2.2.5 skrll u16 i, j; 487 1.2.2.2 skrll u16 checksum = 0; 488 1.2.2.2 skrll u16 length = 0; 489 1.2.2.2 skrll u16 pointer = 0; 490 1.2.2.2 skrll u16 word = 0; 491 1.2.2.5 skrll u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM; 492 1.2.2.5 skrll u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 493 1.2.2.2 skrll 494 1.2.2.5 skrll /* Do not use hw->eeprom.ops.read because we do not want to take 495 1.2.2.2 skrll * the synchronization semaphores here. Instead use 496 1.2.2.2 skrll * ixgbe_read_eerd_generic 497 1.2.2.2 skrll */ 498 1.2.2.2 skrll 499 1.2.2.2 skrll DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 500 1.2.2.2 skrll 501 1.2.2.2 skrll /* Include 0x0-0x3F in the checksum */ 502 1.2.2.5 skrll for (i = 0; i <= checksum_last_word; i++) { 503 1.2.2.5 skrll if (ixgbe_read_eerd_generic(hw, i, &word)) { 504 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 505 1.2.2.5 skrll return IXGBE_ERR_EEPROM; 506 1.2.2.2 skrll } 507 1.2.2.5 skrll if (i != IXGBE_EEPROM_CHECKSUM) 508 1.2.2.5 skrll checksum += word; 509 1.2.2.2 skrll } 510 1.2.2.2 skrll 511 1.2.2.5 skrll /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 512 1.2.2.2 skrll * FW, PHY module, and PCIe Expansion/Option ROM pointers. 513 1.2.2.2 skrll */ 514 1.2.2.5 skrll for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 515 1.2.2.2 skrll if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 516 1.2.2.2 skrll continue; 517 1.2.2.2 skrll 518 1.2.2.5 skrll if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 519 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 520 1.2.2.5 skrll return IXGBE_ERR_EEPROM; 521 1.2.2.2 skrll } 522 1.2.2.2 skrll 523 1.2.2.2 skrll /* Skip pointer section if the pointer is invalid. */ 524 1.2.2.2 skrll if (pointer == 0xFFFF || pointer == 0 || 525 1.2.2.2 skrll pointer >= hw->eeprom.word_size) 526 1.2.2.2 skrll continue; 527 1.2.2.2 skrll 528 1.2.2.5 skrll if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 529 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 530 1.2.2.5 skrll return IXGBE_ERR_EEPROM; 531 1.2.2.2 skrll } 532 1.2.2.2 skrll 533 1.2.2.2 skrll /* Skip pointer section if length is invalid. */ 534 1.2.2.2 skrll if (length == 0xFFFF || length == 0 || 535 1.2.2.2 skrll (pointer + length) >= hw->eeprom.word_size) 536 1.2.2.2 skrll continue; 537 1.2.2.2 skrll 538 1.2.2.5 skrll for (j = pointer + 1; j <= pointer + length; j++) { 539 1.2.2.5 skrll if (ixgbe_read_eerd_generic(hw, j, &word)) { 540 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 541 1.2.2.5 skrll return IXGBE_ERR_EEPROM; 542 1.2.2.2 skrll } 543 1.2.2.2 skrll checksum += word; 544 1.2.2.2 skrll } 545 1.2.2.2 skrll } 546 1.2.2.2 skrll 547 1.2.2.2 skrll checksum = (u16)IXGBE_EEPROM_SUM - checksum; 548 1.2.2.2 skrll 549 1.2.2.5 skrll return (s32)checksum; 550 1.2.2.2 skrll } 551 1.2.2.2 skrll 552 1.2.2.2 skrll /** 553 1.2.2.2 skrll * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 554 1.2.2.2 skrll * @hw: pointer to hardware structure 555 1.2.2.2 skrll * @checksum_val: calculated checksum 556 1.2.2.2 skrll * 557 1.2.2.2 skrll * Performs checksum calculation and validates the EEPROM checksum. If the 558 1.2.2.2 skrll * caller does not need checksum_val, the value can be NULL. 559 1.2.2.2 skrll **/ 560 1.2.2.2 skrll s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 561 1.2.2.2 skrll u16 *checksum_val) 562 1.2.2.2 skrll { 563 1.2.2.2 skrll s32 status; 564 1.2.2.2 skrll u16 checksum; 565 1.2.2.2 skrll u16 read_checksum = 0; 566 1.2.2.2 skrll 567 1.2.2.2 skrll DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 568 1.2.2.2 skrll 569 1.2.2.5 skrll /* Read the first word from the EEPROM. If this times out or fails, do 570 1.2.2.2 skrll * not continue or we could be in for a very long wait while every 571 1.2.2.2 skrll * EEPROM read fails 572 1.2.2.2 skrll */ 573 1.2.2.2 skrll status = hw->eeprom.ops.read(hw, 0, &checksum); 574 1.2.2.5 skrll if (status) { 575 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 576 1.2.2.5 skrll return status; 577 1.2.2.2 skrll } 578 1.2.2.2 skrll 579 1.2.2.5 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 580 1.2.2.5 skrll return IXGBE_ERR_SWFW_SYNC; 581 1.2.2.2 skrll 582 1.2.2.5 skrll status = hw->eeprom.ops.calc_checksum(hw); 583 1.2.2.5 skrll if (status < 0) 584 1.2.2.5 skrll goto out; 585 1.2.2.2 skrll 586 1.2.2.5 skrll checksum = (u16)(status & 0xffff); 587 1.2.2.2 skrll 588 1.2.2.5 skrll /* Do not use hw->eeprom.ops.read because we do not want to take 589 1.2.2.5 skrll * the synchronization semaphores twice here. 590 1.2.2.5 skrll */ 591 1.2.2.5 skrll status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 592 1.2.2.5 skrll &read_checksum); 593 1.2.2.5 skrll if (status) 594 1.2.2.5 skrll goto out; 595 1.2.2.5 skrll 596 1.2.2.5 skrll /* Verify read checksum from EEPROM is the same as 597 1.2.2.5 skrll * calculated checksum 598 1.2.2.5 skrll */ 599 1.2.2.5 skrll if (read_checksum != checksum) { 600 1.2.2.5 skrll ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 601 1.2.2.5 skrll "Invalid EEPROM checksum"); 602 1.2.2.5 skrll status = IXGBE_ERR_EEPROM_CHECKSUM; 603 1.2.2.2 skrll } 604 1.2.2.2 skrll 605 1.2.2.5 skrll /* If the user cares, return the calculated checksum */ 606 1.2.2.5 skrll if (checksum_val) 607 1.2.2.5 skrll *checksum_val = checksum; 608 1.2.2.5 skrll 609 1.2.2.2 skrll out: 610 1.2.2.5 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 611 1.2.2.5 skrll 612 1.2.2.2 skrll return status; 613 1.2.2.2 skrll } 614 1.2.2.2 skrll 615 1.2.2.2 skrll /** 616 1.2.2.2 skrll * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 617 1.2.2.2 skrll * @hw: pointer to hardware structure 618 1.2.2.2 skrll * 619 1.2.2.2 skrll * After writing EEPROM to shadow RAM using EEWR register, software calculates 620 1.2.2.2 skrll * checksum and updates the EEPROM and instructs the hardware to update 621 1.2.2.2 skrll * the flash. 622 1.2.2.2 skrll **/ 623 1.2.2.2 skrll s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 624 1.2.2.2 skrll { 625 1.2.2.2 skrll s32 status; 626 1.2.2.2 skrll u16 checksum; 627 1.2.2.2 skrll 628 1.2.2.2 skrll DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 629 1.2.2.2 skrll 630 1.2.2.5 skrll /* Read the first word from the EEPROM. If this times out or fails, do 631 1.2.2.2 skrll * not continue or we could be in for a very long wait while every 632 1.2.2.2 skrll * EEPROM read fails 633 1.2.2.2 skrll */ 634 1.2.2.2 skrll status = hw->eeprom.ops.read(hw, 0, &checksum); 635 1.2.2.5 skrll if (status) { 636 1.2.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 637 1.2.2.5 skrll return status; 638 1.2.2.5 skrll } 639 1.2.2.2 skrll 640 1.2.2.5 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 641 1.2.2.5 skrll return IXGBE_ERR_SWFW_SYNC; 642 1.2.2.2 skrll 643 1.2.2.5 skrll status = hw->eeprom.ops.calc_checksum(hw); 644 1.2.2.5 skrll if (status < 0) 645 1.2.2.5 skrll goto out; 646 1.2.2.2 skrll 647 1.2.2.5 skrll checksum = (u16)(status & 0xffff); 648 1.2.2.5 skrll 649 1.2.2.5 skrll /* Do not use hw->eeprom.ops.write because we do not want to 650 1.2.2.5 skrll * take the synchronization semaphores twice here. 651 1.2.2.5 skrll */ 652 1.2.2.5 skrll status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 653 1.2.2.5 skrll if (status) 654 1.2.2.5 skrll goto out; 655 1.2.2.5 skrll 656 1.2.2.5 skrll status = ixgbe_update_flash_X540(hw); 657 1.2.2.5 skrll 658 1.2.2.5 skrll out: 659 1.2.2.5 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 660 1.2.2.2 skrll 661 1.2.2.2 skrll return status; 662 1.2.2.2 skrll } 663 1.2.2.2 skrll 664 1.2.2.2 skrll /** 665 1.2.2.2 skrll * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 666 1.2.2.2 skrll * @hw: pointer to hardware structure 667 1.2.2.2 skrll * 668 1.2.2.2 skrll * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 669 1.2.2.2 skrll * EEPROM from shadow RAM to the flash device. 670 1.2.2.2 skrll **/ 671 1.2.2.4 skrll s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 672 1.2.2.2 skrll { 673 1.2.2.2 skrll u32 flup; 674 1.2.2.5 skrll s32 status; 675 1.2.2.2 skrll 676 1.2.2.2 skrll DEBUGFUNC("ixgbe_update_flash_X540"); 677 1.2.2.2 skrll 678 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 679 1.2.2.2 skrll if (status == IXGBE_ERR_EEPROM) { 680 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 681 1.2.2.2 skrll goto out; 682 1.2.2.2 skrll } 683 1.2.2.2 skrll 684 1.2.2.5 skrll flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP; 685 1.2.2.5 skrll IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 686 1.2.2.2 skrll 687 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 688 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 689 1.2.2.2 skrll DEBUGOUT("Flash update complete\n"); 690 1.2.2.2 skrll else 691 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 692 1.2.2.2 skrll 693 1.2.2.4 skrll if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 694 1.2.2.5 skrll flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 695 1.2.2.2 skrll 696 1.2.2.2 skrll if (flup & IXGBE_EEC_SEC1VAL) { 697 1.2.2.2 skrll flup |= IXGBE_EEC_FLUP; 698 1.2.2.5 skrll IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 699 1.2.2.2 skrll } 700 1.2.2.2 skrll 701 1.2.2.2 skrll status = ixgbe_poll_flash_update_done_X540(hw); 702 1.2.2.2 skrll if (status == IXGBE_SUCCESS) 703 1.2.2.2 skrll DEBUGOUT("Flash update complete\n"); 704 1.2.2.2 skrll else 705 1.2.2.2 skrll DEBUGOUT("Flash update time out\n"); 706 1.2.2.2 skrll } 707 1.2.2.2 skrll out: 708 1.2.2.2 skrll return status; 709 1.2.2.2 skrll } 710 1.2.2.2 skrll 711 1.2.2.2 skrll /** 712 1.2.2.2 skrll * ixgbe_poll_flash_update_done_X540 - Poll flash update status 713 1.2.2.2 skrll * @hw: pointer to hardware structure 714 1.2.2.2 skrll * 715 1.2.2.2 skrll * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 716 1.2.2.2 skrll * flash update is done. 717 1.2.2.2 skrll **/ 718 1.2.2.2 skrll static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 719 1.2.2.2 skrll { 720 1.2.2.2 skrll u32 i; 721 1.2.2.2 skrll u32 reg; 722 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 723 1.2.2.2 skrll 724 1.2.2.2 skrll DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 725 1.2.2.2 skrll 726 1.2.2.2 skrll for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 727 1.2.2.5 skrll reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 728 1.2.2.2 skrll if (reg & IXGBE_EEC_FLUDONE) { 729 1.2.2.2 skrll status = IXGBE_SUCCESS; 730 1.2.2.2 skrll break; 731 1.2.2.2 skrll } 732 1.2.2.5 skrll msec_delay(5); 733 1.2.2.2 skrll } 734 1.2.2.4 skrll 735 1.2.2.4 skrll if (i == IXGBE_FLUDONE_ATTEMPTS) 736 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 737 1.2.2.4 skrll "Flash update status polling timed out"); 738 1.2.2.4 skrll 739 1.2.2.2 skrll return status; 740 1.2.2.2 skrll } 741 1.2.2.2 skrll 742 1.2.2.2 skrll /** 743 1.2.2.2 skrll * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 744 1.2.2.2 skrll * @hw: pointer to hardware structure 745 1.2.2.2 skrll * @mask: Mask to specify which semaphore to acquire 746 1.2.2.2 skrll * 747 1.2.2.2 skrll * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 748 1.2.2.2 skrll * the specified function (CSR, PHY0, PHY1, NVM, Flash) 749 1.2.2.2 skrll **/ 750 1.2.2.5 skrll s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 751 1.2.2.2 skrll { 752 1.2.2.5 skrll u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; 753 1.2.2.5 skrll u32 fwmask = swmask << 5; 754 1.2.2.5 skrll u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; 755 1.2.2.2 skrll u32 timeout = 200; 756 1.2.2.5 skrll u32 hwmask = 0; 757 1.2.2.5 skrll u32 swfw_sync; 758 1.2.2.2 skrll u32 i; 759 1.2.2.2 skrll 760 1.2.2.2 skrll DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 761 1.2.2.2 skrll 762 1.2.2.5 skrll if (swmask & IXGBE_GSSR_EEP_SM) 763 1.2.2.5 skrll hwmask |= IXGBE_GSSR_FLASH_SM; 764 1.2.2.2 skrll 765 1.2.2.2 skrll /* SW only mask doesn't have FW bit pair */ 766 1.2.2.5 skrll if (mask & IXGBE_GSSR_SW_MNG_SM) 767 1.2.2.5 skrll swmask |= IXGBE_GSSR_SW_MNG_SM; 768 1.2.2.2 skrll 769 1.2.2.5 skrll swmask |= swi2c_mask; 770 1.2.2.5 skrll fwmask |= swi2c_mask << 2; 771 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 772 1.2.2.5 skrll /* SW NVM semaphore bit is used for access to all 773 1.2.2.2 skrll * SW_FW_SYNC bits (not just NVM) 774 1.2.2.2 skrll */ 775 1.2.2.5 skrll if (ixgbe_get_swfw_sync_semaphore(hw)) 776 1.2.2.5 skrll return IXGBE_ERR_SWFW_SYNC; 777 1.2.2.2 skrll 778 1.2.2.5 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 779 1.2.2.2 skrll if (!(swfw_sync & (fwmask | swmask | hwmask))) { 780 1.2.2.2 skrll swfw_sync |= swmask; 781 1.2.2.5 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), 782 1.2.2.5 skrll swfw_sync); 783 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 784 1.2.2.2 skrll msec_delay(5); 785 1.2.2.5 skrll return IXGBE_SUCCESS; 786 1.2.2.2 skrll } 787 1.2.2.5 skrll /* Firmware currently using resource (fwmask), hardware 788 1.2.2.5 skrll * currently using resource (hwmask), or other software 789 1.2.2.5 skrll * thread currently using resource (swmask) 790 1.2.2.5 skrll */ 791 1.2.2.5 skrll ixgbe_release_swfw_sync_semaphore(hw); 792 1.2.2.5 skrll msec_delay(5); 793 1.2.2.2 skrll } 794 1.2.2.2 skrll 795 1.2.2.2 skrll /* Failed to get SW only semaphore */ 796 1.2.2.2 skrll if (swmask == IXGBE_GSSR_SW_MNG_SM) { 797 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 798 1.2.2.4 skrll "Failed to get SW only semaphore"); 799 1.2.2.5 skrll return IXGBE_ERR_SWFW_SYNC; 800 1.2.2.2 skrll } 801 1.2.2.2 skrll 802 1.2.2.2 skrll /* If the resource is not released by the FW/HW the SW can assume that 803 1.2.2.4 skrll * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 804 1.2.2.2 skrll * of the requested resource(s) while ignoring the corresponding FW/HW 805 1.2.2.2 skrll * bits in the SW_FW_SYNC register. 806 1.2.2.2 skrll */ 807 1.2.2.5 skrll if (ixgbe_get_swfw_sync_semaphore(hw)) 808 1.2.2.5 skrll return IXGBE_ERR_SWFW_SYNC; 809 1.2.2.5 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 810 1.2.2.2 skrll if (swfw_sync & (fwmask | hwmask)) { 811 1.2.2.2 skrll swfw_sync |= swmask; 812 1.2.2.5 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 813 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 814 1.2.2.2 skrll msec_delay(5); 815 1.2.2.5 skrll return IXGBE_SUCCESS; 816 1.2.2.2 skrll } 817 1.2.2.4 skrll /* If the resource is not released by other SW the SW can assume that 818 1.2.2.4 skrll * the other SW malfunctions. In that case the SW should clear all SW 819 1.2.2.4 skrll * flags that it does not own and then repeat the whole process once 820 1.2.2.4 skrll * again. 821 1.2.2.4 skrll */ 822 1.2.2.5 skrll if (swfw_sync & swmask) { 823 1.2.2.5 skrll u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 824 1.2.2.5 skrll IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM; 825 1.2.2.5 skrll 826 1.2.2.5 skrll if (swi2c_mask) 827 1.2.2.5 skrll rmask |= IXGBE_GSSR_I2C_MASK; 828 1.2.2.5 skrll ixgbe_release_swfw_sync_X540(hw, rmask); 829 1.2.2.5 skrll ixgbe_release_swfw_sync_semaphore(hw); 830 1.2.2.5 skrll return IXGBE_ERR_SWFW_SYNC; 831 1.2.2.4 skrll } 832 1.2.2.5 skrll ixgbe_release_swfw_sync_semaphore(hw); 833 1.2.2.2 skrll 834 1.2.2.5 skrll return IXGBE_ERR_SWFW_SYNC; 835 1.2.2.2 skrll } 836 1.2.2.2 skrll 837 1.2.2.2 skrll /** 838 1.2.2.2 skrll * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 839 1.2.2.2 skrll * @hw: pointer to hardware structure 840 1.2.2.2 skrll * @mask: Mask to specify which semaphore to release 841 1.2.2.2 skrll * 842 1.2.2.2 skrll * Releases the SWFW semaphore through the SW_FW_SYNC register 843 1.2.2.2 skrll * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 844 1.2.2.2 skrll **/ 845 1.2.2.5 skrll void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 846 1.2.2.2 skrll { 847 1.2.2.5 skrll u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); 848 1.2.2.2 skrll u32 swfw_sync; 849 1.2.2.2 skrll 850 1.2.2.2 skrll DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 851 1.2.2.2 skrll 852 1.2.2.5 skrll if (mask & IXGBE_GSSR_I2C_MASK) 853 1.2.2.5 skrll swmask |= mask & IXGBE_GSSR_I2C_MASK; 854 1.2.2.2 skrll ixgbe_get_swfw_sync_semaphore(hw); 855 1.2.2.2 skrll 856 1.2.2.5 skrll swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 857 1.2.2.2 skrll swfw_sync &= ~swmask; 858 1.2.2.5 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 859 1.2.2.2 skrll 860 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 861 1.2.2.5 skrll msec_delay(5); 862 1.2.2.2 skrll } 863 1.2.2.2 skrll 864 1.2.2.2 skrll /** 865 1.2.2.5 skrll * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 866 1.2.2.2 skrll * @hw: pointer to hardware structure 867 1.2.2.2 skrll * 868 1.2.2.2 skrll * Sets the hardware semaphores so SW/FW can gain control of shared resources 869 1.2.2.2 skrll **/ 870 1.2.2.2 skrll static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 871 1.2.2.2 skrll { 872 1.2.2.2 skrll s32 status = IXGBE_ERR_EEPROM; 873 1.2.2.2 skrll u32 timeout = 2000; 874 1.2.2.2 skrll u32 i; 875 1.2.2.2 skrll u32 swsm; 876 1.2.2.2 skrll 877 1.2.2.2 skrll DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 878 1.2.2.2 skrll 879 1.2.2.2 skrll /* Get SMBI software semaphore between device drivers first */ 880 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 881 1.2.2.2 skrll /* 882 1.2.2.2 skrll * If the SMBI bit is 0 when we read it, then the bit will be 883 1.2.2.2 skrll * set and we have the semaphore 884 1.2.2.2 skrll */ 885 1.2.2.5 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 886 1.2.2.2 skrll if (!(swsm & IXGBE_SWSM_SMBI)) { 887 1.2.2.2 skrll status = IXGBE_SUCCESS; 888 1.2.2.2 skrll break; 889 1.2.2.2 skrll } 890 1.2.2.2 skrll usec_delay(50); 891 1.2.2.2 skrll } 892 1.2.2.2 skrll 893 1.2.2.2 skrll /* Now get the semaphore between SW/FW through the REGSMP bit */ 894 1.2.2.2 skrll if (status == IXGBE_SUCCESS) { 895 1.2.2.2 skrll for (i = 0; i < timeout; i++) { 896 1.2.2.5 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 897 1.2.2.2 skrll if (!(swsm & IXGBE_SWFW_REGSMP)) 898 1.2.2.2 skrll break; 899 1.2.2.2 skrll 900 1.2.2.2 skrll usec_delay(50); 901 1.2.2.2 skrll } 902 1.2.2.2 skrll 903 1.2.2.2 skrll /* 904 1.2.2.2 skrll * Release semaphores and return error if SW NVM semaphore 905 1.2.2.2 skrll * was not granted because we don't have access to the EEPROM 906 1.2.2.2 skrll */ 907 1.2.2.2 skrll if (i >= timeout) { 908 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 909 1.2.2.4 skrll "REGSMP Software NVM semaphore not granted.\n"); 910 1.2.2.2 skrll ixgbe_release_swfw_sync_semaphore(hw); 911 1.2.2.2 skrll status = IXGBE_ERR_EEPROM; 912 1.2.2.2 skrll } 913 1.2.2.2 skrll } else { 914 1.2.2.4 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, 915 1.2.2.4 skrll "Software semaphore SMBI between device drivers " 916 1.2.2.4 skrll "not granted.\n"); 917 1.2.2.2 skrll } 918 1.2.2.2 skrll 919 1.2.2.2 skrll return status; 920 1.2.2.2 skrll } 921 1.2.2.2 skrll 922 1.2.2.2 skrll /** 923 1.2.2.5 skrll * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore 924 1.2.2.2 skrll * @hw: pointer to hardware structure 925 1.2.2.2 skrll * 926 1.2.2.2 skrll * This function clears hardware semaphore bits. 927 1.2.2.2 skrll **/ 928 1.2.2.2 skrll static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 929 1.2.2.2 skrll { 930 1.2.2.2 skrll u32 swsm; 931 1.2.2.2 skrll 932 1.2.2.2 skrll DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 933 1.2.2.2 skrll 934 1.2.2.2 skrll /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 935 1.2.2.2 skrll 936 1.2.2.5 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 937 1.2.2.2 skrll swsm &= ~IXGBE_SWFW_REGSMP; 938 1.2.2.5 skrll IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); 939 1.2.2.5 skrll 940 1.2.2.5 skrll swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 941 1.2.2.5 skrll swsm &= ~IXGBE_SWSM_SMBI; 942 1.2.2.5 skrll IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 943 1.2.2.2 skrll 944 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 945 1.2.2.2 skrll } 946 1.2.2.2 skrll 947 1.2.2.2 skrll /** 948 1.2.2.2 skrll * ixgbe_blink_led_start_X540 - Blink LED based on index. 949 1.2.2.2 skrll * @hw: pointer to hardware structure 950 1.2.2.2 skrll * @index: led number to blink 951 1.2.2.2 skrll * 952 1.2.2.2 skrll * Devices that implement the version 2 interface: 953 1.2.2.2 skrll * X540 954 1.2.2.2 skrll **/ 955 1.2.2.2 skrll s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 956 1.2.2.2 skrll { 957 1.2.2.2 skrll u32 macc_reg; 958 1.2.2.2 skrll u32 ledctl_reg; 959 1.2.2.2 skrll ixgbe_link_speed speed; 960 1.2.2.2 skrll bool link_up; 961 1.2.2.2 skrll 962 1.2.2.2 skrll DEBUGFUNC("ixgbe_blink_led_start_X540"); 963 1.2.2.2 skrll 964 1.2.2.2 skrll /* 965 1.2.2.2 skrll * Link should be up in order for the blink bit in the LED control 966 1.2.2.2 skrll * register to work. Force link and speed in the MAC if link is down. 967 1.2.2.2 skrll * This will be reversed when we stop the blinking. 968 1.2.2.2 skrll */ 969 1.2.2.2 skrll hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 970 1.2.2.2 skrll if (link_up == FALSE) { 971 1.2.2.2 skrll macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 972 1.2.2.2 skrll macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 973 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 974 1.2.2.2 skrll } 975 1.2.2.2 skrll /* Set the LED to LINK_UP + BLINK. */ 976 1.2.2.2 skrll ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 977 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 978 1.2.2.2 skrll ledctl_reg |= IXGBE_LED_BLINK(index); 979 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 980 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 981 1.2.2.2 skrll 982 1.2.2.2 skrll return IXGBE_SUCCESS; 983 1.2.2.2 skrll } 984 1.2.2.2 skrll 985 1.2.2.2 skrll /** 986 1.2.2.2 skrll * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 987 1.2.2.2 skrll * @hw: pointer to hardware structure 988 1.2.2.2 skrll * @index: led number to stop blinking 989 1.2.2.2 skrll * 990 1.2.2.2 skrll * Devices that implement the version 2 interface: 991 1.2.2.2 skrll * X540 992 1.2.2.2 skrll **/ 993 1.2.2.2 skrll s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 994 1.2.2.2 skrll { 995 1.2.2.2 skrll u32 macc_reg; 996 1.2.2.2 skrll u32 ledctl_reg; 997 1.2.2.2 skrll 998 1.2.2.2 skrll DEBUGFUNC("ixgbe_blink_led_stop_X540"); 999 1.2.2.2 skrll 1000 1.2.2.2 skrll /* Restore the LED to its default value. */ 1001 1.2.2.2 skrll ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1002 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1003 1.2.2.2 skrll ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 1004 1.2.2.2 skrll ledctl_reg &= ~IXGBE_LED_BLINK(index); 1005 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1006 1.2.2.2 skrll 1007 1.2.2.2 skrll /* Unforce link and speed in the MAC. */ 1008 1.2.2.2 skrll macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1009 1.2.2.2 skrll macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 1010 1.2.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1011 1.2.2.2 skrll IXGBE_WRITE_FLUSH(hw); 1012 1.2.2.2 skrll 1013 1.2.2.2 skrll return IXGBE_SUCCESS; 1014 1.2.2.2 skrll } 1015
Indexes created Mon Oct 20 20:10:13 GMT 2025