ixgbe_x540.c revision 1.11.2.2
1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 320688 2017-07-05 17:27:03Z erj $*/ 34 35 #include "ixgbe_x540.h" 36 #include "ixgbe_type.h" 37 #include "ixgbe_api.h" 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 41 #define IXGBE_X540_MAX_TX_QUEUES 128 42 #define IXGBE_X540_MAX_RX_QUEUES 128 43 #define IXGBE_X540_RAR_ENTRIES 128 44 #define IXGBE_X540_MC_TBL_SIZE 128 45 #define IXGBE_X540_VFT_TBL_SIZE 128 46 #define IXGBE_X540_RX_PB_SIZE 384 47 48 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 49 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 50 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 54 * @hw: pointer to hardware structure 55 * 56 * Initialize the function pointers and assign the MAC type for X540. 57 * Does not touch the hardware. 58 **/ 59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 60 { 61 struct ixgbe_mac_info *mac = &hw->mac; 62 struct ixgbe_phy_info *phy = &hw->phy; 63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 64 s32 ret_val; 65 66 DEBUGFUNC("ixgbe_init_ops_X540"); 67 68 ret_val = ixgbe_init_phy_ops_generic(hw); 69 ret_val = ixgbe_init_ops_generic(hw); 70 71 72 /* EEPROM */ 73 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 74 eeprom->ops.read = ixgbe_read_eerd_X540; 75 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; 76 eeprom->ops.write = ixgbe_write_eewr_X540; 77 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540; 78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540; 79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540; 80 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540; 81 82 /* PHY */ 83 phy->ops.init = ixgbe_init_phy_ops_generic; 84 phy->ops.reset = NULL; 85 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; 86 87 /* MAC */ 88 mac->ops.reset_hw = ixgbe_reset_hw_X540; 89 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 90 mac->ops.get_media_type = ixgbe_get_media_type_X540; 91 mac->ops.get_supported_physical_layer = 92 ixgbe_get_supported_physical_layer_X540; 93 mac->ops.read_analog_reg8 = NULL; 94 mac->ops.write_analog_reg8 = NULL; 95 mac->ops.start_hw = ixgbe_start_hw_X540; 96 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 97 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 98 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 99 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 100 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 101 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; 102 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; 103 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540; 104 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 105 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 106 107 /* RAR, Multicast, VLAN */ 108 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 109 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 110 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 111 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 112 mac->rar_highwater = 1; 113 mac->ops.set_vfta = ixgbe_set_vfta_generic; 114 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 115 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 116 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 117 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 118 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 119 120 /* Link */ 121 mac->ops.get_link_capabilities = 122 ixgbe_get_copper_link_capabilities_generic; 123 mac->ops.setup_link = ixgbe_setup_mac_link_X540; 124 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 125 mac->ops.check_link = ixgbe_check_mac_link_generic; 126 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; 127 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; 128 mac->ops.bypass_set = ixgbe_bypass_set_generic; 129 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; 130 131 132 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 133 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 134 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 135 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 136 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 137 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 138 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 139 140 /* 141 * FWSM register 142 * ARC supported; valid only if manageability features are 143 * enabled. 144 */ 145 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 146 & IXGBE_FWSM_MODE_MASK); 147 148 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 149 150 /* LEDs */ 151 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 152 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 153 154 /* Manageability interface */ 155 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 156 157 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 158 159 return ret_val; 160 } 161 162 /** 163 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 164 * @hw: pointer to hardware structure 165 * @speed: pointer to link speed 166 * @autoneg: TRUE when autoneg or autotry is enabled 167 * 168 * Determines the link capabilities by reading the AUTOC register. 169 **/ 170 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 171 ixgbe_link_speed *speed, 172 bool *autoneg) 173 { 174 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 175 176 return IXGBE_SUCCESS; 177 } 178 179 /** 180 * ixgbe_get_media_type_X540 - Get media type 181 * @hw: pointer to hardware structure 182 * 183 * Returns the media type (fiber, copper, backplane) 184 **/ 185 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 186 { 187 UNREFERENCED_1PARAMETER(hw); 188 return ixgbe_media_type_copper; 189 } 190 191 /** 192 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 193 * @hw: pointer to hardware structure 194 * @speed: new link speed 195 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 196 **/ 197 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 198 ixgbe_link_speed speed, 199 bool autoneg_wait_to_complete) 200 { 201 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 202 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 203 } 204 205 /** 206 * ixgbe_reset_hw_X540 - Perform hardware reset 207 * @hw: pointer to hardware structure 208 * 209 * Resets the hardware by resetting the transmit and receive units, masks 210 * and clears all interrupts, and perform a reset. 211 **/ 212 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 213 { 214 s32 status; 215 u32 ctrl, i; 216 u32 swfw_mask = hw->phy.phy_semaphore_mask; 217 218 DEBUGFUNC("ixgbe_reset_hw_X540"); 219 220 /* Call adapter stop to disable tx/rx and clear interrupts */ 221 status = hw->mac.ops.stop_adapter(hw); 222 if (status != IXGBE_SUCCESS) 223 goto reset_hw_out; 224 225 /* flush pending Tx transactions */ 226 ixgbe_clear_tx_pending(hw); 227 228 mac_reset_top: 229 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 230 if (status != IXGBE_SUCCESS) { 231 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 232 "semaphore failed with %d", status); 233 return IXGBE_ERR_SWFW_SYNC; 234 } 235 ctrl = IXGBE_CTRL_RST; 236 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 237 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 238 IXGBE_WRITE_FLUSH(hw); 239 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 240 241 /* Poll for reset bit to self-clear indicating reset is complete */ 242 for (i = 0; i < 10; i++) { 243 usec_delay(1); 244 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 245 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 246 break; 247 } 248 249 if (ctrl & IXGBE_CTRL_RST_MASK) { 250 status = IXGBE_ERR_RESET_FAILED; 251 ERROR_REPORT1(IXGBE_ERROR_POLLING, 252 "Reset polling failed to complete.\n"); 253 } 254 msec_delay(100); 255 256 /* 257 * Double resets are required for recovery from certain error 258 * conditions. Between resets, it is necessary to stall to allow time 259 * for any pending HW events to complete. 260 */ 261 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 262 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 263 goto mac_reset_top; 264 } 265 266 /* Set the Rx packet buffer size. */ 267 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 268 269 /* Store the permanent mac address */ 270 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 271 272 /* 273 * Store MAC address from RAR0, clear receive address registers, and 274 * clear the multicast table. Also reset num_rar_entries to 128, 275 * since we modify this value when programming the SAN MAC address. 276 */ 277 hw->mac.num_rar_entries = 128; 278 hw->mac.ops.init_rx_addrs(hw); 279 280 /* Store the permanent SAN mac address */ 281 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 282 283 /* Add the SAN MAC address to the RAR only if it's a valid address */ 284 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 285 /* Save the SAN MAC RAR index */ 286 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 287 288 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 289 hw->mac.san_addr, 0, IXGBE_RAH_AV); 290 291 /* clear VMDq pool/queue selection for this RAR */ 292 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 293 IXGBE_CLEAR_VMDQ_ALL); 294 295 /* Reserve the last RAR for the SAN MAC address */ 296 hw->mac.num_rar_entries--; 297 } 298 299 /* Store the alternative WWNN/WWPN prefix */ 300 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 301 &hw->mac.wwpn_prefix); 302 303 reset_hw_out: 304 return status; 305 } 306 307 /** 308 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 309 * @hw: pointer to hardware structure 310 * 311 * Starts the hardware using the generic start_hw function 312 * and the generation start_hw function. 313 * Then performs revision-specific operations, if any. 314 **/ 315 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 316 { 317 s32 ret_val = IXGBE_SUCCESS; 318 319 DEBUGFUNC("ixgbe_start_hw_X540"); 320 321 ret_val = ixgbe_start_hw_generic(hw); 322 if (ret_val != IXGBE_SUCCESS) 323 goto out; 324 325 ret_val = ixgbe_start_hw_gen2(hw); 326 327 out: 328 return ret_val; 329 } 330 331 /** 332 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 333 * @hw: pointer to hardware structure 334 * 335 * Determines physical layer capabilities of the current configuration. 336 **/ 337 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 338 { 339 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 340 u16 ext_ability = 0; 341 342 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 343 344 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 345 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 346 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 347 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 348 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 349 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 350 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 351 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 352 353 if (hw->mac.type == ixgbe_mac_X550) { 354 physical_layer |= IXGBE_PHYSICAL_LAYER_2500BASE_T 355 | IXGBE_PHYSICAL_LAYER_5GBASE_T; 356 } 357 358 return physical_layer; 359 } 360 361 /** 362 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 363 * @hw: pointer to hardware structure 364 * 365 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 366 * ixgbe_hw struct in order to set up EEPROM access. 367 **/ 368 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 369 { 370 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 371 u32 eec; 372 u16 eeprom_size; 373 374 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 375 376 if (eeprom->type == ixgbe_eeprom_uninitialized) { 377 eeprom->semaphore_delay = 10; 378 eeprom->type = ixgbe_flash; 379 380 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 381 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 382 IXGBE_EEC_SIZE_SHIFT); 383 eeprom->word_size = 1 << (eeprom_size + 384 IXGBE_EEPROM_WORD_SIZE_SHIFT); 385 386 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 387 eeprom->type, eeprom->word_size); 388 } 389 390 return IXGBE_SUCCESS; 391 } 392 393 /** 394 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 395 * @hw: pointer to hardware structure 396 * @offset: offset of word in the EEPROM to read 397 * @data: word read from the EEPROM 398 * 399 * Reads a 16 bit word from the EEPROM using the EERD register. 400 **/ 401 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 402 { 403 s32 status = IXGBE_SUCCESS; 404 405 DEBUGFUNC("ixgbe_read_eerd_X540"); 406 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 407 IXGBE_SUCCESS) { 408 status = ixgbe_read_eerd_generic(hw, offset, data); 409 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 410 } else { 411 status = IXGBE_ERR_SWFW_SYNC; 412 } 413 414 return status; 415 } 416 417 /** 418 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 419 * @hw: pointer to hardware structure 420 * @offset: offset of word in the EEPROM to read 421 * @words: number of words 422 * @data: word(s) read from the EEPROM 423 * 424 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 425 **/ 426 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 427 u16 offset, u16 words, u16 *data) 428 { 429 s32 status = IXGBE_SUCCESS; 430 431 DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 432 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 433 IXGBE_SUCCESS) { 434 status = ixgbe_read_eerd_buffer_generic(hw, offset, 435 words, data); 436 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 437 } else { 438 status = IXGBE_ERR_SWFW_SYNC; 439 } 440 441 return status; 442 } 443 444 /** 445 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 446 * @hw: pointer to hardware structure 447 * @offset: offset of word in the EEPROM to write 448 * @data: word write to the EEPROM 449 * 450 * Write a 16 bit word to the EEPROM using the EEWR register. 451 **/ 452 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 453 { 454 s32 status = IXGBE_SUCCESS; 455 456 DEBUGFUNC("ixgbe_write_eewr_X540"); 457 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 458 IXGBE_SUCCESS) { 459 status = ixgbe_write_eewr_generic(hw, offset, data); 460 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 461 } else { 462 status = IXGBE_ERR_SWFW_SYNC; 463 } 464 465 return status; 466 } 467 468 /** 469 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 470 * @hw: pointer to hardware structure 471 * @offset: offset of word in the EEPROM to write 472 * @words: number of words 473 * @data: word(s) write to the EEPROM 474 * 475 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 476 **/ 477 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 478 u16 offset, u16 words, u16 *data) 479 { 480 s32 status = IXGBE_SUCCESS; 481 482 DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 483 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 484 IXGBE_SUCCESS) { 485 status = ixgbe_write_eewr_buffer_generic(hw, offset, 486 words, data); 487 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 488 } else { 489 status = IXGBE_ERR_SWFW_SYNC; 490 } 491 492 return status; 493 } 494 495 /** 496 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 497 * 498 * This function does not use synchronization for EERD and EEWR. It can 499 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 500 * 501 * @hw: pointer to hardware structure 502 * 503 * Returns a negative error code on error, or the 16-bit checksum 504 **/ 505 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 506 { 507 u16 i, j; 508 u16 checksum = 0; 509 u16 length = 0; 510 u16 pointer = 0; 511 u16 word = 0; 512 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 513 514 /* Do not use hw->eeprom.ops.read because we do not want to take 515 * the synchronization semaphores here. Instead use 516 * ixgbe_read_eerd_generic 517 */ 518 519 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 520 521 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the 522 * checksum itself 523 */ 524 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 525 if (ixgbe_read_eerd_generic(hw, i, &word)) { 526 DEBUGOUT("EEPROM read failed\n"); 527 return IXGBE_ERR_EEPROM; 528 } 529 checksum += word; 530 } 531 532 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 533 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 534 */ 535 for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 536 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 537 continue; 538 539 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 540 DEBUGOUT("EEPROM read failed\n"); 541 return IXGBE_ERR_EEPROM; 542 } 543 544 /* Skip pointer section if the pointer is invalid. */ 545 if (pointer == 0xFFFF || pointer == 0 || 546 pointer >= hw->eeprom.word_size) 547 continue; 548 549 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 550 DEBUGOUT("EEPROM read failed\n"); 551 return IXGBE_ERR_EEPROM; 552 } 553 554 /* Skip pointer section if length is invalid. */ 555 if (length == 0xFFFF || length == 0 || 556 (pointer + length) >= hw->eeprom.word_size) 557 continue; 558 559 for (j = pointer + 1; j <= pointer + length; j++) { 560 if (ixgbe_read_eerd_generic(hw, j, &word)) { 561 DEBUGOUT("EEPROM read failed\n"); 562 return IXGBE_ERR_EEPROM; 563 } 564 checksum += word; 565 } 566 } 567 568 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 569 570 return (s32)checksum; 571 } 572 573 /** 574 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 575 * @hw: pointer to hardware structure 576 * @checksum_val: calculated checksum 577 * 578 * Performs checksum calculation and validates the EEPROM checksum. If the 579 * caller does not need checksum_val, the value can be NULL. 580 **/ 581 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 582 u16 *checksum_val) 583 { 584 s32 status; 585 u16 checksum; 586 u16 read_checksum = 0; 587 588 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 589 590 /* Read the first word from the EEPROM. If this times out or fails, do 591 * not continue or we could be in for a very long wait while every 592 * EEPROM read fails 593 */ 594 status = hw->eeprom.ops.read(hw, 0, &checksum); 595 if (status) { 596 DEBUGOUT("EEPROM read failed\n"); 597 return status; 598 } 599 600 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 601 return IXGBE_ERR_SWFW_SYNC; 602 603 status = hw->eeprom.ops.calc_checksum(hw); 604 if (status < 0) 605 goto out; 606 607 checksum = (u16)(status & 0xffff); 608 609 /* Do not use hw->eeprom.ops.read because we do not want to take 610 * the synchronization semaphores twice here. 611 */ 612 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 613 &read_checksum); 614 if (status) 615 goto out; 616 617 /* Verify read checksum from EEPROM is the same as 618 * calculated checksum 619 */ 620 if (read_checksum != checksum) { 621 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 622 "Invalid EEPROM checksum"); 623 status = IXGBE_ERR_EEPROM_CHECKSUM; 624 } 625 626 /* If the user cares, return the calculated checksum */ 627 if (checksum_val) 628 *checksum_val = checksum; 629 630 out: 631 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 632 633 return status; 634 } 635 636 /** 637 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 638 * @hw: pointer to hardware structure 639 * 640 * After writing EEPROM to shadow RAM using EEWR register, software calculates 641 * checksum and updates the EEPROM and instructs the hardware to update 642 * the flash. 643 **/ 644 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 645 { 646 s32 status; 647 u16 checksum; 648 649 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 650 651 /* Read the first word from the EEPROM. If this times out or fails, do 652 * not continue or we could be in for a very long wait while every 653 * EEPROM read fails 654 */ 655 status = hw->eeprom.ops.read(hw, 0, &checksum); 656 if (status) { 657 DEBUGOUT("EEPROM read failed\n"); 658 return status; 659 } 660 661 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 662 return IXGBE_ERR_SWFW_SYNC; 663 664 status = hw->eeprom.ops.calc_checksum(hw); 665 if (status < 0) 666 goto out; 667 668 checksum = (u16)(status & 0xffff); 669 670 /* Do not use hw->eeprom.ops.write because we do not want to 671 * take the synchronization semaphores twice here. 672 */ 673 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 674 if (status) 675 goto out; 676 677 status = ixgbe_update_flash_X540(hw); 678 679 out: 680 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 681 682 return status; 683 } 684 685 /** 686 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 687 * @hw: pointer to hardware structure 688 * 689 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 690 * EEPROM from shadow RAM to the flash device. 691 **/ 692 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 693 { 694 u32 flup; 695 s32 status; 696 697 DEBUGFUNC("ixgbe_update_flash_X540"); 698 699 status = ixgbe_poll_flash_update_done_X540(hw); 700 if (status == IXGBE_ERR_EEPROM) { 701 DEBUGOUT("Flash update time out\n"); 702 goto out; 703 } 704 705 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP; 706 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 707 708 status = ixgbe_poll_flash_update_done_X540(hw); 709 if (status == IXGBE_SUCCESS) 710 DEBUGOUT("Flash update complete\n"); 711 else 712 DEBUGOUT("Flash update time out\n"); 713 714 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 715 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 716 717 if (flup & IXGBE_EEC_SEC1VAL) { 718 flup |= IXGBE_EEC_FLUP; 719 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 720 } 721 722 status = ixgbe_poll_flash_update_done_X540(hw); 723 if (status == IXGBE_SUCCESS) 724 DEBUGOUT("Flash update complete\n"); 725 else 726 DEBUGOUT("Flash update time out\n"); 727 } 728 out: 729 return status; 730 } 731 732 /** 733 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 734 * @hw: pointer to hardware structure 735 * 736 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 737 * flash update is done. 738 **/ 739 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 740 { 741 u32 i; 742 u32 reg; 743 s32 status = IXGBE_ERR_EEPROM; 744 745 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 746 747 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 748 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 749 if (reg & IXGBE_EEC_FLUDONE) { 750 status = IXGBE_SUCCESS; 751 break; 752 } 753 msec_delay(5); 754 } 755 756 if (i == IXGBE_FLUDONE_ATTEMPTS) 757 ERROR_REPORT1(IXGBE_ERROR_POLLING, 758 "Flash update status polling timed out"); 759 760 return status; 761 } 762 763 /** 764 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 765 * @hw: pointer to hardware structure 766 * @mask: Mask to specify which semaphore to acquire 767 * 768 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 769 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 770 **/ 771 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 772 { 773 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; 774 u32 fwmask = swmask << 5; 775 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; 776 u32 timeout = 200; 777 u32 hwmask = 0; 778 u32 swfw_sync; 779 u32 i; 780 781 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 782 783 if (swmask & IXGBE_GSSR_EEP_SM) 784 hwmask |= IXGBE_GSSR_FLASH_SM; 785 786 /* SW only mask doesn't have FW bit pair */ 787 if (mask & IXGBE_GSSR_SW_MNG_SM) 788 swmask |= IXGBE_GSSR_SW_MNG_SM; 789 790 swmask |= swi2c_mask; 791 fwmask |= swi2c_mask << 2; 792 for (i = 0; i < timeout; i++) { 793 /* SW NVM semaphore bit is used for access to all 794 * SW_FW_SYNC bits (not just NVM) 795 */ 796 if (ixgbe_get_swfw_sync_semaphore(hw)) { 797 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n"); 798 return IXGBE_ERR_SWFW_SYNC; 799 } 800 801 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 802 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 803 swfw_sync |= swmask; 804 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), 805 swfw_sync); 806 ixgbe_release_swfw_sync_semaphore(hw); 807 return IXGBE_SUCCESS; 808 } 809 /* Firmware currently using resource (fwmask), hardware 810 * currently using resource (hwmask), or other software 811 * thread currently using resource (swmask) 812 */ 813 ixgbe_release_swfw_sync_semaphore(hw); 814 msec_delay(5); 815 } 816 817 /* If the resource is not released by the FW/HW the SW can assume that 818 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 819 * of the requested resource(s) while ignoring the corresponding FW/HW 820 * bits in the SW_FW_SYNC register. 821 */ 822 if (ixgbe_get_swfw_sync_semaphore(hw)) { 823 DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n"); 824 return IXGBE_ERR_SWFW_SYNC; 825 } 826 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 827 if (swfw_sync & (fwmask | hwmask)) { 828 swfw_sync |= swmask; 829 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 830 ixgbe_release_swfw_sync_semaphore(hw); 831 msec_delay(5); 832 return IXGBE_SUCCESS; 833 } 834 /* If the resource is not released by other SW the SW can assume that 835 * the other SW malfunctions. In that case the SW should clear all SW 836 * flags that it does not own and then repeat the whole process once 837 * again. 838 */ 839 if (swfw_sync & swmask) { 840 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 841 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 842 IXGBE_GSSR_SW_MNG_SM; 843 844 if (swi2c_mask) 845 rmask |= IXGBE_GSSR_I2C_MASK; 846 ixgbe_release_swfw_sync_X540(hw, rmask); 847 ixgbe_release_swfw_sync_semaphore(hw); 848 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n"); 849 return IXGBE_ERR_SWFW_SYNC; 850 } 851 ixgbe_release_swfw_sync_semaphore(hw); 852 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n"); 853 854 return IXGBE_ERR_SWFW_SYNC; 855 } 856 857 /** 858 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 859 * @hw: pointer to hardware structure 860 * @mask: Mask to specify which semaphore to release 861 * 862 * Releases the SWFW semaphore through the SW_FW_SYNC register 863 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 864 **/ 865 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 866 { 867 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); 868 u32 swfw_sync; 869 870 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 871 872 if (mask & IXGBE_GSSR_I2C_MASK) 873 swmask |= mask & IXGBE_GSSR_I2C_MASK; 874 ixgbe_get_swfw_sync_semaphore(hw); 875 876 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 877 swfw_sync &= ~swmask; 878 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 879 880 ixgbe_release_swfw_sync_semaphore(hw); 881 msec_delay(2); 882 } 883 884 /** 885 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 886 * @hw: pointer to hardware structure 887 * 888 * Sets the hardware semaphores so SW/FW can gain control of shared resources 889 **/ 890 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 891 { 892 s32 status = IXGBE_ERR_EEPROM; 893 u32 timeout = 2000; 894 u32 i; 895 u32 swsm; 896 897 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 898 899 /* Get SMBI software semaphore between device drivers first */ 900 for (i = 0; i < timeout; i++) { 901 /* 902 * If the SMBI bit is 0 when we read it, then the bit will be 903 * set and we have the semaphore 904 */ 905 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 906 if (!(swsm & IXGBE_SWSM_SMBI)) { 907 status = IXGBE_SUCCESS; 908 break; 909 } 910 usec_delay(50); 911 } 912 913 /* Now get the semaphore between SW/FW through the REGSMP bit */ 914 if (status == IXGBE_SUCCESS) { 915 for (i = 0; i < timeout; i++) { 916 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 917 if (!(swsm & IXGBE_SWFW_REGSMP)) 918 break; 919 920 usec_delay(50); 921 } 922 923 /* 924 * Release semaphores and return error if SW NVM semaphore 925 * was not granted because we don't have access to the EEPROM 926 */ 927 if (i >= timeout) { 928 ERROR_REPORT1(IXGBE_ERROR_POLLING, 929 "REGSMP Software NVM semaphore not granted.\n"); 930 ixgbe_release_swfw_sync_semaphore(hw); 931 status = IXGBE_ERR_EEPROM; 932 } 933 } else { 934 ERROR_REPORT1(IXGBE_ERROR_POLLING, 935 "Software semaphore SMBI between device drivers " 936 "not granted.\n"); 937 } 938 939 return status; 940 } 941 942 /** 943 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore 944 * @hw: pointer to hardware structure 945 * 946 * This function clears hardware semaphore bits. 947 **/ 948 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 949 { 950 u32 swsm; 951 952 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 953 954 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 955 956 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 957 swsm &= ~IXGBE_SWFW_REGSMP; 958 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); 959 960 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 961 swsm &= ~IXGBE_SWSM_SMBI; 962 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 963 964 IXGBE_WRITE_FLUSH(hw); 965 } 966 967 /** 968 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore 969 * @hw: pointer to hardware structure 970 * 971 * This function reset hardware semaphore bits for a semaphore that may 972 * have be left locked due to a catastrophic failure. 973 **/ 974 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw) 975 { 976 u32 rmask; 977 978 /* First try to grab the semaphore but we don't need to bother 979 * looking to see whether we got the lock or not since we do 980 * the same thing regardless of whether we got the lock or not. 981 * We got the lock - we release it. 982 * We timeout trying to get the lock - we force its release. 983 */ 984 ixgbe_get_swfw_sync_semaphore(hw); 985 ixgbe_release_swfw_sync_semaphore(hw); 986 987 /* Acquire and release all software resources. */ 988 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 989 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 990 IXGBE_GSSR_SW_MNG_SM; 991 992 rmask |= IXGBE_GSSR_I2C_MASK; 993 ixgbe_acquire_swfw_sync_X540(hw, rmask); 994 ixgbe_release_swfw_sync_X540(hw, rmask); 995 } 996 997 /** 998 * ixgbe_blink_led_start_X540 - Blink LED based on index. 999 * @hw: pointer to hardware structure 1000 * @index: led number to blink 1001 * 1002 * Devices that implement the version 2 interface: 1003 * X540 1004 **/ 1005 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 1006 { 1007 u32 macc_reg; 1008 u32 ledctl_reg; 1009 ixgbe_link_speed speed; 1010 bool link_up; 1011 1012 DEBUGFUNC("ixgbe_blink_led_start_X540"); 1013 1014 if (index > 3) 1015 return IXGBE_ERR_PARAM; 1016 1017 /* 1018 * Link should be up in order for the blink bit in the LED control 1019 * register to work. Force link and speed in the MAC if link is down. 1020 * This will be reversed when we stop the blinking. 1021 */ 1022 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1023 if (link_up == FALSE) { 1024 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1025 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 1026 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1027 } 1028 /* Set the LED to LINK_UP + BLINK. */ 1029 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1030 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1031 ledctl_reg |= IXGBE_LED_BLINK(index); 1032 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1033 IXGBE_WRITE_FLUSH(hw); 1034 1035 return IXGBE_SUCCESS; 1036 } 1037 1038 /** 1039 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 1040 * @hw: pointer to hardware structure 1041 * @index: led number to stop blinking 1042 * 1043 * Devices that implement the version 2 interface: 1044 * X540 1045 **/ 1046 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 1047 { 1048 u32 macc_reg; 1049 u32 ledctl_reg; 1050 1051 if (index > 3) 1052 return IXGBE_ERR_PARAM; 1053 1054 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 1055 1056 /* Restore the LED to its default value. */ 1057 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1058 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1059 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 1060 ledctl_reg &= ~IXGBE_LED_BLINK(index); 1061 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1062 1063 /* Unforce link and speed in the MAC. */ 1064 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1065 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 1066 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1067 IXGBE_WRITE_FLUSH(hw); 1068 1069 return IXGBE_SUCCESS; 1070 } 1071
Indexes created Mon Oct 20 20:10:13 GMT 2025