ixgbe_x540.c revision 1.16.16.1
1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2017, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 331224 2018-03-19 20:55:05Z erj $*/ 35 36 #include "ixgbe_x540.h" 37 #include "ixgbe_type.h" 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 42 #define IXGBE_X540_MAX_TX_QUEUES 128 43 #define IXGBE_X540_MAX_RX_QUEUES 128 44 #define IXGBE_X540_RAR_ENTRIES 128 45 #define IXGBE_X540_MC_TBL_SIZE 128 46 #define IXGBE_X540_VFT_TBL_SIZE 128 47 #define IXGBE_X540_RX_PB_SIZE 384 48 49 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 50 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 51 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 52 53 /** 54 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 55 * @hw: pointer to hardware structure 56 * 57 * Initialize the function pointers and assign the MAC type for X540. 58 * Does not touch the hardware. 59 **/ 60 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 61 { 62 struct ixgbe_mac_info *mac = &hw->mac; 63 struct ixgbe_phy_info *phy = &hw->phy; 64 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 65 s32 ret_val; 66 67 DEBUGFUNC("ixgbe_init_ops_X540"); 68 69 ret_val = ixgbe_init_phy_ops_generic(hw); 70 ret_val = ixgbe_init_ops_generic(hw); 71 72 73 /* EEPROM */ 74 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 75 eeprom->ops.read = ixgbe_read_eerd_X540; 76 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; 77 eeprom->ops.write = ixgbe_write_eewr_X540; 78 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540; 79 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540; 80 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540; 81 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540; 82 83 /* PHY */ 84 phy->ops.init = ixgbe_init_phy_ops_generic; 85 phy->ops.reset = NULL; 86 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; 87 88 /* MAC */ 89 mac->ops.reset_hw = ixgbe_reset_hw_X540; 90 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 91 mac->ops.get_media_type = ixgbe_get_media_type_X540; 92 mac->ops.get_supported_physical_layer = 93 ixgbe_get_supported_physical_layer_X540; 94 mac->ops.read_analog_reg8 = NULL; 95 mac->ops.write_analog_reg8 = NULL; 96 mac->ops.start_hw = ixgbe_start_hw_X540; 97 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 98 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 99 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 100 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 101 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 102 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; 103 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; 104 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540; 105 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 106 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 107 108 /* RAR, Multicast, VLAN */ 109 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 110 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 111 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 112 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 113 mac->rar_highwater = 1; 114 mac->ops.set_vfta = ixgbe_set_vfta_generic; 115 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 116 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 117 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 118 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 119 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 120 121 /* Link */ 122 mac->ops.get_link_capabilities = 123 ixgbe_get_copper_link_capabilities_generic; 124 mac->ops.setup_link = ixgbe_setup_mac_link_X540; 125 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 126 mac->ops.check_link = ixgbe_check_mac_link_generic; 127 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; 128 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; 129 mac->ops.bypass_set = ixgbe_bypass_set_generic; 130 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; 131 132 133 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 134 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 135 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 136 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 137 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 138 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 139 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 140 141 /* 142 * FWSM register 143 * ARC supported; valid only if manageability features are 144 * enabled. 145 */ 146 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 147 & IXGBE_FWSM_MODE_MASK); 148 149 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 150 151 /* LEDs */ 152 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 153 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 154 155 /* Manageability interface */ 156 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 157 158 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 159 160 return ret_val; 161 } 162 163 /** 164 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 165 * @hw: pointer to hardware structure 166 * @speed: pointer to link speed 167 * @autoneg: TRUE when autoneg or autotry is enabled 168 * 169 * Determines the link capabilities by reading the AUTOC register. 170 **/ 171 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 172 ixgbe_link_speed *speed, 173 bool *autoneg) 174 { 175 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 176 177 return IXGBE_SUCCESS; 178 } 179 180 /** 181 * ixgbe_get_media_type_X540 - Get media type 182 * @hw: pointer to hardware structure 183 * 184 * Returns the media type (fiber, copper, backplane) 185 **/ 186 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 187 { 188 UNREFERENCED_1PARAMETER(hw); 189 return ixgbe_media_type_copper; 190 } 191 192 /** 193 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 194 * @hw: pointer to hardware structure 195 * @speed: new link speed 196 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 197 **/ 198 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 199 ixgbe_link_speed speed, 200 bool autoneg_wait_to_complete) 201 { 202 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 203 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 204 } 205 206 /** 207 * ixgbe_reset_hw_X540 - Perform hardware reset 208 * @hw: pointer to hardware structure 209 * 210 * Resets the hardware by resetting the transmit and receive units, masks 211 * and clears all interrupts, and perform a reset. 212 **/ 213 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 214 { 215 s32 status; 216 u32 ctrl, i; 217 u32 swfw_mask = hw->phy.phy_semaphore_mask; 218 219 DEBUGFUNC("ixgbe_reset_hw_X540"); 220 221 /* Call adapter stop to disable tx/rx and clear interrupts */ 222 status = hw->mac.ops.stop_adapter(hw); 223 if (status != IXGBE_SUCCESS) 224 goto reset_hw_out; 225 226 /* flush pending Tx transactions */ 227 ixgbe_clear_tx_pending(hw); 228 229 mac_reset_top: 230 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 231 if (status != IXGBE_SUCCESS) { 232 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 233 "semaphore failed with %d", status); 234 return IXGBE_ERR_SWFW_SYNC; 235 } 236 ctrl = IXGBE_CTRL_RST; 237 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 238 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 239 IXGBE_WRITE_FLUSH(hw); 240 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 241 242 /* Poll for reset bit to self-clear indicating reset is complete */ 243 for (i = 0; i < 10; i++) { 244 usec_delay(1); 245 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 246 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 247 break; 248 } 249 250 if (ctrl & IXGBE_CTRL_RST_MASK) { 251 status = IXGBE_ERR_RESET_FAILED; 252 ERROR_REPORT1(IXGBE_ERROR_POLLING, 253 "Reset polling failed to complete.\n"); 254 } 255 msec_delay(100); 256 257 /* 258 * Double resets are required for recovery from certain error 259 * conditions. Between resets, it is necessary to stall to allow time 260 * for any pending HW events to complete. 261 */ 262 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 263 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 264 goto mac_reset_top; 265 } 266 267 /* Set the Rx packet buffer size. */ 268 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 269 270 /* Store the permanent mac address */ 271 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 272 273 /* 274 * Store MAC address from RAR0, clear receive address registers, and 275 * clear the multicast table. Also reset num_rar_entries to 128, 276 * since we modify this value when programming the SAN MAC address. 277 */ 278 hw->mac.num_rar_entries = 128; 279 hw->mac.ops.init_rx_addrs(hw); 280 281 /* Store the permanent SAN mac address */ 282 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 283 284 /* Add the SAN MAC address to the RAR only if it's a valid address */ 285 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 286 /* Save the SAN MAC RAR index */ 287 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 288 289 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 290 hw->mac.san_addr, 0, IXGBE_RAH_AV); 291 292 /* clear VMDq pool/queue selection for this RAR */ 293 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 294 IXGBE_CLEAR_VMDQ_ALL); 295 296 /* Reserve the last RAR for the SAN MAC address */ 297 hw->mac.num_rar_entries--; 298 } 299 300 /* Store the alternative WWNN/WWPN prefix */ 301 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 302 &hw->mac.wwpn_prefix); 303 304 reset_hw_out: 305 return status; 306 } 307 308 /** 309 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 310 * @hw: pointer to hardware structure 311 * 312 * Starts the hardware using the generic start_hw function 313 * and the generation start_hw function. 314 * Then performs revision-specific operations, if any. 315 **/ 316 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 317 { 318 s32 ret_val = IXGBE_SUCCESS; 319 320 DEBUGFUNC("ixgbe_start_hw_X540"); 321 322 ret_val = ixgbe_start_hw_generic(hw); 323 if (ret_val != IXGBE_SUCCESS) 324 goto out; 325 326 ret_val = ixgbe_start_hw_gen2(hw); 327 328 out: 329 return ret_val; 330 } 331 332 /** 333 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 334 * @hw: pointer to hardware structure 335 * 336 * Determines physical layer capabilities of the current configuration. 337 **/ 338 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 339 { 340 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 341 u16 ext_ability = 0; 342 343 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 344 345 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 346 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 347 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 348 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 349 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 350 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 351 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 352 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 353 354 if (hw->mac.type == ixgbe_mac_X550) { 355 physical_layer |= IXGBE_PHYSICAL_LAYER_2500BASE_T 356 | IXGBE_PHYSICAL_LAYER_5GBASE_T; 357 } 358 359 return physical_layer; 360 } 361 362 /** 363 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 364 * @hw: pointer to hardware structure 365 * 366 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 367 * ixgbe_hw struct in order to set up EEPROM access. 368 **/ 369 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 370 { 371 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 372 u32 eec; 373 u16 eeprom_size; 374 375 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 376 377 if (eeprom->type == ixgbe_eeprom_uninitialized) { 378 eeprom->semaphore_delay = 10; 379 eeprom->type = ixgbe_flash; 380 381 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 382 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 383 IXGBE_EEC_SIZE_SHIFT); 384 eeprom->word_size = 1 << (eeprom_size + 385 IXGBE_EEPROM_WORD_SIZE_SHIFT); 386 387 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 388 eeprom->type, eeprom->word_size); 389 } 390 391 return IXGBE_SUCCESS; 392 } 393 394 /** 395 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 396 * @hw: pointer to hardware structure 397 * @offset: offset of word in the EEPROM to read 398 * @data: word read from the EEPROM 399 * 400 * Reads a 16 bit word from the EEPROM using the EERD register. 401 **/ 402 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 403 { 404 s32 status = IXGBE_SUCCESS; 405 406 DEBUGFUNC("ixgbe_read_eerd_X540"); 407 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 408 IXGBE_SUCCESS) { 409 status = ixgbe_read_eerd_generic(hw, offset, data); 410 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 411 } else { 412 status = IXGBE_ERR_SWFW_SYNC; 413 } 414 415 return status; 416 } 417 418 /** 419 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 420 * @hw: pointer to hardware structure 421 * @offset: offset of word in the EEPROM to read 422 * @words: number of words 423 * @data: word(s) read from the EEPROM 424 * 425 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 426 **/ 427 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 428 u16 offset, u16 words, u16 *data) 429 { 430 s32 status = IXGBE_SUCCESS; 431 432 DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 433 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 434 IXGBE_SUCCESS) { 435 status = ixgbe_read_eerd_buffer_generic(hw, offset, 436 words, data); 437 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 438 } else { 439 status = IXGBE_ERR_SWFW_SYNC; 440 } 441 442 return status; 443 } 444 445 /** 446 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 447 * @hw: pointer to hardware structure 448 * @offset: offset of word in the EEPROM to write 449 * @data: word write to the EEPROM 450 * 451 * Write a 16 bit word to the EEPROM using the EEWR register. 452 **/ 453 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 454 { 455 s32 status = IXGBE_SUCCESS; 456 457 DEBUGFUNC("ixgbe_write_eewr_X540"); 458 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 459 IXGBE_SUCCESS) { 460 status = ixgbe_write_eewr_generic(hw, offset, data); 461 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 462 } else { 463 status = IXGBE_ERR_SWFW_SYNC; 464 } 465 466 return status; 467 } 468 469 /** 470 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 471 * @hw: pointer to hardware structure 472 * @offset: offset of word in the EEPROM to write 473 * @words: number of words 474 * @data: word(s) write to the EEPROM 475 * 476 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 477 **/ 478 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 479 u16 offset, u16 words, u16 *data) 480 { 481 s32 status = IXGBE_SUCCESS; 482 483 DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 484 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 485 IXGBE_SUCCESS) { 486 status = ixgbe_write_eewr_buffer_generic(hw, offset, 487 words, data); 488 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 489 } else { 490 status = IXGBE_ERR_SWFW_SYNC; 491 } 492 493 return status; 494 } 495 496 /** 497 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 498 * 499 * This function does not use synchronization for EERD and EEWR. It can 500 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 501 * 502 * @hw: pointer to hardware structure 503 * 504 * Returns a negative error code on error, or the 16-bit checksum 505 **/ 506 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 507 { 508 u16 i, j; 509 u16 checksum = 0; 510 u16 length = 0; 511 u16 pointer = 0; 512 u16 word = 0; 513 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 514 515 /* Do not use hw->eeprom.ops.read because we do not want to take 516 * the synchronization semaphores here. Instead use 517 * ixgbe_read_eerd_generic 518 */ 519 520 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 521 522 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the 523 * checksum itself 524 */ 525 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 526 if (ixgbe_read_eerd_generic(hw, i, &word)) { 527 DEBUGOUT("EEPROM read failed\n"); 528 return IXGBE_ERR_EEPROM; 529 } 530 checksum += word; 531 } 532 533 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 534 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 535 */ 536 for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 537 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 538 continue; 539 540 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 541 DEBUGOUT("EEPROM read failed\n"); 542 return IXGBE_ERR_EEPROM; 543 } 544 545 /* Skip pointer section if the pointer is invalid. */ 546 if (pointer == 0xFFFF || pointer == 0 || 547 pointer >= hw->eeprom.word_size) 548 continue; 549 550 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 551 DEBUGOUT("EEPROM read failed\n"); 552 return IXGBE_ERR_EEPROM; 553 } 554 555 /* Skip pointer section if length is invalid. */ 556 if (length == 0xFFFF || length == 0 || 557 (pointer + length) >= hw->eeprom.word_size) 558 continue; 559 560 for (j = pointer + 1; j <= pointer + length; j++) { 561 if (ixgbe_read_eerd_generic(hw, j, &word)) { 562 DEBUGOUT("EEPROM read failed\n"); 563 return IXGBE_ERR_EEPROM; 564 } 565 checksum += word; 566 } 567 } 568 569 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 570 571 return (s32)checksum; 572 } 573 574 /** 575 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 576 * @hw: pointer to hardware structure 577 * @checksum_val: calculated checksum 578 * 579 * Performs checksum calculation and validates the EEPROM checksum. If the 580 * caller does not need checksum_val, the value can be NULL. 581 **/ 582 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 583 u16 *checksum_val) 584 { 585 s32 status; 586 u16 checksum; 587 u16 read_checksum = 0; 588 589 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 590 591 /* Read the first word from the EEPROM. If this times out or fails, do 592 * not continue or we could be in for a very long wait while every 593 * EEPROM read fails 594 */ 595 status = hw->eeprom.ops.read(hw, 0, &checksum); 596 if (status) { 597 DEBUGOUT("EEPROM read failed\n"); 598 return status; 599 } 600 601 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 602 return IXGBE_ERR_SWFW_SYNC; 603 604 status = hw->eeprom.ops.calc_checksum(hw); 605 if (status < 0) 606 goto out; 607 608 checksum = (u16)(status & 0xffff); 609 610 /* Do not use hw->eeprom.ops.read because we do not want to take 611 * the synchronization semaphores twice here. 612 */ 613 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 614 &read_checksum); 615 if (status) 616 goto out; 617 618 /* Verify read checksum from EEPROM is the same as 619 * calculated checksum 620 */ 621 if (read_checksum != checksum) { 622 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 623 "Invalid EEPROM checksum"); 624 status = IXGBE_ERR_EEPROM_CHECKSUM; 625 } 626 627 /* If the user cares, return the calculated checksum */ 628 if (checksum_val) 629 *checksum_val = checksum; 630 631 out: 632 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 633 634 return status; 635 } 636 637 /** 638 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 639 * @hw: pointer to hardware structure 640 * 641 * After writing EEPROM to shadow RAM using EEWR register, software calculates 642 * checksum and updates the EEPROM and instructs the hardware to update 643 * the flash. 644 **/ 645 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 646 { 647 s32 status; 648 u16 checksum; 649 650 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 651 652 /* Read the first word from the EEPROM. If this times out or fails, do 653 * not continue or we could be in for a very long wait while every 654 * EEPROM read fails 655 */ 656 status = hw->eeprom.ops.read(hw, 0, &checksum); 657 if (status) { 658 DEBUGOUT("EEPROM read failed\n"); 659 return status; 660 } 661 662 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 663 return IXGBE_ERR_SWFW_SYNC; 664 665 status = hw->eeprom.ops.calc_checksum(hw); 666 if (status < 0) 667 goto out; 668 669 checksum = (u16)(status & 0xffff); 670 671 /* Do not use hw->eeprom.ops.write because we do not want to 672 * take the synchronization semaphores twice here. 673 */ 674 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 675 if (status) 676 goto out; 677 678 status = ixgbe_update_flash_X540(hw); 679 680 out: 681 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 682 683 return status; 684 } 685 686 /** 687 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 688 * @hw: pointer to hardware structure 689 * 690 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 691 * EEPROM from shadow RAM to the flash device. 692 **/ 693 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 694 { 695 u32 flup; 696 s32 status; 697 698 DEBUGFUNC("ixgbe_update_flash_X540"); 699 700 status = ixgbe_poll_flash_update_done_X540(hw); 701 if (status == IXGBE_ERR_EEPROM) { 702 DEBUGOUT("Flash update time out\n"); 703 goto out; 704 } 705 706 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP; 707 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 708 709 status = ixgbe_poll_flash_update_done_X540(hw); 710 if (status == IXGBE_SUCCESS) 711 DEBUGOUT("Flash update complete\n"); 712 else 713 DEBUGOUT("Flash update time out\n"); 714 715 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 716 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 717 718 if (flup & IXGBE_EEC_SEC1VAL) { 719 flup |= IXGBE_EEC_FLUP; 720 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 721 } 722 723 status = ixgbe_poll_flash_update_done_X540(hw); 724 if (status == IXGBE_SUCCESS) 725 DEBUGOUT("Flash update complete\n"); 726 else 727 DEBUGOUT("Flash update time out\n"); 728 } 729 out: 730 return status; 731 } 732 733 /** 734 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 735 * @hw: pointer to hardware structure 736 * 737 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 738 * flash update is done. 739 **/ 740 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 741 { 742 u32 i; 743 u32 reg; 744 s32 status = IXGBE_ERR_EEPROM; 745 746 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 747 748 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 749 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 750 if (reg & IXGBE_EEC_FLUDONE) { 751 status = IXGBE_SUCCESS; 752 break; 753 } 754 msec_delay(5); 755 } 756 757 if (i == IXGBE_FLUDONE_ATTEMPTS) 758 ERROR_REPORT1(IXGBE_ERROR_POLLING, 759 "Flash update status polling timed out"); 760 761 return status; 762 } 763 764 /** 765 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 766 * @hw: pointer to hardware structure 767 * @mask: Mask to specify which semaphore to acquire 768 * 769 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 770 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 771 **/ 772 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 773 { 774 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; 775 u32 fwmask = swmask << 5; 776 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; 777 u32 timeout = 200; 778 u32 hwmask = 0; 779 u32 swfw_sync; 780 u32 i; 781 782 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 783 784 if (swmask & IXGBE_GSSR_EEP_SM) 785 hwmask |= IXGBE_GSSR_FLASH_SM; 786 787 /* SW only mask doesn't have FW bit pair */ 788 if (mask & IXGBE_GSSR_SW_MNG_SM) 789 swmask |= IXGBE_GSSR_SW_MNG_SM; 790 791 swmask |= swi2c_mask; 792 fwmask |= swi2c_mask << 2; 793 if (hw->mac.type >= ixgbe_mac_X550) 794 timeout = 1000; 795 796 for (i = 0; i < timeout; i++) { 797 /* SW NVM semaphore bit is used for access to all 798 * SW_FW_SYNC bits (not just NVM) 799 */ 800 if (ixgbe_get_swfw_sync_semaphore(hw)) { 801 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n"); 802 return IXGBE_ERR_SWFW_SYNC; 803 } 804 805 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 806 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 807 swfw_sync |= swmask; 808 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), 809 swfw_sync); 810 ixgbe_release_swfw_sync_semaphore(hw); 811 return IXGBE_SUCCESS; 812 } 813 /* Firmware currently using resource (fwmask), hardware 814 * currently using resource (hwmask), or other software 815 * thread currently using resource (swmask) 816 */ 817 ixgbe_release_swfw_sync_semaphore(hw); 818 msec_delay(5); 819 } 820 821 /* If the resource is not released by the FW/HW the SW can assume that 822 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 823 * of the requested resource(s) while ignoring the corresponding FW/HW 824 * bits in the SW_FW_SYNC register. 825 */ 826 if (ixgbe_get_swfw_sync_semaphore(hw)) { 827 DEBUGOUT("Failed to get NVM semaphore and register semaphore while forcefully ignoring FW semaphore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n"); 828 return IXGBE_ERR_SWFW_SYNC; 829 } 830 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 831 if (swfw_sync & (fwmask | hwmask)) { 832 swfw_sync |= swmask; 833 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 834 ixgbe_release_swfw_sync_semaphore(hw); 835 msec_delay(5); 836 return IXGBE_SUCCESS; 837 } 838 /* If the resource is not released by other SW the SW can assume that 839 * the other SW malfunctions. In that case the SW should clear all SW 840 * flags that it does not own and then repeat the whole process once 841 * again. 842 */ 843 if (swfw_sync & swmask) { 844 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 845 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 846 IXGBE_GSSR_SW_MNG_SM; 847 848 if (swi2c_mask) 849 rmask |= IXGBE_GSSR_I2C_MASK; 850 ixgbe_release_swfw_sync_X540(hw, rmask); 851 ixgbe_release_swfw_sync_semaphore(hw); 852 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n"); 853 return IXGBE_ERR_SWFW_SYNC; 854 } 855 ixgbe_release_swfw_sync_semaphore(hw); 856 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n"); 857 858 return IXGBE_ERR_SWFW_SYNC; 859 } 860 861 /** 862 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 863 * @hw: pointer to hardware structure 864 * @mask: Mask to specify which semaphore to release 865 * 866 * Releases the SWFW semaphore through the SW_FW_SYNC register 867 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 868 **/ 869 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 870 { 871 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); 872 u32 swfw_sync; 873 874 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 875 876 if (mask & IXGBE_GSSR_I2C_MASK) 877 swmask |= mask & IXGBE_GSSR_I2C_MASK; 878 ixgbe_get_swfw_sync_semaphore(hw); 879 880 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 881 swfw_sync &= ~swmask; 882 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 883 884 ixgbe_release_swfw_sync_semaphore(hw); 885 msec_delay(2); 886 } 887 888 /** 889 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 890 * @hw: pointer to hardware structure 891 * 892 * Sets the hardware semaphores so SW/FW can gain control of shared resources 893 **/ 894 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 895 { 896 s32 status = IXGBE_ERR_EEPROM; 897 u32 timeout = 2000; 898 u32 i; 899 u32 swsm; 900 901 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 902 903 /* Get SMBI software semaphore between device drivers first */ 904 for (i = 0; i < timeout; i++) { 905 /* 906 * If the SMBI bit is 0 when we read it, then the bit will be 907 * set and we have the semaphore 908 */ 909 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 910 if (!(swsm & IXGBE_SWSM_SMBI)) { 911 status = IXGBE_SUCCESS; 912 break; 913 } 914 usec_delay(50); 915 } 916 917 /* Now get the semaphore between SW/FW through the REGSMP bit */ 918 if (status == IXGBE_SUCCESS) { 919 for (i = 0; i < timeout; i++) { 920 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 921 if (!(swsm & IXGBE_SWFW_REGSMP)) 922 break; 923 924 usec_delay(50); 925 } 926 927 /* 928 * Release semaphores and return error if SW NVM semaphore 929 * was not granted because we don't have access to the EEPROM 930 */ 931 if (i >= timeout) { 932 ERROR_REPORT1(IXGBE_ERROR_POLLING, 933 "REGSMP Software NVM semaphore not granted.\n"); 934 ixgbe_release_swfw_sync_semaphore(hw); 935 status = IXGBE_ERR_EEPROM; 936 } 937 } else { 938 ERROR_REPORT1(IXGBE_ERROR_POLLING, 939 "Software semaphore SMBI between device drivers " 940 "not granted.\n"); 941 } 942 943 return status; 944 } 945 946 /** 947 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore 948 * @hw: pointer to hardware structure 949 * 950 * This function clears hardware semaphore bits. 951 **/ 952 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 953 { 954 u32 swsm; 955 956 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 957 958 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 959 960 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 961 swsm &= ~IXGBE_SWFW_REGSMP; 962 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); 963 964 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 965 swsm &= ~IXGBE_SWSM_SMBI; 966 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 967 968 IXGBE_WRITE_FLUSH(hw); 969 } 970 971 /** 972 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore 973 * @hw: pointer to hardware structure 974 * 975 * This function reset hardware semaphore bits for a semaphore that may 976 * have be left locked due to a catastrophic failure. 977 **/ 978 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw) 979 { 980 u32 rmask; 981 982 /* First try to grab the semaphore but we don't need to bother 983 * looking to see whether we got the lock or not since we do 984 * the same thing regardless of whether we got the lock or not. 985 * We got the lock - we release it. 986 * We timeout trying to get the lock - we force its release. 987 */ 988 ixgbe_get_swfw_sync_semaphore(hw); 989 ixgbe_release_swfw_sync_semaphore(hw); 990 991 /* Acquire and release all software resources. */ 992 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 993 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 994 IXGBE_GSSR_SW_MNG_SM; 995 996 rmask |= IXGBE_GSSR_I2C_MASK; 997 ixgbe_acquire_swfw_sync_X540(hw, rmask); 998 ixgbe_release_swfw_sync_X540(hw, rmask); 999 } 1000 1001 /** 1002 * ixgbe_blink_led_start_X540 - Blink LED based on index. 1003 * @hw: pointer to hardware structure 1004 * @index: led number to blink 1005 * 1006 * Devices that implement the version 2 interface: 1007 * X540 1008 **/ 1009 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 1010 { 1011 u32 macc_reg; 1012 u32 ledctl_reg; 1013 ixgbe_link_speed speed; 1014 bool link_up; 1015 1016 DEBUGFUNC("ixgbe_blink_led_start_X540"); 1017 1018 if (index > 3) 1019 return IXGBE_ERR_PARAM; 1020 1021 /* 1022 * Link should be up in order for the blink bit in the LED control 1023 * register to work. Force link and speed in the MAC if link is down. 1024 * This will be reversed when we stop the blinking. 1025 */ 1026 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1027 if (link_up == FALSE) { 1028 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1029 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 1030 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1031 } 1032 /* Set the LED to LINK_UP + BLINK. */ 1033 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1034 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1035 ledctl_reg |= IXGBE_LED_BLINK(index); 1036 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1037 IXGBE_WRITE_FLUSH(hw); 1038 1039 return IXGBE_SUCCESS; 1040 } 1041 1042 /** 1043 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 1044 * @hw: pointer to hardware structure 1045 * @index: led number to stop blinking 1046 * 1047 * Devices that implement the version 2 interface: 1048 * X540 1049 **/ 1050 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 1051 { 1052 u32 macc_reg; 1053 u32 ledctl_reg; 1054 1055 if (index > 3) 1056 return IXGBE_ERR_PARAM; 1057 1058 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 1059 1060 /* Restore the LED to its default value. */ 1061 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1062 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1063 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 1064 ledctl_reg &= ~IXGBE_LED_BLINK(index); 1065 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1066 1067 /* Unforce link and speed in the MAC. */ 1068 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1069 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 1070 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1071 IXGBE_WRITE_FLUSH(hw); 1072 1073 return IXGBE_SUCCESS; 1074 } 1075
Indexes created Sun Oct 19 02:09:48 GMT 2025