ixgbe_x540.c revision 1.17.4.1
1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2017, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 331224 2018-03-19 20:55:05Z erj $*/ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: ixgbe_x540.c,v 1.17.4.1 2021/05/13 00:47:31 thorpej Exp $"); 38 39 #include "ixgbe_x540.h" 40 #include "ixgbe_type.h" 41 #include "ixgbe_api.h" 42 #include "ixgbe_common.h" 43 #include "ixgbe_phy.h" 44 45 #define IXGBE_X540_MAX_TX_QUEUES 128 46 #define IXGBE_X540_MAX_RX_QUEUES 128 47 #define IXGBE_X540_RAR_ENTRIES 128 48 #define IXGBE_X540_MC_TBL_SIZE 128 49 #define IXGBE_X540_VFT_TBL_SIZE 128 50 #define IXGBE_X540_RX_PB_SIZE 384 51 52 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 53 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 54 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 55 56 /** 57 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 58 * @hw: pointer to hardware structure 59 * 60 * Initialize the function pointers and assign the MAC type for X540. 61 * Does not touch the hardware. 62 **/ 63 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 64 { 65 struct ixgbe_mac_info *mac = &hw->mac; 66 struct ixgbe_phy_info *phy = &hw->phy; 67 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 68 s32 ret_val; 69 70 DEBUGFUNC("ixgbe_init_ops_X540"); 71 72 ret_val = ixgbe_init_phy_ops_generic(hw); 73 ret_val = ixgbe_init_ops_generic(hw); 74 75 76 /* EEPROM */ 77 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 78 eeprom->ops.read = ixgbe_read_eerd_X540; 79 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; 80 eeprom->ops.write = ixgbe_write_eewr_X540; 81 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540; 82 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540; 83 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540; 84 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540; 85 86 /* PHY */ 87 phy->ops.init = ixgbe_init_phy_ops_generic; 88 phy->ops.reset = NULL; 89 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; 90 91 /* MAC */ 92 mac->ops.reset_hw = ixgbe_reset_hw_X540; 93 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 94 mac->ops.get_media_type = ixgbe_get_media_type_X540; 95 mac->ops.get_supported_physical_layer = 96 ixgbe_get_supported_physical_layer_X540; 97 mac->ops.read_analog_reg8 = NULL; 98 mac->ops.write_analog_reg8 = NULL; 99 mac->ops.start_hw = ixgbe_start_hw_X540; 100 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 101 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 102 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 103 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 104 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 105 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; 106 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; 107 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540; 108 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 109 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 110 111 /* RAR, Multicast, VLAN */ 112 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 113 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 114 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 115 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 116 mac->rar_highwater = 1; 117 mac->ops.set_vfta = ixgbe_set_vfta_generic; 118 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 119 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 120 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 121 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 122 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 123 124 /* Link */ 125 mac->ops.get_link_capabilities = 126 ixgbe_get_copper_link_capabilities_generic; 127 mac->ops.setup_link = ixgbe_setup_mac_link_X540; 128 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 129 mac->ops.check_link = ixgbe_check_mac_link_generic; 130 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; 131 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; 132 mac->ops.bypass_set = ixgbe_bypass_set_generic; 133 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; 134 135 136 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 137 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 138 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 139 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 140 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 141 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 142 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 143 144 /* 145 * FWSM register 146 * ARC supported; valid only if manageability features are 147 * enabled. 148 */ 149 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 150 & IXGBE_FWSM_MODE_MASK); 151 152 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 153 154 /* LEDs */ 155 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 156 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 157 158 /* Manageability interface */ 159 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 160 161 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 162 163 return ret_val; 164 } 165 166 /** 167 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 168 * @hw: pointer to hardware structure 169 * @speed: pointer to link speed 170 * @autoneg: TRUE when autoneg or autotry is enabled 171 * 172 * Determines the link capabilities by reading the AUTOC register. 173 **/ 174 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 175 ixgbe_link_speed *speed, 176 bool *autoneg) 177 { 178 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 179 180 return IXGBE_SUCCESS; 181 } 182 183 /** 184 * ixgbe_get_media_type_X540 - Get media type 185 * @hw: pointer to hardware structure 186 * 187 * Returns the media type (fiber, copper, backplane) 188 **/ 189 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 190 { 191 UNREFERENCED_1PARAMETER(hw); 192 return ixgbe_media_type_copper; 193 } 194 195 /** 196 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 197 * @hw: pointer to hardware structure 198 * @speed: new link speed 199 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 200 **/ 201 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 202 ixgbe_link_speed speed, 203 bool autoneg_wait_to_complete) 204 { 205 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 206 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 207 } 208 209 /** 210 * ixgbe_reset_hw_X540 - Perform hardware reset 211 * @hw: pointer to hardware structure 212 * 213 * Resets the hardware by resetting the transmit and receive units, masks 214 * and clears all interrupts, and perform a reset. 215 **/ 216 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 217 { 218 s32 status; 219 u32 ctrl, i; 220 u32 swfw_mask = hw->phy.phy_semaphore_mask; 221 222 DEBUGFUNC("ixgbe_reset_hw_X540"); 223 224 /* Call adapter stop to disable tx/rx and clear interrupts */ 225 status = hw->mac.ops.stop_adapter(hw); 226 if (status != IXGBE_SUCCESS) 227 goto reset_hw_out; 228 229 /* flush pending Tx transactions */ 230 ixgbe_clear_tx_pending(hw); 231 232 mac_reset_top: 233 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 234 if (status != IXGBE_SUCCESS) { 235 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 236 "semaphore failed with %d", status); 237 return IXGBE_ERR_SWFW_SYNC; 238 } 239 ctrl = IXGBE_CTRL_RST; 240 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 241 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 242 IXGBE_WRITE_FLUSH(hw); 243 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 244 245 /* Poll for reset bit to self-clear indicating reset is complete */ 246 for (i = 0; i < 10; i++) { 247 usec_delay(1); 248 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 249 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 250 break; 251 } 252 253 if (ctrl & IXGBE_CTRL_RST_MASK) { 254 status = IXGBE_ERR_RESET_FAILED; 255 ERROR_REPORT1(IXGBE_ERROR_POLLING, 256 "Reset polling failed to complete.\n"); 257 } 258 msec_delay(100); 259 260 /* 261 * Double resets are required for recovery from certain error 262 * conditions. Between resets, it is necessary to stall to allow time 263 * for any pending HW events to complete. 264 */ 265 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 266 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 267 goto mac_reset_top; 268 } 269 270 /* Set the Rx packet buffer size. */ 271 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 272 273 /* Store the permanent mac address */ 274 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 275 276 /* 277 * Store MAC address from RAR0, clear receive address registers, and 278 * clear the multicast table. Also reset num_rar_entries to 128, 279 * since we modify this value when programming the SAN MAC address. 280 */ 281 hw->mac.num_rar_entries = 128; 282 hw->mac.ops.init_rx_addrs(hw); 283 284 /* Store the permanent SAN mac address */ 285 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 286 287 /* Add the SAN MAC address to the RAR only if it's a valid address */ 288 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 289 /* Save the SAN MAC RAR index */ 290 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 291 292 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 293 hw->mac.san_addr, 0, IXGBE_RAH_AV); 294 295 /* clear VMDq pool/queue selection for this RAR */ 296 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 297 IXGBE_CLEAR_VMDQ_ALL); 298 299 /* Reserve the last RAR for the SAN MAC address */ 300 hw->mac.num_rar_entries--; 301 } 302 303 /* Store the alternative WWNN/WWPN prefix */ 304 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 305 &hw->mac.wwpn_prefix); 306 307 reset_hw_out: 308 return status; 309 } 310 311 /** 312 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 313 * @hw: pointer to hardware structure 314 * 315 * Starts the hardware using the generic start_hw function 316 * and the generation start_hw function. 317 * Then performs revision-specific operations, if any. 318 **/ 319 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 320 { 321 s32 ret_val = IXGBE_SUCCESS; 322 323 DEBUGFUNC("ixgbe_start_hw_X540"); 324 325 ret_val = ixgbe_start_hw_generic(hw); 326 if (ret_val != IXGBE_SUCCESS) 327 goto out; 328 329 ret_val = ixgbe_start_hw_gen2(hw); 330 331 out: 332 return ret_val; 333 } 334 335 /** 336 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 337 * @hw: pointer to hardware structure 338 * 339 * Determines physical layer capabilities of the current configuration. 340 **/ 341 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 342 { 343 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 344 u16 ext_ability = 0; 345 346 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 347 348 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 349 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 350 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 351 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 352 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 353 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 354 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 355 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 356 357 if (hw->mac.type == ixgbe_mac_X550) { 358 physical_layer |= IXGBE_PHYSICAL_LAYER_2500BASE_T 359 | IXGBE_PHYSICAL_LAYER_5GBASE_T; 360 } 361 362 return physical_layer; 363 } 364 365 /** 366 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 367 * @hw: pointer to hardware structure 368 * 369 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 370 * ixgbe_hw struct in order to set up EEPROM access. 371 **/ 372 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 373 { 374 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 375 u32 eec; 376 u16 eeprom_size; 377 378 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 379 380 if (eeprom->type == ixgbe_eeprom_uninitialized) { 381 eeprom->semaphore_delay = 10; 382 eeprom->type = ixgbe_flash; 383 384 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 385 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 386 IXGBE_EEC_SIZE_SHIFT); 387 eeprom->word_size = 1 << (eeprom_size + 388 IXGBE_EEPROM_WORD_SIZE_SHIFT); 389 390 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 391 eeprom->type, eeprom->word_size); 392 } 393 394 return IXGBE_SUCCESS; 395 } 396 397 /** 398 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 399 * @hw: pointer to hardware structure 400 * @offset: offset of word in the EEPROM to read 401 * @data: word read from the EEPROM 402 * 403 * Reads a 16 bit word from the EEPROM using the EERD register. 404 **/ 405 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 406 { 407 s32 status = IXGBE_SUCCESS; 408 409 DEBUGFUNC("ixgbe_read_eerd_X540"); 410 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 411 IXGBE_SUCCESS) { 412 status = ixgbe_read_eerd_generic(hw, offset, data); 413 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 414 } else { 415 status = IXGBE_ERR_SWFW_SYNC; 416 } 417 418 return status; 419 } 420 421 /** 422 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 423 * @hw: pointer to hardware structure 424 * @offset: offset of word in the EEPROM to read 425 * @words: number of words 426 * @data: word(s) read from the EEPROM 427 * 428 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 429 **/ 430 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 431 u16 offset, u16 words, u16 *data) 432 { 433 s32 status = IXGBE_SUCCESS; 434 435 DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 436 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 437 IXGBE_SUCCESS) { 438 status = ixgbe_read_eerd_buffer_generic(hw, offset, 439 words, data); 440 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 441 } else { 442 status = IXGBE_ERR_SWFW_SYNC; 443 } 444 445 return status; 446 } 447 448 /** 449 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 450 * @hw: pointer to hardware structure 451 * @offset: offset of word in the EEPROM to write 452 * @data: word write to the EEPROM 453 * 454 * Write a 16 bit word to the EEPROM using the EEWR register. 455 **/ 456 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 457 { 458 s32 status = IXGBE_SUCCESS; 459 460 DEBUGFUNC("ixgbe_write_eewr_X540"); 461 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 462 IXGBE_SUCCESS) { 463 status = ixgbe_write_eewr_generic(hw, offset, data); 464 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 465 } else { 466 status = IXGBE_ERR_SWFW_SYNC; 467 } 468 469 return status; 470 } 471 472 /** 473 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 474 * @hw: pointer to hardware structure 475 * @offset: offset of word in the EEPROM to write 476 * @words: number of words 477 * @data: word(s) write to the EEPROM 478 * 479 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 480 **/ 481 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 482 u16 offset, u16 words, u16 *data) 483 { 484 s32 status = IXGBE_SUCCESS; 485 486 DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 487 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 488 IXGBE_SUCCESS) { 489 status = ixgbe_write_eewr_buffer_generic(hw, offset, 490 words, data); 491 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 492 } else { 493 status = IXGBE_ERR_SWFW_SYNC; 494 } 495 496 return status; 497 } 498 499 /** 500 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 501 * 502 * This function does not use synchronization for EERD and EEWR. It can 503 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 504 * 505 * @hw: pointer to hardware structure 506 * 507 * Returns a negative error code on error, or the 16-bit checksum 508 **/ 509 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 510 { 511 u16 i, j; 512 u16 checksum = 0; 513 u16 length = 0; 514 u16 pointer = 0; 515 u16 word = 0; 516 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 517 518 /* Do not use hw->eeprom.ops.read because we do not want to take 519 * the synchronization semaphores here. Instead use 520 * ixgbe_read_eerd_generic 521 */ 522 523 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 524 525 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the 526 * checksum itself 527 */ 528 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 529 if (ixgbe_read_eerd_generic(hw, i, &word)) { 530 DEBUGOUT("EEPROM read failed\n"); 531 return IXGBE_ERR_EEPROM; 532 } 533 checksum += word; 534 } 535 536 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 537 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 538 */ 539 for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 540 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 541 continue; 542 543 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 544 DEBUGOUT("EEPROM read failed\n"); 545 return IXGBE_ERR_EEPROM; 546 } 547 548 /* Skip pointer section if the pointer is invalid. */ 549 if (pointer == 0xFFFF || pointer == 0 || 550 pointer >= hw->eeprom.word_size) 551 continue; 552 553 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 554 DEBUGOUT("EEPROM read failed\n"); 555 return IXGBE_ERR_EEPROM; 556 } 557 558 /* Skip pointer section if length is invalid. */ 559 if (length == 0xFFFF || length == 0 || 560 (pointer + length) >= hw->eeprom.word_size) 561 continue; 562 563 for (j = pointer + 1; j <= pointer + length; j++) { 564 if (ixgbe_read_eerd_generic(hw, j, &word)) { 565 DEBUGOUT("EEPROM read failed\n"); 566 return IXGBE_ERR_EEPROM; 567 } 568 checksum += word; 569 } 570 } 571 572 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 573 574 return (s32)checksum; 575 } 576 577 /** 578 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 579 * @hw: pointer to hardware structure 580 * @checksum_val: calculated checksum 581 * 582 * Performs checksum calculation and validates the EEPROM checksum. If the 583 * caller does not need checksum_val, the value can be NULL. 584 **/ 585 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 586 u16 *checksum_val) 587 { 588 s32 status; 589 u16 checksum; 590 u16 read_checksum = 0; 591 592 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 593 594 /* Read the first word from the EEPROM. If this times out or fails, do 595 * not continue or we could be in for a very long wait while every 596 * EEPROM read fails 597 */ 598 status = hw->eeprom.ops.read(hw, 0, &checksum); 599 if (status) { 600 DEBUGOUT("EEPROM read failed\n"); 601 return status; 602 } 603 604 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 605 return IXGBE_ERR_SWFW_SYNC; 606 607 status = hw->eeprom.ops.calc_checksum(hw); 608 if (status < 0) 609 goto out; 610 611 checksum = (u16)(status & 0xffff); 612 613 /* Do not use hw->eeprom.ops.read because we do not want to take 614 * the synchronization semaphores twice here. 615 */ 616 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 617 &read_checksum); 618 if (status) 619 goto out; 620 621 /* Verify read checksum from EEPROM is the same as 622 * calculated checksum 623 */ 624 if (read_checksum != checksum) { 625 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 626 "Invalid EEPROM checksum"); 627 status = IXGBE_ERR_EEPROM_CHECKSUM; 628 } 629 630 /* If the user cares, return the calculated checksum */ 631 if (checksum_val) 632 *checksum_val = checksum; 633 634 out: 635 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 636 637 return status; 638 } 639 640 /** 641 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 642 * @hw: pointer to hardware structure 643 * 644 * After writing EEPROM to shadow RAM using EEWR register, software calculates 645 * checksum and updates the EEPROM and instructs the hardware to update 646 * the flash. 647 **/ 648 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 649 { 650 s32 status; 651 u16 checksum; 652 653 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 654 655 /* Read the first word from the EEPROM. If this times out or fails, do 656 * not continue or we could be in for a very long wait while every 657 * EEPROM read fails 658 */ 659 status = hw->eeprom.ops.read(hw, 0, &checksum); 660 if (status) { 661 DEBUGOUT("EEPROM read failed\n"); 662 return status; 663 } 664 665 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 666 return IXGBE_ERR_SWFW_SYNC; 667 668 status = hw->eeprom.ops.calc_checksum(hw); 669 if (status < 0) 670 goto out; 671 672 checksum = (u16)(status & 0xffff); 673 674 /* Do not use hw->eeprom.ops.write because we do not want to 675 * take the synchronization semaphores twice here. 676 */ 677 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 678 if (status) 679 goto out; 680 681 status = ixgbe_update_flash_X540(hw); 682 683 out: 684 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 685 686 return status; 687 } 688 689 /** 690 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 691 * @hw: pointer to hardware structure 692 * 693 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 694 * EEPROM from shadow RAM to the flash device. 695 **/ 696 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 697 { 698 u32 flup; 699 s32 status; 700 701 DEBUGFUNC("ixgbe_update_flash_X540"); 702 703 status = ixgbe_poll_flash_update_done_X540(hw); 704 if (status == IXGBE_ERR_EEPROM) { 705 DEBUGOUT("Flash update time out\n"); 706 goto out; 707 } 708 709 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP; 710 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 711 712 status = ixgbe_poll_flash_update_done_X540(hw); 713 if (status == IXGBE_SUCCESS) 714 DEBUGOUT("Flash update complete\n"); 715 else 716 DEBUGOUT("Flash update time out\n"); 717 718 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 719 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 720 721 if (flup & IXGBE_EEC_SEC1VAL) { 722 flup |= IXGBE_EEC_FLUP; 723 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 724 } 725 726 status = ixgbe_poll_flash_update_done_X540(hw); 727 if (status == IXGBE_SUCCESS) 728 DEBUGOUT("Flash update complete\n"); 729 else 730 DEBUGOUT("Flash update time out\n"); 731 } 732 out: 733 return status; 734 } 735 736 /** 737 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 738 * @hw: pointer to hardware structure 739 * 740 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 741 * flash update is done. 742 **/ 743 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 744 { 745 u32 i; 746 u32 reg; 747 s32 status = IXGBE_ERR_EEPROM; 748 749 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 750 751 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 752 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 753 if (reg & IXGBE_EEC_FLUDONE) { 754 status = IXGBE_SUCCESS; 755 break; 756 } 757 msec_delay(5); 758 } 759 760 if (i == IXGBE_FLUDONE_ATTEMPTS) 761 ERROR_REPORT1(IXGBE_ERROR_POLLING, 762 "Flash update status polling timed out"); 763 764 return status; 765 } 766 767 /** 768 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 769 * @hw: pointer to hardware structure 770 * @mask: Mask to specify which semaphore to acquire 771 * 772 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 773 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 774 **/ 775 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 776 { 777 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; 778 u32 fwmask = swmask << 5; 779 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; 780 u32 timeout = 200; 781 u32 hwmask = 0; 782 u32 swfw_sync; 783 u32 i; 784 785 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 786 787 if (swmask & IXGBE_GSSR_EEP_SM) 788 hwmask |= IXGBE_GSSR_FLASH_SM; 789 790 /* SW only mask doesn't have FW bit pair */ 791 if (mask & IXGBE_GSSR_SW_MNG_SM) 792 swmask |= IXGBE_GSSR_SW_MNG_SM; 793 794 swmask |= swi2c_mask; 795 fwmask |= swi2c_mask << 2; 796 if (hw->mac.type >= ixgbe_mac_X550) 797 timeout = 1000; 798 799 for (i = 0; i < timeout; i++) { 800 /* SW NVM semaphore bit is used for access to all 801 * SW_FW_SYNC bits (not just NVM) 802 */ 803 if (ixgbe_get_swfw_sync_semaphore(hw)) { 804 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n"); 805 return IXGBE_ERR_SWFW_SYNC; 806 } 807 808 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 809 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 810 swfw_sync |= swmask; 811 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), 812 swfw_sync); 813 ixgbe_release_swfw_sync_semaphore(hw); 814 return IXGBE_SUCCESS; 815 } 816 /* Firmware currently using resource (fwmask), hardware 817 * currently using resource (hwmask), or other software 818 * thread currently using resource (swmask) 819 */ 820 ixgbe_release_swfw_sync_semaphore(hw); 821 msec_delay(5); 822 } 823 824 /* If the resource is not released by the FW/HW the SW can assume that 825 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 826 * of the requested resource(s) while ignoring the corresponding FW/HW 827 * bits in the SW_FW_SYNC register. 828 */ 829 if (ixgbe_get_swfw_sync_semaphore(hw)) { 830 DEBUGOUT("Failed to get NVM semaphore and register semaphore while forcefully ignoring FW semaphore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n"); 831 return IXGBE_ERR_SWFW_SYNC; 832 } 833 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 834 if (swfw_sync & (fwmask | hwmask)) { 835 swfw_sync |= swmask; 836 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 837 ixgbe_release_swfw_sync_semaphore(hw); 838 msec_delay(5); 839 return IXGBE_SUCCESS; 840 } 841 /* If the resource is not released by other SW the SW can assume that 842 * the other SW malfunctions. In that case the SW should clear all SW 843 * flags that it does not own and then repeat the whole process once 844 * again. 845 */ 846 if (swfw_sync & swmask) { 847 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 848 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 849 IXGBE_GSSR_SW_MNG_SM; 850 851 if (swi2c_mask) 852 rmask |= IXGBE_GSSR_I2C_MASK; 853 ixgbe_release_swfw_sync_X540(hw, rmask); 854 ixgbe_release_swfw_sync_semaphore(hw); 855 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n"); 856 return IXGBE_ERR_SWFW_SYNC; 857 } 858 ixgbe_release_swfw_sync_semaphore(hw); 859 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n"); 860 861 return IXGBE_ERR_SWFW_SYNC; 862 } 863 864 /** 865 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 866 * @hw: pointer to hardware structure 867 * @mask: Mask to specify which semaphore to release 868 * 869 * Releases the SWFW semaphore through the SW_FW_SYNC register 870 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 871 **/ 872 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 873 { 874 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); 875 u32 swfw_sync; 876 877 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 878 879 if (mask & IXGBE_GSSR_I2C_MASK) 880 swmask |= mask & IXGBE_GSSR_I2C_MASK; 881 ixgbe_get_swfw_sync_semaphore(hw); 882 883 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 884 swfw_sync &= ~swmask; 885 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 886 887 ixgbe_release_swfw_sync_semaphore(hw); 888 msec_delay(2); 889 } 890 891 /** 892 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 893 * @hw: pointer to hardware structure 894 * 895 * Sets the hardware semaphores so SW/FW can gain control of shared resources 896 **/ 897 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 898 { 899 s32 status = IXGBE_ERR_EEPROM; 900 u32 timeout = 2000; 901 u32 i; 902 u32 swsm; 903 904 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 905 906 /* Get SMBI software semaphore between device drivers first */ 907 for (i = 0; i < timeout; i++) { 908 /* 909 * If the SMBI bit is 0 when we read it, then the bit will be 910 * set and we have the semaphore 911 */ 912 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 913 if (!(swsm & IXGBE_SWSM_SMBI)) { 914 status = IXGBE_SUCCESS; 915 break; 916 } 917 usec_delay(50); 918 } 919 920 /* Now get the semaphore between SW/FW through the REGSMP bit */ 921 if (status == IXGBE_SUCCESS) { 922 for (i = 0; i < timeout; i++) { 923 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 924 if (!(swsm & IXGBE_SWFW_REGSMP)) 925 break; 926 927 usec_delay(50); 928 } 929 930 /* 931 * Release semaphores and return error if SW NVM semaphore 932 * was not granted because we don't have access to the EEPROM 933 */ 934 if (i >= timeout) { 935 ERROR_REPORT1(IXGBE_ERROR_POLLING, 936 "REGSMP Software NVM semaphore not granted.\n"); 937 ixgbe_release_swfw_sync_semaphore(hw); 938 status = IXGBE_ERR_EEPROM; 939 } 940 } else { 941 ERROR_REPORT1(IXGBE_ERROR_POLLING, 942 "Software semaphore SMBI between device drivers " 943 "not granted.\n"); 944 } 945 946 return status; 947 } 948 949 /** 950 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore 951 * @hw: pointer to hardware structure 952 * 953 * This function clears hardware semaphore bits. 954 **/ 955 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 956 { 957 u32 swsm; 958 959 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 960 961 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 962 963 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 964 swsm &= ~IXGBE_SWFW_REGSMP; 965 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); 966 967 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 968 swsm &= ~IXGBE_SWSM_SMBI; 969 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 970 971 IXGBE_WRITE_FLUSH(hw); 972 } 973 974 /** 975 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore 976 * @hw: pointer to hardware structure 977 * 978 * This function reset hardware semaphore bits for a semaphore that may 979 * have be left locked due to a catastrophic failure. 980 **/ 981 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw) 982 { 983 u32 rmask; 984 985 /* First try to grab the semaphore but we don't need to bother 986 * looking to see whether we got the lock or not since we do 987 * the same thing regardless of whether we got the lock or not. 988 * We got the lock - we release it. 989 * We timeout trying to get the lock - we force its release. 990 */ 991 ixgbe_get_swfw_sync_semaphore(hw); 992 ixgbe_release_swfw_sync_semaphore(hw); 993 994 /* Acquire and release all software resources. */ 995 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 996 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 997 IXGBE_GSSR_SW_MNG_SM; 998 999 rmask |= IXGBE_GSSR_I2C_MASK; 1000 ixgbe_acquire_swfw_sync_X540(hw, rmask); 1001 ixgbe_release_swfw_sync_X540(hw, rmask); 1002 } 1003 1004 /** 1005 * ixgbe_blink_led_start_X540 - Blink LED based on index. 1006 * @hw: pointer to hardware structure 1007 * @index: led number to blink 1008 * 1009 * Devices that implement the version 2 interface: 1010 * X540 1011 **/ 1012 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 1013 { 1014 u32 macc_reg; 1015 u32 ledctl_reg; 1016 ixgbe_link_speed speed; 1017 bool link_up; 1018 1019 DEBUGFUNC("ixgbe_blink_led_start_X540"); 1020 1021 if (index > 3) 1022 return IXGBE_ERR_PARAM; 1023 1024 /* 1025 * Link should be up in order for the blink bit in the LED control 1026 * register to work. Force link and speed in the MAC if link is down. 1027 * This will be reversed when we stop the blinking. 1028 */ 1029 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1030 if (link_up == FALSE) { 1031 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1032 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 1033 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1034 } 1035 /* Set the LED to LINK_UP + BLINK. */ 1036 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1037 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1038 ledctl_reg |= IXGBE_LED_BLINK(index); 1039 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1040 IXGBE_WRITE_FLUSH(hw); 1041 1042 return IXGBE_SUCCESS; 1043 } 1044 1045 /** 1046 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 1047 * @hw: pointer to hardware structure 1048 * @index: led number to stop blinking 1049 * 1050 * Devices that implement the version 2 interface: 1051 * X540 1052 **/ 1053 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 1054 { 1055 u32 macc_reg; 1056 u32 ledctl_reg; 1057 1058 if (index > 3) 1059 return IXGBE_ERR_PARAM; 1060 1061 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 1062 1063 /* Restore the LED to its default value. */ 1064 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1065 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1066 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 1067 ledctl_reg &= ~IXGBE_LED_BLINK(index); 1068 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1069 1070 /* Unforce link and speed in the MAC. */ 1071 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1072 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 1073 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1074 IXGBE_WRITE_FLUSH(hw); 1075 1076 return IXGBE_SUCCESS; 1077 } 1078
Indexes created Sun Oct 19 02:09:48 GMT 2025