ixgbe_x540.c revision 1.2.4.3
1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 247822 2013-03-04 23:07:40Z jfv $*/ 34 35 #include "ixgbe_x540.h" 36 #include "ixgbe_type.h" 37 #include "ixgbe_api.h" 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 41 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 42 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 43 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 44 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 45 46 /** 47 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 48 * @hw: pointer to hardware structure 49 * 50 * Initialize the function pointers and assign the MAC type for X540. 51 * Does not touch the hardware. 52 **/ 53 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 54 { 55 struct ixgbe_mac_info *mac = &hw->mac; 56 struct ixgbe_phy_info *phy = &hw->phy; 57 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 58 s32 ret_val; 59 60 DEBUGFUNC("ixgbe_init_ops_X540"); 61 62 ret_val = ixgbe_init_phy_ops_generic(hw); 63 ret_val = ixgbe_init_ops_generic(hw); 64 65 66 /* EEPROM */ 67 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540; 68 eeprom->ops.read = &ixgbe_read_eerd_X540; 69 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540; 70 eeprom->ops.write = &ixgbe_write_eewr_X540; 71 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540; 72 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540; 73 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540; 74 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540; 75 76 /* PHY */ 77 phy->ops.init = &ixgbe_init_phy_ops_generic; 78 phy->ops.reset = NULL; 79 80 /* MAC */ 81 mac->ops.reset_hw = &ixgbe_reset_hw_X540; 82 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 83 mac->ops.get_media_type = &ixgbe_get_media_type_X540; 84 mac->ops.get_supported_physical_layer = 85 &ixgbe_get_supported_physical_layer_X540; 86 mac->ops.read_analog_reg8 = NULL; 87 mac->ops.write_analog_reg8 = NULL; 88 mac->ops.start_hw = &ixgbe_start_hw_X540; 89 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 90 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 91 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 92 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 93 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 94 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540; 95 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540; 96 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 97 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 98 99 /* RAR, Multicast, VLAN */ 100 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 101 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic; 102 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 103 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 104 mac->rar_highwater = 1; 105 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 106 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; 107 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 108 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 109 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 110 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 111 112 /* Link */ 113 mac->ops.get_link_capabilities = 114 &ixgbe_get_copper_link_capabilities_generic; 115 mac->ops.setup_link = &ixgbe_setup_mac_link_X540; 116 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; 117 mac->ops.check_link = &ixgbe_check_mac_link_generic; 118 119 120 mac->mcft_size = 128; 121 mac->vft_size = 128; 122 mac->num_rar_entries = 128; 123 mac->rx_pb_size = 384; 124 mac->max_tx_queues = 128; 125 mac->max_rx_queues = 128; 126 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 127 128 /* 129 * FWSM register 130 * ARC supported; valid only if manageability features are 131 * enabled. 132 */ 133 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & 134 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; 135 136 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 137 138 /* LEDs */ 139 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 140 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 141 142 /* Manageability interface */ 143 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; 144 145 return ret_val; 146 } 147 148 /** 149 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 150 * @hw: pointer to hardware structure 151 * @speed: pointer to link speed 152 * @autoneg: TRUE when autoneg or autotry is enabled 153 * 154 * Determines the link capabilities by reading the AUTOC register. 155 **/ 156 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 157 ixgbe_link_speed *speed, 158 bool *autoneg) 159 { 160 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 161 162 return IXGBE_SUCCESS; 163 } 164 165 /** 166 * ixgbe_get_media_type_X540 - Get media type 167 * @hw: pointer to hardware structure 168 * 169 * Returns the media type (fiber, copper, backplane) 170 **/ 171 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 172 { 173 UNREFERENCED_1PARAMETER(hw); 174 return ixgbe_media_type_copper; 175 } 176 177 /** 178 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 179 * @hw: pointer to hardware structure 180 * @speed: new link speed 181 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 182 **/ 183 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 184 ixgbe_link_speed speed, 185 bool autoneg_wait_to_complete) 186 { 187 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 188 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 189 } 190 191 /** 192 * ixgbe_reset_hw_X540 - Perform hardware reset 193 * @hw: pointer to hardware structure 194 * 195 * Resets the hardware by resetting the transmit and receive units, masks 196 * and clears all interrupts, and perform a reset. 197 **/ 198 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 199 { 200 s32 status; 201 u32 ctrl, i; 202 203 DEBUGFUNC("ixgbe_reset_hw_X540"); 204 205 /* Call adapter stop to disable tx/rx and clear interrupts */ 206 status = hw->mac.ops.stop_adapter(hw); 207 if (status != IXGBE_SUCCESS) 208 goto reset_hw_out; 209 210 /* flush pending Tx transactions */ 211 ixgbe_clear_tx_pending(hw); 212 213 mac_reset_top: 214 ctrl = IXGBE_CTRL_RST; 215 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 216 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 217 IXGBE_WRITE_FLUSH(hw); 218 219 /* Poll for reset bit to self-clear indicating reset is complete */ 220 for (i = 0; i < 10; i++) { 221 usec_delay(1); 222 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 223 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 224 break; 225 } 226 227 if (ctrl & IXGBE_CTRL_RST_MASK) { 228 status = IXGBE_ERR_RESET_FAILED; 229 DEBUGOUT("Reset polling failed to complete.\n"); 230 } 231 msec_delay(100); 232 233 /* 234 * Double resets are required for recovery from certain error 235 * conditions. Between resets, it is necessary to stall to allow time 236 * for any pending HW events to complete. 237 */ 238 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 239 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 240 goto mac_reset_top; 241 } 242 243 /* Set the Rx packet buffer size. */ 244 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 245 246 /* Store the permanent mac address */ 247 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 248 249 /* 250 * Store MAC address from RAR0, clear receive address registers, and 251 * clear the multicast table. Also reset num_rar_entries to 128, 252 * since we modify this value when programming the SAN MAC address. 253 */ 254 hw->mac.num_rar_entries = 128; 255 hw->mac.ops.init_rx_addrs(hw); 256 257 /* Store the permanent SAN mac address */ 258 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 259 260 /* Add the SAN MAC address to the RAR only if it's a valid address */ 261 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 262 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 263 hw->mac.san_addr, 0, IXGBE_RAH_AV); 264 265 /* Save the SAN MAC RAR index */ 266 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 267 268 /* Reserve the last RAR for the SAN MAC address */ 269 hw->mac.num_rar_entries--; 270 } 271 272 /* Store the alternative WWNN/WWPN prefix */ 273 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 274 &hw->mac.wwpn_prefix); 275 276 reset_hw_out: 277 return status; 278 } 279 280 /** 281 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 282 * @hw: pointer to hardware structure 283 * 284 * Starts the hardware using the generic start_hw function 285 * and the generation start_hw function. 286 * Then performs revision-specific operations, if any. 287 **/ 288 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 289 { 290 s32 ret_val = IXGBE_SUCCESS; 291 292 DEBUGFUNC("ixgbe_start_hw_X540"); 293 294 ret_val = ixgbe_start_hw_generic(hw); 295 if (ret_val != IXGBE_SUCCESS) 296 goto out; 297 298 ret_val = ixgbe_start_hw_gen2(hw); 299 300 out: 301 return ret_val; 302 } 303 304 /** 305 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 306 * @hw: pointer to hardware structure 307 * 308 * Determines physical layer capabilities of the current configuration. 309 **/ 310 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 311 { 312 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 313 u16 ext_ability = 0; 314 315 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 316 317 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 318 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 319 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 320 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 321 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 322 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 323 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 324 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 325 326 return physical_layer; 327 } 328 329 /** 330 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 331 * @hw: pointer to hardware structure 332 * 333 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 334 * ixgbe_hw struct in order to set up EEPROM access. 335 **/ 336 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 337 { 338 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 339 u32 eec; 340 u16 eeprom_size; 341 342 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 343 344 if (eeprom->type == ixgbe_eeprom_uninitialized) { 345 eeprom->semaphore_delay = 10; 346 eeprom->type = ixgbe_flash; 347 348 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 349 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 350 IXGBE_EEC_SIZE_SHIFT); 351 eeprom->word_size = 1 << (eeprom_size + 352 IXGBE_EEPROM_WORD_SIZE_SHIFT); 353 354 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 355 eeprom->type, eeprom->word_size); 356 } 357 358 return IXGBE_SUCCESS; 359 } 360 361 /** 362 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 363 * @hw: pointer to hardware structure 364 * @offset: offset of word in the EEPROM to read 365 * @data: word read from the EEPROM 366 * 367 * Reads a 16 bit word from the EEPROM using the EERD register. 368 **/ 369 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 370 { 371 s32 status = IXGBE_SUCCESS; 372 373 DEBUGFUNC("ixgbe_read_eerd_X540"); 374 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 375 IXGBE_SUCCESS) 376 status = ixgbe_read_eerd_generic(hw, offset, data); 377 else 378 status = IXGBE_ERR_SWFW_SYNC; 379 380 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 381 return status; 382 } 383 384 /** 385 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 386 * @hw: pointer to hardware structure 387 * @offset: offset of word in the EEPROM to read 388 * @words: number of words 389 * @data: word(s) read from the EEPROM 390 * 391 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 392 **/ 393 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 394 u16 offset, u16 words, u16 *data) 395 { 396 s32 status = IXGBE_SUCCESS; 397 398 DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 399 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 400 IXGBE_SUCCESS) 401 status = ixgbe_read_eerd_buffer_generic(hw, offset, 402 words, data); 403 else 404 status = IXGBE_ERR_SWFW_SYNC; 405 406 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 407 return status; 408 } 409 410 /** 411 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 412 * @hw: pointer to hardware structure 413 * @offset: offset of word in the EEPROM to write 414 * @data: word write to the EEPROM 415 * 416 * Write a 16 bit word to the EEPROM using the EEWR register. 417 **/ 418 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 419 { 420 s32 status = IXGBE_SUCCESS; 421 422 DEBUGFUNC("ixgbe_write_eewr_X540"); 423 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 424 IXGBE_SUCCESS) 425 status = ixgbe_write_eewr_generic(hw, offset, data); 426 else 427 status = IXGBE_ERR_SWFW_SYNC; 428 429 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 430 return status; 431 } 432 433 /** 434 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 435 * @hw: pointer to hardware structure 436 * @offset: offset of word in the EEPROM to write 437 * @words: number of words 438 * @data: word(s) write to the EEPROM 439 * 440 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 441 **/ 442 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 443 u16 offset, u16 words, u16 *data) 444 { 445 s32 status = IXGBE_SUCCESS; 446 447 DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 448 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 449 IXGBE_SUCCESS) 450 status = ixgbe_write_eewr_buffer_generic(hw, offset, 451 words, data); 452 else 453 status = IXGBE_ERR_SWFW_SYNC; 454 455 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 456 return status; 457 } 458 459 /** 460 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 461 * 462 * This function does not use synchronization for EERD and EEWR. It can 463 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 464 * 465 * @hw: pointer to hardware structure 466 **/ 467 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 468 { 469 u16 i; 470 u16 j; 471 u16 checksum = 0; 472 u16 length = 0; 473 u16 pointer = 0; 474 u16 word = 0; 475 476 /* 477 * Do not use hw->eeprom.ops.read because we do not want to take 478 * the synchronization semaphores here. Instead use 479 * ixgbe_read_eerd_generic 480 */ 481 482 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 483 484 /* Include 0x0-0x3F in the checksum */ 485 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 486 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) { 487 DEBUGOUT("EEPROM read failed\n"); 488 break; 489 } 490 checksum += word; 491 } 492 493 /* 494 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 495 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 496 */ 497 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 498 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 499 continue; 500 501 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) { 502 DEBUGOUT("EEPROM read failed\n"); 503 break; 504 } 505 506 /* Skip pointer section if the pointer is invalid. */ 507 if (pointer == 0xFFFF || pointer == 0 || 508 pointer >= hw->eeprom.word_size) 509 continue; 510 511 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 512 IXGBE_SUCCESS) { 513 DEBUGOUT("EEPROM read failed\n"); 514 break; 515 } 516 517 /* Skip pointer section if length is invalid. */ 518 if (length == 0xFFFF || length == 0 || 519 (pointer + length) >= hw->eeprom.word_size) 520 continue; 521 522 for (j = pointer+1; j <= pointer+length; j++) { 523 if (ixgbe_read_eerd_generic(hw, j, &word) != 524 IXGBE_SUCCESS) { 525 DEBUGOUT("EEPROM read failed\n"); 526 break; 527 } 528 checksum += word; 529 } 530 } 531 532 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 533 534 return checksum; 535 } 536 537 /** 538 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 539 * @hw: pointer to hardware structure 540 * @checksum_val: calculated checksum 541 * 542 * Performs checksum calculation and validates the EEPROM checksum. If the 543 * caller does not need checksum_val, the value can be NULL. 544 **/ 545 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 546 u16 *checksum_val) 547 { 548 s32 status; 549 u16 checksum; 550 u16 read_checksum = 0; 551 552 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 553 554 /* 555 * Read the first word from the EEPROM. If this times out or fails, do 556 * not continue or we could be in for a very long wait while every 557 * EEPROM read fails 558 */ 559 status = hw->eeprom.ops.read(hw, 0, &checksum); 560 561 if (status != IXGBE_SUCCESS) { 562 DEBUGOUT("EEPROM read failed\n"); 563 goto out; 564 } 565 566 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 567 IXGBE_SUCCESS) { 568 checksum = hw->eeprom.ops.calc_checksum(hw); 569 570 /* 571 * Do not use hw->eeprom.ops.read because we do not want to take 572 * the synchronization semaphores twice here. 573 */ 574 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 575 &read_checksum); 576 577 /* 578 * Verify read checksum from EEPROM is the same as 579 * calculated checksum 580 */ 581 if (read_checksum != checksum) 582 status = IXGBE_ERR_EEPROM_CHECKSUM; 583 584 /* If the user cares, return the calculated checksum */ 585 if (checksum_val) 586 *checksum_val = checksum; 587 } else { 588 status = IXGBE_ERR_SWFW_SYNC; 589 } 590 591 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 592 out: 593 return status; 594 } 595 596 /** 597 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 598 * @hw: pointer to hardware structure 599 * 600 * After writing EEPROM to shadow RAM using EEWR register, software calculates 601 * checksum and updates the EEPROM and instructs the hardware to update 602 * the flash. 603 **/ 604 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 605 { 606 s32 status; 607 u16 checksum; 608 609 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 610 611 /* 612 * Read the first word from the EEPROM. If this times out or fails, do 613 * not continue or we could be in for a very long wait while every 614 * EEPROM read fails 615 */ 616 status = hw->eeprom.ops.read(hw, 0, &checksum); 617 618 if (status != IXGBE_SUCCESS) 619 DEBUGOUT("EEPROM read failed\n"); 620 621 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 622 IXGBE_SUCCESS) { 623 checksum = hw->eeprom.ops.calc_checksum(hw); 624 625 /* 626 * Do not use hw->eeprom.ops.write because we do not want to 627 * take the synchronization semaphores twice here. 628 */ 629 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, 630 checksum); 631 632 if (status == IXGBE_SUCCESS) 633 status = ixgbe_update_flash_X540(hw); 634 else 635 status = IXGBE_ERR_SWFW_SYNC; 636 } 637 638 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 639 640 return status; 641 } 642 643 /** 644 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 645 * @hw: pointer to hardware structure 646 * 647 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 648 * EEPROM from shadow RAM to the flash device. 649 **/ 650 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 651 { 652 u32 flup; 653 s32 status = IXGBE_ERR_EEPROM; 654 655 DEBUGFUNC("ixgbe_update_flash_X540"); 656 657 status = ixgbe_poll_flash_update_done_X540(hw); 658 if (status == IXGBE_ERR_EEPROM) { 659 DEBUGOUT("Flash update time out\n"); 660 goto out; 661 } 662 663 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 664 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 665 666 status = ixgbe_poll_flash_update_done_X540(hw); 667 if (status == IXGBE_SUCCESS) 668 DEBUGOUT("Flash update complete\n"); 669 else 670 DEBUGOUT("Flash update time out\n"); 671 672 if (hw->revision_id == 0) { 673 flup = IXGBE_READ_REG(hw, IXGBE_EEC); 674 675 if (flup & IXGBE_EEC_SEC1VAL) { 676 flup |= IXGBE_EEC_FLUP; 677 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 678 } 679 680 status = ixgbe_poll_flash_update_done_X540(hw); 681 if (status == IXGBE_SUCCESS) 682 DEBUGOUT("Flash update complete\n"); 683 else 684 DEBUGOUT("Flash update time out\n"); 685 } 686 out: 687 return status; 688 } 689 690 /** 691 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 692 * @hw: pointer to hardware structure 693 * 694 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 695 * flash update is done. 696 **/ 697 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 698 { 699 u32 i; 700 u32 reg; 701 s32 status = IXGBE_ERR_EEPROM; 702 703 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 704 705 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 706 reg = IXGBE_READ_REG(hw, IXGBE_EEC); 707 if (reg & IXGBE_EEC_FLUDONE) { 708 status = IXGBE_SUCCESS; 709 break; 710 } 711 usec_delay(5); 712 } 713 return status; 714 } 715 716 /** 717 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 718 * @hw: pointer to hardware structure 719 * @mask: Mask to specify which semaphore to acquire 720 * 721 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 722 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 723 **/ 724 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 725 { 726 u32 swfw_sync; 727 u32 swmask = mask; 728 u32 fwmask = mask << 5; 729 u32 hwmask = 0; 730 u32 timeout = 200; 731 u32 i; 732 s32 ret_val = IXGBE_SUCCESS; 733 734 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 735 736 if (swmask == IXGBE_GSSR_EEP_SM) 737 hwmask = IXGBE_GSSR_FLASH_SM; 738 739 /* SW only mask doesn't have FW bit pair */ 740 if (swmask == IXGBE_GSSR_SW_MNG_SM) 741 fwmask = 0; 742 743 for (i = 0; i < timeout; i++) { 744 /* 745 * SW NVM semaphore bit is used for access to all 746 * SW_FW_SYNC bits (not just NVM) 747 */ 748 if (ixgbe_get_swfw_sync_semaphore(hw)) { 749 ret_val = IXGBE_ERR_SWFW_SYNC; 750 goto out; 751 } 752 753 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 754 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 755 swfw_sync |= swmask; 756 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 757 ixgbe_release_swfw_sync_semaphore(hw); 758 msec_delay(5); 759 goto out; 760 } else { 761 /* 762 * Firmware currently using resource (fwmask), hardware 763 * currently using resource (hwmask), or other software 764 * thread currently using resource (swmask) 765 */ 766 ixgbe_release_swfw_sync_semaphore(hw); 767 msec_delay(5); 768 } 769 } 770 771 /* Failed to get SW only semaphore */ 772 if (swmask == IXGBE_GSSR_SW_MNG_SM) { 773 ret_val = IXGBE_ERR_SWFW_SYNC; 774 goto out; 775 } 776 777 /* If the resource is not released by the FW/HW the SW can assume that 778 * the FW/HW malfunctions. In that case the SW should sets the SW bit(s) 779 * of the requested resource(s) while ignoring the corresponding FW/HW 780 * bits in the SW_FW_SYNC register. 781 */ 782 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 783 if (swfw_sync & (fwmask | hwmask)) { 784 if (ixgbe_get_swfw_sync_semaphore(hw)) { 785 ret_val = IXGBE_ERR_SWFW_SYNC; 786 goto out; 787 } 788 789 swfw_sync |= swmask; 790 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 791 ixgbe_release_swfw_sync_semaphore(hw); 792 msec_delay(5); 793 } 794 795 out: 796 return ret_val; 797 } 798 799 /** 800 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 801 * @hw: pointer to hardware structure 802 * @mask: Mask to specify which semaphore to release 803 * 804 * Releases the SWFW semaphore through the SW_FW_SYNC register 805 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 806 **/ 807 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 808 { 809 u32 swfw_sync; 810 u32 swmask = mask; 811 812 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 813 814 ixgbe_get_swfw_sync_semaphore(hw); 815 816 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 817 swfw_sync &= ~swmask; 818 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 819 820 ixgbe_release_swfw_sync_semaphore(hw); 821 msec_delay(5); 822 } 823 824 /** 825 * ixgbe_get_nvm_semaphore - Get hardware semaphore 826 * @hw: pointer to hardware structure 827 * 828 * Sets the hardware semaphores so SW/FW can gain control of shared resources 829 **/ 830 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 831 { 832 s32 status = IXGBE_ERR_EEPROM; 833 u32 timeout = 2000; 834 u32 i; 835 u32 swsm; 836 837 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 838 839 /* Get SMBI software semaphore between device drivers first */ 840 for (i = 0; i < timeout; i++) { 841 /* 842 * If the SMBI bit is 0 when we read it, then the bit will be 843 * set and we have the semaphore 844 */ 845 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 846 if (!(swsm & IXGBE_SWSM_SMBI)) { 847 status = IXGBE_SUCCESS; 848 break; 849 } 850 usec_delay(50); 851 } 852 853 /* Now get the semaphore between SW/FW through the REGSMP bit */ 854 if (status == IXGBE_SUCCESS) { 855 for (i = 0; i < timeout; i++) { 856 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 857 if (!(swsm & IXGBE_SWFW_REGSMP)) 858 break; 859 860 usec_delay(50); 861 } 862 863 /* 864 * Release semaphores and return error if SW NVM semaphore 865 * was not granted because we don't have access to the EEPROM 866 */ 867 if (i >= timeout) { 868 DEBUGOUT("REGSMP Software NVM semaphore not " 869 "granted.\n"); 870 ixgbe_release_swfw_sync_semaphore(hw); 871 status = IXGBE_ERR_EEPROM; 872 } 873 } else { 874 DEBUGOUT("Software semaphore SMBI between device drivers " 875 "not granted.\n"); 876 } 877 878 return status; 879 } 880 881 /** 882 * ixgbe_release_nvm_semaphore - Release hardware semaphore 883 * @hw: pointer to hardware structure 884 * 885 * This function clears hardware semaphore bits. 886 **/ 887 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 888 { 889 u32 swsm; 890 891 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 892 893 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 894 895 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 896 swsm &= ~IXGBE_SWSM_SMBI; 897 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 898 899 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 900 swsm &= ~IXGBE_SWFW_REGSMP; 901 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 902 903 IXGBE_WRITE_FLUSH(hw); 904 } 905 906 /** 907 * ixgbe_blink_led_start_X540 - Blink LED based on index. 908 * @hw: pointer to hardware structure 909 * @index: led number to blink 910 * 911 * Devices that implement the version 2 interface: 912 * X540 913 **/ 914 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 915 { 916 u32 macc_reg; 917 u32 ledctl_reg; 918 ixgbe_link_speed speed; 919 bool link_up; 920 921 DEBUGFUNC("ixgbe_blink_led_start_X540"); 922 923 /* 924 * Link should be up in order for the blink bit in the LED control 925 * register to work. Force link and speed in the MAC if link is down. 926 * This will be reversed when we stop the blinking. 927 */ 928 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 929 if (link_up == FALSE) { 930 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 931 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 932 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 933 } 934 /* Set the LED to LINK_UP + BLINK. */ 935 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 936 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 937 ledctl_reg |= IXGBE_LED_BLINK(index); 938 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 939 IXGBE_WRITE_FLUSH(hw); 940 941 return IXGBE_SUCCESS; 942 } 943 944 /** 945 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 946 * @hw: pointer to hardware structure 947 * @index: led number to stop blinking 948 * 949 * Devices that implement the version 2 interface: 950 * X540 951 **/ 952 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 953 { 954 u32 macc_reg; 955 u32 ledctl_reg; 956 957 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 958 959 /* Restore the LED to its default value. */ 960 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 961 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 962 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 963 ledctl_reg &= ~IXGBE_LED_BLINK(index); 964 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 965 966 /* Unforce link and speed in the MAC. */ 967 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 968 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 969 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 970 IXGBE_WRITE_FLUSH(hw); 971 972 return IXGBE_SUCCESS; 973 } 974 975 976
Indexes created Tue Oct 21 08:09:48 GMT 2025