ixpide.c revision 1.11.2.1
1 /* $NetBSD: ixpide.c,v 1.11.2.1 2008/05/18 12:34:20 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2004 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ixpide.c,v 1.11.2.1 2008/05/18 12:34:20 yamt Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_ixp_reg.h> 40 41 static int ixpide_match(device_t, cfdata_t, void *); 42 static void ixpide_attach(device_t, device_t, void *); 43 44 static void ixp_chip_map(struct pciide_softc *, struct pci_attach_args *); 45 static void ixp_setup_channel(struct ata_channel *); 46 47 CFATTACH_DECL_NEW(ixpide, sizeof(struct pciide_softc), 48 ixpide_match, ixpide_attach, NULL, NULL); 49 50 static const char ixpdesc[] = "ATI Technologies IXP IDE Controller"; 51 52 static const struct pciide_product_desc pciide_ixpide_products[] = { 53 { PCI_PRODUCT_ATI_IXP_IDE_200, 0, ixpdesc, ixp_chip_map }, 54 { PCI_PRODUCT_ATI_IXP_IDE_300, 0, ixpdesc, ixp_chip_map }, 55 { PCI_PRODUCT_ATI_IXP_IDE_400, 0, ixpdesc, ixp_chip_map }, 56 { PCI_PRODUCT_ATI_IXP_IDE_600, 0, ixpdesc, ixp_chip_map }, 57 { PCI_PRODUCT_ATI_SB400_SATA_1, 0, ixpdesc, ixp_chip_map }, 58 { PCI_PRODUCT_ATI_SB400_SATA_2, 0, ixpdesc, ixp_chip_map }, 59 { PCI_PRODUCT_ATI_SB600_SATA_1, 0, ixpdesc, ixp_chip_map }, 60 { PCI_PRODUCT_ATI_SB600_SATA_2, 0, ixpdesc, ixp_chip_map }, 61 { 0, 0, NULL, NULL } 62 }; 63 64 static int 65 ixpide_match(device_t parent, cfdata_t cfdata, void *aux) 66 { 67 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 68 69 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 70 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 71 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 72 pciide_lookup_product(pa->pa_id, pciide_ixpide_products)) 73 return (2); 74 return (0); 75 } 76 77 static void 78 ixpide_attach(device_t parent, device_t self, void *aux) 79 { 80 struct pci_attach_args *pa = aux; 81 struct pciide_softc *sc = device_private(self); 82 83 sc->sc_wdcdev.sc_atac.atac_dev = self; 84 85 pciide_common_attach(sc, pa, 86 pciide_lookup_product(pa->pa_id, pciide_ixpide_products)); 87 } 88 89 static void 90 ixp_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 91 { 92 struct pciide_channel *cp; 93 int channel; 94 pcireg_t interface; 95 bus_size_t cmdsize, ctlsize; 96 97 if (pciide_chipen(sc, pa) == 0) 98 return; 99 100 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 101 "bus-master DMA support present"); 102 pciide_mapreg_dma(sc, pa); 103 aprint_verbose("\n"); 104 105 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 106 if (sc->sc_dma_ok) { 107 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 108 sc->sc_wdcdev.irqack = pciide_irqack; 109 } 110 111 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 112 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 113 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 114 sc->sc_wdcdev.sc_atac.atac_set_modes = ixp_setup_channel; 115 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 116 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 117 118 interface = PCI_INTERFACE(pa->pa_class); 119 120 wdc_allocate_regs(&sc->sc_wdcdev); 121 122 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 123 channel++) { 124 cp = &sc->pciide_channels[channel]; 125 if (pciide_chansetup(sc, channel, interface) == 0) 126 continue; 127 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 128 pciide_pci_intr); 129 } 130 } 131 132 /* Values from linux driver */ 133 static const uint8_t ixp_pio_timings[] = { 134 0x5d, 0x47, 0x34, 0x22, 0x20 135 }; 136 137 static const uint8_t ixp_mdma_timings[] = { 138 0x77, 0x21, 0x20 139 }; 140 141 static void 142 ixp_setup_channel(struct ata_channel *chp) 143 { 144 int drive, s; 145 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 146 pcireg_t udma, mdma_timing, pio, pio_timing; 147 struct ata_drive_datas *drvp; 148 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 149 150 pio_timing = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_PIO_TIMING); 151 pio = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_PIO_CTL); 152 mdma_timing = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_MDMA_TIMING); 153 udma = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_UDMA_CTL); 154 155 pciide_channel_dma_setup(cp); 156 157 for (drive = 0; drive < 2; drive++) { 158 drvp = &chp->ch_drive[drive]; 159 if ((drvp->drive_flags & DRIVE) == 0) 160 continue; 161 if (drvp->drive_flags & DRIVE_UDMA) { 162 s = splbio(); 163 drvp->drive_flags &= ~DRIVE_DMA; 164 splx(s); 165 IXP_UDMA_ENABLE(udma, chp->ch_channel, drive); 166 IXP_SET_MODE(udma, chp->ch_channel, drive, drvp->UDMA_mode); 167 } else if (drvp->drive_flags & DRIVE_DMA) { 168 IXP_UDMA_DISABLE(udma, chp->ch_channel, drive); 169 IXP_SET_TIMING(mdma_timing, chp->ch_channel, drive, 170 ixp_mdma_timings[drvp->DMA_mode]); 171 } else 172 IXP_UDMA_DISABLE(udma, chp->ch_channel, drive); 173 174 /* 175 * Set PIO mode and timings 176 * Linux driver avoids PIO mode 1, let's do it too. 177 */ 178 if (drvp->PIO_mode == 1) 179 drvp->PIO_mode = 0; 180 181 IXP_SET_MODE(pio, chp->ch_channel, drive, drvp->PIO_mode); 182 IXP_SET_TIMING(pio_timing, chp->ch_channel, drive, 183 ixp_pio_timings[drvp->PIO_mode]); 184 } 185 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_UDMA_CTL, udma); 186 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_MDMA_TIMING, mdma_timing); 187 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_PIO_CTL, pio); 188 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_PIO_TIMING, pio_timing); 189 ATADEBUG_PRINT(("ixp_setup_channel: udma = %08x, mdma_timing = %08x, pio_mode = %08x," 190 " pio_timing = %08x\n", udma, mdma_timing, pio, pio_timing), DEBUG_PROBE); 191 } 192
Indexes created Mon Oct 13 16:09:52 GMT 2025