jmide.c revision 1.11.6.1
1 /* $NetBSD: jmide.c,v 1.11.6.1 2012/02/18 07:34:44 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: jmide.c,v 1.11.6.1 2012/02/18 07:34:44 mrg Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 39 #include <dev/pci/jmide_reg.h> 40 41 #include <dev/ic/ahcisatavar.h> 42 43 #include "jmide.h" 44 45 static const struct jmide_product *jmide_lookup(pcireg_t); 46 47 static int jmide_match(device_t, cfdata_t, void *); 48 static void jmide_attach(device_t, device_t, void *); 49 static int jmide_intr(void *); 50 51 static void jmpata_chip_map(struct pciide_softc*, const struct pci_attach_args*); 52 static void jmpata_setup_channel(struct ata_channel*); 53 54 static int jmahci_print(void *, const char *); 55 56 struct jmide_product { 57 u_int32_t jm_product; 58 int jm_npata; 59 int jm_nsata; 60 }; 61 62 static const struct jmide_product jm_products[] = { 63 { PCI_PRODUCT_JMICRON_JMB360, 64 0, 65 1 66 }, 67 { PCI_PRODUCT_JMICRON_JMB361, 68 1, 69 1 70 }, 71 { PCI_PRODUCT_JMICRON_JMB363, 72 1, 73 2 74 }, 75 { PCI_PRODUCT_JMICRON_JMB365, 76 2, 77 1 78 }, 79 { PCI_PRODUCT_JMICRON_JMB366, 80 2, 81 2 82 }, 83 { PCI_PRODUCT_JMICRON_JMB368, 84 1, 85 0 86 }, 87 { 0, 88 0, 89 0 90 } 91 }; 92 93 typedef enum { 94 TYPE_INVALID = 0, 95 TYPE_PATA, 96 TYPE_SATA, 97 TYPE_NONE 98 } jmchan_t; 99 100 struct jmide_softc { 101 struct pciide_softc sc_pciide; 102 device_t sc_ahci; 103 int sc_npata; 104 int sc_nsata; 105 jmchan_t sc_chan_type[PCIIDE_NUM_CHANNELS]; 106 int sc_chan_swap; 107 }; 108 109 struct jmahci_attach_args { 110 const struct pci_attach_args *jma_pa; 111 bus_space_tag_t jma_ahcit; 112 bus_space_handle_t jma_ahcih; 113 }; 114 115 #define JM_NAME(sc) (device_xname(sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev)) 116 117 CFATTACH_DECL_NEW(jmide, sizeof(struct jmide_softc), 118 jmide_match, jmide_attach, NULL, NULL); 119 120 static const struct jmide_product * 121 jmide_lookup(pcireg_t id) { 122 const struct jmide_product *jp; 123 124 for (jp = jm_products; jp->jm_product != 0; jp++) { 125 if (jp->jm_product == PCI_PRODUCT(id)) 126 return jp; 127 } 128 return NULL; 129 } 130 131 static int 132 jmide_match(device_t parent, cfdata_t match, void *aux) 133 { 134 struct pci_attach_args *pa = aux; 135 136 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_JMICRON) { 137 if (jmide_lookup(pa->pa_id)) 138 return (4); /* higher than ahcisata */ 139 } 140 return (0); 141 } 142 143 static void 144 jmide_attach(device_t parent, device_t self, void *aux) 145 { 146 struct pci_attach_args *pa = aux; 147 struct jmide_softc *sc = device_private(self); 148 const struct jmide_product *jp; 149 const char *intrstr; 150 pci_intr_handle_t intrhandle; 151 u_int32_t pcictrl0 = pci_conf_read(pa->pa_pc, pa->pa_tag, 152 PCI_JM_CONTROL0); 153 u_int32_t pcictrl1 = pci_conf_read(pa->pa_pc, pa->pa_tag, 154 PCI_JM_CONTROL1); 155 struct pciide_product_desc *pp; 156 int ahci_used = 0; 157 158 sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev = self; 159 160 jp = jmide_lookup(pa->pa_id); 161 if (jp == NULL) { 162 printf("jmide_attach: WTF?\n"); 163 return; 164 } 165 sc->sc_npata = jp->jm_npata; 166 sc->sc_nsata = jp->jm_nsata; 167 168 pci_aprint_devinfo(pa, "JMICRON PATA/SATA disk controller"); 169 170 aprint_normal("%s: ", JM_NAME(sc)); 171 if (sc->sc_npata) 172 aprint_normal("%d PATA port%s", sc->sc_npata, 173 (sc->sc_npata > 1) ? "s" : ""); 174 if (sc->sc_nsata) 175 aprint_normal("%s%d SATA port%s", sc->sc_npata ? ", " : "", 176 sc->sc_nsata, (sc->sc_nsata > 1) ? "s" : ""); 177 aprint_normal("\n"); 178 179 if (pci_intr_map(pa, &intrhandle) != 0) { 180 aprint_error("%s: couldn't map interrupt\n", JM_NAME(sc)); 181 return; 182 } 183 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 184 sc->sc_pciide.sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, 185 IPL_BIO, jmide_intr, sc); 186 if (sc->sc_pciide.sc_pci_ih == NULL) { 187 aprint_error("%s: couldn't establish interrupt", JM_NAME(sc)); 188 return; 189 } 190 aprint_normal("%s: interrupting at %s\n", JM_NAME(sc), 191 intrstr ? intrstr : "unknown interrupt"); 192 193 if (pcictrl0 & JM_CONTROL0_AHCI_EN) { 194 bus_size_t size; 195 struct jmahci_attach_args jma; 196 u_int32_t saved_pcictrl0; 197 /* 198 * ahci controller enabled; disable sata on pciide and 199 * enable on ahci 200 */ 201 saved_pcictrl0 = pcictrl0; 202 pcictrl0 |= JM_CONTROL0_SATA0_AHCI | JM_CONTROL0_SATA1_AHCI; 203 pcictrl0 &= ~(JM_CONTROL0_SATA0_IDE | JM_CONTROL0_SATA1_IDE); 204 pci_conf_write(pa->pa_pc, pa->pa_tag, 205 PCI_JM_CONTROL0, pcictrl0); 206 /* attach ahci controller if on the right function */ 207 if ((pa->pa_function == 0 && 208 (pcictrl0 & JM_CONTROL0_AHCI_F1) == 0) || 209 (pa->pa_function == 1 && 210 (pcictrl0 & JM_CONTROL0_AHCI_F1) != 0)) { 211 jma.jma_pa = pa; 212 /* map registers */ 213 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 214 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 215 &jma.jma_ahcit, &jma.jma_ahcih, NULL, &size) != 0) { 216 aprint_error("%s: can't map ahci registers\n", 217 JM_NAME(sc)); 218 } else { 219 sc->sc_ahci = config_found_ia( 220 sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev, 221 "jmide_hl", &jma, jmahci_print); 222 } 223 /* 224 * if we couldn't attach an ahci, try to fall back 225 * to pciide. Note that this will not work if IDE 226 * is on function 0 and AHCI on function 1. 227 */ 228 if (sc->sc_ahci == NULL) { 229 pcictrl0 = saved_pcictrl0 & 230 ~(JM_CONTROL0_SATA0_AHCI | 231 JM_CONTROL0_SATA1_AHCI | 232 JM_CONTROL0_AHCI_EN); 233 pcictrl0 |= JM_CONTROL0_SATA1_IDE | 234 JM_CONTROL0_SATA0_IDE; 235 pci_conf_write(pa->pa_pc, pa->pa_tag, 236 PCI_JM_CONTROL0, pcictrl0); 237 } else 238 ahci_used = 1; 239 } 240 } 241 sc->sc_chan_swap = ((pcictrl0 & JM_CONTROL0_PCIIDE_CS) != 0); 242 /* compute the type of internal primary channel */ 243 if (pcictrl1 & JM_CONTROL1_PATA1_PRI) { 244 if (sc->sc_npata > 1) 245 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_PATA; 246 else 247 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE; 248 } else if (ahci_used == 0 && sc->sc_nsata > 0) 249 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_SATA; 250 else 251 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE; 252 /* compute the type of internal secondary channel */ 253 if (sc->sc_nsata > 1 && ahci_used == 0 && 254 (pcictrl0 & JM_CONTROL0_PCIIDE0_MS) == 0) { 255 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_SATA; 256 } else { 257 /* only a drive if first PATA enabled */ 258 if (sc->sc_npata > 0 && (pcictrl0 & JM_CONTROL0_PATA0_EN) 259 && (pcictrl0 & 260 (sc->sc_chan_swap ? JM_CONTROL0_PATA0_PRI: JM_CONTROL0_PATA0_SEC))) 261 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_PATA; 262 else 263 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE; 264 } 265 266 if (sc->sc_chan_type[0] == TYPE_NONE && 267 sc->sc_chan_type[1] == TYPE_NONE) 268 return; 269 if (pa->pa_function == 0 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1)) 270 return; 271 if (pa->pa_function == 1 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1) == 0) 272 return; 273 pp = malloc(sizeof(struct pciide_product_desc), M_DEVBUF, M_NOWAIT); 274 if (pp == NULL) { 275 aprint_error("%s: can't malloc sc_pp\n", JM_NAME(sc)); 276 return; 277 } 278 aprint_normal("%s: PCI IDE interface used", JM_NAME(sc)); 279 pp->ide_product = 0; 280 pp->ide_flags = 0; 281 pp->ide_name = NULL; 282 pp->chip_map = jmpata_chip_map; 283 pciide_common_attach(&sc->sc_pciide, pa, pp); 284 285 } 286 287 static int 288 jmide_intr(void *arg) 289 { 290 struct jmide_softc *sc = arg; 291 int ret = 0; 292 293 #ifdef NJMAHCI 294 if (sc->sc_ahci) 295 ret |= ahci_intr(device_private(sc->sc_ahci)); 296 #endif 297 if (sc->sc_npata) 298 ret |= pciide_pci_intr(&sc->sc_pciide); 299 return ret; 300 } 301 302 static void 303 jmpata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 304 { 305 struct jmide_softc *jmidesc = (struct jmide_softc *)sc; 306 int channel; 307 pcireg_t interface; 308 struct pciide_channel *cp; 309 310 if (pciide_chipen(sc, pa) == 0) 311 return; 312 aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc)); 313 pciide_mapreg_dma(sc, pa); 314 aprint_verbose("\n"); 315 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 316 if (sc->sc_dma_ok) { 317 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 318 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 319 } 320 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 321 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 322 sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel; 323 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 324 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 325 wdc_allocate_regs(&sc->sc_wdcdev); 326 /* 327 * can't rely on the PCI_CLASS_REG content if the chip was in raid 328 * mode. We have to fake interface 329 */ 330 interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 331 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 332 channel++) { 333 cp = &sc->pciide_channels[channel]; 334 if (pciide_chansetup(sc, channel, interface) == 0) 335 continue; 336 aprint_normal("%s: %s channel is ", JM_NAME(jmidesc), 337 PCIIDE_CHANNEL_NAME(channel)); 338 switch(jmidesc->sc_chan_type[channel]) { 339 case TYPE_PATA: 340 aprint_normal("PATA"); 341 break; 342 case TYPE_SATA: 343 aprint_normal("SATA"); 344 break; 345 case TYPE_NONE: 346 aprint_normal("unused"); 347 break; 348 default: 349 aprint_normal("impossible"); 350 panic("jmide: wrong/uninitialised channel type"); 351 } 352 aprint_normal("\n"); 353 if (jmidesc->sc_chan_type[channel] == TYPE_NONE) { 354 cp->ata_channel.ch_flags |= ATACH_DISABLED; 355 continue; 356 } 357 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 358 } 359 } 360 361 static void 362 jmpata_setup_channel(struct ata_channel *chp) 363 { 364 struct ata_drive_datas *drvp; 365 int drive, s; 366 u_int32_t idedma_ctl; 367 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 368 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 369 struct jmide_softc *jmidesc = (struct jmide_softc *)sc; 370 int ide80p; 371 372 /* setup DMA if needed */ 373 pciide_channel_dma_setup(cp); 374 375 idedma_ctl = 0; 376 377 /* cable type detect */ 378 ide80p = 1; 379 if (chp->ch_channel == (jmidesc->sc_chan_swap ? 1 : 0)) { 380 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA && 381 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL1) & 382 JM_CONTROL1_PATA1_40P)) 383 ide80p = 0; 384 } else { 385 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA && 386 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL0) & 387 JM_CONTROL0_PATA0_40P)) 388 ide80p = 0; 389 } 390 391 for (drive = 0; drive < 2; drive++) { 392 drvp = &chp->ch_drive[drive]; 393 /* If no drive, skip */ 394 if ((drvp->drive_flags & DRIVE) == 0) 395 continue; 396 if (drvp->drive_flags & DRIVE_UDMA) { 397 /* use Ultra/DMA */ 398 s = splbio(); 399 drvp->drive_flags &= ~DRIVE_DMA; 400 if (drvp->UDMA_mode > 2 && ide80p == 0) 401 drvp->UDMA_mode = 2; 402 splx(s); 403 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 404 } else if (drvp->drive_flags & DRIVE_DMA) { 405 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 406 } 407 } 408 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 409 if (idedma_ctl != 0) { 410 /* Add software bits in status register */ 411 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 412 0, idedma_ctl); 413 } 414 } 415 416 static int 417 jmahci_print(void *aux, const char *pnp) 418 { 419 if (pnp) 420 aprint_normal("ahcisata at %s", pnp); 421 422 return (UNCONF); 423 } 424 425 426 #ifdef NJMAHCI 427 static int jmahci_match(device_t, cfdata_t, void *); 428 static void jmahci_attach(device_t, device_t, void *); 429 static int jmahci_detach(device_t, int); 430 static bool jmahci_resume(device_t, const pmf_qual_t *); 431 432 CFATTACH_DECL_NEW(jmahci, sizeof(struct ahci_softc), 433 jmahci_match, jmahci_attach, jmahci_detach, NULL); 434 435 static int 436 jmahci_match(device_t parent, cfdata_t match, void *aux) 437 { 438 return 1; 439 } 440 441 static void 442 jmahci_attach(device_t parent, device_t self, void *aux) 443 { 444 struct jmahci_attach_args *jma = aux; 445 const struct pci_attach_args *pa = jma->jma_pa; 446 struct ahci_softc *sc = device_private(self); 447 uint32_t ahci_cap; 448 449 aprint_naive(": AHCI disk controller\n"); 450 aprint_normal("\n"); 451 452 sc->sc_atac.atac_dev = self; 453 sc->sc_ahcit = jma->jma_ahcit; 454 sc->sc_ahcih = jma->jma_ahcih; 455 456 ahci_cap = AHCI_READ(sc, AHCI_CAP); 457 458 if (pci_dma64_available(jma->jma_pa) && (ahci_cap & AHCI_CAP_64BIT)) 459 sc->sc_dmat = jma->jma_pa->pa_dmat64; 460 else 461 sc->sc_dmat = jma->jma_pa->pa_dmat; 462 463 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 464 sc->sc_atac_capflags = ATAC_CAP_RAID; 465 466 ahci_attach(sc); 467 468 if (!pmf_device_register(self, NULL, jmahci_resume)) 469 aprint_error_dev(self, "couldn't establish power handler\n"); 470 } 471 472 static int 473 jmahci_detach(device_t dv, int flags) 474 { 475 struct ahci_softc *sc; 476 sc = device_private(dv); 477 478 int rv; 479 480 if ((rv = ahci_detach(sc, flags))) 481 return rv; 482 483 return 0; 484 } 485 486 static bool 487 jmahci_resume(device_t dv, const pmf_qual_t *qual) 488 { 489 struct ahci_softc *sc; 490 int s; 491 492 sc = device_private(dv); 493 494 s = splbio(); 495 ahci_resume(sc); 496 splx(s); 497 498 return true; 499 } 500 #endif 501
Indexes created Wed Oct 15 16:09:53 GMT 2025