jmide.c revision 1.18.2.3
1 /* $NetBSD: jmide.c,v 1.18.2.3 2017/12/03 11:37:08 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: jmide.c,v 1.18.2.3 2017/12/03 11:37:08 jdolecek Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 39 #include <dev/pci/jmide_reg.h> 40 41 #include <dev/ic/ahcisatavar.h> 42 43 #include "jmide.h" 44 45 static const struct jmide_product *jmide_lookup(pcireg_t); 46 47 static int jmide_match(device_t, cfdata_t, void *); 48 static void jmide_attach(device_t, device_t, void *); 49 static int jmide_intr(void *); 50 51 static void jmpata_chip_map(struct pciide_softc*, 52 const struct pci_attach_args*); 53 static void jmpata_setup_channel(struct ata_channel*); 54 55 static int jmahci_print(void *, const char *); 56 57 struct jmide_product { 58 u_int32_t jm_product; 59 int jm_npata; 60 int jm_nsata; 61 }; 62 63 static const struct jmide_product jm_products[] = { 64 { PCI_PRODUCT_JMICRON_JMB360, 65 0, 66 1 67 }, 68 { PCI_PRODUCT_JMICRON_JMB361, 69 1, 70 1 71 }, 72 { PCI_PRODUCT_JMICRON_JMB362, 73 0, 74 2 75 }, 76 { PCI_PRODUCT_JMICRON_JMB363, 77 1, 78 2 79 }, 80 { PCI_PRODUCT_JMICRON_JMB365, 81 2, 82 1 83 }, 84 { PCI_PRODUCT_JMICRON_JMB366, 85 2, 86 2 87 }, 88 { PCI_PRODUCT_JMICRON_JMB368, 89 1, 90 0 91 }, 92 { 0, 93 0, 94 0 95 } 96 }; 97 98 typedef enum { 99 TYPE_INVALID = 0, 100 TYPE_PATA, 101 TYPE_SATA, 102 TYPE_NONE 103 } jmchan_t; 104 105 struct jmide_softc { 106 struct pciide_softc sc_pciide; 107 device_t sc_ahci; 108 int sc_npata; 109 int sc_nsata; 110 jmchan_t sc_chan_type[PCIIDE_NUM_CHANNELS]; 111 int sc_chan_swap; 112 }; 113 114 struct jmahci_attach_args { 115 const struct pci_attach_args *jma_pa; 116 bus_space_tag_t jma_ahcit; 117 bus_space_handle_t jma_ahcih; 118 }; 119 120 #define JM_NAME(sc) (device_xname(sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev)) 121 122 CFATTACH_DECL_NEW(jmide, sizeof(struct jmide_softc), 123 jmide_match, jmide_attach, NULL, NULL); 124 125 static const struct jmide_product * 126 jmide_lookup(pcireg_t id) { 127 const struct jmide_product *jp; 128 129 for (jp = jm_products; jp->jm_product != 0; jp++) { 130 if (jp->jm_product == PCI_PRODUCT(id)) 131 return jp; 132 } 133 return NULL; 134 } 135 136 static int 137 jmide_match(device_t parent, cfdata_t match, void *aux) 138 { 139 struct pci_attach_args *pa = aux; 140 141 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_JMICRON) { 142 if (jmide_lookup(pa->pa_id)) 143 return (4); /* higher than ahcisata */ 144 } 145 return (0); 146 } 147 148 static void 149 jmide_attach(device_t parent, device_t self, void *aux) 150 { 151 struct pci_attach_args *pa = aux; 152 struct jmide_softc *sc = device_private(self); 153 const struct jmide_product *jp; 154 const char *intrstr; 155 pci_intr_handle_t intrhandle; 156 u_int32_t pcictrl0 = pci_conf_read(pa->pa_pc, pa->pa_tag, 157 PCI_JM_CONTROL0); 158 u_int32_t pcictrl1 = pci_conf_read(pa->pa_pc, pa->pa_tag, 159 PCI_JM_CONTROL1); 160 struct pciide_product_desc *pp; 161 int ahci_used = 0; 162 char intrbuf[PCI_INTRSTR_LEN]; 163 164 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 165 166 aprint_naive("\n"); 167 sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev = self; 168 169 jp = jmide_lookup(pa->pa_id); 170 if (jp == NULL) { 171 aprint_error_dev(self, "jmide_attach: WTF?\n"); 172 return; 173 } 174 sc->sc_npata = jp->jm_npata; 175 sc->sc_nsata = jp->jm_nsata; 176 177 pci_aprint_devinfo(pa, "JMICRON PATA/SATA disk controller"); 178 179 aprint_normal("%s: ", JM_NAME(sc)); 180 if (sc->sc_npata) 181 aprint_normal("%d PATA port%s", sc->sc_npata, 182 (sc->sc_npata > 1) ? "s" : ""); 183 if (sc->sc_nsata) 184 aprint_normal("%s%d SATA port%s", sc->sc_npata ? ", " : "", 185 sc->sc_nsata, (sc->sc_nsata > 1) ? "s" : ""); 186 aprint_normal("\n"); 187 188 if (pci_intr_map(pa, &intrhandle) != 0) { 189 aprint_error("%s: couldn't map interrupt\n", JM_NAME(sc)); 190 return; 191 } 192 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 193 sizeof(intrbuf)); 194 sc->sc_pciide.sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, 195 IPL_BIO, jmide_intr, sc); 196 if (sc->sc_pciide.sc_pci_ih == NULL) { 197 aprint_error("%s: couldn't establish interrupt", JM_NAME(sc)); 198 return; 199 } 200 aprint_normal("%s: interrupting at %s\n", JM_NAME(sc), 201 intrstr ? intrstr : "unknown interrupt"); 202 203 if (pcictrl0 & JM_CONTROL0_AHCI_EN) { 204 bus_size_t size; 205 struct jmahci_attach_args jma; 206 u_int32_t saved_pcictrl0; 207 /* 208 * ahci controller enabled; disable sata on pciide and 209 * enable on ahci 210 */ 211 saved_pcictrl0 = pcictrl0; 212 pcictrl0 |= JM_CONTROL0_SATA0_AHCI | JM_CONTROL0_SATA1_AHCI; 213 pcictrl0 &= ~(JM_CONTROL0_SATA0_IDE | JM_CONTROL0_SATA1_IDE); 214 pci_conf_write(pa->pa_pc, pa->pa_tag, 215 PCI_JM_CONTROL0, pcictrl0); 216 /* attach ahci controller if on the right function */ 217 if ((pa->pa_function == 0 && 218 (pcictrl0 & JM_CONTROL0_AHCI_F1) == 0) || 219 (pa->pa_function == 1 && 220 (pcictrl0 & JM_CONTROL0_AHCI_F1) != 0)) { 221 jma.jma_pa = pa; 222 /* map registers */ 223 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 224 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 225 &jma.jma_ahcit, &jma.jma_ahcih, NULL, &size) != 0) { 226 aprint_error("%s: can't map ahci registers\n", 227 JM_NAME(sc)); 228 } else { 229 sc->sc_ahci = config_found_ia( 230 sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev, 231 "jmide_hl", &jma, jmahci_print); 232 } 233 /* 234 * if we couldn't attach an ahci, try to fall back 235 * to pciide. Note that this will not work if IDE 236 * is on function 0 and AHCI on function 1. 237 */ 238 if (sc->sc_ahci == NULL) { 239 pcictrl0 = saved_pcictrl0 & 240 ~(JM_CONTROL0_SATA0_AHCI | 241 JM_CONTROL0_SATA1_AHCI | 242 JM_CONTROL0_AHCI_EN); 243 pcictrl0 |= JM_CONTROL0_SATA1_IDE | 244 JM_CONTROL0_SATA0_IDE; 245 pci_conf_write(pa->pa_pc, pa->pa_tag, 246 PCI_JM_CONTROL0, pcictrl0); 247 } else 248 ahci_used = 1; 249 } 250 } 251 sc->sc_chan_swap = ((pcictrl0 & JM_CONTROL0_PCIIDE_CS) != 0); 252 /* compute the type of internal primary channel */ 253 if (pcictrl1 & JM_CONTROL1_PATA1_PRI) { 254 if (sc->sc_npata > 1) 255 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_PATA; 256 else 257 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE; 258 } else if (ahci_used == 0 && sc->sc_nsata > 0) 259 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_SATA; 260 else 261 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE; 262 /* compute the type of internal secondary channel */ 263 if (sc->sc_nsata > 1 && ahci_used == 0 && 264 (pcictrl0 & JM_CONTROL0_PCIIDE0_MS) == 0) { 265 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_SATA; 266 } else { 267 /* only a drive if first PATA enabled */ 268 if (sc->sc_npata > 0 && (pcictrl0 & JM_CONTROL0_PATA0_EN) 269 && (pcictrl0 & 270 (sc->sc_chan_swap ? JM_CONTROL0_PATA0_PRI: JM_CONTROL0_PATA0_SEC))) 271 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_PATA; 272 else 273 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE; 274 } 275 276 if (sc->sc_chan_type[0] == TYPE_NONE && 277 sc->sc_chan_type[1] == TYPE_NONE) 278 return; 279 if (pa->pa_function == 0 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1)) 280 return; 281 if (pa->pa_function == 1 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1) == 0) 282 return; 283 pp = malloc(sizeof(struct pciide_product_desc), M_DEVBUF, M_NOWAIT); 284 if (pp == NULL) { 285 aprint_error("%s: can't malloc sc_pp\n", JM_NAME(sc)); 286 return; 287 } 288 aprint_normal("%s: PCI IDE interface used", JM_NAME(sc)); 289 pp->ide_product = 0; 290 pp->ide_flags = 0; 291 pp->ide_name = NULL; 292 pp->chip_map = jmpata_chip_map; 293 pciide_common_attach(&sc->sc_pciide, pa, pp); 294 } 295 296 static int 297 jmide_intr(void *arg) 298 { 299 struct jmide_softc *sc = arg; 300 int ret = 0; 301 302 #ifdef NJMAHCI 303 if (sc->sc_ahci) 304 ret |= ahci_intr(device_private(sc->sc_ahci)); 305 #endif 306 if (sc->sc_npata) 307 ret |= pciide_pci_intr(&sc->sc_pciide); 308 return ret; 309 } 310 311 static void 312 jmpata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 313 { 314 struct jmide_softc *jmidesc = (struct jmide_softc *)sc; 315 int channel; 316 pcireg_t interface; 317 struct pciide_channel *cp; 318 319 if (pciide_chipen(sc, pa) == 0) 320 return; 321 aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc)); 322 pciide_mapreg_dma(sc, pa); 323 aprint_verbose("\n"); 324 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 325 if (sc->sc_dma_ok) { 326 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 327 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 328 } 329 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 330 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 331 sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel; 332 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 333 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 334 sc->sc_wdcdev.wdc_maxdrives = 2; 335 wdc_allocate_regs(&sc->sc_wdcdev); 336 /* 337 * can't rely on the PCI_CLASS_REG content if the chip was in raid 338 * mode. We have to fake interface 339 */ 340 interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 341 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 342 channel++) { 343 cp = &sc->pciide_channels[channel]; 344 if (pciide_chansetup(sc, channel, interface) == 0) 345 continue; 346 aprint_normal("%s: %s channel is ", JM_NAME(jmidesc), 347 PCIIDE_CHANNEL_NAME(channel)); 348 switch(jmidesc->sc_chan_type[channel]) { 349 case TYPE_PATA: 350 aprint_normal("PATA"); 351 break; 352 case TYPE_SATA: 353 aprint_normal("SATA"); 354 break; 355 case TYPE_NONE: 356 aprint_normal("unused"); 357 break; 358 default: 359 aprint_normal("impossible"); 360 panic("jmide: wrong/uninitialised channel type"); 361 } 362 aprint_normal("\n"); 363 if (jmidesc->sc_chan_type[channel] == TYPE_NONE) { 364 cp->ata_channel.ch_flags |= ATACH_DISABLED; 365 continue; 366 } 367 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 368 } 369 } 370 371 static void 372 jmpata_setup_channel(struct ata_channel *chp) 373 { 374 struct ata_drive_datas *drvp; 375 int drive, s; 376 u_int32_t idedma_ctl; 377 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 378 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 379 struct jmide_softc *jmidesc = (struct jmide_softc *)sc; 380 int ide80p; 381 382 /* setup DMA if needed */ 383 pciide_channel_dma_setup(cp); 384 385 idedma_ctl = 0; 386 387 /* cable type detect */ 388 ide80p = 1; 389 if (chp->ch_channel == (jmidesc->sc_chan_swap ? 1 : 0)) { 390 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA && 391 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL1) & 392 JM_CONTROL1_PATA1_40P)) 393 ide80p = 0; 394 } else { 395 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA && 396 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL0) & 397 JM_CONTROL0_PATA0_40P)) 398 ide80p = 0; 399 } 400 401 for (drive = 0; drive < 2; drive++) { 402 drvp = &chp->ch_drive[drive]; 403 /* If no drive, skip */ 404 if (drvp->drive_type == ATA_DRIVET_NONE) 405 continue; 406 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 407 /* use Ultra/DMA */ 408 s = splbio(); 409 drvp->drive_flags &= ~ATA_DRIVE_DMA; 410 if (drvp->UDMA_mode > 2 && ide80p == 0) 411 drvp->UDMA_mode = 2; 412 splx(s); 413 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 414 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 415 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 416 } 417 } 418 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 419 if (idedma_ctl != 0) { 420 /* Add software bits in status register */ 421 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 422 0, idedma_ctl); 423 } 424 } 425 426 static int 427 jmahci_print(void *aux, const char *pnp) 428 { 429 if (pnp) 430 aprint_normal("ahcisata at %s", pnp); 431 432 return (UNCONF); 433 } 434 435 436 #ifdef NJMAHCI 437 static int jmahci_match(device_t, cfdata_t, void *); 438 static void jmahci_attach(device_t, device_t, void *); 439 static int jmahci_detach(device_t, int); 440 static bool jmahci_resume(device_t, const pmf_qual_t *); 441 442 CFATTACH_DECL_NEW(jmahci, sizeof(struct ahci_softc), 443 jmahci_match, jmahci_attach, jmahci_detach, NULL); 444 445 static int 446 jmahci_match(device_t parent, cfdata_t match, void *aux) 447 { 448 return 1; 449 } 450 451 static void 452 jmahci_attach(device_t parent, device_t self, void *aux) 453 { 454 struct jmahci_attach_args *jma = aux; 455 const struct pci_attach_args *pa = jma->jma_pa; 456 struct ahci_softc *sc = device_private(self); 457 uint32_t ahci_cap; 458 459 aprint_naive(": AHCI disk controller\n"); 460 aprint_normal("\n"); 461 462 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 463 464 sc->sc_atac.atac_dev = self; 465 sc->sc_ahcit = jma->jma_ahcit; 466 sc->sc_ahcih = jma->jma_ahcih; 467 468 ahci_cap = AHCI_READ(sc, AHCI_CAP); 469 470 if (pci_dma64_available(jma->jma_pa) && (ahci_cap & AHCI_CAP_64BIT)) 471 sc->sc_dmat = jma->jma_pa->pa_dmat64; 472 else 473 sc->sc_dmat = jma->jma_pa->pa_dmat; 474 475 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 476 sc->sc_atac_capflags = ATAC_CAP_RAID; 477 478 ahci_attach(sc); 479 480 if (!pmf_device_register(self, NULL, jmahci_resume)) 481 aprint_error_dev(self, "couldn't establish power handler\n"); 482 } 483 484 static int 485 jmahci_detach(device_t dv, int flags) 486 { 487 struct ahci_softc *sc; 488 sc = device_private(dv); 489 490 int rv; 491 492 if ((rv = ahci_detach(sc, flags))) 493 return rv; 494 495 return 0; 496 } 497 498 static bool 499 jmahci_resume(device_t dv, const pmf_qual_t *qual) 500 { 501 struct ahci_softc *sc; 502 int s; 503 504 sc = device_private(dv); 505 506 s = splbio(); 507 ahci_resume(sc); 508 splx(s); 509 510 return true; 511 } 512 #endif 513
Indexes created Wed Oct 15 16:09:53 GMT 2025