jmide.c revision 1.3
1 /* $NetBSD: jmide.c,v 1.3 2008/02/11 08:23:48 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: jmide.c,v 1.3 2008/02/11 08:23:48 xtraeme Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 44 #include <dev/pci/jmide_reg.h> 45 46 #include <dev/ic/ahcisatavar.h> 47 48 #include "jmide.h" 49 50 static const struct jmide_product *jmide_lookup(pcireg_t); 51 52 static int jmide_match(struct device *, struct cfdata *, void *); 53 static void jmide_attach(struct device *, struct device *, void *); 54 static int jmide_intr(void *); 55 56 static void jmpata_chip_map(struct pciide_softc*, struct pci_attach_args*); 57 static void jmpata_setup_channel(struct ata_channel*); 58 59 static int jmahci_print(void *, const char *); 60 61 struct jmide_product { 62 u_int32_t jm_product; 63 int jm_npata; 64 int jm_nsata; 65 }; 66 67 static const struct jmide_product jm_products[] = { 68 { PCI_PRODUCT_JMICRON_JMB360, 69 0, 70 1 71 }, 72 { PCI_PRODUCT_JMICRON_JMB361, 73 1, 74 1 75 }, 76 { PCI_PRODUCT_JMICRON_JMB363, 77 1, 78 2 79 }, 80 { PCI_PRODUCT_JMICRON_JMB365, 81 2, 82 1 83 }, 84 { PCI_PRODUCT_JMICRON_JMB366, 85 2, 86 2 87 }, 88 { PCI_PRODUCT_JMICRON_JMB368, 89 1, 90 0 91 }, 92 { 0, 93 0, 94 0 95 } 96 }; 97 98 typedef enum { 99 TYPE_INVALID = 0, 100 TYPE_PATA, 101 TYPE_SATA, 102 TYPE_NONE 103 } jmchan_t; 104 105 struct jmide_softc { 106 struct pciide_softc sc_pciide; 107 void *sc_ahci; 108 int sc_npata; 109 int sc_nsata; 110 jmchan_t sc_chan_type[PCIIDE_NUM_CHANNELS]; 111 int sc_chan_swap; 112 }; 113 114 struct jmahci_attach_args { 115 struct pci_attach_args *jma_pa; 116 bus_space_tag_t jma_ahcit; 117 bus_space_handle_t jma_ahcih; 118 }; 119 120 #define JM_NAME(sc) (sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev.dv_xname) 121 122 CFATTACH_DECL(jmide, sizeof(struct jmide_softc), 123 jmide_match, jmide_attach, NULL, NULL); 124 125 static const struct jmide_product * 126 jmide_lookup(pcireg_t id) { 127 const struct jmide_product *jp; 128 129 for (jp = jm_products; jp->jm_product != 0; jp++) { 130 if (jp->jm_product == PCI_PRODUCT(id)) 131 return jp; 132 } 133 return NULL; 134 } 135 136 static int 137 jmide_match(struct device *parent, struct cfdata *match, 138 void *aux) 139 { 140 struct pci_attach_args *pa = aux; 141 142 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_JMICRON) { 143 if (jmide_lookup(pa->pa_id)) 144 return (4); /* highter than ahcisata */ 145 } 146 return (0); 147 } 148 149 static void 150 jmide_attach(struct device *parent, struct device *self, void *aux) 151 { 152 struct pci_attach_args *pa = aux; 153 struct jmide_softc *sc = (struct jmide_softc *)self; 154 const struct jmide_product *jp; 155 char devinfo[256]; 156 const char *intrstr; 157 pci_intr_handle_t intrhandle; 158 u_int32_t pcictrl0 = pci_conf_read(pa->pa_pc, pa->pa_tag, 159 PCI_JM_CONTROL0); 160 u_int32_t pcictrl1 = pci_conf_read(pa->pa_pc, pa->pa_tag, 161 PCI_JM_CONTROL1); 162 struct pciide_product_desc *pp; 163 int ahci_used = 0; 164 165 jp = jmide_lookup(pa->pa_id); 166 if (jp == NULL) { 167 printf("jmide_attach: WTF?\n"); 168 return; 169 } 170 sc->sc_npata = jp->jm_npata; 171 sc->sc_nsata = jp->jm_nsata; 172 173 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 174 aprint_naive(": JMICRON PATA/SATA disk controller\n"); 175 aprint_normal(": %s\n", devinfo); 176 177 aprint_normal("%s: ", JM_NAME(sc)); 178 if (sc->sc_npata) 179 aprint_normal("%d PATA port%s", sc->sc_npata, 180 (sc->sc_npata > 1) ? "s" : ""); 181 if (sc->sc_nsata) 182 aprint_normal("%s%d SATA port%s", sc->sc_npata ? ", " : "", 183 sc->sc_nsata, (sc->sc_nsata > 1) ? "s" : ""); 184 aprint_normal("\n"); 185 186 if (pci_intr_map(pa, &intrhandle) != 0) { 187 aprint_error("%s: couldn't map interrupt\n", JM_NAME(sc)); 188 return; 189 } 190 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 191 sc->sc_pciide.sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, 192 IPL_BIO, jmide_intr, sc); 193 if (sc->sc_pciide.sc_pci_ih == NULL) { 194 aprint_error("%s: couldn't establish interrupt", JM_NAME(sc)); 195 return; 196 } 197 aprint_normal("%s: interrupting at %s\n", JM_NAME(sc), 198 intrstr ? intrstr : "unknown interrupt"); 199 200 if (pcictrl0 & JM_CONTROL0_AHCI_EN) { 201 bus_size_t size; 202 struct jmahci_attach_args jma; 203 u_int32_t saved_pcictrl0; 204 /* 205 * ahci controller enabled; disable sata on pciide and 206 * enable on ahci 207 */ 208 saved_pcictrl0 = pcictrl0; 209 pcictrl0 |= JM_CONTROL0_SATA0_AHCI | JM_CONTROL0_SATA1_AHCI; 210 pcictrl0 &= ~(JM_CONTROL0_SATA0_IDE | JM_CONTROL0_SATA1_IDE); 211 pci_conf_write(pa->pa_pc, pa->pa_tag, 212 PCI_JM_CONTROL0, pcictrl0); 213 /* attach ahci controller if on the right function */ 214 if ((pa->pa_function == 0 && 215 (pcictrl0 & JM_CONTROL0_AHCI_F1) == 0) || 216 (pa->pa_function == 1 && 217 (pcictrl0 & JM_CONTROL0_AHCI_F1) != 0)) { 218 jma.jma_pa = pa; 219 /* map registers */ 220 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 221 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 222 &jma.jma_ahcit, &jma.jma_ahcih, NULL, &size) != 0) { 223 aprint_error("%s: can't map ahci registers\n", 224 JM_NAME(sc)); 225 } else { 226 sc->sc_ahci = config_found_ia( 227 &sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev, 228 "jmide_hl", &jma, jmahci_print); 229 } 230 /* 231 * if we couldn't attach an ahci, try to fall back 232 * to pciide. Note that this will not work if IDE 233 * is on function 0 and AHCI on function 1. 234 */ 235 if (sc->sc_ahci == NULL) { 236 pcictrl0 = saved_pcictrl0 & 237 ~(JM_CONTROL0_SATA0_AHCI | 238 JM_CONTROL0_SATA1_AHCI | 239 JM_CONTROL0_AHCI_EN); 240 pcictrl0 |= JM_CONTROL0_SATA1_IDE | 241 JM_CONTROL0_SATA0_IDE; 242 pci_conf_write(pa->pa_pc, pa->pa_tag, 243 PCI_JM_CONTROL0, pcictrl0); 244 } else 245 ahci_used = 1; 246 } 247 } 248 sc->sc_chan_swap = ((pcictrl0 & JM_CONTROL0_PCIIDE_CS) != 0); 249 /* compute the type of internal primary channel */ 250 if (pcictrl1 & JM_CONTROL1_PATA1_PRI) { 251 if (sc->sc_npata > 1) 252 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_PATA; 253 else 254 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE; 255 } else if (ahci_used == 0 && sc->sc_nsata > 0) 256 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_SATA; 257 else 258 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE; 259 /* compute the type of internal secondary channel */ 260 if (sc->sc_nsata > 1 && ahci_used == 0 && 261 (pcictrl0 & JM_CONTROL0_PCIIDE0_MS) == 0) { 262 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_SATA; 263 } else { 264 /* only a drive if first PATA enabled */ 265 if (sc->sc_npata > 0 && (pcictrl0 & JM_CONTROL0_PATA0_EN) 266 && (pcictrl0 & 267 (sc->sc_chan_swap ? JM_CONTROL0_PATA0_PRI: JM_CONTROL0_PATA0_SEC))) 268 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_PATA; 269 else 270 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE; 271 } 272 273 if (sc->sc_chan_type[0] == TYPE_NONE && 274 sc->sc_chan_type[1] == TYPE_NONE) 275 return; 276 if (pa->pa_function == 0 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1)) 277 return; 278 if (pa->pa_function == 1 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1) == 0) 279 return; 280 pp = malloc(sizeof(struct pciide_product_desc), M_DEVBUF, M_NOWAIT); 281 if (pp == NULL) { 282 aprint_error("%s: can't malloc sc_pp\n", JM_NAME(sc)); 283 return; 284 } 285 aprint_normal("%s: PCI IDE interface used", JM_NAME(sc)); 286 pp->ide_product = 0; 287 pp->ide_flags = 0; 288 pp->ide_name = NULL; 289 pp->chip_map = jmpata_chip_map; 290 pciide_common_attach(&sc->sc_pciide, pa, pp); 291 292 } 293 294 static int 295 jmide_intr(void *arg) 296 { 297 struct jmide_softc *sc = arg; 298 int ret = 0; 299 300 #ifdef NJMAHCI 301 if (sc->sc_ahci) 302 ret |= ahci_intr(sc->sc_ahci); 303 #endif 304 if (sc->sc_npata) 305 ret |= pciide_pci_intr(&sc->sc_pciide); 306 return ret; 307 } 308 309 static void 310 jmpata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 311 { 312 struct jmide_softc *jmidesc = (struct jmide_softc *)sc; 313 int channel; 314 pcireg_t interface; 315 bus_size_t cmdsize, ctlsize; 316 struct pciide_channel *cp; 317 318 if (pciide_chipen(sc, pa) == 0) 319 return; 320 aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc)); 321 pciide_mapreg_dma(sc, pa); 322 aprint_verbose("\n"); 323 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 324 if (sc->sc_dma_ok) { 325 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 326 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 327 } 328 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 329 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 330 sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel; 331 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 332 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 333 wdc_allocate_regs(&sc->sc_wdcdev); 334 /* 335 * can't rely on the PCI_CLASS_REG content if the chip was in raid 336 * mode. We have to fake interface 337 */ 338 interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 339 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 340 channel++) { 341 cp = &sc->pciide_channels[channel]; 342 if (pciide_chansetup(sc, channel, interface) == 0) 343 continue; 344 aprint_normal("%s: %s channel is ", JM_NAME(jmidesc), 345 PCIIDE_CHANNEL_NAME(channel)); 346 switch(jmidesc->sc_chan_type[channel]) { 347 case TYPE_PATA: 348 aprint_normal("PATA"); 349 break; 350 case TYPE_SATA: 351 aprint_normal("SATA"); 352 break; 353 case TYPE_NONE: 354 aprint_normal("unused"); 355 break; 356 default: 357 aprint_normal("impossible"); 358 panic("jmide: wrong/uninitialised channel type"); 359 } 360 aprint_normal("\n"); 361 if (jmidesc->sc_chan_type[channel] == TYPE_NONE) { 362 cp->ata_channel.ch_flags |= ATACH_DISABLED; 363 continue; 364 } 365 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 366 pciide_pci_intr); 367 } 368 } 369 370 static void 371 jmpata_setup_channel(struct ata_channel *chp) 372 { 373 struct ata_drive_datas *drvp; 374 int drive, s; 375 u_int32_t idedma_ctl; 376 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 377 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 378 struct jmide_softc *jmidesc = (struct jmide_softc *)sc; 379 int ide80p; 380 381 /* setup DMA if needed */ 382 pciide_channel_dma_setup(cp); 383 384 idedma_ctl = 0; 385 386 /* cable type detect */ 387 ide80p = 1; 388 if (chp->ch_channel == (jmidesc->sc_chan_swap ? 1 : 0)) { 389 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA && 390 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL1) & 391 JM_CONTROL1_PATA1_40P)) 392 ide80p = 0; 393 } else { 394 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA && 395 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL0) & 396 JM_CONTROL0_PATA0_40P)) 397 ide80p = 0; 398 } 399 400 for (drive = 0; drive < 2; drive++) { 401 drvp = &chp->ch_drive[drive]; 402 /* If no drive, skip */ 403 if ((drvp->drive_flags & DRIVE) == 0) 404 continue; 405 if (drvp->drive_flags & DRIVE_UDMA) { 406 /* use Ultra/DMA */ 407 s = splbio(); 408 drvp->drive_flags &= ~DRIVE_DMA; 409 if (drvp->UDMA_mode > 2 && ide80p == 0) 410 drvp->UDMA_mode = 2; 411 splx(s); 412 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 413 } else if (drvp->drive_flags & DRIVE_DMA) { 414 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 415 } 416 } 417 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 418 if (idedma_ctl != 0) { 419 /* Add software bits in status register */ 420 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 421 0, idedma_ctl); 422 } 423 } 424 425 static int 426 jmahci_print(void *aux, const char *pnp) 427 { 428 if (pnp) 429 aprint_normal("ahcisata at %s", pnp); 430 431 return (UNCONF); 432 } 433 434 435 #ifdef NJMAHCI 436 static int jmahci_match(struct device *, struct cfdata *, void *); 437 static void jmahci_attach(struct device *, struct device *, void *); 438 439 CFATTACH_DECL(jmahci, sizeof(struct ahci_softc), 440 jmahci_match, jmahci_attach, NULL, NULL); 441 442 static int 443 jmahci_match(struct device *parent, struct cfdata *match, void *aux) 444 { 445 return 1; 446 } 447 448 static void 449 jmahci_attach(struct device *parent, struct device *self, void *aux) 450 { 451 struct jmahci_attach_args *jma = aux; 452 struct pci_attach_args *pa = jma->jma_pa; 453 struct ahci_softc *sc = (struct ahci_softc *)self; 454 455 aprint_naive(": AHCI disk controller\n"); 456 aprint_normal("\n"); 457 458 sc->sc_ahcit = jma->jma_ahcit; 459 sc->sc_ahcih = jma->jma_ahcih; 460 sc->sc_dmat = jma->jma_pa->pa_dmat; 461 462 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 463 sc->sc_atac_capflags = ATAC_CAP_RAID; 464 465 ahci_attach(sc); 466 } 467 #endif 468
Indexes created Tue Sep 23 20:09:58 GMT 2025