jmide.c revision 1.9
1 /* $NetBSD: jmide.c,v 1.9 2010/11/05 18:07:24 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: jmide.c,v 1.9 2010/11/05 18:07:24 jakllsch Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 39 #include <dev/pci/jmide_reg.h> 40 41 #include <dev/ic/ahcisatavar.h> 42 43 #include "jmide.h" 44 45 static const struct jmide_product *jmide_lookup(pcireg_t); 46 47 static int jmide_match(device_t, cfdata_t, void *); 48 static void jmide_attach(device_t, device_t, void *); 49 static int jmide_intr(void *); 50 51 static void jmpata_chip_map(struct pciide_softc*, struct pci_attach_args*); 52 static void jmpata_setup_channel(struct ata_channel*); 53 54 static int jmahci_print(void *, const char *); 55 56 struct jmide_product { 57 u_int32_t jm_product; 58 int jm_npata; 59 int jm_nsata; 60 }; 61 62 static const struct jmide_product jm_products[] = { 63 { PCI_PRODUCT_JMICRON_JMB360, 64 0, 65 1 66 }, 67 { PCI_PRODUCT_JMICRON_JMB361, 68 1, 69 1 70 }, 71 { PCI_PRODUCT_JMICRON_JMB363, 72 1, 73 2 74 }, 75 { PCI_PRODUCT_JMICRON_JMB365, 76 2, 77 1 78 }, 79 { PCI_PRODUCT_JMICRON_JMB366, 80 2, 81 2 82 }, 83 { PCI_PRODUCT_JMICRON_JMB368, 84 1, 85 0 86 }, 87 { 0, 88 0, 89 0 90 } 91 }; 92 93 typedef enum { 94 TYPE_INVALID = 0, 95 TYPE_PATA, 96 TYPE_SATA, 97 TYPE_NONE 98 } jmchan_t; 99 100 struct jmide_softc { 101 struct pciide_softc sc_pciide; 102 device_t sc_ahci; 103 int sc_npata; 104 int sc_nsata; 105 jmchan_t sc_chan_type[PCIIDE_NUM_CHANNELS]; 106 int sc_chan_swap; 107 }; 108 109 struct jmahci_attach_args { 110 struct pci_attach_args *jma_pa; 111 bus_space_tag_t jma_ahcit; 112 bus_space_handle_t jma_ahcih; 113 }; 114 115 #define JM_NAME(sc) (device_xname(sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev)) 116 117 CFATTACH_DECL_NEW(jmide, sizeof(struct jmide_softc), 118 jmide_match, jmide_attach, NULL, NULL); 119 120 static const struct jmide_product * 121 jmide_lookup(pcireg_t id) { 122 const struct jmide_product *jp; 123 124 for (jp = jm_products; jp->jm_product != 0; jp++) { 125 if (jp->jm_product == PCI_PRODUCT(id)) 126 return jp; 127 } 128 return NULL; 129 } 130 131 static int 132 jmide_match(device_t parent, cfdata_t match, void *aux) 133 { 134 struct pci_attach_args *pa = aux; 135 136 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_JMICRON) { 137 if (jmide_lookup(pa->pa_id)) 138 return (4); /* highter than ahcisata */ 139 } 140 return (0); 141 } 142 143 static void 144 jmide_attach(device_t parent, device_t self, void *aux) 145 { 146 struct pci_attach_args *pa = aux; 147 struct jmide_softc *sc = device_private(self); 148 const struct jmide_product *jp; 149 char devinfo[256]; 150 const char *intrstr; 151 pci_intr_handle_t intrhandle; 152 u_int32_t pcictrl0 = pci_conf_read(pa->pa_pc, pa->pa_tag, 153 PCI_JM_CONTROL0); 154 u_int32_t pcictrl1 = pci_conf_read(pa->pa_pc, pa->pa_tag, 155 PCI_JM_CONTROL1); 156 struct pciide_product_desc *pp; 157 int ahci_used = 0; 158 159 sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev = self; 160 161 jp = jmide_lookup(pa->pa_id); 162 if (jp == NULL) { 163 printf("jmide_attach: WTF?\n"); 164 return; 165 } 166 sc->sc_npata = jp->jm_npata; 167 sc->sc_nsata = jp->jm_nsata; 168 169 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 170 aprint_naive(": JMICRON PATA/SATA disk controller\n"); 171 aprint_normal(": %s\n", devinfo); 172 173 aprint_normal("%s: ", JM_NAME(sc)); 174 if (sc->sc_npata) 175 aprint_normal("%d PATA port%s", sc->sc_npata, 176 (sc->sc_npata > 1) ? "s" : ""); 177 if (sc->sc_nsata) 178 aprint_normal("%s%d SATA port%s", sc->sc_npata ? ", " : "", 179 sc->sc_nsata, (sc->sc_nsata > 1) ? "s" : ""); 180 aprint_normal("\n"); 181 182 if (pci_intr_map(pa, &intrhandle) != 0) { 183 aprint_error("%s: couldn't map interrupt\n", JM_NAME(sc)); 184 return; 185 } 186 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 187 sc->sc_pciide.sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, 188 IPL_BIO, jmide_intr, sc); 189 if (sc->sc_pciide.sc_pci_ih == NULL) { 190 aprint_error("%s: couldn't establish interrupt", JM_NAME(sc)); 191 return; 192 } 193 aprint_normal("%s: interrupting at %s\n", JM_NAME(sc), 194 intrstr ? intrstr : "unknown interrupt"); 195 196 if (pcictrl0 & JM_CONTROL0_AHCI_EN) { 197 bus_size_t size; 198 struct jmahci_attach_args jma; 199 u_int32_t saved_pcictrl0; 200 /* 201 * ahci controller enabled; disable sata on pciide and 202 * enable on ahci 203 */ 204 saved_pcictrl0 = pcictrl0; 205 pcictrl0 |= JM_CONTROL0_SATA0_AHCI | JM_CONTROL0_SATA1_AHCI; 206 pcictrl0 &= ~(JM_CONTROL0_SATA0_IDE | JM_CONTROL0_SATA1_IDE); 207 pci_conf_write(pa->pa_pc, pa->pa_tag, 208 PCI_JM_CONTROL0, pcictrl0); 209 /* attach ahci controller if on the right function */ 210 if ((pa->pa_function == 0 && 211 (pcictrl0 & JM_CONTROL0_AHCI_F1) == 0) || 212 (pa->pa_function == 1 && 213 (pcictrl0 & JM_CONTROL0_AHCI_F1) != 0)) { 214 jma.jma_pa = pa; 215 /* map registers */ 216 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 217 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 218 &jma.jma_ahcit, &jma.jma_ahcih, NULL, &size) != 0) { 219 aprint_error("%s: can't map ahci registers\n", 220 JM_NAME(sc)); 221 } else { 222 sc->sc_ahci = config_found_ia( 223 sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev, 224 "jmide_hl", &jma, jmahci_print); 225 } 226 /* 227 * if we couldn't attach an ahci, try to fall back 228 * to pciide. Note that this will not work if IDE 229 * is on function 0 and AHCI on function 1. 230 */ 231 if (sc->sc_ahci == NULL) { 232 pcictrl0 = saved_pcictrl0 & 233 ~(JM_CONTROL0_SATA0_AHCI | 234 JM_CONTROL0_SATA1_AHCI | 235 JM_CONTROL0_AHCI_EN); 236 pcictrl0 |= JM_CONTROL0_SATA1_IDE | 237 JM_CONTROL0_SATA0_IDE; 238 pci_conf_write(pa->pa_pc, pa->pa_tag, 239 PCI_JM_CONTROL0, pcictrl0); 240 } else 241 ahci_used = 1; 242 } 243 } 244 sc->sc_chan_swap = ((pcictrl0 & JM_CONTROL0_PCIIDE_CS) != 0); 245 /* compute the type of internal primary channel */ 246 if (pcictrl1 & JM_CONTROL1_PATA1_PRI) { 247 if (sc->sc_npata > 1) 248 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_PATA; 249 else 250 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE; 251 } else if (ahci_used == 0 && sc->sc_nsata > 0) 252 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_SATA; 253 else 254 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE; 255 /* compute the type of internal secondary channel */ 256 if (sc->sc_nsata > 1 && ahci_used == 0 && 257 (pcictrl0 & JM_CONTROL0_PCIIDE0_MS) == 0) { 258 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_SATA; 259 } else { 260 /* only a drive if first PATA enabled */ 261 if (sc->sc_npata > 0 && (pcictrl0 & JM_CONTROL0_PATA0_EN) 262 && (pcictrl0 & 263 (sc->sc_chan_swap ? JM_CONTROL0_PATA0_PRI: JM_CONTROL0_PATA0_SEC))) 264 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_PATA; 265 else 266 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE; 267 } 268 269 if (sc->sc_chan_type[0] == TYPE_NONE && 270 sc->sc_chan_type[1] == TYPE_NONE) 271 return; 272 if (pa->pa_function == 0 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1)) 273 return; 274 if (pa->pa_function == 1 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1) == 0) 275 return; 276 pp = malloc(sizeof(struct pciide_product_desc), M_DEVBUF, M_NOWAIT); 277 if (pp == NULL) { 278 aprint_error("%s: can't malloc sc_pp\n", JM_NAME(sc)); 279 return; 280 } 281 aprint_normal("%s: PCI IDE interface used", JM_NAME(sc)); 282 pp->ide_product = 0; 283 pp->ide_flags = 0; 284 pp->ide_name = NULL; 285 pp->chip_map = jmpata_chip_map; 286 pciide_common_attach(&sc->sc_pciide, pa, pp); 287 288 } 289 290 static int 291 jmide_intr(void *arg) 292 { 293 struct jmide_softc *sc = arg; 294 int ret = 0; 295 296 #ifdef NJMAHCI 297 if (sc->sc_ahci) 298 ret |= ahci_intr(device_private(sc->sc_ahci)); 299 #endif 300 if (sc->sc_npata) 301 ret |= pciide_pci_intr(&sc->sc_pciide); 302 return ret; 303 } 304 305 static void 306 jmpata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 307 { 308 struct jmide_softc *jmidesc = (struct jmide_softc *)sc; 309 int channel; 310 pcireg_t interface; 311 struct pciide_channel *cp; 312 313 if (pciide_chipen(sc, pa) == 0) 314 return; 315 aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc)); 316 pciide_mapreg_dma(sc, pa); 317 aprint_verbose("\n"); 318 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 319 if (sc->sc_dma_ok) { 320 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 321 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 322 } 323 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 324 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 325 sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel; 326 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 327 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 328 wdc_allocate_regs(&sc->sc_wdcdev); 329 /* 330 * can't rely on the PCI_CLASS_REG content if the chip was in raid 331 * mode. We have to fake interface 332 */ 333 interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 334 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 335 channel++) { 336 cp = &sc->pciide_channels[channel]; 337 if (pciide_chansetup(sc, channel, interface) == 0) 338 continue; 339 aprint_normal("%s: %s channel is ", JM_NAME(jmidesc), 340 PCIIDE_CHANNEL_NAME(channel)); 341 switch(jmidesc->sc_chan_type[channel]) { 342 case TYPE_PATA: 343 aprint_normal("PATA"); 344 break; 345 case TYPE_SATA: 346 aprint_normal("SATA"); 347 break; 348 case TYPE_NONE: 349 aprint_normal("unused"); 350 break; 351 default: 352 aprint_normal("impossible"); 353 panic("jmide: wrong/uninitialised channel type"); 354 } 355 aprint_normal("\n"); 356 if (jmidesc->sc_chan_type[channel] == TYPE_NONE) { 357 cp->ata_channel.ch_flags |= ATACH_DISABLED; 358 continue; 359 } 360 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 361 } 362 } 363 364 static void 365 jmpata_setup_channel(struct ata_channel *chp) 366 { 367 struct ata_drive_datas *drvp; 368 int drive, s; 369 u_int32_t idedma_ctl; 370 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 371 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 372 struct jmide_softc *jmidesc = (struct jmide_softc *)sc; 373 int ide80p; 374 375 /* setup DMA if needed */ 376 pciide_channel_dma_setup(cp); 377 378 idedma_ctl = 0; 379 380 /* cable type detect */ 381 ide80p = 1; 382 if (chp->ch_channel == (jmidesc->sc_chan_swap ? 1 : 0)) { 383 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA && 384 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL1) & 385 JM_CONTROL1_PATA1_40P)) 386 ide80p = 0; 387 } else { 388 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA && 389 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL0) & 390 JM_CONTROL0_PATA0_40P)) 391 ide80p = 0; 392 } 393 394 for (drive = 0; drive < 2; drive++) { 395 drvp = &chp->ch_drive[drive]; 396 /* If no drive, skip */ 397 if ((drvp->drive_flags & DRIVE) == 0) 398 continue; 399 if (drvp->drive_flags & DRIVE_UDMA) { 400 /* use Ultra/DMA */ 401 s = splbio(); 402 drvp->drive_flags &= ~DRIVE_DMA; 403 if (drvp->UDMA_mode > 2 && ide80p == 0) 404 drvp->UDMA_mode = 2; 405 splx(s); 406 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 407 } else if (drvp->drive_flags & DRIVE_DMA) { 408 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 409 } 410 } 411 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 412 if (idedma_ctl != 0) { 413 /* Add software bits in status register */ 414 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 415 0, idedma_ctl); 416 } 417 } 418 419 static int 420 jmahci_print(void *aux, const char *pnp) 421 { 422 if (pnp) 423 aprint_normal("ahcisata at %s", pnp); 424 425 return (UNCONF); 426 } 427 428 429 #ifdef NJMAHCI 430 static int jmahci_match(device_t, cfdata_t, void *); 431 static void jmahci_attach(device_t, device_t, void *); 432 static int jmahci_detach(device_t, int); 433 static bool jmahci_resume(device_t, const pmf_qual_t *); 434 435 CFATTACH_DECL_NEW(jmahci, sizeof(struct ahci_softc), 436 jmahci_match, jmahci_attach, jmahci_detach, NULL); 437 438 static int 439 jmahci_match(device_t parent, cfdata_t match, void *aux) 440 { 441 return 1; 442 } 443 444 static void 445 jmahci_attach(device_t parent, device_t self, void *aux) 446 { 447 struct jmahci_attach_args *jma = aux; 448 struct pci_attach_args *pa = jma->jma_pa; 449 struct ahci_softc *sc = device_private(self); 450 uint32_t ahci_cap; 451 452 aprint_naive(": AHCI disk controller\n"); 453 aprint_normal("\n"); 454 455 sc->sc_atac.atac_dev = self; 456 sc->sc_ahcit = jma->jma_ahcit; 457 sc->sc_ahcih = jma->jma_ahcih; 458 459 ahci_cap = AHCI_READ(sc, AHCI_CAP); 460 461 if (pci_dma64_available(jma->jma_pa) && (ahci_cap & AHCI_CAP_64BIT)) 462 sc->sc_dmat = jma->jma_pa->pa_dmat64; 463 else 464 sc->sc_dmat = jma->jma_pa->pa_dmat; 465 466 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 467 sc->sc_atac_capflags = ATAC_CAP_RAID; 468 469 ahci_attach(sc); 470 471 if (!pmf_device_register(self, NULL, jmahci_resume)) 472 aprint_error_dev(self, "couldn't establish power handler\n"); 473 } 474 475 static int 476 jmahci_detach(device_t dv, int flags) 477 { 478 struct ahci_softc *sc; 479 sc = device_private(dv); 480 481 int rv; 482 483 if ((rv = ahci_detach(sc, flags))) 484 return rv; 485 486 return 0; 487 } 488 489 static bool 490 jmahci_resume(device_t dv, const pmf_qual_t *qual) 491 { 492 struct ahci_softc *sc; 493 int s; 494 495 sc = device_private(dv); 496 497 s = splbio(); 498 ahci_resume(sc); 499 splx(s); 500 501 return true; 502 } 503 #endif 504
Indexes created Mon Sep 22 21:09:42 GMT 2025