ld_virtio.c revision 1.4.4.2 1 1.4.4.2 riz /* $NetBSD: ld_virtio.c,v 1.4.4.2 2012/01/25 21:18:15 riz Exp $ */
2 1.4.4.2 riz
3 1.4.4.2 riz /*
4 1.4.4.2 riz * Copyright (c) 2010 Minoura Makoto.
5 1.4.4.2 riz * All rights reserved.
6 1.4.4.2 riz *
7 1.4.4.2 riz * Redistribution and use in source and binary forms, with or without
8 1.4.4.2 riz * modification, are permitted provided that the following conditions
9 1.4.4.2 riz * are met:
10 1.4.4.2 riz * 1. Redistributions of source code must retain the above copyright
11 1.4.4.2 riz * notice, this list of conditions and the following disclaimer.
12 1.4.4.2 riz * 2. Redistributions in binary form must reproduce the above copyright
13 1.4.4.2 riz * notice, this list of conditions and the following disclaimer in the
14 1.4.4.2 riz * documentation and/or other materials provided with the distribution.
15 1.4.4.2 riz *
16 1.4.4.2 riz * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.4.4.2 riz * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.4.4.2 riz * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.4.4.2 riz * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.4.4.2 riz * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 1.4.4.2 riz * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 1.4.4.2 riz * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 1.4.4.2 riz * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 1.4.4.2 riz * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 1.4.4.2 riz * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 1.4.4.2 riz */
27 1.4.4.2 riz
28 1.4.4.2 riz #include <sys/cdefs.h>
29 1.4.4.2 riz __KERNEL_RCSID(0, "$NetBSD: ld_virtio.c,v 1.4.4.2 2012/01/25 21:18:15 riz Exp $");
30 1.4.4.2 riz
31 1.4.4.2 riz #include "rnd.h"
32 1.4.4.2 riz
33 1.4.4.2 riz #include <sys/param.h>
34 1.4.4.2 riz #include <sys/systm.h>
35 1.4.4.2 riz #include <sys/kernel.h>
36 1.4.4.2 riz #include <sys/buf.h>
37 1.4.4.2 riz #include <sys/bus.h>
38 1.4.4.2 riz #include <sys/device.h>
39 1.4.4.2 riz #include <sys/disk.h>
40 1.4.4.2 riz #include <sys/mutex.h>
41 1.4.4.2 riz #if NRND > 0
42 1.4.4.2 riz #include <sys/rnd.h>
43 1.4.4.2 riz #endif
44 1.4.4.2 riz
45 1.4.4.2 riz #include <dev/pci/pcidevs.h>
46 1.4.4.2 riz #include <dev/pci/pcireg.h>
47 1.4.4.2 riz #include <dev/pci/pcivar.h>
48 1.4.4.2 riz
49 1.4.4.2 riz #include <dev/ldvar.h>
50 1.4.4.2 riz #include <dev/pci/virtioreg.h>
51 1.4.4.2 riz #include <dev/pci/virtiovar.h>
52 1.4.4.2 riz
53 1.4.4.2 riz #include <uvm/uvm_extern.h>
54 1.4.4.2 riz
55 1.4.4.2 riz /*
56 1.4.4.2 riz * ld_virtioreg:
57 1.4.4.2 riz */
58 1.4.4.2 riz /* Configuration registers */
59 1.4.4.2 riz #define VIRTIO_BLK_CONFIG_CAPACITY 0 /* 64bit */
60 1.4.4.2 riz #define VIRTIO_BLK_CONFIG_SIZE_MAX 8 /* 32bit */
61 1.4.4.2 riz #define VIRTIO_BLK_CONFIG_SEG_MAX 12 /* 32bit */
62 1.4.4.2 riz #define VIRTIO_BLK_CONFIG_GEOMETRY_C 16 /* 16bit */
63 1.4.4.2 riz #define VIRTIO_BLK_CONFIG_GEOMETRY_H 18 /* 8bit */
64 1.4.4.2 riz #define VIRTIO_BLK_CONFIG_GEOMETRY_S 19 /* 8bit */
65 1.4.4.2 riz #define VIRTIO_BLK_CONFIG_BLK_SIZE 20 /* 32bit */
66 1.4.4.2 riz
67 1.4.4.2 riz /* Feature bits */
68 1.4.4.2 riz #define VIRTIO_BLK_F_BARRIER (1<<0)
69 1.4.4.2 riz #define VIRTIO_BLK_F_SIZE_MAX (1<<1)
70 1.4.4.2 riz #define VIRTIO_BLK_F_SEG_MAX (1<<2)
71 1.4.4.2 riz #define VIRTIO_BLK_F_GEOMETRY (1<<4)
72 1.4.4.2 riz #define VIRTIO_BLK_F_RO (1<<5)
73 1.4.4.2 riz #define VIRTIO_BLK_F_BLK_SIZE (1<<6)
74 1.4.4.2 riz #define VIRTIO_BLK_F_SCSI (1<<7)
75 1.4.4.2 riz #define VIRTIO_BLK_F_FLUSH (1<<9)
76 1.4.4.2 riz
77 1.4.4.2 riz /* Command */
78 1.4.4.2 riz #define VIRTIO_BLK_T_IN 0
79 1.4.4.2 riz #define VIRTIO_BLK_T_OUT 1
80 1.4.4.2 riz #define VIRTIO_BLK_T_BARRIER 0x80000000
81 1.4.4.2 riz
82 1.4.4.2 riz /* Status */
83 1.4.4.2 riz #define VIRTIO_BLK_S_OK 0
84 1.4.4.2 riz #define VIRTIO_BLK_S_IOERR 1
85 1.4.4.2 riz
86 1.4.4.2 riz /* Request header structure */
87 1.4.4.2 riz struct virtio_blk_req_hdr {
88 1.4.4.2 riz uint32_t type; /* VIRTIO_BLK_T_* */
89 1.4.4.2 riz uint32_t ioprio;
90 1.4.4.2 riz uint64_t sector;
91 1.4.4.2 riz } __packed;
92 1.4.4.2 riz /* 512*virtio_blk_req_hdr.sector byte payload and 1 byte status follows */
93 1.4.4.2 riz
94 1.4.4.2 riz
95 1.4.4.2 riz /*
96 1.4.4.2 riz * ld_virtiovar:
97 1.4.4.2 riz */
98 1.4.4.2 riz struct virtio_blk_req {
99 1.4.4.2 riz struct virtio_blk_req_hdr vr_hdr;
100 1.4.4.2 riz uint8_t vr_status;
101 1.4.4.2 riz struct buf *vr_bp;
102 1.4.4.2 riz bus_dmamap_t vr_cmdsts;
103 1.4.4.2 riz bus_dmamap_t vr_payload;
104 1.4.4.2 riz };
105 1.4.4.2 riz
106 1.4.4.2 riz struct ld_virtio_softc {
107 1.4.4.2 riz struct ld_softc sc_ld;
108 1.4.4.2 riz device_t sc_dev;
109 1.4.4.2 riz
110 1.4.4.2 riz struct virtio_softc *sc_virtio;
111 1.4.4.2 riz struct virtqueue sc_vq[1];
112 1.4.4.2 riz
113 1.4.4.2 riz struct virtio_blk_req *sc_reqs;
114 1.4.4.2 riz bus_dma_segment_t sc_reqs_segs[1];
115 1.4.4.2 riz
116 1.4.4.2 riz kmutex_t sc_lock;
117 1.4.4.2 riz
118 1.4.4.2 riz int sc_readonly;
119 1.4.4.2 riz };
120 1.4.4.2 riz
121 1.4.4.2 riz static int ld_virtio_match(device_t, cfdata_t, void *);
122 1.4.4.2 riz static void ld_virtio_attach(device_t, device_t, void *);
123 1.4.4.2 riz static int ld_virtio_detach(device_t, int);
124 1.4.4.2 riz
125 1.4.4.2 riz CFATTACH_DECL_NEW(ld_virtio, sizeof(struct ld_virtio_softc),
126 1.4.4.2 riz ld_virtio_match, ld_virtio_attach, ld_virtio_detach, NULL);
127 1.4.4.2 riz
128 1.4.4.2 riz static int
129 1.4.4.2 riz ld_virtio_match(device_t parent, cfdata_t match, void *aux)
130 1.4.4.2 riz {
131 1.4.4.2 riz struct virtio_softc *va = aux;
132 1.4.4.2 riz
133 1.4.4.2 riz if (va->sc_childdevid == PCI_PRODUCT_VIRTIO_BLOCK)
134 1.4.4.2 riz return 1;
135 1.4.4.2 riz
136 1.4.4.2 riz return 0;
137 1.4.4.2 riz }
138 1.4.4.2 riz
139 1.4.4.2 riz static int ld_virtio_vq_done(struct virtqueue *);
140 1.4.4.2 riz static int ld_virtio_dump(struct ld_softc *, void *, int, int);
141 1.4.4.2 riz static int ld_virtio_start(struct ld_softc *, struct buf *);
142 1.4.4.2 riz
143 1.4.4.2 riz static int
144 1.4.4.2 riz ld_virtio_alloc_reqs(struct ld_virtio_softc *sc, int qsize)
145 1.4.4.2 riz {
146 1.4.4.2 riz int allocsize, r, rsegs, i;
147 1.4.4.2 riz struct ld_softc *ld = &sc->sc_ld;
148 1.4.4.2 riz void *vaddr;
149 1.4.4.2 riz
150 1.4.4.2 riz allocsize = sizeof(struct virtio_blk_req) * qsize;
151 1.4.4.2 riz r = bus_dmamem_alloc(sc->sc_virtio->sc_dmat, allocsize, 0, 0,
152 1.4.4.2 riz &sc->sc_reqs_segs[0], 1, &rsegs, BUS_DMA_NOWAIT);
153 1.4.4.2 riz if (r != 0) {
154 1.4.4.2 riz aprint_error_dev(sc->sc_dev,
155 1.4.4.2 riz "DMA memory allocation failed, size %d, "
156 1.4.4.2 riz "error code %d\n", allocsize, r);
157 1.4.4.2 riz goto err_none;
158 1.4.4.2 riz }
159 1.4.4.2 riz r = bus_dmamem_map(sc->sc_virtio->sc_dmat,
160 1.4.4.2 riz &sc->sc_reqs_segs[0], 1, allocsize,
161 1.4.4.2 riz &vaddr, BUS_DMA_NOWAIT);
162 1.4.4.2 riz if (r != 0) {
163 1.4.4.2 riz aprint_error_dev(sc->sc_dev,
164 1.4.4.2 riz "DMA memory map failed, "
165 1.4.4.2 riz "error code %d\n", r);
166 1.4.4.2 riz goto err_dmamem_alloc;
167 1.4.4.2 riz }
168 1.4.4.2 riz sc->sc_reqs = vaddr;
169 1.4.4.2 riz memset(vaddr, 0, allocsize);
170 1.4.4.2 riz for (i = 0; i < qsize; i++) {
171 1.4.4.2 riz struct virtio_blk_req *vr = &sc->sc_reqs[i];
172 1.4.4.2 riz r = bus_dmamap_create(sc->sc_virtio->sc_dmat,
173 1.4.4.2 riz offsetof(struct virtio_blk_req, vr_bp),
174 1.4.4.2 riz 1,
175 1.4.4.2 riz offsetof(struct virtio_blk_req, vr_bp),
176 1.4.4.2 riz 0,
177 1.4.4.2 riz BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW,
178 1.4.4.2 riz &vr->vr_cmdsts);
179 1.4.4.2 riz if (r != 0) {
180 1.4.4.2 riz aprint_error_dev(sc->sc_dev,
181 1.4.4.2 riz "command dmamap creation failed, "
182 1.4.4.2 riz "error code %d\n", r);
183 1.4.4.2 riz goto err_reqs;
184 1.4.4.2 riz }
185 1.4.4.2 riz r = bus_dmamap_load(sc->sc_virtio->sc_dmat, vr->vr_cmdsts,
186 1.4.4.2 riz &vr->vr_hdr,
187 1.4.4.2 riz offsetof(struct virtio_blk_req, vr_bp),
188 1.4.4.2 riz NULL, BUS_DMA_NOWAIT);
189 1.4.4.2 riz if (r != 0) {
190 1.4.4.2 riz aprint_error_dev(sc->sc_dev,
191 1.4.4.2 riz "command dmamap load failed, "
192 1.4.4.2 riz "error code %d\n", r);
193 1.4.4.2 riz goto err_reqs;
194 1.4.4.2 riz }
195 1.4.4.2 riz r = bus_dmamap_create(sc->sc_virtio->sc_dmat,
196 1.4.4.2 riz ld->sc_maxxfer,
197 1.4.4.2 riz (ld->sc_maxxfer / NBPG) + 2,
198 1.4.4.2 riz ld->sc_maxxfer,
199 1.4.4.2 riz 0,
200 1.4.4.2 riz BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW,
201 1.4.4.2 riz &vr->vr_payload);
202 1.4.4.2 riz if (r != 0) {
203 1.4.4.2 riz aprint_error_dev(sc->sc_dev,
204 1.4.4.2 riz "payload dmamap creation failed, "
205 1.4.4.2 riz "error code %d\n", r);
206 1.4.4.2 riz goto err_reqs;
207 1.4.4.2 riz }
208 1.4.4.2 riz }
209 1.4.4.2 riz return 0;
210 1.4.4.2 riz
211 1.4.4.2 riz err_reqs:
212 1.4.4.2 riz for (i = 0; i < qsize; i++) {
213 1.4.4.2 riz struct virtio_blk_req *vr = &sc->sc_reqs[i];
214 1.4.4.2 riz if (vr->vr_cmdsts) {
215 1.4.4.2 riz bus_dmamap_destroy(sc->sc_virtio->sc_dmat,
216 1.4.4.2 riz vr->vr_cmdsts);
217 1.4.4.2 riz vr->vr_cmdsts = 0;
218 1.4.4.2 riz }
219 1.4.4.2 riz if (vr->vr_payload) {
220 1.4.4.2 riz bus_dmamap_destroy(sc->sc_virtio->sc_dmat,
221 1.4.4.2 riz vr->vr_payload);
222 1.4.4.2 riz vr->vr_payload = 0;
223 1.4.4.2 riz }
224 1.4.4.2 riz }
225 1.4.4.2 riz bus_dmamem_unmap(sc->sc_virtio->sc_dmat, sc->sc_reqs, allocsize);
226 1.4.4.2 riz err_dmamem_alloc:
227 1.4.4.2 riz bus_dmamem_free(sc->sc_virtio->sc_dmat, &sc->sc_reqs_segs[0], 1);
228 1.4.4.2 riz err_none:
229 1.4.4.2 riz return -1;
230 1.4.4.2 riz }
231 1.4.4.2 riz
232 1.4.4.2 riz static void
233 1.4.4.2 riz ld_virtio_attach(device_t parent, device_t self, void *aux)
234 1.4.4.2 riz {
235 1.4.4.2 riz struct ld_virtio_softc *sc = device_private(self);
236 1.4.4.2 riz struct ld_softc *ld = &sc->sc_ld;
237 1.4.4.2 riz struct virtio_softc *vsc = device_private(parent);
238 1.4.4.2 riz uint32_t features;
239 1.4.4.2 riz int qsize, maxxfersize;
240 1.4.4.2 riz
241 1.4.4.2 riz if (vsc->sc_child != NULL) {
242 1.4.4.2 riz aprint_normal(": child already attached for %s; "
243 1.4.4.2 riz "something wrong...\n",
244 1.4.4.2 riz device_xname(parent));
245 1.4.4.2 riz return;
246 1.4.4.2 riz }
247 1.4.4.2 riz aprint_normal("\n");
248 1.4.4.2 riz aprint_naive("\n");
249 1.4.4.2 riz
250 1.4.4.2 riz sc->sc_dev = self;
251 1.4.4.2 riz sc->sc_virtio = vsc;
252 1.4.4.2 riz
253 1.4.4.2 riz vsc->sc_child = self;
254 1.4.4.2 riz vsc->sc_ipl = IPL_BIO;
255 1.4.4.2 riz vsc->sc_vqs = &sc->sc_vq[0];
256 1.4.4.2 riz vsc->sc_nvqs = 1;
257 1.4.4.2 riz vsc->sc_config_change = 0;
258 1.4.4.2 riz vsc->sc_intrhand = virtio_vq_intr;
259 1.4.4.2 riz
260 1.4.4.2 riz features = virtio_negotiate_features(vsc,
261 1.4.4.2 riz (VIRTIO_BLK_F_SIZE_MAX |
262 1.4.4.2 riz VIRTIO_BLK_F_SEG_MAX |
263 1.4.4.2 riz VIRTIO_BLK_F_GEOMETRY |
264 1.4.4.2 riz VIRTIO_BLK_F_RO |
265 1.4.4.2 riz VIRTIO_BLK_F_BLK_SIZE));
266 1.4.4.2 riz if (features & VIRTIO_BLK_F_RO)
267 1.4.4.2 riz sc->sc_readonly = 1;
268 1.4.4.2 riz else
269 1.4.4.2 riz sc->sc_readonly = 0;
270 1.4.4.2 riz
271 1.4.4.2 riz ld->sc_secsize = 512;
272 1.4.4.2 riz if (features & VIRTIO_BLK_F_BLK_SIZE) {
273 1.4.4.2 riz ld->sc_secsize = virtio_read_device_config_4(vsc,
274 1.4.4.2 riz VIRTIO_BLK_CONFIG_BLK_SIZE);
275 1.4.4.2 riz }
276 1.4.4.2 riz maxxfersize = MAXPHYS;
277 1.4.4.2 riz #if 0 /* At least genfs_io assumes maxxfer == MAXPHYS. */
278 1.4.4.2 riz if (features & VIRTIO_BLK_F_SEG_MAX) {
279 1.4.4.2 riz maxxfersize = virtio_read_device_config_4(vsc,
280 1.4.4.2 riz VIRTIO_BLK_CONFIG_SEG_MAX)
281 1.4.4.2 riz * ld->sc_secsize;
282 1.4.4.2 riz if (maxxfersize > MAXPHYS)
283 1.4.4.2 riz maxxfersize = MAXPHYS;
284 1.4.4.2 riz }
285 1.4.4.2 riz #endif
286 1.4.4.2 riz
287 1.4.4.2 riz if (virtio_alloc_vq(vsc, &sc->sc_vq[0], 0,
288 1.4.4.2 riz maxxfersize, maxxfersize / NBPG + 2,
289 1.4.4.2 riz "I/O request") != 0) {
290 1.4.4.2 riz goto err;
291 1.4.4.2 riz }
292 1.4.4.2 riz qsize = sc->sc_vq[0].vq_num;
293 1.4.4.2 riz sc->sc_vq[0].vq_done = ld_virtio_vq_done;
294 1.4.4.2 riz
295 1.4.4.2 riz ld->sc_dv = self;
296 1.4.4.2 riz ld->sc_secperunit = virtio_read_device_config_8(vsc,
297 1.4.4.2 riz VIRTIO_BLK_CONFIG_CAPACITY);
298 1.4.4.2 riz ld->sc_maxxfer = maxxfersize;
299 1.4.4.2 riz if (features & VIRTIO_BLK_F_GEOMETRY) {
300 1.4.4.2 riz ld->sc_ncylinders = virtio_read_device_config_2(vsc,
301 1.4.4.2 riz VIRTIO_BLK_CONFIG_GEOMETRY_C);
302 1.4.4.2 riz ld->sc_nheads = virtio_read_device_config_1(vsc,
303 1.4.4.2 riz VIRTIO_BLK_CONFIG_GEOMETRY_H);
304 1.4.4.2 riz ld->sc_nsectors = virtio_read_device_config_1(vsc,
305 1.4.4.2 riz VIRTIO_BLK_CONFIG_GEOMETRY_S);
306 1.4.4.2 riz }
307 1.4.4.2 riz ld->sc_maxqueuecnt = qsize;
308 1.4.4.2 riz
309 1.4.4.2 riz if (ld_virtio_alloc_reqs(sc, qsize) < 0)
310 1.4.4.2 riz goto err;
311 1.4.4.2 riz
312 1.4.4.2 riz mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_BIO);
313 1.4.4.2 riz
314 1.4.4.2 riz ld->sc_dump = ld_virtio_dump;
315 1.4.4.2 riz ld->sc_flush = NULL;
316 1.4.4.2 riz ld->sc_start = ld_virtio_start;
317 1.4.4.2 riz
318 1.4.4.2 riz ld->sc_flags = LDF_ENABLED;
319 1.4.4.2 riz ldattach(ld);
320 1.4.4.2 riz
321 1.4.4.2 riz return;
322 1.4.4.2 riz
323 1.4.4.2 riz err:
324 1.4.4.2 riz vsc->sc_child = (void*)1;
325 1.4.4.2 riz return;
326 1.4.4.2 riz }
327 1.4.4.2 riz
328 1.4.4.2 riz static int
329 1.4.4.2 riz ld_virtio_start(struct ld_softc *ld, struct buf *bp)
330 1.4.4.2 riz {
331 1.4.4.2 riz /* splbio */
332 1.4.4.2 riz struct ld_virtio_softc *sc = device_private(ld->sc_dv);
333 1.4.4.2 riz struct virtio_softc *vsc = sc->sc_virtio;
334 1.4.4.2 riz struct virtqueue *vq = &sc->sc_vq[0];
335 1.4.4.2 riz struct virtio_blk_req *vr;
336 1.4.4.2 riz int r;
337 1.4.4.2 riz int isread = (bp->b_flags & B_READ);
338 1.4.4.2 riz int slot;
339 1.4.4.2 riz
340 1.4.4.2 riz if (sc->sc_readonly && !isread)
341 1.4.4.2 riz return EIO;
342 1.4.4.2 riz
343 1.4.4.2 riz r = virtio_enqueue_prep(vsc, vq, &slot);
344 1.4.4.2 riz if (r != 0)
345 1.4.4.2 riz return r;
346 1.4.4.2 riz vr = &sc->sc_reqs[slot];
347 1.4.4.2 riz r = bus_dmamap_load(vsc->sc_dmat, vr->vr_payload,
348 1.4.4.2 riz bp->b_data, bp->b_bcount, NULL,
349 1.4.4.2 riz ((isread?BUS_DMA_READ:BUS_DMA_WRITE)
350 1.4.4.2 riz |BUS_DMA_NOWAIT));
351 1.4.4.2 riz if (r != 0)
352 1.4.4.2 riz return r;
353 1.4.4.2 riz
354 1.4.4.2 riz r = virtio_enqueue_reserve(vsc, vq, slot, vr->vr_payload->dm_nsegs + 2);
355 1.4.4.2 riz if (r != 0) {
356 1.4.4.2 riz bus_dmamap_unload(vsc->sc_dmat, vr->vr_payload);
357 1.4.4.2 riz return r;
358 1.4.4.2 riz }
359 1.4.4.2 riz
360 1.4.4.2 riz vr->vr_bp = bp;
361 1.4.4.2 riz vr->vr_hdr.type = isread?VIRTIO_BLK_T_IN:VIRTIO_BLK_T_OUT;
362 1.4.4.2 riz vr->vr_hdr.ioprio = 0;
363 1.4.4.2 riz vr->vr_hdr.sector = bp->b_rawblkno * sc->sc_ld.sc_secsize / 512;
364 1.4.4.2 riz
365 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts,
366 1.4.4.2 riz 0, sizeof(struct virtio_blk_req_hdr),
367 1.4.4.2 riz BUS_DMASYNC_PREWRITE);
368 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_payload,
369 1.4.4.2 riz 0, bp->b_bcount,
370 1.4.4.2 riz isread?BUS_DMASYNC_PREREAD:BUS_DMASYNC_PREWRITE);
371 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts,
372 1.4.4.2 riz offsetof(struct virtio_blk_req, vr_status),
373 1.4.4.2 riz sizeof(uint8_t),
374 1.4.4.2 riz BUS_DMASYNC_PREREAD);
375 1.4.4.2 riz
376 1.4.4.2 riz virtio_enqueue_p(vsc, vq, slot, vr->vr_cmdsts,
377 1.4.4.2 riz 0, sizeof(struct virtio_blk_req_hdr),
378 1.4.4.2 riz true);
379 1.4.4.2 riz virtio_enqueue(vsc, vq, slot, vr->vr_payload, !isread);
380 1.4.4.2 riz virtio_enqueue_p(vsc, vq, slot, vr->vr_cmdsts,
381 1.4.4.2 riz offsetof(struct virtio_blk_req, vr_status),
382 1.4.4.2 riz sizeof(uint8_t),
383 1.4.4.2 riz false);
384 1.4.4.2 riz virtio_enqueue_commit(vsc, vq, slot, true);
385 1.4.4.2 riz
386 1.4.4.2 riz return 0;
387 1.4.4.2 riz }
388 1.4.4.2 riz
389 1.4.4.2 riz static void
390 1.4.4.2 riz ld_virtio_vq_done1(struct ld_virtio_softc *sc, struct virtio_softc *vsc,
391 1.4.4.2 riz struct virtqueue *vq, int slot)
392 1.4.4.2 riz {
393 1.4.4.2 riz struct virtio_blk_req *vr = &sc->sc_reqs[slot];
394 1.4.4.2 riz struct buf *bp = vr->vr_bp;
395 1.4.4.2 riz
396 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts,
397 1.4.4.2 riz 0, sizeof(struct virtio_blk_req_hdr),
398 1.4.4.2 riz BUS_DMASYNC_POSTWRITE);
399 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_payload,
400 1.4.4.2 riz 0, bp->b_bcount,
401 1.4.4.2 riz (bp->b_flags & B_READ)?BUS_DMASYNC_POSTREAD
402 1.4.4.2 riz :BUS_DMASYNC_POSTWRITE);
403 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts,
404 1.4.4.2 riz sizeof(struct virtio_blk_req_hdr), sizeof(uint8_t),
405 1.4.4.2 riz BUS_DMASYNC_POSTREAD);
406 1.4.4.2 riz
407 1.4.4.2 riz if (vr->vr_status != VIRTIO_BLK_S_OK) {
408 1.4.4.2 riz bp->b_error = EIO;
409 1.4.4.2 riz bp->b_resid = bp->b_bcount;
410 1.4.4.2 riz } else {
411 1.4.4.2 riz bp->b_error = 0;
412 1.4.4.2 riz bp->b_resid = 0;
413 1.4.4.2 riz }
414 1.4.4.2 riz
415 1.4.4.2 riz virtio_dequeue_commit(vsc, vq, slot);
416 1.4.4.2 riz
417 1.4.4.2 riz lddone(&sc->sc_ld, bp);
418 1.4.4.2 riz }
419 1.4.4.2 riz
420 1.4.4.2 riz static int
421 1.4.4.2 riz ld_virtio_vq_done(struct virtqueue *vq)
422 1.4.4.2 riz {
423 1.4.4.2 riz struct virtio_softc *vsc = vq->vq_owner;
424 1.4.4.2 riz struct ld_virtio_softc *sc = device_private(vsc->sc_child);
425 1.4.4.2 riz int r = 0;
426 1.4.4.2 riz int slot;
427 1.4.4.2 riz
428 1.4.4.2 riz again:
429 1.4.4.2 riz if (virtio_dequeue(vsc, vq, &slot, NULL))
430 1.4.4.2 riz return r;
431 1.4.4.2 riz r = 1;
432 1.4.4.2 riz
433 1.4.4.2 riz ld_virtio_vq_done1(sc, vsc, vq, slot);
434 1.4.4.2 riz goto again;
435 1.4.4.2 riz }
436 1.4.4.2 riz
437 1.4.4.2 riz static int
438 1.4.4.2 riz ld_virtio_dump(struct ld_softc *ld, void *data, int blkno, int blkcnt)
439 1.4.4.2 riz {
440 1.4.4.2 riz struct ld_virtio_softc *sc = device_private(ld->sc_dv);
441 1.4.4.2 riz struct virtio_softc *vsc = sc->sc_virtio;
442 1.4.4.2 riz struct virtqueue *vq = &sc->sc_vq[0];
443 1.4.4.2 riz struct virtio_blk_req *vr;
444 1.4.4.2 riz int slot, r;
445 1.4.4.2 riz
446 1.4.4.2 riz if (sc->sc_readonly)
447 1.4.4.2 riz return EIO;
448 1.4.4.2 riz
449 1.4.4.2 riz r = virtio_enqueue_prep(vsc, vq, &slot);
450 1.4.4.2 riz if (r != 0) {
451 1.4.4.2 riz if (r == EAGAIN) { /* no free slot; dequeue first */
452 1.4.4.2 riz delay(100);
453 1.4.4.2 riz ld_virtio_vq_done(vq);
454 1.4.4.2 riz r = virtio_enqueue_prep(vsc, vq, &slot);
455 1.4.4.2 riz if (r != 0)
456 1.4.4.2 riz return r;
457 1.4.4.2 riz }
458 1.4.4.2 riz return r;
459 1.4.4.2 riz }
460 1.4.4.2 riz vr = &sc->sc_reqs[slot];
461 1.4.4.2 riz r = bus_dmamap_load(vsc->sc_dmat, vr->vr_payload,
462 1.4.4.2 riz data, blkcnt*ld->sc_secsize, NULL,
463 1.4.4.2 riz BUS_DMA_WRITE|BUS_DMA_NOWAIT);
464 1.4.4.2 riz if (r != 0)
465 1.4.4.2 riz return r;
466 1.4.4.2 riz
467 1.4.4.2 riz r = virtio_enqueue_reserve(vsc, vq, slot, vr->vr_payload->dm_nsegs + 2);
468 1.4.4.2 riz if (r != 0) {
469 1.4.4.2 riz bus_dmamap_unload(vsc->sc_dmat, vr->vr_payload);
470 1.4.4.2 riz return r;
471 1.4.4.2 riz }
472 1.4.4.2 riz
473 1.4.4.2 riz vr->vr_bp = (void*)0xdeadbeef;
474 1.4.4.2 riz vr->vr_hdr.type = VIRTIO_BLK_T_OUT;
475 1.4.4.2 riz vr->vr_hdr.ioprio = 0;
476 1.4.4.2 riz vr->vr_hdr.sector = (daddr_t) blkno * ld->sc_secsize / 512;
477 1.4.4.2 riz
478 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts,
479 1.4.4.2 riz 0, sizeof(struct virtio_blk_req_hdr),
480 1.4.4.2 riz BUS_DMASYNC_PREWRITE);
481 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_payload,
482 1.4.4.2 riz 0, blkcnt*ld->sc_secsize,
483 1.4.4.2 riz BUS_DMASYNC_PREWRITE);
484 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts,
485 1.4.4.2 riz offsetof(struct virtio_blk_req, vr_status),
486 1.4.4.2 riz sizeof(uint8_t),
487 1.4.4.2 riz BUS_DMASYNC_PREREAD);
488 1.4.4.2 riz
489 1.4.4.2 riz virtio_enqueue_p(vsc, vq, slot, vr->vr_cmdsts,
490 1.4.4.2 riz 0, sizeof(struct virtio_blk_req_hdr),
491 1.4.4.2 riz true);
492 1.4.4.2 riz virtio_enqueue(vsc, vq, slot, vr->vr_payload, true);
493 1.4.4.2 riz virtio_enqueue_p(vsc, vq, slot, vr->vr_cmdsts,
494 1.4.4.2 riz offsetof(struct virtio_blk_req, vr_status),
495 1.4.4.2 riz sizeof(uint8_t),
496 1.4.4.2 riz false);
497 1.4.4.2 riz virtio_enqueue_commit(vsc, vq, slot, true);
498 1.4.4.2 riz
499 1.4.4.2 riz for ( ; ; ) {
500 1.4.4.2 riz int dslot;
501 1.4.4.2 riz
502 1.4.4.2 riz r = virtio_dequeue(vsc, vq, &dslot, NULL);
503 1.4.4.2 riz if (r != 0)
504 1.4.4.2 riz continue;
505 1.4.4.2 riz if (dslot != slot) {
506 1.4.4.2 riz ld_virtio_vq_done1(sc, vsc, vq, dslot);
507 1.4.4.2 riz continue;
508 1.4.4.2 riz } else
509 1.4.4.2 riz break;
510 1.4.4.2 riz }
511 1.4.4.2 riz
512 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts,
513 1.4.4.2 riz 0, sizeof(struct virtio_blk_req_hdr),
514 1.4.4.2 riz BUS_DMASYNC_POSTWRITE);
515 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_payload,
516 1.4.4.2 riz 0, blkcnt*ld->sc_secsize,
517 1.4.4.2 riz BUS_DMASYNC_POSTWRITE);
518 1.4.4.2 riz bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts,
519 1.4.4.2 riz offsetof(struct virtio_blk_req, vr_status),
520 1.4.4.2 riz sizeof(uint8_t),
521 1.4.4.2 riz BUS_DMASYNC_POSTREAD);
522 1.4.4.2 riz if (vr->vr_status == VIRTIO_BLK_S_OK)
523 1.4.4.2 riz r = 0;
524 1.4.4.2 riz else
525 1.4.4.2 riz r = EIO;
526 1.4.4.2 riz virtio_dequeue_commit(vsc, vq, slot);
527 1.4.4.2 riz
528 1.4.4.2 riz return r;
529 1.4.4.2 riz }
530 1.4.4.2 riz
531 1.4.4.2 riz static int
532 1.4.4.2 riz ld_virtio_detach(device_t self, int flags)
533 1.4.4.2 riz {
534 1.4.4.2 riz struct ld_virtio_softc *sc = device_private(self);
535 1.4.4.2 riz struct ld_softc *ld = &sc->sc_ld;
536 1.4.4.2 riz bus_dma_tag_t dmat = sc->sc_virtio->sc_dmat;
537 1.4.4.2 riz int r, i, qsize;
538 1.4.4.2 riz
539 1.4.4.2 riz qsize = sc->sc_vq[0].vq_num;
540 1.4.4.2 riz r = ldbegindetach(ld, flags);
541 1.4.4.2 riz if (r != 0)
542 1.4.4.2 riz return r;
543 1.4.4.2 riz virtio_reset(sc->sc_virtio);
544 1.4.4.2 riz virtio_free_vq(sc->sc_virtio, &sc->sc_vq[0]);
545 1.4.4.2 riz
546 1.4.4.2 riz for (i = 0; i < qsize; i++) {
547 1.4.4.2 riz bus_dmamap_destroy(dmat,
548 1.4.4.2 riz sc->sc_reqs[i].vr_cmdsts);
549 1.4.4.2 riz bus_dmamap_destroy(dmat,
550 1.4.4.2 riz sc->sc_reqs[i].vr_payload);
551 1.4.4.2 riz }
552 1.4.4.2 riz bus_dmamem_unmap(dmat, sc->sc_reqs,
553 1.4.4.2 riz sizeof(struct virtio_blk_req) * qsize);
554 1.4.4.2 riz bus_dmamem_free(dmat, &sc->sc_reqs_segs[0], 1);
555 1.4.4.2 riz
556 1.4.4.2 riz ldenddetach(ld);
557 1.4.4.2 riz
558 1.4.4.2 riz return 0;
559 1.4.4.2 riz }
560