ld_virtio.c revision 1.14
1 /* $NetBSD: ld_virtio.c,v 1.14 2017/02/27 21:32:33 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2010 Minoura Makoto. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ld_virtio.c,v 1.14 2017/02/27 21:32:33 jdolecek Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/buf.h> 35 #include <sys/bufq.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/disk.h> 39 #include <sys/mutex.h> 40 #include <sys/module.h> 41 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/ldvar.h> 47 #include <dev/pci/virtioreg.h> 48 #include <dev/pci/virtiovar.h> 49 50 #include "ioconf.h" 51 52 /* 53 * ld_virtioreg: 54 */ 55 /* Configuration registers */ 56 #define VIRTIO_BLK_CONFIG_CAPACITY 0 /* 64bit */ 57 #define VIRTIO_BLK_CONFIG_SIZE_MAX 8 /* 32bit */ 58 #define VIRTIO_BLK_CONFIG_SEG_MAX 12 /* 32bit */ 59 #define VIRTIO_BLK_CONFIG_GEOMETRY_C 16 /* 16bit */ 60 #define VIRTIO_BLK_CONFIG_GEOMETRY_H 18 /* 8bit */ 61 #define VIRTIO_BLK_CONFIG_GEOMETRY_S 19 /* 8bit */ 62 #define VIRTIO_BLK_CONFIG_BLK_SIZE 20 /* 32bit */ 63 64 /* Feature bits */ 65 #define VIRTIO_BLK_F_BARRIER (1<<0) 66 #define VIRTIO_BLK_F_SIZE_MAX (1<<1) 67 #define VIRTIO_BLK_F_SEG_MAX (1<<2) 68 #define VIRTIO_BLK_F_GEOMETRY (1<<4) 69 #define VIRTIO_BLK_F_RO (1<<5) 70 #define VIRTIO_BLK_F_BLK_SIZE (1<<6) 71 #define VIRTIO_BLK_F_SCSI (1<<7) 72 #define VIRTIO_BLK_F_FLUSH (1<<9) 73 74 /* 75 * Each block request uses at least two segments - one for the header 76 * and one for the status. 77 */ 78 #define VIRTIO_BLK_MIN_SEGMENTS 2 79 80 #define VIRTIO_BLK_FLAG_BITS \ 81 VIRTIO_COMMON_FLAG_BITS \ 82 "\x0a""FLUSH" \ 83 "\x08""SCSI" \ 84 "\x07""BLK_SIZE" \ 85 "\x06""RO" \ 86 "\x05""GEOMETRY" \ 87 "\x03""SEG_MAX" \ 88 "\x02""SIZE_MAX" \ 89 "\x01""BARRIER" 90 91 /* Command */ 92 #define VIRTIO_BLK_T_IN 0 93 #define VIRTIO_BLK_T_OUT 1 94 #define VIRTIO_BLK_T_BARRIER 0x80000000 95 96 /* Status */ 97 #define VIRTIO_BLK_S_OK 0 98 #define VIRTIO_BLK_S_IOERR 1 99 100 /* Request header structure */ 101 struct virtio_blk_req_hdr { 102 uint32_t type; /* VIRTIO_BLK_T_* */ 103 uint32_t ioprio; 104 uint64_t sector; 105 } __packed; 106 /* 512*virtio_blk_req_hdr.sector byte payload and 1 byte status follows */ 107 108 109 /* 110 * ld_virtiovar: 111 */ 112 struct virtio_blk_req { 113 struct virtio_blk_req_hdr vr_hdr; 114 uint8_t vr_status; 115 struct buf *vr_bp; 116 bus_dmamap_t vr_cmdsts; 117 bus_dmamap_t vr_payload; 118 }; 119 120 struct ld_virtio_softc { 121 struct ld_softc sc_ld; 122 device_t sc_dev; 123 124 struct virtio_softc *sc_virtio; 125 struct virtqueue sc_vq; 126 127 struct virtio_blk_req *sc_reqs; 128 bus_dma_segment_t sc_reqs_seg; 129 130 int sc_readonly; 131 }; 132 133 static int ld_virtio_match(device_t, cfdata_t, void *); 134 static void ld_virtio_attach(device_t, device_t, void *); 135 static int ld_virtio_detach(device_t, int); 136 137 CFATTACH_DECL_NEW(ld_virtio, sizeof(struct ld_virtio_softc), 138 ld_virtio_match, ld_virtio_attach, ld_virtio_detach, NULL); 139 140 static int 141 ld_virtio_match(device_t parent, cfdata_t match, void *aux) 142 { 143 struct virtio_softc *va = aux; 144 145 if (va->sc_childdevid == PCI_PRODUCT_VIRTIO_BLOCK) 146 return 1; 147 148 return 0; 149 } 150 151 static int ld_virtio_vq_done(struct virtqueue *); 152 static int ld_virtio_dump(struct ld_softc *, void *, int, int); 153 static int ld_virtio_start(struct ld_softc *, struct buf *); 154 155 static int 156 ld_virtio_alloc_reqs(struct ld_virtio_softc *sc, int qsize) 157 { 158 int allocsize, r, rsegs, i; 159 struct ld_softc *ld = &sc->sc_ld; 160 void *vaddr; 161 162 allocsize = sizeof(struct virtio_blk_req) * qsize; 163 r = bus_dmamem_alloc(sc->sc_virtio->sc_dmat, allocsize, 0, 0, 164 &sc->sc_reqs_seg, 1, &rsegs, BUS_DMA_NOWAIT); 165 if (r != 0) { 166 aprint_error_dev(sc->sc_dev, 167 "DMA memory allocation failed, size %d, " 168 "error code %d\n", allocsize, r); 169 goto err_none; 170 } 171 r = bus_dmamem_map(sc->sc_virtio->sc_dmat, 172 &sc->sc_reqs_seg, 1, allocsize, 173 &vaddr, BUS_DMA_NOWAIT); 174 if (r != 0) { 175 aprint_error_dev(sc->sc_dev, 176 "DMA memory map failed, " 177 "error code %d\n", r); 178 goto err_dmamem_alloc; 179 } 180 sc->sc_reqs = vaddr; 181 memset(vaddr, 0, allocsize); 182 for (i = 0; i < qsize; i++) { 183 struct virtio_blk_req *vr = &sc->sc_reqs[i]; 184 r = bus_dmamap_create(sc->sc_virtio->sc_dmat, 185 offsetof(struct virtio_blk_req, vr_bp), 186 1, 187 offsetof(struct virtio_blk_req, vr_bp), 188 0, 189 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 190 &vr->vr_cmdsts); 191 if (r != 0) { 192 aprint_error_dev(sc->sc_dev, 193 "command dmamap creation failed, " 194 "error code %d\n", r); 195 goto err_reqs; 196 } 197 r = bus_dmamap_load(sc->sc_virtio->sc_dmat, vr->vr_cmdsts, 198 &vr->vr_hdr, 199 offsetof(struct virtio_blk_req, vr_bp), 200 NULL, BUS_DMA_NOWAIT); 201 if (r != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "command dmamap load failed, " 204 "error code %d\n", r); 205 goto err_reqs; 206 } 207 r = bus_dmamap_create(sc->sc_virtio->sc_dmat, 208 ld->sc_maxxfer, 209 (ld->sc_maxxfer / NBPG) + 210 VIRTIO_BLK_MIN_SEGMENTS, 211 ld->sc_maxxfer, 212 0, 213 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 214 &vr->vr_payload); 215 if (r != 0) { 216 aprint_error_dev(sc->sc_dev, 217 "payload dmamap creation failed, " 218 "error code %d\n", r); 219 goto err_reqs; 220 } 221 } 222 return 0; 223 224 err_reqs: 225 for (i = 0; i < qsize; i++) { 226 struct virtio_blk_req *vr = &sc->sc_reqs[i]; 227 if (vr->vr_cmdsts) { 228 bus_dmamap_destroy(sc->sc_virtio->sc_dmat, 229 vr->vr_cmdsts); 230 vr->vr_cmdsts = 0; 231 } 232 if (vr->vr_payload) { 233 bus_dmamap_destroy(sc->sc_virtio->sc_dmat, 234 vr->vr_payload); 235 vr->vr_payload = 0; 236 } 237 } 238 bus_dmamem_unmap(sc->sc_virtio->sc_dmat, sc->sc_reqs, allocsize); 239 err_dmamem_alloc: 240 bus_dmamem_free(sc->sc_virtio->sc_dmat, &sc->sc_reqs_seg, 1); 241 err_none: 242 return -1; 243 } 244 245 static void 246 ld_virtio_attach(device_t parent, device_t self, void *aux) 247 { 248 struct ld_virtio_softc *sc = device_private(self); 249 struct ld_softc *ld = &sc->sc_ld; 250 struct virtio_softc *vsc = device_private(parent); 251 uint32_t features; 252 char buf[256]; 253 int qsize, maxxfersize, maxnsegs; 254 255 if (vsc->sc_child != NULL) { 256 aprint_normal(": child already attached for %s; " 257 "something wrong...\n", device_xname(parent)); 258 return; 259 } 260 261 sc->sc_dev = self; 262 sc->sc_virtio = vsc; 263 264 vsc->sc_child = self; 265 vsc->sc_ipl = IPL_BIO; 266 vsc->sc_vqs = &sc->sc_vq; 267 vsc->sc_nvqs = 1; 268 vsc->sc_config_change = NULL; 269 vsc->sc_intrhand = virtio_vq_intr; 270 vsc->sc_flags = 0; 271 272 features = virtio_negotiate_features(vsc, 273 (VIRTIO_BLK_F_SIZE_MAX | 274 VIRTIO_BLK_F_SEG_MAX | 275 VIRTIO_BLK_F_GEOMETRY | 276 VIRTIO_BLK_F_RO | 277 VIRTIO_BLK_F_BLK_SIZE)); 278 if (features & VIRTIO_BLK_F_RO) 279 sc->sc_readonly = 1; 280 else 281 sc->sc_readonly = 0; 282 283 snprintb(buf, sizeof(buf), VIRTIO_BLK_FLAG_BITS, features); 284 aprint_normal(": Features: %s\n", buf); 285 aprint_naive("\n"); 286 if (features & VIRTIO_BLK_F_BLK_SIZE) { 287 ld->sc_secsize = virtio_read_device_config_4(vsc, 288 VIRTIO_BLK_CONFIG_BLK_SIZE); 289 } else 290 ld->sc_secsize = 512; 291 292 /* At least genfs_io assumes maxxfer == MAXPHYS. */ 293 if (features & VIRTIO_BLK_F_SIZE_MAX) { 294 maxxfersize = virtio_read_device_config_4(vsc, 295 VIRTIO_BLK_CONFIG_SIZE_MAX); 296 if (maxxfersize < MAXPHYS) { 297 aprint_error_dev(sc->sc_dev, 298 "Too small SIZE_MAX %dK minimum is %dK\n", 299 maxxfersize / 1024, MAXPHYS / 1024); 300 // goto err; 301 maxxfersize = MAXPHYS; 302 } else if (maxxfersize > MAXPHYS) { 303 aprint_normal_dev(sc->sc_dev, 304 "Clip SEG_MAX from %dK to %dK\n", 305 maxxfersize / 1024, 306 MAXPHYS / 1024); 307 maxxfersize = MAXPHYS; 308 } 309 } else 310 maxxfersize = MAXPHYS; 311 312 if (features & VIRTIO_BLK_F_SEG_MAX) { 313 maxnsegs = virtio_read_device_config_4(vsc, 314 VIRTIO_BLK_CONFIG_SEG_MAX); 315 if (maxnsegs < VIRTIO_BLK_MIN_SEGMENTS) { 316 aprint_error_dev(sc->sc_dev, 317 "Too small SEG_MAX %d minimum is %d\n", 318 maxnsegs, VIRTIO_BLK_MIN_SEGMENTS); 319 maxnsegs = maxxfersize / NBPG; 320 // goto err; 321 } 322 } else 323 maxnsegs = maxxfersize / NBPG; 324 325 /* 2 for the minimum size */ 326 maxnsegs += VIRTIO_BLK_MIN_SEGMENTS; 327 328 if (virtio_alloc_vq(vsc, &sc->sc_vq, 0, maxxfersize, maxnsegs, 329 "I/O request") != 0) { 330 goto err; 331 } 332 qsize = sc->sc_vq.vq_num; 333 sc->sc_vq.vq_done = ld_virtio_vq_done; 334 335 ld->sc_dv = self; 336 ld->sc_secperunit = virtio_read_device_config_8(vsc, 337 VIRTIO_BLK_CONFIG_CAPACITY); 338 ld->sc_maxxfer = maxxfersize; 339 if (features & VIRTIO_BLK_F_GEOMETRY) { 340 ld->sc_ncylinders = virtio_read_device_config_2(vsc, 341 VIRTIO_BLK_CONFIG_GEOMETRY_C); 342 ld->sc_nheads = virtio_read_device_config_1(vsc, 343 VIRTIO_BLK_CONFIG_GEOMETRY_H); 344 ld->sc_nsectors = virtio_read_device_config_1(vsc, 345 VIRTIO_BLK_CONFIG_GEOMETRY_S); 346 } 347 ld->sc_maxqueuecnt = qsize; 348 349 if (ld_virtio_alloc_reqs(sc, qsize) < 0) 350 goto err; 351 352 ld->sc_dump = ld_virtio_dump; 353 ld->sc_start = ld_virtio_start; 354 355 ld->sc_flags = LDF_ENABLED; 356 ldattach(ld, BUFQ_DISK_DEFAULT_STRAT); 357 358 return; 359 360 err: 361 vsc->sc_child = (void*)1; 362 return; 363 } 364 365 static int 366 ld_virtio_start(struct ld_softc *ld, struct buf *bp) 367 { 368 /* splbio */ 369 struct ld_virtio_softc *sc = device_private(ld->sc_dv); 370 struct virtio_softc *vsc = sc->sc_virtio; 371 struct virtqueue *vq = &sc->sc_vq; 372 struct virtio_blk_req *vr; 373 int r; 374 int isread = (bp->b_flags & B_READ); 375 int slot; 376 377 if (sc->sc_readonly && !isread) 378 return EIO; 379 380 r = virtio_enqueue_prep(vsc, vq, &slot); 381 if (r != 0) 382 return r; 383 384 vr = &sc->sc_reqs[slot]; 385 KASSERT(vr->vr_bp == NULL); 386 387 r = bus_dmamap_load(vsc->sc_dmat, vr->vr_payload, 388 bp->b_data, bp->b_bcount, NULL, 389 ((isread?BUS_DMA_READ:BUS_DMA_WRITE) 390 |BUS_DMA_NOWAIT)); 391 if (r != 0) { 392 aprint_error_dev(sc->sc_dev, 393 "payload dmamap failed, error code %d\n", r); 394 virtio_enqueue_abort(vsc, vq, slot); 395 return r; 396 } 397 398 r = virtio_enqueue_reserve(vsc, vq, slot, vr->vr_payload->dm_nsegs + 399 VIRTIO_BLK_MIN_SEGMENTS); 400 if (r != 0) { 401 bus_dmamap_unload(vsc->sc_dmat, vr->vr_payload); 402 return r; 403 } 404 405 vr->vr_bp = bp; 406 vr->vr_hdr.type = isread?VIRTIO_BLK_T_IN:VIRTIO_BLK_T_OUT; 407 vr->vr_hdr.ioprio = 0; 408 vr->vr_hdr.sector = bp->b_rawblkno * sc->sc_ld.sc_secsize / 512; 409 410 bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts, 411 0, sizeof(struct virtio_blk_req_hdr), 412 BUS_DMASYNC_PREWRITE); 413 bus_dmamap_sync(vsc->sc_dmat, vr->vr_payload, 414 0, bp->b_bcount, 415 isread?BUS_DMASYNC_PREREAD:BUS_DMASYNC_PREWRITE); 416 bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts, 417 offsetof(struct virtio_blk_req, vr_status), 418 sizeof(uint8_t), 419 BUS_DMASYNC_PREREAD); 420 421 virtio_enqueue_p(vsc, vq, slot, vr->vr_cmdsts, 422 0, sizeof(struct virtio_blk_req_hdr), 423 true); 424 virtio_enqueue(vsc, vq, slot, vr->vr_payload, !isread); 425 virtio_enqueue_p(vsc, vq, slot, vr->vr_cmdsts, 426 offsetof(struct virtio_blk_req, vr_status), 427 sizeof(uint8_t), 428 false); 429 virtio_enqueue_commit(vsc, vq, slot, true); 430 431 return 0; 432 } 433 434 static void 435 ld_virtio_vq_done1(struct ld_virtio_softc *sc, struct virtio_softc *vsc, 436 struct virtqueue *vq, int slot) 437 { 438 struct virtio_blk_req *vr = &sc->sc_reqs[slot]; 439 struct buf *bp = vr->vr_bp; 440 441 vr->vr_bp = NULL; 442 443 bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts, 444 0, sizeof(struct virtio_blk_req_hdr), 445 BUS_DMASYNC_POSTWRITE); 446 bus_dmamap_sync(vsc->sc_dmat, vr->vr_payload, 447 0, bp->b_bcount, 448 (bp->b_flags & B_READ)?BUS_DMASYNC_POSTREAD 449 :BUS_DMASYNC_POSTWRITE); 450 bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts, 451 sizeof(struct virtio_blk_req_hdr), sizeof(uint8_t), 452 BUS_DMASYNC_POSTREAD); 453 454 if (vr->vr_status != VIRTIO_BLK_S_OK) { 455 bp->b_error = EIO; 456 bp->b_resid = bp->b_bcount; 457 } else { 458 bp->b_error = 0; 459 bp->b_resid = 0; 460 } 461 462 virtio_dequeue_commit(vsc, vq, slot); 463 464 lddone(&sc->sc_ld, bp); 465 } 466 467 static int 468 ld_virtio_vq_done(struct virtqueue *vq) 469 { 470 struct virtio_softc *vsc = vq->vq_owner; 471 struct ld_virtio_softc *sc = device_private(vsc->sc_child); 472 int r = 0; 473 int slot; 474 475 again: 476 if (virtio_dequeue(vsc, vq, &slot, NULL)) 477 return r; 478 r = 1; 479 480 ld_virtio_vq_done1(sc, vsc, vq, slot); 481 goto again; 482 } 483 484 static int 485 ld_virtio_dump(struct ld_softc *ld, void *data, int blkno, int blkcnt) 486 { 487 struct ld_virtio_softc *sc = device_private(ld->sc_dv); 488 struct virtio_softc *vsc = sc->sc_virtio; 489 struct virtqueue *vq = &sc->sc_vq; 490 struct virtio_blk_req *vr; 491 int slot, r; 492 493 if (sc->sc_readonly) 494 return EIO; 495 496 r = virtio_enqueue_prep(vsc, vq, &slot); 497 if (r != 0) { 498 if (r == EAGAIN) { /* no free slot; dequeue first */ 499 delay(100); 500 ld_virtio_vq_done(vq); 501 r = virtio_enqueue_prep(vsc, vq, &slot); 502 if (r != 0) 503 return r; 504 } 505 return r; 506 } 507 vr = &sc->sc_reqs[slot]; 508 r = bus_dmamap_load(vsc->sc_dmat, vr->vr_payload, 509 data, blkcnt*ld->sc_secsize, NULL, 510 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 511 if (r != 0) 512 return r; 513 514 r = virtio_enqueue_reserve(vsc, vq, slot, vr->vr_payload->dm_nsegs + 515 VIRTIO_BLK_MIN_SEGMENTS); 516 if (r != 0) { 517 bus_dmamap_unload(vsc->sc_dmat, vr->vr_payload); 518 return r; 519 } 520 521 vr->vr_bp = (void*)0xdeadbeef; 522 vr->vr_hdr.type = VIRTIO_BLK_T_OUT; 523 vr->vr_hdr.ioprio = 0; 524 vr->vr_hdr.sector = (daddr_t) blkno * ld->sc_secsize / 512; 525 526 bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts, 527 0, sizeof(struct virtio_blk_req_hdr), 528 BUS_DMASYNC_PREWRITE); 529 bus_dmamap_sync(vsc->sc_dmat, vr->vr_payload, 530 0, blkcnt*ld->sc_secsize, 531 BUS_DMASYNC_PREWRITE); 532 bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts, 533 offsetof(struct virtio_blk_req, vr_status), 534 sizeof(uint8_t), 535 BUS_DMASYNC_PREREAD); 536 537 virtio_enqueue_p(vsc, vq, slot, vr->vr_cmdsts, 538 0, sizeof(struct virtio_blk_req_hdr), 539 true); 540 virtio_enqueue(vsc, vq, slot, vr->vr_payload, true); 541 virtio_enqueue_p(vsc, vq, slot, vr->vr_cmdsts, 542 offsetof(struct virtio_blk_req, vr_status), 543 sizeof(uint8_t), 544 false); 545 virtio_enqueue_commit(vsc, vq, slot, true); 546 547 for ( ; ; ) { 548 int dslot; 549 550 r = virtio_dequeue(vsc, vq, &dslot, NULL); 551 if (r != 0) 552 continue; 553 if (dslot != slot) { 554 ld_virtio_vq_done1(sc, vsc, vq, dslot); 555 continue; 556 } else 557 break; 558 } 559 560 bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts, 561 0, sizeof(struct virtio_blk_req_hdr), 562 BUS_DMASYNC_POSTWRITE); 563 bus_dmamap_sync(vsc->sc_dmat, vr->vr_payload, 564 0, blkcnt*ld->sc_secsize, 565 BUS_DMASYNC_POSTWRITE); 566 bus_dmamap_sync(vsc->sc_dmat, vr->vr_cmdsts, 567 offsetof(struct virtio_blk_req, vr_status), 568 sizeof(uint8_t), 569 BUS_DMASYNC_POSTREAD); 570 if (vr->vr_status == VIRTIO_BLK_S_OK) 571 r = 0; 572 else 573 r = EIO; 574 virtio_dequeue_commit(vsc, vq, slot); 575 576 return r; 577 } 578 579 static int 580 ld_virtio_detach(device_t self, int flags) 581 { 582 struct ld_virtio_softc *sc = device_private(self); 583 struct ld_softc *ld = &sc->sc_ld; 584 bus_dma_tag_t dmat = sc->sc_virtio->sc_dmat; 585 int r, i, qsize; 586 587 qsize = sc->sc_vq.vq_num; 588 r = ldbegindetach(ld, flags); 589 if (r != 0) 590 return r; 591 virtio_reset(sc->sc_virtio); 592 virtio_free_vq(sc->sc_virtio, &sc->sc_vq); 593 594 for (i = 0; i < qsize; i++) { 595 bus_dmamap_destroy(dmat, 596 sc->sc_reqs[i].vr_cmdsts); 597 bus_dmamap_destroy(dmat, 598 sc->sc_reqs[i].vr_payload); 599 } 600 bus_dmamem_unmap(dmat, sc->sc_reqs, 601 sizeof(struct virtio_blk_req) * qsize); 602 bus_dmamem_free(dmat, &sc->sc_reqs_seg, 1); 603 604 ldenddetach(ld); 605 606 return 0; 607 } 608 609 MODULE(MODULE_CLASS_DRIVER, ld_virtio, "ld,virtio"); 610 611 #ifdef _MODULE 612 /* 613 * XXX Don't allow ioconf.c to redefine the "struct cfdriver ld_cd" 614 * XXX it will be defined in the common-code module 615 */ 616 #undef CFDRIVER_DECL 617 #define CFDRIVER_DECL(name, class, attr) 618 #include "ioconf.c" 619 #endif 620 621 static int 622 ld_virtio_modcmd(modcmd_t cmd, void *opaque) 623 { 624 #ifdef _MODULE 625 /* 626 * We ignore the cfdriver_vec[] that ioconf provides, since 627 * the cfdrivers are attached already. 628 */ 629 static struct cfdriver * const no_cfdriver_vec[] = { NULL }; 630 #endif 631 int error = 0; 632 633 #ifdef _MODULE 634 switch (cmd) { 635 case MODULE_CMD_INIT: 636 error = config_init_component(no_cfdriver_vec, 637 cfattach_ioconf_ld_virtio, cfdata_ioconf_ld_virtio); 638 break; 639 case MODULE_CMD_FINI: 640 error = config_fini_component(no_cfdriver_vec, 641 cfattach_ioconf_ld_virtio, cfdata_ioconf_ld_virtio); 642 break; 643 default: 644 error = ENOTTY; 645 break; 646 } 647 #endif 648 649 return error; 650 } 651
Indexes created Fri Oct 03 02:09:57 GMT 2025