machfb.c revision 1.1
1 /* $NetBSD: machfb.c,v 1.1 2002/10/24 18:15:57 junyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/callout.h> 42 43 #include <dev/ic/videomode.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciio.h> 49 #include <dev/pci/machfbreg.h> 50 51 #include <dev/wscons/wsdisplayvar.h> 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wsfont/wsfont.h> 54 #include <dev/rasops/rasops.h> 55 56 #define MACH64_REG_SIZE 1024 57 58 #define NBARS 3 /* number of Mach64 PCI BARs */ 59 60 struct vga_bar { 61 bus_addr_t vb_base; 62 bus_size_t vb_size; 63 pcireg_t vb_type; 64 int vb_flags; 65 }; 66 67 struct mach64_softc { 68 struct device sc_dev; 69 pci_chipset_tag_t sc_pc; 70 pcitag_t sc_pcitag; 71 72 struct vga_bar sc_bars[NBARS]; 73 struct vga_bar sc_rom; 74 75 #define sc_aperbase sc_bars[0].vb_base 76 #define sc_apersize sc_bars[0].vb_size 77 78 #define sc_iobase sc_bars[1].vb_base 79 #define sc_iosize sc_bars[1].vb_size 80 81 #define sc_regbase sc_bars[2].vb_base 82 #define sc_regsize sc_bars[2].vb_size 83 84 bus_space_handle_t sc_regh; 85 bus_space_handle_t sc_memh; 86 87 u_int aperbase; 88 size_t apersize; 89 u_int regbase; 90 size_t regsize; 91 size_t memsize; 92 int memtype; 93 94 int has_dsp; 95 int bits_per_pixel; 96 int max_x, max_y; 97 int virt_x, virt_y; 98 int color_depth; 99 100 int mem_freq; 101 int ramdac_freq; 102 int ref_freq; 103 104 int ref_div; 105 int log2_vclk_post_div; 106 int vclk_post_div; 107 int vclk_fb_div; 108 int mclk_post_div; 109 int mclk_fb_div; 110 111 struct mach64screen *wanted; 112 struct mach64screen *active; 113 void (*switchcb)(void *, int, int); 114 void *switchcbarg; 115 struct callout switch_callout; 116 int nscreens; 117 LIST_HEAD(, mach64screen) screens; 118 const struct wsscreen_descr *currenttype; 119 }; 120 121 struct mach64screen { 122 LIST_ENTRY(mach64screen) next; 123 struct mach64_softc *sc; 124 const struct wsscreen_descr *type; 125 int active; 126 u_int16_t *mem; 127 int dispoffset; 128 int mindispoffset; 129 int maxdispoffset; 130 131 int cursoron; 132 int cursorcol; 133 int cursorrow; 134 u_int16_t cursortmp; 135 }; 136 137 struct mach64_crtcregs { 138 u_int32_t h_total_disp; 139 u_int32_t h_sync_strt_wid; 140 u_int32_t v_total_disp; 141 u_int32_t v_sync_strt_wid; 142 u_int32_t gen_cntl; 143 u_int32_t clock_cntl; 144 u_int32_t color_depth; 145 u_int32_t dot_clock; 146 }; 147 148 struct { 149 u_int16_t chip_id; 150 u_int32_t ramdac_freq; 151 } mach64_info[] = { 152 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 153 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 154 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 155 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 156 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 157 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 158 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 159 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 160 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 161 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 162 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 163 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 164 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 165 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 166 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 167 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 168 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 169 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 172 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 173 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 174 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 175 }; 176 177 static int mach64_chip_id, mach64_chip_rev; 178 static struct videomode default_mode; 179 struct rasops_info mach64_rasops_info; 180 static struct mach64screen mach64_console_screen; 181 182 static char *mach64_memtype_names[] = { 183 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 184 "(unknown type)" 185 }; 186 187 struct videomode mach64_modes[] = { 188 /* 640x400 @ 70 Hz, 31.5 kHz */ 189 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 190 /* 640x480 @ 72 Hz, 36.5 kHz */ 191 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 192 /* 800x600 @ 72 Hz, 48.0 kHz */ 193 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 194 VID_PHSYNC | VID_PVSYNC }, 195 /* 1024x768 @ 70 Hz, 56.5 kHz */ 196 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 197 VID_NHSYNC | VID_NVSYNC }, 198 /* 1152x864 @ 70 Hz, 62.4 kHz */ 199 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 200 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 201 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 202 VID_NHSYNC | VID_NVSYNC } 203 }; 204 205 /* FIXME values are wrong! */ 206 const u_char mach64_cmap[16 * 3] = { 207 0x00, 0x00, 0x00, /* black */ 208 0x7f, 0x00, 0x00, /* red */ 209 0x00, 0x7f, 0x00, /* green */ 210 0x7f, 0x7f, 0x00, /* brown */ 211 0x00, 0x00, 0x7f, /* blue */ 212 0x7f, 0x00, 0x7f, /* magenta */ 213 0x00, 0x7f, 0x7f, /* cyan */ 214 0xff, 0xff, 0xff, /* white */ 215 216 0x7f, 0x7f, 0x7f, /* black */ 217 0xff, 0x00, 0x00, /* red */ 218 0x00, 0xff, 0x00, /* green */ 219 0xff, 0xff, 0x00, /* brown */ 220 0x00, 0x00, 0xff, /* blue */ 221 0xff, 0x00, 0xff, /* magenta */ 222 0x00, 0xff, 0xff, /* cyan */ 223 0xff, 0xff, 0xff, /* white */ 224 }; 225 226 int mach64_match(struct device *, struct cfdata *, void *); 227 void mach64_attach(struct device *, struct device *, void *); 228 229 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 230 NULL, NULL); 231 232 void mach64_init(struct mach64_softc *, bus_space_tag_t); 233 int mach64_get_memsize(struct mach64_softc *); 234 int mach64_get_max_ramdac(struct mach64_softc *); 235 void mach64_get_mode(struct mach64_softc *, struct videomode *); 236 int mach64_calc_crtcregs(struct mach64_softc *, struct mach64_crtcregs *, 237 struct videomode *); 238 void mach64_set_crtcregs(struct mach64_softc *, struct mach64_crtcregs *); 239 int mach64_modeswitch(struct mach64_softc *, struct videomode *); 240 void mach64_set_dsp(struct mach64_softc *); 241 void mach64_set_pll(struct mach64_softc *, int); 242 void mach64_reset_engine(struct mach64_softc *); 243 void mach64_init_engine(struct mach64_softc *); 244 void mach64_adjust_frame(struct mach64_softc *, int, int); 245 void mach64_init_lut(struct mach64_softc *); 246 void mach64_switch_screen(struct mach64_softc *); 247 void mach64_init_screen(struct mach64_softc *, struct mach64screen *, 248 const struct wsscreen_descr *, int, long *); 249 void mach64_restore_screen(struct mach64screen *, 250 const struct wsscreen_descr *, u_int16_t *); 251 void mach64_set_screentype(struct mach64_softc *, 252 const struct wsscreen_descr *); 253 254 void mach64_cursor(void *, int, int, int); 255 int mach64_mapchar(void *, int, u_int *); 256 void mach64_putchar(void *, int, int, u_int, long); 257 void mach64_copycols(void *, int, int, int, int); 258 void mach64_erasecols(void *, int, int, int, long); 259 void mach64_copyrows(void *, int, int, int); 260 void mach64_eraserows(void *, int, int, long); 261 int mach64_allocattr(void *, int, int, int, long *); 262 263 const struct wsdisplay_emulops mach64_emulops = { 264 mach64_cursor, 265 mach64_mapchar, 266 mach64_putchar, 267 mach64_copycols, 268 mach64_erasecols, 269 mach64_copyrows, 270 mach64_eraserows, 271 mach64_allocattr, 272 }; 273 274 struct wsscreen_descr mach64_defaultscreen = { 275 "default", 276 0, 0, 277 &mach64_rasops_info.ri_ops, 278 8, 16, 279 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 280 &default_mode 281 }, mach64_80x25_screen = { 282 "80x25", 80, 25, 283 &mach64_rasops_info.ri_ops, 284 8, 16, 285 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 286 &mach64_modes[0] 287 }, mach64_80x30_screen = { 288 "80x30", 80, 30, 289 &mach64_rasops_info.ri_ops, 290 8, 16, 291 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 292 &mach64_modes[1] 293 }, mach64_80x40_screen = { 294 "80x40", 80, 40, 295 &mach64_rasops_info.ri_ops, 296 8, 10, 297 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 298 &mach64_modes[0] 299 }, mach64_80x50_screen = { 300 "80x50", 80, 50, 301 &mach64_rasops_info.ri_ops, 302 8, 8, 303 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 304 &mach64_modes[0] 305 }, mach64_100x37_screen = { 306 "100x37", 100, 37, 307 &mach64_rasops_info.ri_ops, 308 8, 16, 309 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 310 &mach64_modes[2] 311 }, mach64_128x48_screen = { 312 "128x48", 128, 48, 313 &mach64_rasops_info.ri_ops, 314 8, 16, 315 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 316 &mach64_modes[3] 317 }, mach64_144x54_screen = { 318 "144x54", 144, 54, 319 &mach64_rasops_info.ri_ops, 320 8, 16, 321 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 322 &mach64_modes[4] 323 }, mach64_160x64_screen = { 324 "160x54", 160, 64, 325 &mach64_rasops_info.ri_ops, 326 8, 16, 327 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 328 &mach64_modes[5] 329 }; 330 331 const struct wsscreen_descr *_mach64_scrlist[] = { 332 &mach64_defaultscreen, 333 &mach64_80x25_screen, 334 &mach64_80x30_screen, 335 &mach64_80x40_screen, 336 &mach64_80x50_screen, 337 &mach64_100x37_screen, 338 &mach64_128x48_screen, 339 &mach64_144x54_screen, 340 &mach64_160x64_screen 341 }; 342 343 struct wsscreen_list mach64_screenlist = { 344 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 345 _mach64_scrlist 346 }; 347 348 int mach64_ioctl(void *, u_long, caddr_t, int, struct proc *); 349 paddr_t mach64_mmap(void *, off_t, int); 350 int mach64_alloc_screen(void *, const struct wsscreen_descr *, void **, 351 int *, int *, long *); 352 void mach64_free_screen(void *, void *); 353 int mach64_show_screen(void *, void *, int, void (*)(void *, int, int), 354 void *); 355 int mach64_load_font(void *, void *, struct wsdisplay_font *); 356 357 struct wsdisplay_accessops mach64_accessops = { 358 mach64_ioctl, 359 mach64_mmap, 360 mach64_alloc_screen, 361 mach64_free_screen, 362 mach64_show_screen, 363 NULL 364 }; 365 366 /* 367 * Inline functions for getting access to register aperture. 368 */ 369 static inline u_int32_t regr(struct mach64_softc *, u_int32_t); 370 static inline u_int8_t regrb(struct mach64_softc *, u_int32_t); 371 static inline void regw(struct mach64_softc *, u_int32_t, u_int32_t); 372 static inline void regwb(struct mach64_softc *, u_int32_t, u_int8_t); 373 static inline void regwb_pll(struct mach64_softc *, u_int32_t, u_int8_t); 374 375 static inline u_int32_t 376 regr(struct mach64_softc *sc, u_int32_t index) 377 { 378 379 return (*(u_int32_t *)(sc->regbase + index)); 380 } 381 382 static inline u_int8_t 383 regrb(struct mach64_softc *sc, u_int32_t index) 384 { 385 386 return (*(u_int8_t *)(sc->regbase + index)); 387 } 388 389 static inline void 390 regw(struct mach64_softc *sc, u_int32_t index, u_int32_t data) 391 { 392 393 *(u_int32_t *)(sc->regbase + index) = data; 394 } 395 396 static inline void 397 regwb(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 398 { 399 400 *(u_int8_t *)(sc->regbase + index) = data; 401 } 402 403 static inline void 404 regwb_pll(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 405 { 406 407 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 408 regwb(sc, CLOCK_CNTL + 2, data); 409 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 410 } 411 412 static inline void 413 wait_for_fifo(struct mach64_softc *sc, u_int8_t v) 414 { 415 416 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 417 ; 418 } 419 420 static inline void 421 wait_for_idle(struct mach64_softc *sc) 422 { 423 424 wait_for_fifo(sc, 16); 425 while ((regr(sc, GUI_STAT) & 1) != 0) 426 ; 427 } 428 429 int 430 mach64_match(struct device *parent, struct cfdata *match, void *aux) 431 { 432 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 433 int i; 434 435 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 436 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 437 return 0; 438 439 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 440 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 441 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 442 mach64_chip_rev = PCI_REVISION(pa->pa_class); 443 return 1; 444 } 445 446 return 0; 447 } 448 449 void 450 mach64_attach(struct device *parent, struct device *self, void *aux) 451 { 452 struct mach64_softc *sc = (void *)self; 453 struct pci_attach_args *pa = aux; 454 char devinfo[256]; 455 int bar, reg, id; 456 struct wsemuldisplaydev_attach_args aa; 457 int console; 458 long defattr; 459 460 sc->sc_pc = pa->pa_pc; 461 sc->sc_pcitag = pa->pa_tag; 462 463 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 464 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 465 466 for (bar = 0; bar < NBARS; bar++) { 467 reg = PCI_MAPREG_START + (bar * 4); 468 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 469 sc->sc_pcitag, reg); 470 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 471 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 472 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 473 } 474 475 mach64_init(sc, pa->pa_memt); 476 477 sc->aperbase = (vaddr_t)bus_space_vaddr(pa->pa_memt, sc->sc_memh); 478 sc->apersize = sc->sc_apersize; 479 480 sc->regbase = sc->aperbase + 0x7ffc00; 481 sc->regsize = MACH64_REG_SIZE; 482 483 #if _BYTE_ORDER == _BIG_ENDIAN 484 sc->aperbase += 0x800000; 485 sc->apersize -= 0x800000; 486 #endif 487 488 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 489 sc->sc_dev.dv_xname, (u_int)(sc->apersize / (1024 * 1024)), 490 (u_int)sc->aperbase, (u_int)(sc->regsize / 1024), 491 (u_int)sc->regbase); 492 493 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 494 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 495 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 496 (mach64_chip_rev & 0x07) == 0)) 497 sc->has_dsp = 0; 498 else 499 sc->has_dsp = 1; 500 501 sc->memsize = mach64_get_memsize(sc); 502 if (sc->memsize == 8192) 503 /* The last page is used as register aperture. */ 504 sc->memsize -= 4; 505 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 506 507 /* XXX is there any way to calculate reference frequency from 508 known values? */ 509 if (mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) 510 sc->ref_freq = 29498; 511 else 512 sc->ref_freq = 14318; 513 514 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 515 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 516 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 517 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 518 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 519 (sc->ref_div * 2); 520 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 521 (sc->mem_freq * sc->ref_div); 522 sc->ramdac_freq = mach64_get_max_ramdac(sc); 523 printf("%s: %d KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 524 sc->sc_dev.dv_xname, sc->memsize, 525 mach64_memtype_names[sc->memtype], 526 sc->mem_freq / 1000, sc->mem_freq % 1000, 527 sc->ramdac_freq / 1000); 528 529 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 530 if (id != mach64_chip_id) { 531 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 532 sc->sc_dev.dv_xname, id, mach64_chip_id); 533 return; 534 } 535 536 #ifdef __sparc__ 537 mach64_get_mode(sc, &default_mode); 538 #else 539 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)) ; 540 #endif 541 542 sc->bits_per_pixel = 8; 543 sc->virt_x = default_mode.hdisplay; 544 sc->virt_y = default_mode.vdisplay; 545 sc->max_x = sc->virt_x - 1; 546 sc->max_y = (sc->memsize * 1024) / 547 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 548 549 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 550 551 mach64_init_engine(sc); 552 #if 0 553 mach64_adjust_frame(0, 0); 554 if (sc->bits_per_pixel == 8) 555 mach64_init_lut(sc); 556 #endif 557 558 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 559 default_mode.hdisplay, default_mode.vdisplay, 560 sc->bits_per_pixel); 561 562 mach64_rasops_info.ri_depth = sc->bits_per_pixel; 563 mach64_rasops_info.ri_bits = (void *)sc->aperbase; 564 mach64_rasops_info.ri_width = default_mode.hdisplay; 565 mach64_rasops_info.ri_height = default_mode.vdisplay; 566 mach64_rasops_info.ri_stride = mach64_rasops_info.ri_width; 567 mach64_rasops_info.ri_flg = RI_CLEAR; 568 569 rasops_init(&mach64_rasops_info, mach64_rasops_info.ri_height / 16, 570 mach64_rasops_info.ri_width / 8); 571 572 mach64_defaultscreen.nrows = mach64_rasops_info.ri_rows; 573 mach64_defaultscreen.ncols = mach64_rasops_info.ri_cols; 574 575 mach64_init_screen(sc, &mach64_console_screen, 576 &mach64_defaultscreen, 1, &defattr); 577 578 mach64_rasops_info.ri_ops.allocattr(&mach64_rasops_info, 0, 0, 0, 579 &defattr); 580 wsdisplay_cnattach(&mach64_defaultscreen, &mach64_rasops_info, 581 0, 0, defattr); 582 583 console = 1; 584 585 aa.console = console; 586 aa.scrdata = &mach64_screenlist; 587 aa.accessops = &mach64_accessops; 588 aa.accesscookie = sc; 589 590 config_found(self, &aa, wsemuldisplaydevprint); 591 } 592 593 void 594 mach64_init_screen(struct mach64_softc *sc, struct mach64screen *scr, 595 const struct wsscreen_descr *type, int existing, long *attrp) 596 { 597 struct videomode *mode = (struct videomode *)type->modecookie; 598 599 scr->sc = sc; 600 scr->type = type; 601 scr->mindispoffset = 0; 602 scr->maxdispoffset = sc->memsize * 1024; 603 scr->dispoffset = 0; 604 scr->cursorcol = 0; 605 scr->cursorrow = 0; 606 607 if (existing) { 608 scr->mem = (u_int16_t *)malloc(type->nrows * type->ncols * 2, 609 M_DEVBUF, M_WAITOK); 610 scr->active = 1; 611 612 #if !defined(__sparc__) 613 if (mach64_modeswitch(sc, mode)) { 614 panic("%s: failed to switch video mode", 615 sc->sc_dev.dv_xname); 616 } 617 #endif 618 } else { 619 scr->active = 0; 620 scr->mem = NULL; 621 } 622 623 wsfont_init(); 624 625 sc->nscreens++; 626 LIST_INSERT_HEAD(&sc->screens, scr, next); 627 } 628 629 void 630 mach64_init(struct mach64_softc *sc, bus_space_tag_t memt) 631 { 632 633 if (bus_space_map(memt, sc->sc_aperbase, sc->sc_apersize, 634 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 635 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 636 } 637 638 sc->nscreens = 0; 639 LIST_INIT(&sc->screens); 640 sc->active = NULL; 641 sc->currenttype = &mach64_defaultscreen; 642 callout_init(&sc->switch_callout); 643 } 644 645 int 646 mach64_get_memsize(struct mach64_softc *sc) 647 { 648 int tmp, memsize; 649 int mem_tab[] = { 650 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 651 }; 652 653 tmp = regr(sc, MEM_CNTL); 654 if (sc->has_dsp) { 655 tmp &= 0x0000000f; 656 if (tmp < 8) 657 memsize = (tmp + 1) * 512; 658 else if (tmp < 12) 659 memsize = (tmp - 3) * 1024; 660 else 661 memsize = (tmp - 7) * 2048; 662 } else { 663 memsize = mem_tab[tmp & 0x07]; 664 } 665 666 return memsize; 667 } 668 669 int 670 mach64_get_max_ramdac(struct mach64_softc *sc) 671 { 672 int i; 673 674 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 675 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 676 (mach64_chip_rev & 0x07)) 677 return 170000; 678 679 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 680 if (mach64_chip_id == mach64_info[i].chip_id) 681 return mach64_info[i].ramdac_freq; 682 683 if (sc->bits_per_pixel == 8) 684 return 135000; 685 else 686 return 80000; 687 } 688 689 void 690 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 691 { 692 struct mach64_crtcregs crtc; 693 694 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 695 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 696 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 697 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 698 699 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 700 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 701 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 702 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 703 mode->hsync_start; 704 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 705 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 706 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 707 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 708 709 #ifdef MACH64_DEBUG 710 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 711 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 712 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 713 #endif 714 } 715 716 int 717 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 718 struct videomode *mode) 719 { 720 721 if (mode->dot_clock > sc->ramdac_freq) 722 /* Clock too high. */ 723 return 1; 724 725 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 726 ((mode->htotal >> 3) - 1); 727 crtc->h_sync_strt_wid = 728 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 729 ((mode->hsync_start >> 3) - 1); 730 731 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 732 (mode->vtotal - 1); 733 crtc->v_sync_strt_wid = 734 ((mode->vsync_end - mode->vsync_start) << 16) | 735 (mode->vsync_start - 1); 736 737 if (mode->flags & VID_NVSYNC) 738 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 739 740 switch (sc->bits_per_pixel) { 741 case 8: 742 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 743 break; 744 case 16: 745 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 746 break; 747 case 32: 748 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 749 break; 750 } 751 752 crtc->gen_cntl = 0; 753 if (mode->flags & VID_INTERLACE) 754 crtc->gen_cntl |= CRTC_INTERLACE_EN; 755 if (mode->flags & VID_CSYNC) 756 crtc->gen_cntl |= CRTC_CSYNC_EN; 757 758 crtc->dot_clock = mode->dot_clock; 759 760 return 0; 761 } 762 763 void 764 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 765 { 766 767 mach64_set_pll(sc, crtc->dot_clock); 768 769 if (sc->has_dsp) 770 mach64_set_dsp(sc); 771 772 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 773 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 774 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 775 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 776 777 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 778 779 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 780 781 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 782 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 783 } 784 785 int 786 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 787 { 788 struct mach64_crtcregs crtc; 789 790 if (mach64_calc_crtcregs(sc, &crtc, mode)) 791 return 1; 792 793 mach64_set_crtcregs(sc, &crtc); 794 return 0; 795 } 796 797 void 798 mach64_reset_engine(struct mach64_softc *sc) 799 { 800 801 /* Reset engine.*/ 802 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 803 804 /* Enable engine. */ 805 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 806 807 /* Ensure engine is not locked up by clearing any FIFO or 808 host errors. */ 809 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 810 BUS_FIFO_ERR_ACK); 811 } 812 813 void 814 mach64_init_engine(struct mach64_softc *sc) 815 { 816 u_int32_t pitch_value; 817 818 pitch_value = sc->virt_x; 819 820 if (sc->bits_per_pixel == 24) 821 pitch_value *= 3; 822 823 mach64_reset_engine(sc); 824 825 wait_for_fifo(sc, 14); 826 827 regw(sc, CONTEXT_MASK, 0xffffffff); 828 829 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 830 831 regw(sc, DST_Y_X, 0); 832 regw(sc, DST_HEIGHT, 0); 833 regw(sc, DST_BRES_ERR, 0); 834 regw(sc, DST_BRES_INC, 0); 835 regw(sc, DST_BRES_DEC, 0); 836 837 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 838 DST_Y_TOP_TO_BOTTOM); 839 840 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 841 842 regw(sc, SRC_Y_X, 0); 843 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 844 regw(sc, SRC_Y_X_START, 0); 845 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 846 847 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 848 849 wait_for_fifo(sc, 13); 850 regw(sc, HOST_CNTL, 0); 851 852 regw(sc, PAT_REG0, 0); 853 regw(sc, PAT_REG1, 0); 854 regw(sc, PAT_CNTL, 0); 855 856 regw(sc, SC_LEFT, 0); 857 regw(sc, SC_TOP, 0); 858 regw(sc, SC_BOTTOM, default_mode.vdisplay - 1); 859 regw(sc, SC_RIGHT, pitch_value - 1); 860 861 regw(sc, DP_BKGD_CLR, 0); 862 regw(sc, DP_FRGD_CLR, 0xffffffff); 863 regw(sc, DP_WRITE_MASK, 0xffffffff); 864 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 865 866 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 867 868 wait_for_fifo(sc, 3); 869 regw(sc, CLR_CMP_CLR, 0); 870 regw(sc, CLR_CMP_MASK, 0xffffffff); 871 regw(sc, CLR_CMP_CNTL, 0); 872 873 wait_for_fifo(sc, 2); 874 switch (sc->bits_per_pixel) { 875 case 8: 876 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 877 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 878 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) & ~DAC_8BIT_EN); 879 break; 880 #if 0 881 case 32: 882 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 883 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 884 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 885 break; 886 #endif 887 } 888 889 wait_for_fifo(sc, 5); 890 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 891 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 892 893 wait_for_idle(sc); 894 } 895 896 void 897 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 898 { 899 int offset; 900 901 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 902 903 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 904 offset); 905 } 906 907 void 908 mach64_set_dsp(struct mach64_softc *sc) 909 { 910 u_int32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 911 u_int32_t dsp_off, dsp_on, dsp_xclks_per_qw; 912 u_int32_t xclks_per_qw, y; 913 u_int32_t fifo_off, fifo_on; 914 915 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 916 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 917 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 918 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 919 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 920 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 921 dsp_loop_latency = 0; 922 fifo_depth = 24; 923 } else { 924 dsp_loop_latency = 2; 925 fifo_depth = 32; 926 } 927 928 dsp_precision = 0; 929 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 930 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 931 y = (xclks_per_qw * fifo_depth) >> 11; 932 while (y) { 933 y >>= 1; 934 dsp_precision++; 935 } 936 dsp_precision -= 5; 937 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 938 939 switch (sc->memtype) { 940 case DRAM: 941 case EDO_DRAM: 942 case PSEUDO_EDO: 943 if (sc->memsize > 1024) { 944 page_size = 9; 945 dsp_loop_latency += 6; 946 } else { 947 page_size = 10; 948 if (sc->memtype == DRAM) 949 dsp_loop_latency += 8; 950 else 951 dsp_loop_latency += 7; 952 } 953 break; 954 case SDRAM: 955 case SGRAM: 956 if (sc->memsize > 1024) { 957 page_size = 8; 958 dsp_loop_latency += 8; 959 } else { 960 page_size = 10; 961 dsp_loop_latency += 9; 962 } 963 break; 964 default: 965 page_size = 10; 966 dsp_loop_latency += 9; 967 break; 968 } 969 970 if (xclks_per_qw >= (page_size << 11)) 971 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 972 else 973 fifo_on = (3 * page_size + 2) << 6; 974 975 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 976 dsp_on = fifo_on >> dsp_precision; 977 dsp_off = fifo_off >> dsp_precision; 978 979 #ifdef MACH64_DEBUG 980 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 981 "dsp_precision = %d, dsp_loop_latency = %d,\n" 982 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 983 "mclk_post_div = %d, vclk_post_div = %d\n", 984 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 985 sc->mclk_fb_div, sc->vclk_fb_div, 986 sc->mclk_post_div, sc->vclk_post_div); 987 #endif 988 989 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 990 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 991 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 992 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 993 } 994 995 void 996 mach64_set_pll(struct mach64_softc *sc, int clock) 997 { 998 int q; 999 1000 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1001 #ifdef MACH64_DEBUG 1002 printf("q = %d\n", q); 1003 #endif 1004 if (q > 25500) { 1005 printf("Warning: q > 25500\n"); 1006 q = 25500; 1007 sc->vclk_post_div = 1; 1008 sc->log2_vclk_post_div = 0; 1009 } else if (q > 12750) { 1010 sc->vclk_post_div = 1; 1011 sc->log2_vclk_post_div = 0; 1012 } else if (q > 6350) { 1013 sc->vclk_post_div = 2; 1014 sc->log2_vclk_post_div = 1; 1015 } else if (q > 3150) { 1016 sc->vclk_post_div = 4; 1017 sc->log2_vclk_post_div = 2; 1018 } else if (q >= 1600) { 1019 sc->vclk_post_div = 8; 1020 sc->log2_vclk_post_div = 3; 1021 } else { 1022 printf("Warning: q < 1600\n"); 1023 sc->vclk_post_div = 8; 1024 sc->log2_vclk_post_div = 3; 1025 } 1026 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1027 1028 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1029 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1030 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1031 } 1032 1033 void 1034 mach64_init_lut(struct mach64_softc *sc) 1035 { 1036 int i; 1037 1038 regwb(sc, DAC_REGS, 0); 1039 1040 for (i = 0; i < 16; i++) { 1041 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3]); 1042 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3 + 1]); 1043 regwb(sc, DAC_REGS + 1, mach64_cmap[i + 3 + 2]); 1044 } 1045 } 1046 1047 void 1048 mach64_switch_screen(struct mach64_softc *sc) 1049 { 1050 struct mach64screen *scr, *oldscr; 1051 const struct wsscreen_descr *type; 1052 1053 scr = sc->wanted; 1054 if (!scr) { 1055 printf("mach64_switch_screen: disappeared\n"); 1056 (*sc->switchcb)(sc->switchcbarg, EIO, 0); 1057 return; 1058 } 1059 type = scr->type; 1060 oldscr = sc->active; /* can be NULL! */ 1061 #ifdef DIAGNOSTIC 1062 if (oldscr) { 1063 if (!oldscr->active) 1064 panic("mach64_switch_screen: not active"); 1065 if (oldscr->type != vc->currenttype) 1066 panic("mach64_switch_screen: bad type"); 1067 } 1068 #endif 1069 if (scr == oldscr) 1070 return; 1071 1072 #ifdef DIAGNOSTIC 1073 if (scr->active) 1074 panic("mach64_switch_screen: active"); 1075 #endif 1076 1077 if (oldscr) 1078 oldscr->active = 0; 1079 1080 if (sc->currenttype != type) { 1081 mach64_set_screentype(sc, type); 1082 sc->currenttype = type; 1083 } 1084 1085 scr->dispoffset = scr->mindispoffset; 1086 1087 if (!oldscr || (scr->dispoffset != oldscr->dispoffset)) { 1088 1089 } 1090 1091 /* Clear the entire screen. */ 1092 1093 scr->active = 1; 1094 mach64_restore_screen(scr, type, scr->mem); 1095 1096 sc->active = scr; 1097 1098 mach64_cursor(scr, scr->cursoron, scr->cursorrow, scr->cursorcol); 1099 1100 sc->wanted = 0; 1101 if (sc->switchcb) 1102 (*sc->switchcb)(sc->switchcbarg, 0, 0); 1103 } 1104 1105 void 1106 mach64_restore_screen(struct mach64screen *scr, 1107 const struct wsscreen_descr *type, u_int16_t *mem) 1108 { 1109 1110 } 1111 1112 void 1113 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1114 { 1115 1116 } 1117 1118 /* 1119 * wsdisplay_emulops 1120 */ 1121 1122 void 1123 mach64_cursor(void *cookie, int on, int row, int col) 1124 { 1125 1126 } 1127 1128 int 1129 mach64_mapchar(void *cookie, int uni, u_int *index) 1130 { 1131 1132 return 0; 1133 } 1134 1135 void 1136 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1137 { 1138 1139 } 1140 1141 void 1142 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1143 { 1144 1145 } 1146 1147 void 1148 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1149 { 1150 1151 } 1152 1153 void 1154 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1155 { 1156 1157 } 1158 1159 void 1160 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1161 { 1162 1163 } 1164 1165 int 1166 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1167 { 1168 1169 return 0; 1170 } 1171 1172 /* 1173 * wsdisplay_accessops 1174 */ 1175 1176 int 1177 mach64_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 1178 { 1179 1180 return ENOTTY; 1181 } 1182 1183 paddr_t 1184 mach64_mmap(void *v, off_t offset, int prot) 1185 { 1186 1187 return -1; 1188 } 1189 1190 int 1191 mach64_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 1192 int *curxp, int *curyp, long *defattrp) 1193 { 1194 struct mach64_softc *sc = v; 1195 struct mach64screen *scr; 1196 1197 if (sc->nscreens == 1) 1198 sc->screens.lh_first->mem = scr->mem; 1199 1200 scr = malloc(sizeof(struct mach64screen), M_DEVBUF, M_WAITOK); 1201 mach64_init_screen(sc, scr, type, 0, defattrp); 1202 1203 if (sc->nscreens == 1) { 1204 scr->active = 1; 1205 sc->active = scr; 1206 sc->currenttype = type; 1207 } else { 1208 scr->mem = malloc(type->ncols * type->nrows * 2, M_DEVBUF, 1209 M_WAITOK); 1210 mach64_eraserows(sc, 0, type->nrows, *defattrp); 1211 } 1212 1213 *cookiep = scr; 1214 *curxp = scr->cursorcol; 1215 *curyp = scr->cursorrow; 1216 1217 return 0; 1218 } 1219 1220 void 1221 mach64_free_screen(void *v, void *cookie) 1222 { 1223 struct mach64_softc *sc = v; 1224 struct mach64screen *scr = cookie; 1225 1226 LIST_REMOVE(scr, next); 1227 if (scr != &mach64_console_screen) 1228 free(scr, M_DEVBUF); 1229 else 1230 panic("mach64_free_screen: console"); 1231 1232 if (sc->active == scr) 1233 sc->active = 0; 1234 } 1235 1236 int 1237 mach64_show_screen(void *v, void *cookie, int waitok, 1238 void (*cb)(void *, int, int), void *cbarg) 1239 { 1240 struct mach64_softc *sc = v; 1241 struct mach64screen *scr, *oldscr; 1242 1243 scr = cookie; 1244 oldscr = sc->active; 1245 if (scr == oldscr) 1246 return 0; 1247 1248 sc->wanted = scr; 1249 sc->switchcb = cb; 1250 sc->switchcbarg = cbarg; 1251 if (cb) { 1252 callout_reset(&sc->switch_callout, 0, 1253 (void(*)(void *))mach64_switch_screen, sc); 1254 return EAGAIN; 1255 } 1256 1257 mach64_switch_screen(sc); 1258 1259 return 0; 1260 } 1261 1262 int 1263 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1264 { 1265 1266 return 0; 1267 } 1268
Indexes created Thu Oct 02 14:10:14 GMT 2025