machfb.c revision 1.101
1 /* $NetBSD: machfb.c,v 1.101 2020/08/07 18:26:33 jdc Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.101 2020/08/07 18:26:33 jdc Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #include <dev/wscons/wsdisplayvar.h> 58 59 #include <dev/wscons/wsconsio.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/rasops/rasops.h> 62 #include <dev/pci/wsdisplay_pci.h> 63 64 #include <dev/wscons/wsdisplay_vconsvar.h> 65 #include <dev/wscons/wsdisplay_glyphcachevar.h> 66 67 #include "opt_wsemul.h" 68 #include "opt_machfb.h" 69 #include "opt_glyphcache.h" 70 71 #ifdef MACHFB_DEBUG 72 #define DPRINTF printf 73 #else 74 #define DPRINTF while (0) printf 75 #endif 76 77 #define MACH64_REG_SIZE 0x800 78 #define MACH64_REG_OFF 0x7ff800 79 80 #define NBARS 3 /* number of Mach64 PCI BARs */ 81 82 struct vga_bar { 83 bus_addr_t vb_base; 84 bus_size_t vb_size; 85 pcireg_t vb_type; 86 int vb_flags; 87 }; 88 89 struct mach64_softc { 90 device_t sc_dev; 91 pci_chipset_tag_t sc_pc; 92 pcitag_t sc_pcitag; 93 94 struct vga_bar sc_bars[NBARS]; 95 struct vga_bar sc_rom; 96 97 #define sc_aperbase sc_bars[0].vb_base 98 #define sc_apersize sc_bars[0].vb_size 99 100 #define sc_iobase sc_bars[1].vb_base 101 #define sc_iosize sc_bars[1].vb_size 102 103 #define sc_regbase sc_bars[2].vb_base 104 #define sc_regsize sc_bars[2].vb_size 105 106 bus_space_tag_t sc_regt; 107 bus_space_tag_t sc_memt; 108 bus_space_tag_t sc_iot; 109 bus_space_handle_t sc_regh; 110 bus_space_handle_t sc_memh; 111 #if 0 112 void *sc_aperture; /* mapped aperture vaddr */ 113 void *sc_registers; /* mapped registers vaddr */ 114 #endif 115 uint32_t sc_nbus, sc_ndev, sc_nfunc; 116 size_t memsize; 117 int memtype; 118 119 int sc_mode; 120 int sc_bg; 121 int sc_locked; 122 123 int has_dsp; 124 int bits_per_pixel; 125 int max_x; 126 int max_y; 127 int virt_x; 128 int virt_y; 129 int color_depth; 130 131 int mem_freq; 132 int ramdac_freq; 133 int ref_freq; 134 int vclk_freq; 135 136 int ref_div; 137 int log2_vclk_post_div; 138 int vclk_post_div; 139 int vclk_fb_div; 140 int mclk_post_div; 141 int mclk_fb_div; 142 int sc_clock; /* which clock to use */ 143 int minref, m; 144 145 struct videomode *sc_my_mode; 146 int sc_edid_size; 147 uint8_t sc_edid_data[1024]; 148 struct edid_info sc_ei; 149 int sc_setmode; 150 int sc_gen_cntl; 151 152 u_char sc_cmap_red[256]; 153 u_char sc_cmap_green[256]; 154 u_char sc_cmap_blue[256]; 155 int sc_dacw, sc_blanked, sc_console; 156 struct vcons_data vd; 157 struct wsdisplay_accessops sc_accessops; 158 glyphcache sc_gc; 159 }; 160 161 struct mach64_crtcregs { 162 uint32_t h_total_disp; 163 uint32_t h_sync_strt_wid; 164 uint32_t v_total_disp; 165 uint32_t v_sync_strt_wid; 166 uint32_t gen_cntl; 167 uint32_t clock_cntl; 168 uint32_t color_depth; 169 uint32_t dot_clock; 170 }; 171 172 static struct { 173 uint16_t chip_id; 174 uint32_t ramdac_freq; 175 } const mach64_info[] = { 176 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 177 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 178 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 179 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 188 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 189 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 190 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 192 #if 0 193 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 194 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 196 #endif 197 { PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI, 230000 }, 198 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 199 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 200 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 201 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 202 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 203 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 204 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 205 }; 206 207 static int mach64_chip_id, mach64_chip_rev; 208 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 209 210 static const char *mach64_gx_memtype_names[] = { 211 "DRAM", "VRAM", "VRAM", "DRAM", 212 "DRAM", "VRAM", "VRAM", "(unknown type)" 213 }; 214 215 static const char *mach64_memtype_names[] = { 216 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 217 "(unknown type)" 218 }; 219 220 extern const u_char rasops_cmap[768]; 221 222 static int mach64_match(device_t, cfdata_t, void *); 223 static void mach64_attach(device_t, device_t, void *); 224 225 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, 226 mach64_attach, NULL, NULL); 227 228 static void mach64_init(struct mach64_softc *); 229 static int mach64_get_memsize(struct mach64_softc *); 230 static int mach64_get_max_ramdac(struct mach64_softc *); 231 static int mach64_ref_freq(void); 232 233 #ifdef MACHFB_DEBUG 234 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 235 #endif 236 237 static int mach64_calc_crtcregs(struct mach64_softc *, 238 struct mach64_crtcregs *, 239 struct videomode *); 240 static void mach64_set_crtcregs(struct mach64_softc *, 241 struct mach64_crtcregs *); 242 243 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 244 static void mach64_set_dsp(struct mach64_softc *); 245 static void mach64_set_pll(struct mach64_softc *, int); 246 static void mach64_reset_engine(struct mach64_softc *); 247 static void mach64_init_engine(struct mach64_softc *); 248 #if 0 249 static void mach64_adjust_frame(struct mach64_softc *, int, int); 250 #endif 251 static void mach64_init_lut(struct mach64_softc *); 252 253 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 254 static int mach64_is_console(struct mach64_softc *); 255 256 static void mach64_cursor(void *, int, int, int); 257 #if 0 258 static int mach64_mapchar(void *, int, u_int *); 259 #endif 260 static void mach64_putchar_mono(void *, int, int, u_int, long); 261 static void mach64_putchar_aa8(void *, int, int, u_int, long); 262 static void mach64_copycols(void *, int, int, int, int); 263 static void mach64_erasecols(void *, int, int, int, long); 264 static void mach64_copyrows(void *, int, int, int); 265 static void mach64_eraserows(void *, int, int, long); 266 static void mach64_clearscreen(struct mach64_softc *); 267 268 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 269 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 270 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 271 uint8_t, uint8_t); 272 static void mach64_bitblt(void *, int, int, int, int, int, int, int); 273 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 274 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 275 uint32_t, uint32_t); 276 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 277 #if 0 278 static void mach64_showpal(struct mach64_softc *); 279 #endif 280 281 static void machfb_blank(struct mach64_softc *, int); 282 static int machfb_drm_print(void *, const char *); 283 284 static struct wsscreen_descr mach64_defaultscreen = { 285 "default", 286 80, 30, 287 NULL, 288 8, 16, 289 WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE 290 | WSSCREEN_RESIZE , 291 NULL 292 }; 293 294 static const struct wsscreen_descr *_mach64_scrlist[] = { 295 &mach64_defaultscreen, 296 }; 297 298 static struct wsscreen_list mach64_screenlist = { 299 __arraycount(_mach64_scrlist), 300 _mach64_scrlist 301 }; 302 303 static int mach64_ioctl(void *, void *, u_long, void *, int, 304 struct lwp *); 305 static paddr_t mach64_mmap(void *, void *, off_t, int); 306 307 static struct vcons_screen mach64_console_screen; 308 309 /* 310 * Inline functions for getting access to register aperture. 311 */ 312 313 static inline uint32_t 314 regr(struct mach64_softc *sc, uint32_t index) 315 { 316 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400); 317 } 318 319 static inline uint8_t 320 regrb(struct mach64_softc *sc, uint32_t index) 321 { 322 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400); 323 } 324 325 static inline void 326 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 327 { 328 bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 329 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 330 BUS_SPACE_BARRIER_WRITE); 331 } 332 333 static inline void 334 regws(struct mach64_softc *sc, uint32_t index, uint32_t data) 335 { 336 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 337 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4, 338 BUS_SPACE_BARRIER_WRITE); 339 } 340 341 static inline void 342 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 343 { 344 bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data); 345 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1, 346 BUS_SPACE_BARRIER_WRITE); 347 } 348 349 static inline void 350 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 351 { 352 uint32_t reg; 353 354 reg = regr(sc, CLOCK_CNTL); 355 reg |= PLL_WR_EN; 356 regw(sc, CLOCK_CNTL, reg); 357 reg &= ~(PLL_ADDR | PLL_DATA); 358 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 359 reg |= data << PLL_DATA_SHIFT; 360 reg |= CLOCK_STROBE; 361 regw(sc, CLOCK_CNTL, reg); 362 reg &= ~PLL_WR_EN; 363 regw(sc, CLOCK_CNTL, reg); 364 } 365 366 static inline uint8_t 367 regrb_pll(struct mach64_softc *sc, uint32_t index) 368 { 369 370 regwb(sc, CLOCK_CNTL + 1, index << 2); 371 return regrb(sc, CLOCK_CNTL + 2); 372 } 373 374 static inline void 375 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 376 { 377 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 378 continue; 379 } 380 381 static inline void 382 wait_for_idle(struct mach64_softc *sc) 383 { 384 wait_for_fifo(sc, 16); 385 while ((regr(sc, GUI_STAT) & 1) != 0) 386 continue; 387 } 388 389 static int 390 mach64_match(device_t parent, cfdata_t match, void *aux) 391 { 392 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 393 int i; 394 395 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 396 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 397 return 0; 398 399 for (i = 0; i < __arraycount(mach64_info); i++) 400 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 401 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 402 mach64_chip_rev = PCI_REVISION(pa->pa_class); 403 return 100; 404 } 405 406 return 0; 407 } 408 409 static void 410 mach64_attach(device_t parent, device_t self, void *aux) 411 { 412 struct mach64_softc *sc = device_private(self); 413 struct pci_attach_args *pa = aux; 414 struct rasops_info *ri; 415 prop_data_t edid_data; 416 const struct videomode *mode = NULL; 417 int bar, id, expected_id; 418 int is_gx; 419 const char **memtype_names; 420 struct wsemuldisplaydev_attach_args aa; 421 long defattr; 422 int width = 1024, height = 768; 423 pcireg_t screg; 424 uint32_t reg; 425 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 426 int use_mmio = FALSE; 427 428 sc->sc_dev = self; 429 sc->sc_pc = pa->pa_pc; 430 sc->sc_pcitag = pa->pa_tag; 431 sc->sc_dacw = -1; 432 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 433 sc->sc_nbus = pa->pa_bus; 434 sc->sc_ndev = pa->pa_device; 435 sc->sc_nfunc = pa->pa_function; 436 sc->sc_locked = 0; 437 sc->sc_iot = pa->pa_iot; 438 sc->sc_accessops.ioctl = mach64_ioctl; 439 sc->sc_accessops.mmap = mach64_mmap; 440 sc->sc_setmode = 0; 441 442 pci_aprint_devinfo(pa, "Graphics processor"); 443 #ifdef MACHFB_DEBUG 444 printf(prop_dictionary_externalize(device_properties(self))); 445 #endif 446 447 /* enable memory access */ 448 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 449 if ((screg & enables) != enables) { 450 screg |= enables; 451 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 452 PCI_COMMAND_STATUS_REG, screg); 453 } 454 for (bar = 0; bar < NBARS; bar++) { 455 reg = PCI_MAPREG_START + (bar * 4); 456 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 457 sc->sc_pcitag, reg); 458 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 459 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 460 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 461 } 462 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 463 (uint32_t)sc->sc_apersize); 464 465 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 466 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 467 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 468 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 469 sc->sc_memt = pa->pa_memt; 470 471 /* use MMIO register aperture if available */ 472 if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) { 473 if (pci_mapreg_map(pa, MACH64_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 474 0, &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase, 475 &sc->sc_regsize) == 0) { 476 477 /* 478 * the MMIO aperture maps both 1KB register blocks, but 479 * all register offsets are relative to the 2nd one so 480 * for now fix this up in MACH64_REG_OFF and the access 481 * functions 482 */ 483 aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n"); 484 use_mmio = TRUE; 485 } 486 } 487 if (!use_mmio) { 488 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, 489 sc->sc_apersize, BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 490 panic("%s: failed to map aperture", 491 device_xname(sc->sc_dev)); 492 } 493 494 sc->sc_regt = sc->sc_memt; 495 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 496 MACH64_REG_SIZE, &sc->sc_regh); 497 } 498 499 mach64_init(sc); 500 501 aprint_normal_dev(sc->sc_dev, 502 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 503 (u_int)(sc->sc_apersize / (1024 * 1024)), 504 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 505 (u_int)sc->sc_regbase); 506 507 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 508 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 509 #ifdef MACHFB_DEBUG 510 mach64_get_mode(sc, NULL); 511 #endif 512 513 prop_dictionary_get_uint32(device_properties(self), "width", &width); 514 prop_dictionary_get_uint32(device_properties(self), "height", &height); 515 516 default_mode.hdisplay = width; 517 default_mode.vdisplay = height; 518 519 memset(&sc->sc_ei, 0, sizeof(sc->sc_ei)); 520 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 521 != NULL) { 522 523 sc->sc_edid_size = uimin(1024, prop_data_size(edid_data)); 524 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 525 memcpy(sc->sc_edid_data, prop_data_value(edid_data), 526 sc->sc_edid_size); 527 528 edid_parse(sc->sc_edid_data, &sc->sc_ei); 529 530 #ifdef MACHFB_DEBUG 531 edid_print(&sc->sc_ei); 532 #endif 533 } 534 is_gx = 0; 535 switch(mach64_chip_id) { 536 case PCI_PRODUCT_ATI_MACH64_GX: 537 case PCI_PRODUCT_ATI_MACH64_CX: 538 is_gx = 1; 539 /* FALLTHROUGH */ 540 case PCI_PRODUCT_ATI_MACH64_CT: 541 sc->has_dsp = 0; 542 break; 543 case PCI_PRODUCT_ATI_MACH64_VT: 544 case PCI_PRODUCT_ATI_RAGE_II: 545 if((mach64_chip_rev & 0x07) == 0) { 546 sc->has_dsp = 0; 547 break; 548 } 549 /* FALLTHROUGH */ 550 default: 551 sc->has_dsp = 1; 552 } 553 554 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 555 556 sc->memsize = mach64_get_memsize(sc); 557 558 if(is_gx) 559 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 560 else 561 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 562 563 sc->ref_freq = mach64_ref_freq(); 564 565 reg = regr(sc, CLOCK_CNTL); 566 sc->sc_clock = reg & 3; 567 DPRINTF("using clock %d\n", sc->sc_clock); 568 569 DPRINTF("ref_freq: %d\n", sc->ref_freq); 570 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 571 DPRINTF("ref_div: %d\n", sc->ref_div); 572 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 573 DPRINTF("mclk_fb_div: %d\n", sc->mclk_fb_div); 574 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 575 (sc->ref_div * 2); 576 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 577 (sc->mem_freq * sc->ref_div); 578 sc->ramdac_freq = mach64_get_max_ramdac(sc); 579 { 580 sc->minref = sc->ramdac_freq / 510; 581 sc->m = sc->ref_freq / sc->minref; 582 DPRINTF("minref: %d m: %d\n", sc->minref, sc->m); 583 } 584 aprint_normal_dev(sc->sc_dev, 585 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 586 (u_long)sc->memsize, 587 memtype_names[sc->memtype], 588 sc->mem_freq / 1000, sc->mem_freq % 1000, 589 sc->ramdac_freq / 1000); 590 591 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 592 switch(mach64_chip_id) { 593 case PCI_PRODUCT_ATI_MACH64_GX: 594 expected_id = 0x00d7; 595 break; 596 case PCI_PRODUCT_ATI_MACH64_CX: 597 expected_id = 0x0057; 598 break; 599 default: 600 /* Most chip IDs match their PCI product ID. */ 601 expected_id = mach64_chip_id; 602 } 603 604 if (id != expected_id) { 605 aprint_error_dev(sc->sc_dev, 606 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 607 return; 608 } 609 610 sc->sc_console = mach64_is_console(sc); 611 sc->sc_gen_cntl = regr(sc, CRTC_GEN_CNTL); 612 aprint_debug("gen_cntl: %08x\n", sc->sc_gen_cntl); 613 sc->sc_gen_cntl &= CRTC_CSYNC_EN; 614 aprint_normal_dev(sc->sc_dev, "found composite sync %s\n", 615 sc->sc_gen_cntl ? "enabled" : "disabled"); 616 617 #define MODE_IS_VALID(m) ((sc->ramdac_freq >= (m)->dot_clock) && \ 618 ((m)->hdisplay <= 1280)) 619 620 /* no mode setting support on ancient chips with external clocks */ 621 sc->sc_setmode = 0; 622 if (!is_gx) { 623 /* 624 * Now pick a mode. 625 */ 626 if ((sc->sc_ei.edid_preferred_mode != NULL)) { 627 struct videomode *m = sc->sc_ei.edid_preferred_mode; 628 if (MODE_IS_VALID(m)) { 629 memcpy(&default_mode, m, 630 sizeof(struct videomode)); 631 sc->sc_setmode = 1; 632 } else { 633 aprint_normal_dev(sc->sc_dev, 634 "unable to use EDID preferred mode " 635 "(%d x %d)\n", m->hdisplay, m->vdisplay); 636 } 637 } 638 /* 639 * if we can't use the preferred mode go look for the 640 * best one we can support 641 */ 642 if (sc->sc_setmode == 0) { 643 struct videomode *m = sc->sc_ei.edid_modes; 644 645 mode = NULL; 646 sort_modes(sc->sc_ei.edid_modes, 647 &sc->sc_ei.edid_preferred_mode, 648 sc->sc_ei.edid_nmodes); 649 for (int n = 0; n < sc->sc_ei.edid_nmodes; n++) 650 if (MODE_IS_VALID(&m[n])) { 651 mode = &m[n]; 652 break; 653 } 654 if (mode != NULL) { 655 memcpy(&default_mode, mode, 656 sizeof(struct videomode)); 657 sc->sc_setmode = 1; 658 } 659 } 660 } 661 662 /* make sure my_mode points at something sensible if the above fails */ 663 if (default_mode.dot_clock == 0) { 664 sc->sc_setmode = 0; 665 mode = pick_mode_by_ref(width, height, 60); 666 if (mode != NULL) { 667 memcpy(&default_mode, mode, sizeof(default_mode)); 668 } else if ((width > 0) && (height > 0)) { 669 default_mode.hdisplay = width; 670 default_mode.vdisplay = height; 671 } else { 672 /* 673 * if we end up here we're probably dealing with 674 * uninitialized hardware - try to set 1024x768@60 and 675 * hope for the best... 676 */ 677 mode = pick_mode_by_ref(1024, 768, 60); 678 if (mode == NULL) return; 679 memcpy(&default_mode, mode, sizeof(default_mode)); 680 if (!is_gx) sc->sc_setmode = 1; 681 } 682 } 683 684 sc->sc_my_mode = &default_mode; 685 686 if ((width == sc->sc_my_mode->hdisplay) && 687 (height == sc->sc_my_mode->vdisplay)) 688 sc->sc_setmode = 0; 689 690 sc->bits_per_pixel = 8; 691 sc->virt_x = sc->sc_my_mode->hdisplay; 692 sc->virt_y = sc->sc_my_mode->vdisplay; 693 sc->max_x = sc->virt_x - 1; 694 sc->max_y = (sc->memsize * 1024) / 695 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 696 697 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 698 699 mach64_init_engine(sc); 700 701 if (sc->sc_setmode) 702 mach64_modeswitch(sc, sc->sc_my_mode); 703 704 aprint_normal_dev(sc->sc_dev, 705 "initial resolution %dx%d at %d bpp\n", 706 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 707 sc->bits_per_pixel); 708 709 wsfont_init(); 710 711 #ifdef GLYPHCACHE_DEBUG 712 /* shrink the screen so we can see part of the glyph cache */ 713 sc->sc_my_mode->vdisplay -= 200; 714 #endif 715 716 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 717 sc->vd.init_screen = mach64_init_screen; 718 sc->vd.show_screen_cookie = &sc->sc_gc; 719 sc->vd.show_screen_cb = glyphcache_adapt; 720 721 sc->sc_gc.gc_bitblt = mach64_bitblt; 722 sc->sc_gc.gc_blitcookie = sc; 723 sc->sc_gc.gc_rop = MIX_SRC; 724 725 ri = &mach64_console_screen.scr_ri; 726 if (sc->sc_console) { 727 728 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 729 &defattr); 730 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 731 732 mach64_defaultscreen.textops = &ri->ri_ops; 733 mach64_defaultscreen.capabilities = ri->ri_caps; 734 mach64_defaultscreen.nrows = ri->ri_rows; 735 mach64_defaultscreen.ncols = ri->ri_cols; 736 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 737 ((sc->memsize * 1024) / sc->sc_my_mode->hdisplay) - 738 sc->sc_my_mode->vdisplay - 5, 739 sc->sc_my_mode->hdisplay, 740 ri->ri_font->fontwidth, 741 ri->ri_font->fontheight, 742 defattr); 743 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 744 } else { 745 /* 746 * since we're not the console we can postpone the rest 747 * until someone actually allocates a screen for us 748 */ 749 if (mach64_console_screen.scr_ri.ri_rows == 0) { 750 /* do some minimal setup to avoid weirdnesses later */ 751 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 752 &defattr); 753 } else 754 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 755 756 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 757 ((sc->memsize * 1024) / sc->sc_my_mode->hdisplay) - 758 sc->sc_my_mode->vdisplay - 5, 759 sc->sc_my_mode->hdisplay, 760 ri->ri_font->fontwidth, 761 ri->ri_font->fontheight, 762 defattr); 763 } 764 765 sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG]; 766 mach64_clearscreen(sc); 767 mach64_init_lut(sc); 768 769 if (sc->sc_console) 770 vcons_replay_msgbuf(&mach64_console_screen); 771 772 machfb_blank(sc, 0); /* unblank the screen */ 773 774 aa.console = sc->sc_console; 775 aa.scrdata = &mach64_screenlist; 776 aa.accessops = &sc->sc_accessops; 777 aa.accesscookie = &sc->vd; 778 779 config_found(self, &aa, wsemuldisplaydevprint); 780 #if 0 781 /* XXX 782 * turns out some firmware doesn't turn these back on when needed 783 * so we need to turn them off only when mapping vram in 784 * WSDISPLAYIO_MODE_DUMB would overlap ( unlikely but far from 785 * impossible ) 786 */ 787 if (use_mmio) { 788 /* 789 * Now that we took over, turn off the aperture registers if we 790 * don't use them. Can't do this earlier since on some hardware 791 * we use firmware calls as early console output which may in 792 * turn try to access these registers. 793 */ 794 reg = regr(sc, BUS_CNTL); 795 aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg); 796 reg |= BUS_APER_REG_DIS; 797 regw(sc, BUS_CNTL, reg); 798 } 799 #endif 800 config_found_ia(self, "drm", aux, machfb_drm_print); 801 } 802 803 static int 804 machfb_drm_print(void *aux, const char *pnp) 805 { 806 if (pnp) 807 aprint_normal("direct rendering for %s", pnp); 808 return (UNSUPP); 809 } 810 811 static void 812 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 813 long *defattr) 814 { 815 struct mach64_softc *sc = cookie; 816 struct rasops_info *ri = &scr->scr_ri; 817 818 ri->ri_depth = sc->bits_per_pixel; 819 ri->ri_width = sc->sc_my_mode->hdisplay; 820 ri->ri_height = sc->sc_my_mode->vdisplay; 821 ri->ri_stride = ri->ri_width; 822 ri->ri_flg = RI_CENTER | RI_FULLCLEAR; 823 if (ri->ri_depth == 8) 824 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA | 825 RI_PREFER_ALPHA; 826 827 #ifdef VCONS_DRAW_INTR 828 scr->scr_flags |= VCONS_DONT_READ; 829 #endif 830 scr->scr_flags |= VCONS_LOADFONT; 831 832 rasops_init(ri, 0, 0); 833 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE | 834 WSSCREEN_RESIZE; 835 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 836 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 837 838 /* enable acceleration */ 839 ri->ri_hw = scr; 840 ri->ri_ops.copyrows = mach64_copyrows; 841 ri->ri_ops.copycols = mach64_copycols; 842 ri->ri_ops.eraserows = mach64_eraserows; 843 ri->ri_ops.erasecols = mach64_erasecols; 844 ri->ri_ops.cursor = mach64_cursor; 845 if (FONT_IS_ALPHA(ri->ri_font)) { 846 ri->ri_ops.putchar = mach64_putchar_aa8; 847 } else 848 ri->ri_ops.putchar = mach64_putchar_mono; 849 } 850 851 static void 852 mach64_init(struct mach64_softc *sc) 853 { 854 sc->sc_blanked = 0; 855 } 856 857 static int 858 mach64_get_memsize(struct mach64_softc *sc) 859 { 860 int tmp, memsize; 861 int mem_tab[] = { 862 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 863 }; 864 tmp = regr(sc, MEM_CNTL); 865 #ifdef DIAGNOSTIC 866 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 867 #endif 868 if (sc->has_dsp) { 869 tmp &= 0x0000000f; 870 if (tmp < 8) 871 memsize = (tmp + 1) * 512; 872 else if (tmp < 12) 873 memsize = (tmp - 3) * 1024; 874 else 875 memsize = (tmp - 7) * 2048; 876 } else { 877 memsize = mem_tab[tmp & 0x07]; 878 } 879 880 return memsize; 881 } 882 883 static int 884 mach64_get_max_ramdac(struct mach64_softc *sc) 885 { 886 int i; 887 888 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 889 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 890 (mach64_chip_rev & 0x07)) 891 return 170000; 892 893 for (i = 0; i < __arraycount(mach64_info); i++) 894 if (mach64_chip_id == mach64_info[i].chip_id) 895 return mach64_info[i].ramdac_freq; 896 897 if (sc->bits_per_pixel == 8) 898 return 135000; 899 else 900 return 80000; 901 } 902 903 static int 904 mach64_ref_freq(void) 905 { 906 /* 907 * There doesn't seem to be any way to calculate the reference 908 * frequency from known values 909 */ 910 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 911 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 912 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI))) 913 return 29498; 914 else 915 return 14318; 916 } 917 918 #ifdef MACHFB_DEBUG 919 static void 920 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 921 { 922 int htotal, hdisplay, hsync_start, hsync_end; 923 int vtotal, vdisplay, vsync_start, vsync_end; 924 int gen_ctl, clk_ctl, clock; 925 int ref_freq, ref_div, mclk_fb_div, vclk_post_div, vclk_fb_div; 926 int nhsync, nvsync; 927 int post_div, dot_clock, vrefresh, vrefresh2; 928 929 hdisplay = regr(sc, CRTC_H_TOTAL_DISP); 930 hsync_end = regr(sc, CRTC_H_SYNC_STRT_WID); 931 vdisplay = regr(sc, CRTC_V_TOTAL_DISP); 932 vsync_end = regr(sc, CRTC_V_SYNC_STRT_WID); 933 gen_ctl = regr(sc, CRTC_GEN_CNTL); 934 clk_ctl = regr(sc, CLOCK_CNTL); 935 clock = clk_ctl & 3; 936 ref_div = regrb_pll(sc, PLL_REF_DIV); 937 mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 938 vclk_post_div = regrb_pll(sc, VCLK_POST_DIV); 939 vclk_fb_div = regrb_pll(sc, VCLK0_FB_DIV + clock); 940 ref_freq = mach64_ref_freq(); 941 942 aprint_normal_dev(sc->sc_dev, "CRTC registers:\n"); 943 aprint_normal("\th total: 0x%08x h sync: 0x%08x\n", 944 hdisplay, hsync_end); 945 aprint_normal("\tv total: 0x%08x v sync: 0x%08x\n", 946 vdisplay, vsync_end); 947 aprint_normal("\t g cntl: 0x%08x c cntl: 0x%08x\n", 948 gen_ctl, clk_ctl); 949 aprint_normal("\t rfreq %d rdiv: %d\n", ref_freq, ref_div); 950 aprint_normal_dev(sc->sc_dev, "PLL registers:\n"); 951 aprint_normal("\t m div: 0x%02x p div: 0x%02x v%d div: 0x%02x\n", 952 mclk_fb_div, vclk_post_div, clock, vclk_fb_div); 953 954 htotal = ((hdisplay & 0x01ff) + 1) << 3; 955 hdisplay = (((hdisplay & 0x1ff0000) >> 16) + 1) << 3; 956 if (hsync_end & CRTC_HSYNC_NEG) 957 nhsync = 1; 958 else 959 nhsync = 0; 960 hsync_start = (((hsync_end & 0xff) + 1) << 3) + 961 ((hsync_end & 0x700) >> 8); 962 hsync_end = (((hsync_end & 0x1f0000) >> 16) << 3) + hsync_start; 963 964 vtotal = (vdisplay & 0x07ff) + 1; 965 vdisplay = ((vdisplay & 0x7ff0000) >> 16) + 1; 966 if (vsync_end & CRTC_VSYNC_NEG) 967 nvsync = 1; 968 else 969 nvsync = 0; 970 vsync_start = (vsync_end & 0x07ff) + 1; 971 vsync_end = ((vsync_end & 0x1f0000) >> 16) + vsync_start; 972 973 switch ((vclk_post_div >> (clock * 2)) & 3) { 974 case 3: 975 post_div = 8; 976 break; 977 case 2: 978 post_div = 4; 979 break; 980 case 1: 981 post_div = 2; 982 break; 983 default: 984 post_div = 1; 985 break; 986 } 987 dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div); 988 vrefresh = (dot_clock * 1000) / (htotal * vtotal); 989 vrefresh2 = ((dot_clock * 1000) - (vrefresh * htotal * vtotal)) * 100 / 990 (htotal * vtotal); 991 992 aprint_normal_dev(sc->sc_dev, "Video mode:\n"); 993 aprint_normal("\t%d" "x%d @ %d.%02dHz " 994 "(%d %d %d %d %d %d %d %cH %cV)\n", 995 hdisplay, vdisplay, vrefresh, vrefresh2, dot_clock, 996 hsync_start, hsync_end, htotal, vsync_start, vsync_end, vtotal, 997 nhsync == 1 ? '-' : '+', nvsync == 1 ? '-' : '+'); 998 999 if (mode != NULL) { 1000 mode->dot_clock = dot_clock; 1001 mode->htotal = htotal; 1002 mode->hdisplay = hdisplay; 1003 mode->hsync_start = hsync_start; 1004 mode->hsync_end = hsync_end; 1005 mode->vtotal = vtotal; 1006 mode->vdisplay = vdisplay; 1007 mode->vsync_start = vsync_start; 1008 mode->vsync_end = vsync_end; 1009 mode->flags = 0; 1010 if (nhsync) 1011 mode->flags |= VID_NHSYNC; 1012 if (nvsync) 1013 mode->flags |= VID_NVSYNC; 1014 } 1015 } 1016 #endif 1017 1018 static int 1019 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 1020 struct videomode *mode) 1021 { 1022 1023 if (mode->dot_clock > sc->ramdac_freq) 1024 /* Clock too high. */ 1025 return 1; 1026 1027 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 1028 ((mode->htotal >> 3) - 1); 1029 crtc->h_sync_strt_wid = 1030 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 1031 ((mode->hsync_start >> 3) - 1) | ((mode->hsync_start & 7) << 8); 1032 1033 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 1034 (mode->vtotal - 1); 1035 crtc->v_sync_strt_wid = 1036 ((mode->vsync_end - mode->vsync_start) << 16) | 1037 (mode->vsync_start - 1); 1038 1039 if (mode->flags & VID_NVSYNC) 1040 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 1041 1042 switch (sc->bits_per_pixel) { 1043 case 8: 1044 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 1045 break; 1046 case 16: 1047 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 1048 break; 1049 case 32: 1050 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 1051 break; 1052 } 1053 1054 crtc->gen_cntl = 0; 1055 if (mode->flags & VID_INTERLACE) 1056 crtc->gen_cntl |= CRTC_INTERLACE_EN; 1057 1058 if (mode->flags & VID_CSYNC) 1059 crtc->gen_cntl |= CRTC_CSYNC_EN; 1060 1061 crtc->dot_clock = mode->dot_clock; 1062 1063 return 0; 1064 } 1065 1066 static void 1067 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1068 { 1069 1070 mach64_set_pll(sc, crtc->dot_clock); 1071 1072 if (sc->has_dsp) 1073 mach64_set_dsp(sc); 1074 1075 DPRINTF("\th total: 0x%08x h sync: 0x%08x\n", 1076 crtc->h_total_disp, crtc->h_sync_strt_wid); 1077 DPRINTF("\tv total: 0x%08x v sync: 0x%08x\n", 1078 crtc->v_total_disp, crtc->v_sync_strt_wid); 1079 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1080 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1081 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1082 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1083 1084 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1085 1086 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1087 1088 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1089 sc->sc_gen_cntl | CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1090 } 1091 1092 static int 1093 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1094 { 1095 struct mach64_crtcregs crtc; 1096 1097 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1098 1099 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1100 return 1; 1101 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1102 if (crtc.dot_clock == 0) { 1103 aprint_error("%s: preposterous dot clock (%d)\n", 1104 device_xname(sc->sc_dev), crtc.dot_clock); 1105 return 1; 1106 } 1107 mach64_set_crtcregs(sc, &crtc); 1108 return 0; 1109 } 1110 1111 static void 1112 mach64_reset_engine(struct mach64_softc *sc) 1113 { 1114 1115 /* Reset engine.*/ 1116 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1117 1118 /* Enable engine. */ 1119 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1120 1121 /* Ensure engine is not locked up by clearing any FIFO or 1122 host errors. */ 1123 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1124 BUS_FIFO_ERR_ACK); 1125 } 1126 1127 static void 1128 mach64_init_engine(struct mach64_softc *sc) 1129 { 1130 uint32_t pitch_value; 1131 1132 pitch_value = sc->virt_x; 1133 1134 if (sc->bits_per_pixel == 24) 1135 pitch_value *= 3; 1136 1137 mach64_reset_engine(sc); 1138 1139 wait_for_fifo(sc, 14); 1140 1141 regw(sc, CONTEXT_MASK, 0xffffffff); 1142 1143 regw(sc, DST_OFF_PITCH, (pitch_value >> 3) << 22); 1144 1145 /* make sure the visible area starts where we're going to draw */ 1146 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1147 1148 regw(sc, DST_Y_X, 0); 1149 regw(sc, DST_HEIGHT, 0); 1150 regw(sc, DST_BRES_ERR, 0); 1151 regw(sc, DST_BRES_INC, 0); 1152 regw(sc, DST_BRES_DEC, 0); 1153 1154 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1155 DST_Y_TOP_TO_BOTTOM); 1156 1157 regw(sc, SRC_OFF_PITCH, (pitch_value >> 3) << 22); 1158 1159 regw(sc, SRC_Y_X, 0); 1160 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1161 regw(sc, SRC_Y_X_START, 0); 1162 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1163 1164 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1165 1166 wait_for_fifo(sc, 13); 1167 regw(sc, HOST_CNTL, 0); 1168 1169 regw(sc, PAT_REG0, 0); 1170 regw(sc, PAT_REG1, 0); 1171 regw(sc, PAT_CNTL, 0); 1172 1173 regw(sc, SC_LEFT, 0); 1174 regw(sc, SC_TOP, 0); 1175 regw(sc, SC_BOTTOM, 0x3fff); 1176 regw(sc, SC_RIGHT, pitch_value - 1); 1177 1178 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1179 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1180 regw(sc, DP_WRITE_MASK, 0xffffffff); 1181 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1182 1183 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1184 1185 wait_for_fifo(sc, 3); 1186 regw(sc, CLR_CMP_CLR, 0); 1187 regw(sc, CLR_CMP_MASK, 0xffffffff); 1188 regw(sc, CLR_CMP_CNTL, 0); 1189 1190 wait_for_fifo(sc, 3); 1191 switch (sc->bits_per_pixel) { 1192 case 8: 1193 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1194 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1195 /* We want 8 bit per channel */ 1196 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1197 break; 1198 case 32: 1199 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1200 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1201 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1202 break; 1203 } 1204 regw(sc, DP_WRITE_MASK, 0xff); 1205 1206 wait_for_fifo(sc, 5); 1207 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1208 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1209 1210 wait_for_idle(sc); 1211 } 1212 1213 #if 0 1214 static void 1215 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1216 { 1217 int offset; 1218 1219 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1220 1221 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1222 offset); 1223 } 1224 #endif 1225 1226 static void 1227 mach64_set_dsp(struct mach64_softc *sc) 1228 { 1229 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1230 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1231 uint32_t xclks_per_qw, xclks_per_qw_m, y; 1232 uint32_t fifo_off, fifo_on; 1233 1234 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1235 1236 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1237 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1238 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1239 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1240 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1241 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1242 dsp_loop_latency = 0; 1243 fifo_depth = 24; 1244 } else { 1245 dsp_loop_latency = 2; 1246 fifo_depth = 32; 1247 } 1248 1249 dsp_precision = 0; 1250 1251 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1252 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1253 1254 xclks_per_qw_m = (sc->mem_freq * 64 << 4) / 1255 (sc->vclk_freq * sc->bits_per_pixel); 1256 1257 DPRINTF("xclks_per_qw %d %d\n", xclks_per_qw >> 7, xclks_per_qw_m); 1258 DPRINTF("mem %dkHz v %dkHz\n", sc->mem_freq, sc->vclk_freq); 1259 1260 y = (xclks_per_qw * fifo_depth) >> 11; 1261 1262 while (y) { 1263 y >>= 1; 1264 dsp_precision++; 1265 } 1266 dsp_precision -= 5; 1267 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1268 1269 switch (sc->memtype) { 1270 case DRAM: 1271 case EDO_DRAM: 1272 case PSEUDO_EDO: 1273 if (sc->memsize > 1024) { 1274 page_size = 9; 1275 dsp_loop_latency += 6; 1276 } else { 1277 page_size = 10; 1278 if (sc->memtype == DRAM) 1279 dsp_loop_latency += 8; 1280 else 1281 dsp_loop_latency += 7; 1282 } 1283 break; 1284 case SDRAM: 1285 if (sc->memsize > 1024) { 1286 page_size = 8; 1287 dsp_loop_latency += 8; 1288 } else { 1289 page_size = 10; 1290 dsp_loop_latency += 9; 1291 } 1292 break; 1293 case SGRAM: 1294 page_size = 8; 1295 dsp_loop_latency = 8; 1296 break; 1297 default: 1298 page_size = 10; 1299 dsp_loop_latency += 9; 1300 break; 1301 } 1302 1303 if (xclks_per_qw >= (page_size << 11)) 1304 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1305 else 1306 fifo_on = (3 * page_size + 2) << 6; 1307 1308 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1309 dsp_on = fifo_on >> dsp_precision; 1310 dsp_off = fifo_off >> dsp_precision; 1311 1312 DPRINTF("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1313 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1314 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1315 "mclk_post_div = %d, vclk_post_div = %d\n", 1316 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1317 sc->mclk_fb_div, sc->vclk_fb_div, 1318 sc->mclk_post_div, sc->vclk_post_div); 1319 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1320 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1321 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1322 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1323 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1324 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1325 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1326 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1327 } 1328 1329 static void 1330 mach64_set_pll(struct mach64_softc *sc, int clock) 1331 { 1332 uint32_t q, clockreg; 1333 int clockshift = sc->sc_clock << 1; 1334 uint8_t reg, vclk_ctl; 1335 1336 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1337 #ifdef MACHFB_DEBUG 1338 printf("q = %d\n", q); 1339 #endif 1340 if (q > 25500) { 1341 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1342 q = 25500; 1343 sc->vclk_post_div = 1; 1344 sc->log2_vclk_post_div = 0; 1345 } else if (q > 12750) { 1346 sc->vclk_post_div = 1; 1347 sc->log2_vclk_post_div = 0; 1348 } else if (q > 6350) { 1349 sc->vclk_post_div = 2; 1350 sc->log2_vclk_post_div = 1; 1351 } else if (q > 3150) { 1352 sc->vclk_post_div = 4; 1353 sc->log2_vclk_post_div = 2; 1354 } else if (q >= 1600) { 1355 sc->vclk_post_div = 8; 1356 sc->log2_vclk_post_div = 3; 1357 } else { 1358 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1359 sc->vclk_post_div = 8; 1360 sc->log2_vclk_post_div = 3; 1361 } 1362 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1363 DPRINTF("post_div: %d log2_post_div: %d mclk_div: %d\n", 1364 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1365 1366 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1367 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1368 vclk_ctl |= PLL_VCLK_RESET; 1369 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1370 1371 DPRINTF("target: %d output: %d\n", clock, 1372 (2 * sc->ref_freq * sc->vclk_fb_div) / 1373 (sc->ref_div * sc->vclk_post_div)); 1374 1375 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1376 reg = regrb_pll(sc, VCLK_POST_DIV); 1377 reg &= ~(3 << clockshift); 1378 reg |= (sc->log2_vclk_post_div << clockshift); 1379 regwb_pll(sc, VCLK_POST_DIV, reg); 1380 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1381 1382 vclk_ctl &= ~PLL_VCLK_RESET; 1383 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1384 1385 clockreg = regr(sc, CLOCK_CNTL); 1386 clockreg &= ~CLOCK_SEL; 1387 clockreg |= sc->sc_clock | CLOCK_STROBE; 1388 regw(sc, CLOCK_CNTL, clockreg); 1389 sc->vclk_freq = clock; 1390 } 1391 1392 static void 1393 mach64_init_lut(struct mach64_softc *sc) 1394 { 1395 uint8_t cmap[768]; 1396 int i, idx; 1397 1398 rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap)); 1399 idx = 0; 1400 for (i = 0; i < 256; i++) { 1401 mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1], 1402 cmap[idx + 2]); 1403 idx += 3; 1404 } 1405 } 1406 1407 static int 1408 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1409 uint8_t b) 1410 { 1411 sc->sc_cmap_red[index] = r; 1412 sc->sc_cmap_green[index] = g; 1413 sc->sc_cmap_blue[index] = b; 1414 /* 1415 * writing the dac index takes a while, in theory we can poll some 1416 * register to see when it's ready - but we better avoid writing it 1417 * unnecessarily 1418 */ 1419 if (index != sc->sc_dacw) { 1420 regwb(sc, DAC_MASK, 0xff); 1421 regwb(sc, DAC_WINDEX, index); 1422 } 1423 sc->sc_dacw = index + 1; 1424 regwb(sc, DAC_DATA, r); 1425 regwb(sc, DAC_DATA, g); 1426 regwb(sc, DAC_DATA, b); 1427 return 0; 1428 } 1429 1430 static int 1431 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1432 { 1433 uint index = cm->index; 1434 uint count = cm->count; 1435 int i, error; 1436 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1437 uint8_t *r, *g, *b; 1438 1439 if (cm->index >= 256 || cm->count > 256 || 1440 (cm->index + cm->count) > 256) 1441 return EINVAL; 1442 error = copyin(cm->red, &rbuf[index], count); 1443 if (error) 1444 return error; 1445 error = copyin(cm->green, &gbuf[index], count); 1446 if (error) 1447 return error; 1448 error = copyin(cm->blue, &bbuf[index], count); 1449 if (error) 1450 return error; 1451 1452 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1453 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1454 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1455 1456 r = &sc->sc_cmap_red[index]; 1457 g = &sc->sc_cmap_green[index]; 1458 b = &sc->sc_cmap_blue[index]; 1459 1460 for (i = 0; i < count; i++) { 1461 mach64_putpalreg(sc, index, *r, *g, *b); 1462 index++; 1463 r++, g++, b++; 1464 } 1465 return 0; 1466 } 1467 1468 static int 1469 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1470 { 1471 u_int index = cm->index; 1472 u_int count = cm->count; 1473 int error; 1474 1475 if (index >= 255 || count > 256 || index + count > 256) 1476 return EINVAL; 1477 1478 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1479 if (error) 1480 return error; 1481 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1482 if (error) 1483 return error; 1484 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1485 if (error) 1486 return error; 1487 1488 return 0; 1489 } 1490 1491 static int 1492 mach64_is_console(struct mach64_softc *sc) 1493 { 1494 bool console = 0; 1495 1496 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1497 "is_console", &console); 1498 return console; 1499 } 1500 1501 /* 1502 * wsdisplay_emulops 1503 */ 1504 1505 static void 1506 mach64_cursor(void *cookie, int on, int row, int col) 1507 { 1508 struct rasops_info *ri = cookie; 1509 struct vcons_screen *scr = ri->ri_hw; 1510 struct mach64_softc *sc = scr->scr_cookie; 1511 int x, y, wi, he; 1512 1513 wi = ri->ri_font->fontwidth; 1514 he = ri->ri_font->fontheight; 1515 1516 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1517 x = ri->ri_ccol * wi + ri->ri_xorigin; 1518 y = ri->ri_crow * he + ri->ri_yorigin; 1519 if (ri->ri_flg & RI_CURSOR) { 1520 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1521 ri->ri_flg &= ~RI_CURSOR; 1522 } 1523 ri->ri_crow = row; 1524 ri->ri_ccol = col; 1525 if (on) { 1526 x = ri->ri_ccol * wi + ri->ri_xorigin; 1527 y = ri->ri_crow * he + ri->ri_yorigin; 1528 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1529 ri->ri_flg |= RI_CURSOR; 1530 } 1531 } else { 1532 scr->scr_ri.ri_crow = row; 1533 scr->scr_ri.ri_ccol = col; 1534 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1535 } 1536 } 1537 1538 #if 0 1539 static int 1540 mach64_mapchar(void *cookie, int uni, u_int *index) 1541 { 1542 return 0; 1543 } 1544 #endif 1545 1546 static void 1547 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1548 { 1549 struct rasops_info *ri = cookie; 1550 struct wsdisplay_font *font = PICK_FONT(ri, c); 1551 struct vcons_screen *scr = ri->ri_hw; 1552 struct mach64_softc *sc = scr->scr_cookie; 1553 1554 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1555 int fg, bg, uc; 1556 uint8_t *data; 1557 int x, y, wi, he; 1558 wi = font->fontwidth; 1559 he = font->fontheight; 1560 1561 if (!CHAR_IN_FONT(c, font)) 1562 return; 1563 bg = ri->ri_devcmap[(attr >> 16) & 0x0f]; 1564 fg = ri->ri_devcmap[(attr >> 24) & 0x0f]; 1565 x = ri->ri_xorigin + col * wi; 1566 y = ri->ri_yorigin + row * he; 1567 if (c == 0x20) { 1568 mach64_rectfill(sc, x, y, wi, he, bg); 1569 } else { 1570 uc = c - font->firstchar; 1571 data = (uint8_t *)font->data + uc * 1572 ri->ri_fontscale; 1573 1574 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1575 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1576 } 1577 if (attr & 1) 1578 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1579 } 1580 } 1581 1582 static void 1583 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 1584 { 1585 struct rasops_info *ri = cookie; 1586 struct wsdisplay_font *font = PICK_FONT(ri, c); 1587 struct vcons_screen *scr = ri->ri_hw; 1588 struct mach64_softc *sc = scr->scr_cookie; 1589 uint32_t bg, fg, latch = 0, bg8, fg8, pixel; 1590 int i, x, y, wi, he, r, g, b, aval; 1591 int r1, g1, b1, r0, g0, b0, fgo, bgo; 1592 uint8_t *data8; 1593 int rv = 0, cnt = 0; 1594 1595 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1596 return; 1597 1598 if (!CHAR_IN_FONT(c, font)) 1599 return; 1600 1601 wi = font->fontwidth; 1602 he = font->fontheight; 1603 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1604 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1605 x = ri->ri_xorigin + col * wi; 1606 y = ri->ri_yorigin + row * he; 1607 1608 if (c == 0x20) { 1609 mach64_rectfill(sc, x, y, wi, he, bg); 1610 if (attr & 1) 1611 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1612 return; 1613 } 1614 1615 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1616 if (rv == GC_OK) 1617 return; 1618 1619 data8 = WSFONT_GLYPH(c, font); 1620 1621 wait_for_fifo(sc, 11); 1622 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1623 regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST); 1624 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1625 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1626 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1627 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1628 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1629 regw(sc, SRC_Y_X, 0); 1630 regw(sc, SRC_WIDTH1, wi); 1631 regw(sc, DST_Y_X, (x << 16) | y); 1632 regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he); 1633 1634 /* 1635 * we need the RGB colours here, so get offsets into rasops_cmap 1636 */ 1637 fgo = ((attr >> 24) & 0xf) * 3; 1638 bgo = ((attr >> 16) & 0xf) * 3; 1639 1640 r0 = rasops_cmap[bgo]; 1641 r1 = rasops_cmap[fgo]; 1642 g0 = rasops_cmap[bgo + 1]; 1643 g1 = rasops_cmap[fgo + 1]; 1644 b0 = rasops_cmap[bgo + 2]; 1645 b1 = rasops_cmap[fgo + 2]; 1646 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 1647 bg8 = R3G3B2(r0, g0, b0); 1648 fg8 = R3G3B2(r1, g1, b1); 1649 1650 wait_for_fifo(sc, 10); 1651 1652 for (i = 0; i < ri->ri_fontscale; i++) { 1653 aval = *data8; 1654 if (aval == 0) { 1655 pixel = bg8; 1656 } else if (aval == 255) { 1657 pixel = fg8; 1658 } else { 1659 r = aval * r1 + (255 - aval) * r0; 1660 g = aval * g1 + (255 - aval) * g0; 1661 b = aval * b1 + (255 - aval) * b0; 1662 pixel = ((r & 0xe000) >> 8) | 1663 ((g & 0xe000) >> 11) | 1664 ((b & 0xc000) >> 14); 1665 } 1666 latch = (latch << 8) | pixel; 1667 /* write in 32bit chunks */ 1668 if ((i & 3) == 3) { 1669 regws(sc, HOST_DATA0, latch); 1670 /* 1671 * not strictly necessary, old data should be shifted 1672 * out 1673 */ 1674 latch = 0; 1675 cnt++; 1676 if (cnt > 8) { 1677 wait_for_fifo(sc, 10); 1678 cnt = 0; 1679 } 1680 } 1681 data8++; 1682 } 1683 /* if we have pixels left in latch write them out */ 1684 if ((i & 3) != 0) { 1685 latch = latch << ((4 - (i & 3)) << 3); 1686 regws(sc, HOST_DATA0, latch); 1687 } 1688 1689 if (rv == GC_ADD) { 1690 glyphcache_add(&sc->sc_gc, c, x, y); 1691 } else if (attr & 1) { 1692 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1693 } 1694 1695 } 1696 1697 static void 1698 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1699 { 1700 struct rasops_info *ri = cookie; 1701 struct vcons_screen *scr = ri->ri_hw; 1702 struct mach64_softc *sc = scr->scr_cookie; 1703 int32_t xs, xd, y, width, height; 1704 1705 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1706 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1707 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1708 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1709 width = ri->ri_font->fontwidth * ncols; 1710 height = ri->ri_font->fontheight; 1711 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC); 1712 } 1713 } 1714 1715 static void 1716 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1717 { 1718 struct rasops_info *ri = cookie; 1719 struct vcons_screen *scr = ri->ri_hw; 1720 struct mach64_softc *sc = scr->scr_cookie; 1721 int32_t x, y, width, height, fg, bg, ul; 1722 1723 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1724 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1725 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1726 width = ri->ri_font->fontwidth * ncols; 1727 height = ri->ri_font->fontheight; 1728 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1729 1730 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1731 } 1732 } 1733 1734 static void 1735 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1736 { 1737 struct rasops_info *ri = cookie; 1738 struct vcons_screen *scr = ri->ri_hw; 1739 struct mach64_softc *sc = scr->scr_cookie; 1740 int32_t x, ys, yd, width, height; 1741 1742 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1743 x = ri->ri_xorigin; 1744 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1745 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1746 width = ri->ri_emuwidth; 1747 height = ri->ri_font->fontheight*nrows; 1748 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC); 1749 } 1750 } 1751 1752 static void 1753 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1754 { 1755 struct rasops_info *ri = cookie; 1756 struct vcons_screen *scr = ri->ri_hw; 1757 struct mach64_softc *sc = scr->scr_cookie; 1758 int32_t x, y, width, height, fg, bg, ul; 1759 1760 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1761 if ((row == 0) && (nrows == ri->ri_rows)) { 1762 /* clear full screen */ 1763 x = 0; 1764 y = 0; 1765 width = sc->virt_x; 1766 height = sc->virt_y; 1767 } else { 1768 x = ri->ri_xorigin; 1769 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1770 width = ri->ri_emuwidth; 1771 height = ri->ri_font->fontheight * nrows; 1772 } 1773 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1774 1775 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1776 } 1777 } 1778 1779 static void 1780 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width, 1781 int height, int rop) 1782 { 1783 struct mach64_softc *sc = cookie; 1784 uint32_t dest_ctl = 0; 1785 1786 #if 0 1787 wait_for_idle(sc); 1788 #else 1789 wait_for_fifo(sc, 10); 1790 #endif 1791 1792 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1793 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1794 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1795 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1796 if (yd < ys) { 1797 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1798 } else { 1799 ys += height - 1; 1800 yd += height - 1; 1801 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1802 } 1803 if (xd < xs) { 1804 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1805 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1806 } else { 1807 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1808 xs += width - 1; 1809 xd += width - 1; 1810 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1811 } 1812 regw(sc, DST_CNTL, dest_ctl); 1813 1814 regw(sc, SRC_Y_X, (xs << 16) | ys); 1815 regw(sc, SRC_WIDTH1, width); 1816 regw(sc, DST_Y_X, (xd << 16) | yd); 1817 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1818 } 1819 1820 static void 1821 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1822 int height, uint32_t fg, uint32_t bg) 1823 { 1824 wait_for_idle(sc); 1825 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1826 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1827 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1828 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1829 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1830 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1831 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1832 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1833 regw(sc, DP_BKGD_CLR, bg); 1834 regw(sc, DP_FRGD_CLR, fg); 1835 regw(sc, SRC_Y_X, 0); 1836 regw(sc, SRC_WIDTH1, width); 1837 regw(sc, DST_Y_X, (xd << 16) | yd); 1838 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1839 /* now feed the data into the chip */ 1840 } 1841 1842 static void 1843 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1844 { 1845 int i; 1846 uint32_t latch = 0, bork; 1847 int shift = 0; 1848 int reg = 0; 1849 1850 for (i = 0; i < count; i++) { 1851 bork = data[i]; 1852 latch |= (bork << shift); 1853 if (shift == 24) { 1854 regw(sc, HOST_DATA0 + reg, latch); 1855 latch = 0; 1856 shift = 0; 1857 reg = (reg + 4) & 0x3c; 1858 } else 1859 shift += 8; 1860 } 1861 if (shift != 0) /* 24 */ 1862 regw(sc, HOST_DATA0 + reg, latch); 1863 } 1864 1865 1866 static void 1867 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1868 int colour) 1869 { 1870 wait_for_fifo(sc, 11); 1871 regw(sc, DP_FRGD_CLR, colour); 1872 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1873 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1874 regw(sc, DP_MIX, MIX_SRC << 16); 1875 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1876 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1877 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1878 1879 regw(sc, SRC_Y_X, (x << 16) | y); 1880 regw(sc, SRC_WIDTH1, width); 1881 regw(sc, DST_Y_X, (x << 16) | y); 1882 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1883 } 1884 1885 static void 1886 mach64_clearscreen(struct mach64_softc *sc) 1887 { 1888 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1889 } 1890 1891 1892 #if 0 1893 static void 1894 mach64_showpal(struct mach64_softc *sc) 1895 { 1896 int i, x = 0; 1897 1898 for (i = 0; i < 16; i++) { 1899 mach64_rectfill(sc, x, 0, 64, 64, i); 1900 x += 64; 1901 } 1902 } 1903 #endif 1904 1905 /* 1906 * wsdisplay_accessops 1907 */ 1908 1909 static int 1910 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1911 struct lwp *l) 1912 { 1913 struct vcons_data *vd = v; 1914 struct mach64_softc *sc = vd->cookie; 1915 struct wsdisplay_fbinfo *wdf; 1916 struct vcons_screen *ms = vd->active; 1917 1918 switch (cmd) { 1919 case WSDISPLAYIO_GTYPE: 1920 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1921 return 0; 1922 1923 case WSDISPLAYIO_LINEBYTES: 1924 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1925 return 0; 1926 1927 case WSDISPLAYIO_GINFO: 1928 wdf = (void *)data; 1929 wdf->height = sc->virt_y; 1930 wdf->width = sc->virt_x; 1931 wdf->depth = sc->bits_per_pixel; 1932 wdf->cmsize = 256; 1933 return 0; 1934 1935 case WSDISPLAYIO_GETCMAP: 1936 return mach64_getcmap(sc, 1937 (struct wsdisplay_cmap *)data); 1938 1939 case WSDISPLAYIO_PUTCMAP: 1940 return mach64_putcmap(sc, 1941 (struct wsdisplay_cmap *)data); 1942 1943 /* PCI config read/write passthrough. */ 1944 case PCI_IOC_CFGREAD: 1945 case PCI_IOC_CFGWRITE: 1946 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1947 cmd, data, flag, l); 1948 1949 case WSDISPLAYIO_GET_BUSID: 1950 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1951 sc->sc_pcitag, data); 1952 1953 case WSDISPLAYIO_SMODE: { 1954 int new_mode = *(int*)data; 1955 if (new_mode != sc->sc_mode) { 1956 sc->sc_mode = new_mode; 1957 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1958 && (ms != NULL)) 1959 { 1960 /* restore initial video mode */ 1961 mach64_init(sc); 1962 mach64_init_engine(sc); 1963 mach64_init_lut(sc); 1964 if (sc->sc_setmode) 1965 mach64_modeswitch(sc, sc->sc_my_mode); 1966 mach64_clearscreen(sc); 1967 glyphcache_wipe(&sc->sc_gc); 1968 vcons_redraw_screen(ms); 1969 } 1970 } 1971 } 1972 return 0; 1973 case WSDISPLAYIO_GET_EDID: { 1974 struct wsdisplayio_edid_info *d = data; 1975 return wsdisplayio_get_edid(sc->sc_dev, d); 1976 } 1977 1978 case WSDISPLAYIO_GET_FBINFO: { 1979 struct wsdisplayio_fbinfo *fbi = data; 1980 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1981 } 1982 } 1983 return EPASSTHROUGH; 1984 } 1985 1986 static paddr_t 1987 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1988 { 1989 struct vcons_data *vd = v; 1990 struct mach64_softc *sc = vd->cookie; 1991 paddr_t pa; 1992 1993 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 1994 /* 1995 *'regular' framebuffer mmap()ing 1996 */ 1997 if (offset < (sc->memsize * 1024)) { 1998 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, 1999 offset, prot, BUS_SPACE_MAP_LINEAR); 2000 return pa; 2001 } 2002 } else if (sc->sc_mode == WSDISPLAYIO_MODE_MAPPED) { 2003 /* 2004 * restrict all other mappings to processes with superuser 2005 * privileges 2006 */ 2007 if (kauth_authorize_machdep(kauth_cred_get(), 2008 KAUTH_MACHDEP_UNMANAGEDMEM, 2009 NULL, NULL, NULL, NULL) != 0) { 2010 return -1; 2011 } 2012 if ((offset >= sc->sc_aperbase) && 2013 (offset < (sc->sc_aperbase + sc->sc_apersize))) { 2014 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2015 BUS_SPACE_MAP_LINEAR); 2016 return pa; 2017 } 2018 2019 if ((offset >= sc->sc_regbase) && 2020 (offset < (sc->sc_regbase + sc->sc_regsize))) { 2021 pa = bus_space_mmap(sc->sc_regt, offset, 0, prot, 2022 BUS_SPACE_MAP_LINEAR); 2023 return pa; 2024 } 2025 2026 if ((offset >= sc->sc_rom.vb_base) && 2027 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 2028 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2029 BUS_SPACE_MAP_LINEAR); 2030 return pa; 2031 } 2032 2033 #ifdef PCI_MAGIC_IO_RANGE 2034 if ((offset >= PCI_MAGIC_IO_RANGE) && 2035 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 2036 return bus_space_mmap(sc->sc_iot, 2037 offset - PCI_MAGIC_IO_RANGE, 0, prot, 0); 2038 } 2039 #endif 2040 } 2041 return -1; 2042 } 2043 2044 #if 0 2045 static int 2046 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 2047 { 2048 2049 return 0; 2050 } 2051 #endif 2052 2053 void 2054 machfb_blank(struct mach64_softc *sc, int blank) 2055 { 2056 uint32_t reg; 2057 2058 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 2059 2060 switch (blank) 2061 { 2062 case 0: 2063 reg = regr(sc, CRTC_GEN_CNTL); 2064 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 2065 sc->sc_blanked = 0; 2066 break; 2067 case 1: 2068 reg = regr(sc, CRTC_GEN_CNTL); 2069 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 2070 sc->sc_blanked = 1; 2071 break; 2072 default: 2073 break; 2074 } 2075 } 2076
Indexes created Thu Oct 02 14:10:14 GMT 2025