machfb.c revision 1.102
1 /* $NetBSD: machfb.c,v 1.102 2020/08/07 23:31:07 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.102 2020/08/07 23:31:07 macallan Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #include <dev/wscons/wsdisplayvar.h> 58 59 #include <dev/wscons/wsconsio.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/rasops/rasops.h> 62 #include <dev/pci/wsdisplay_pci.h> 63 64 #include <dev/wscons/wsdisplay_vconsvar.h> 65 #include <dev/wscons/wsdisplay_glyphcachevar.h> 66 67 #include "opt_wsemul.h" 68 #include "opt_machfb.h" 69 #include "opt_glyphcache.h" 70 71 #ifdef MACHFB_DEBUG 72 #define DPRINTF printf 73 #else 74 #define DPRINTF while (0) printf 75 #endif 76 77 #define MACH64_REG_SIZE 0x800 78 #define MACH64_REG_OFF 0x7ff800 79 80 #define NBARS 3 /* number of Mach64 PCI BARs */ 81 82 struct vga_bar { 83 bus_addr_t vb_base; 84 bus_size_t vb_size; 85 pcireg_t vb_type; 86 int vb_flags; 87 }; 88 89 struct mach64_softc { 90 device_t sc_dev; 91 pci_chipset_tag_t sc_pc; 92 pcitag_t sc_pcitag; 93 94 struct vga_bar sc_bars[NBARS]; 95 struct vga_bar sc_rom; 96 97 #define sc_aperbase sc_bars[0].vb_base 98 #define sc_apersize sc_bars[0].vb_size 99 100 #define sc_iobase sc_bars[1].vb_base 101 #define sc_iosize sc_bars[1].vb_size 102 103 #define sc_regbase sc_bars[2].vb_base 104 #define sc_regsize sc_bars[2].vb_size 105 106 bus_space_tag_t sc_regt; 107 bus_space_tag_t sc_memt; 108 bus_space_tag_t sc_iot; 109 bus_space_handle_t sc_regh; 110 bus_space_handle_t sc_memh; 111 #if 0 112 void *sc_aperture; /* mapped aperture vaddr */ 113 void *sc_registers; /* mapped registers vaddr */ 114 #endif 115 uint32_t sc_nbus, sc_ndev, sc_nfunc; 116 size_t memsize; 117 int memtype; 118 119 int sc_mode; 120 int sc_bg; 121 int sc_locked; 122 123 int has_dsp; 124 int bits_per_pixel; 125 int max_x; 126 int max_y; 127 int virt_x; 128 int virt_y; 129 int stride; /* in pixels */ 130 int color_depth; 131 132 int mem_freq; 133 int ramdac_freq; 134 int ref_freq; 135 int vclk_freq; 136 137 int ref_div; 138 int log2_vclk_post_div; 139 int vclk_post_div; 140 int vclk_fb_div; 141 int mclk_post_div; 142 int mclk_fb_div; 143 int sc_clock; /* which clock to use */ 144 int minref, m; 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 struct edid_info sc_ei; 150 int sc_setmode; 151 int sc_gen_cntl; 152 153 u_char sc_cmap_red[256]; 154 u_char sc_cmap_green[256]; 155 u_char sc_cmap_blue[256]; 156 int sc_dacw, sc_blanked, sc_console; 157 struct vcons_data vd; 158 struct wsdisplay_accessops sc_accessops; 159 glyphcache sc_gc; 160 }; 161 162 struct mach64_crtcregs { 163 uint32_t h_total_disp; 164 uint32_t h_sync_strt_wid; 165 uint32_t v_total_disp; 166 uint32_t v_sync_strt_wid; 167 uint32_t gen_cntl; 168 uint32_t clock_cntl; 169 uint32_t color_depth; 170 uint32_t dot_clock; 171 }; 172 173 static struct { 174 uint16_t chip_id; 175 uint32_t ramdac_freq; 176 } const mach64_info[] = { 177 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 178 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 179 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 189 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 190 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 193 #if 0 194 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 197 #endif 198 { PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI, 230000 }, 199 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 200 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 201 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 202 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 203 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 204 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 205 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 206 }; 207 208 static int mach64_chip_id, mach64_chip_rev; 209 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 210 211 static const char *mach64_gx_memtype_names[] = { 212 "DRAM", "VRAM", "VRAM", "DRAM", 213 "DRAM", "VRAM", "VRAM", "(unknown type)" 214 }; 215 216 static const char *mach64_memtype_names[] = { 217 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 218 "(unknown type)" 219 }; 220 221 extern const u_char rasops_cmap[768]; 222 223 static int mach64_match(device_t, cfdata_t, void *); 224 static void mach64_attach(device_t, device_t, void *); 225 226 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, 227 mach64_attach, NULL, NULL); 228 229 static void mach64_init(struct mach64_softc *); 230 static int mach64_get_memsize(struct mach64_softc *); 231 static int mach64_get_max_ramdac(struct mach64_softc *); 232 static int mach64_ref_freq(void); 233 234 #ifdef MACHFB_DEBUG 235 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 236 #endif 237 238 static int mach64_calc_crtcregs(struct mach64_softc *, 239 struct mach64_crtcregs *, 240 struct videomode *); 241 static void mach64_set_crtcregs(struct mach64_softc *, 242 struct mach64_crtcregs *); 243 244 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 245 static void mach64_set_dsp(struct mach64_softc *); 246 static void mach64_set_pll(struct mach64_softc *, int); 247 static void mach64_reset_engine(struct mach64_softc *); 248 static void mach64_init_engine(struct mach64_softc *); 249 #if 0 250 static void mach64_adjust_frame(struct mach64_softc *, int, int); 251 #endif 252 static void mach64_init_lut(struct mach64_softc *); 253 254 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 255 static int mach64_is_console(struct mach64_softc *); 256 257 static void mach64_cursor(void *, int, int, int); 258 #if 0 259 static int mach64_mapchar(void *, int, u_int *); 260 #endif 261 static void mach64_putchar_mono(void *, int, int, u_int, long); 262 static void mach64_putchar_aa8(void *, int, int, u_int, long); 263 static void mach64_copycols(void *, int, int, int, int); 264 static void mach64_erasecols(void *, int, int, int, long); 265 static void mach64_copyrows(void *, int, int, int); 266 static void mach64_eraserows(void *, int, int, long); 267 static void mach64_clearscreen(struct mach64_softc *); 268 269 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 270 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 271 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 272 uint8_t, uint8_t); 273 static void mach64_bitblt(void *, int, int, int, int, int, int, int); 274 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 275 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 276 uint32_t, uint32_t); 277 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 278 #if 0 279 static void mach64_showpal(struct mach64_softc *); 280 #endif 281 282 static void machfb_blank(struct mach64_softc *, int); 283 static int machfb_drm_print(void *, const char *); 284 285 static struct wsscreen_descr mach64_defaultscreen = { 286 "default", 287 80, 30, 288 NULL, 289 8, 16, 290 WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE 291 | WSSCREEN_RESIZE , 292 NULL 293 }; 294 295 static const struct wsscreen_descr *_mach64_scrlist[] = { 296 &mach64_defaultscreen, 297 }; 298 299 static struct wsscreen_list mach64_screenlist = { 300 __arraycount(_mach64_scrlist), 301 _mach64_scrlist 302 }; 303 304 static int mach64_ioctl(void *, void *, u_long, void *, int, 305 struct lwp *); 306 static paddr_t mach64_mmap(void *, void *, off_t, int); 307 308 static struct vcons_screen mach64_console_screen; 309 310 /* 311 * Inline functions for getting access to register aperture. 312 */ 313 314 static inline uint32_t 315 regr(struct mach64_softc *sc, uint32_t index) 316 { 317 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400); 318 } 319 320 static inline uint8_t 321 regrb(struct mach64_softc *sc, uint32_t index) 322 { 323 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400); 324 } 325 326 static inline void 327 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 328 { 329 bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 330 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 331 BUS_SPACE_BARRIER_WRITE); 332 } 333 334 static inline void 335 regws(struct mach64_softc *sc, uint32_t index, uint32_t data) 336 { 337 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 338 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4, 339 BUS_SPACE_BARRIER_WRITE); 340 } 341 342 static inline void 343 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 344 { 345 bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data); 346 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1, 347 BUS_SPACE_BARRIER_WRITE); 348 } 349 350 static inline void 351 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 352 { 353 uint32_t reg; 354 355 reg = regr(sc, CLOCK_CNTL); 356 reg |= PLL_WR_EN; 357 regw(sc, CLOCK_CNTL, reg); 358 reg &= ~(PLL_ADDR | PLL_DATA); 359 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 360 reg |= data << PLL_DATA_SHIFT; 361 reg |= CLOCK_STROBE; 362 regw(sc, CLOCK_CNTL, reg); 363 reg &= ~PLL_WR_EN; 364 regw(sc, CLOCK_CNTL, reg); 365 } 366 367 static inline uint8_t 368 regrb_pll(struct mach64_softc *sc, uint32_t index) 369 { 370 371 regwb(sc, CLOCK_CNTL + 1, index << 2); 372 return regrb(sc, CLOCK_CNTL + 2); 373 } 374 375 static inline void 376 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 377 { 378 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 379 continue; 380 } 381 382 static inline void 383 wait_for_idle(struct mach64_softc *sc) 384 { 385 wait_for_fifo(sc, 16); 386 while ((regr(sc, GUI_STAT) & 1) != 0) 387 continue; 388 } 389 390 static int 391 mach64_match(device_t parent, cfdata_t match, void *aux) 392 { 393 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 394 int i; 395 396 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 397 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 398 return 0; 399 400 for (i = 0; i < __arraycount(mach64_info); i++) 401 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 402 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 403 mach64_chip_rev = PCI_REVISION(pa->pa_class); 404 return 100; 405 } 406 407 return 0; 408 } 409 410 static void 411 mach64_attach(device_t parent, device_t self, void *aux) 412 { 413 struct mach64_softc *sc = device_private(self); 414 struct pci_attach_args *pa = aux; 415 struct rasops_info *ri; 416 prop_data_t edid_data; 417 const struct videomode *mode = NULL; 418 int bar, id, expected_id; 419 int is_gx; 420 const char **memtype_names; 421 struct wsemuldisplaydev_attach_args aa; 422 long defattr; 423 int width = 1024, height = 768; 424 pcireg_t screg; 425 uint32_t reg; 426 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 427 int use_mmio = FALSE; 428 429 sc->sc_dev = self; 430 sc->sc_pc = pa->pa_pc; 431 sc->sc_pcitag = pa->pa_tag; 432 sc->sc_dacw = -1; 433 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 434 sc->sc_nbus = pa->pa_bus; 435 sc->sc_ndev = pa->pa_device; 436 sc->sc_nfunc = pa->pa_function; 437 sc->sc_locked = 0; 438 sc->sc_iot = pa->pa_iot; 439 sc->sc_accessops.ioctl = mach64_ioctl; 440 sc->sc_accessops.mmap = mach64_mmap; 441 sc->sc_setmode = 0; 442 443 pci_aprint_devinfo(pa, "Graphics processor"); 444 #ifdef MACHFB_DEBUG 445 printf(prop_dictionary_externalize(device_properties(self))); 446 #endif 447 448 /* enable memory access */ 449 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 450 if ((screg & enables) != enables) { 451 screg |= enables; 452 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 453 PCI_COMMAND_STATUS_REG, screg); 454 } 455 for (bar = 0; bar < NBARS; bar++) { 456 reg = PCI_MAPREG_START + (bar * 4); 457 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 458 sc->sc_pcitag, reg); 459 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 460 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 461 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 462 } 463 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 464 (uint32_t)sc->sc_apersize); 465 466 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 467 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 468 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 469 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 470 sc->sc_memt = pa->pa_memt; 471 472 /* use MMIO register aperture if available */ 473 if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) { 474 if (pci_mapreg_map(pa, MACH64_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 475 0, &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase, 476 &sc->sc_regsize) == 0) { 477 478 /* 479 * the MMIO aperture maps both 1KB register blocks, but 480 * all register offsets are relative to the 2nd one so 481 * for now fix this up in MACH64_REG_OFF and the access 482 * functions 483 */ 484 aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n"); 485 use_mmio = TRUE; 486 } 487 } 488 if (!use_mmio) { 489 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, 490 sc->sc_apersize, BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 491 panic("%s: failed to map aperture", 492 device_xname(sc->sc_dev)); 493 } 494 495 sc->sc_regt = sc->sc_memt; 496 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 497 MACH64_REG_SIZE, &sc->sc_regh); 498 } 499 500 mach64_init(sc); 501 502 aprint_normal_dev(sc->sc_dev, 503 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 504 (u_int)(sc->sc_apersize / (1024 * 1024)), 505 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 506 (u_int)sc->sc_regbase); 507 508 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 509 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 510 #ifdef MACHFB_DEBUG 511 mach64_get_mode(sc, NULL); 512 #endif 513 514 prop_dictionary_get_uint32(device_properties(self), "width", &width); 515 prop_dictionary_get_uint32(device_properties(self), "height", &height); 516 517 default_mode.hdisplay = width; 518 default_mode.vdisplay = height; 519 520 memset(&sc->sc_ei, 0, sizeof(sc->sc_ei)); 521 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 522 != NULL) { 523 524 sc->sc_edid_size = uimin(1024, prop_data_size(edid_data)); 525 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 526 memcpy(sc->sc_edid_data, prop_data_value(edid_data), 527 sc->sc_edid_size); 528 529 edid_parse(sc->sc_edid_data, &sc->sc_ei); 530 531 #ifdef MACHFB_DEBUG 532 edid_print(&sc->sc_ei); 533 #endif 534 } 535 is_gx = 0; 536 switch(mach64_chip_id) { 537 case PCI_PRODUCT_ATI_MACH64_GX: 538 case PCI_PRODUCT_ATI_MACH64_CX: 539 is_gx = 1; 540 /* FALLTHROUGH */ 541 case PCI_PRODUCT_ATI_MACH64_CT: 542 sc->has_dsp = 0; 543 break; 544 case PCI_PRODUCT_ATI_MACH64_VT: 545 case PCI_PRODUCT_ATI_RAGE_II: 546 if((mach64_chip_rev & 0x07) == 0) { 547 sc->has_dsp = 0; 548 break; 549 } 550 /* FALLTHROUGH */ 551 default: 552 sc->has_dsp = 1; 553 } 554 555 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 556 557 sc->memsize = mach64_get_memsize(sc); 558 559 if(is_gx) 560 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 561 else 562 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 563 564 sc->ref_freq = mach64_ref_freq(); 565 566 reg = regr(sc, CLOCK_CNTL); 567 sc->sc_clock = reg & 3; 568 DPRINTF("using clock %d\n", sc->sc_clock); 569 570 DPRINTF("ref_freq: %d\n", sc->ref_freq); 571 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 572 DPRINTF("ref_div: %d\n", sc->ref_div); 573 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 574 DPRINTF("mclk_fb_div: %d\n", sc->mclk_fb_div); 575 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 576 (sc->ref_div * 2); 577 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 578 (sc->mem_freq * sc->ref_div); 579 sc->ramdac_freq = mach64_get_max_ramdac(sc); 580 { 581 sc->minref = sc->ramdac_freq / 510; 582 sc->m = sc->ref_freq / sc->minref; 583 DPRINTF("minref: %d m: %d\n", sc->minref, sc->m); 584 } 585 aprint_normal_dev(sc->sc_dev, 586 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 587 (u_long)sc->memsize, 588 memtype_names[sc->memtype], 589 sc->mem_freq / 1000, sc->mem_freq % 1000, 590 sc->ramdac_freq / 1000); 591 592 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 593 switch(mach64_chip_id) { 594 case PCI_PRODUCT_ATI_MACH64_GX: 595 expected_id = 0x00d7; 596 break; 597 case PCI_PRODUCT_ATI_MACH64_CX: 598 expected_id = 0x0057; 599 break; 600 default: 601 /* Most chip IDs match their PCI product ID. */ 602 expected_id = mach64_chip_id; 603 } 604 605 if (id != expected_id) { 606 aprint_error_dev(sc->sc_dev, 607 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 608 return; 609 } 610 611 sc->sc_console = mach64_is_console(sc); 612 sc->sc_gen_cntl = regr(sc, CRTC_GEN_CNTL); 613 aprint_debug("gen_cntl: %08x\n", sc->sc_gen_cntl); 614 sc->sc_gen_cntl &= CRTC_CSYNC_EN; 615 aprint_normal_dev(sc->sc_dev, "found composite sync %s\n", 616 sc->sc_gen_cntl ? "enabled" : "disabled"); 617 618 #define MODE_IS_VALID(m) ((sc->ramdac_freq >= (m)->dot_clock) && \ 619 ((m)->hdisplay <= 1280)) 620 621 /* no mode setting support on ancient chips with external clocks */ 622 sc->sc_setmode = 0; 623 if (!is_gx) { 624 /* 625 * Now pick a mode. 626 */ 627 if ((sc->sc_ei.edid_preferred_mode != NULL)) { 628 struct videomode *m = sc->sc_ei.edid_preferred_mode; 629 if (MODE_IS_VALID(m)) { 630 memcpy(&default_mode, m, 631 sizeof(struct videomode)); 632 sc->sc_setmode = 1; 633 } else { 634 aprint_normal_dev(sc->sc_dev, 635 "unable to use EDID preferred mode " 636 "(%d x %d)\n", m->hdisplay, m->vdisplay); 637 } 638 } 639 /* 640 * if we can't use the preferred mode go look for the 641 * best one we can support 642 */ 643 if (sc->sc_setmode == 0) { 644 struct videomode *m = sc->sc_ei.edid_modes; 645 646 mode = NULL; 647 sort_modes(sc->sc_ei.edid_modes, 648 &sc->sc_ei.edid_preferred_mode, 649 sc->sc_ei.edid_nmodes); 650 for (int n = 0; n < sc->sc_ei.edid_nmodes; n++) 651 if (MODE_IS_VALID(&m[n])) { 652 mode = &m[n]; 653 break; 654 } 655 if (mode != NULL) { 656 memcpy(&default_mode, mode, 657 sizeof(struct videomode)); 658 sc->sc_setmode = 1; 659 } 660 } 661 } 662 663 /* make sure my_mode points at something sensible if the above fails */ 664 if (default_mode.dot_clock == 0) { 665 sc->sc_setmode = 0; 666 mode = pick_mode_by_ref(width, height, 60); 667 if (mode != NULL) { 668 memcpy(&default_mode, mode, sizeof(default_mode)); 669 } else if ((width > 0) && (height > 0)) { 670 default_mode.hdisplay = width; 671 default_mode.vdisplay = height; 672 } else { 673 /* 674 * if we end up here we're probably dealing with 675 * uninitialized hardware - try to set 1024x768@60 and 676 * hope for the best... 677 */ 678 mode = pick_mode_by_ref(1024, 768, 60); 679 if (mode == NULL) return; 680 memcpy(&default_mode, mode, sizeof(default_mode)); 681 if (!is_gx) sc->sc_setmode = 1; 682 } 683 } 684 685 sc->sc_my_mode = &default_mode; 686 687 if ((width == sc->sc_my_mode->hdisplay) && 688 (height == sc->sc_my_mode->vdisplay)) 689 sc->sc_setmode = 0; 690 691 sc->bits_per_pixel = 8; 692 sc->virt_x = sc->sc_my_mode->hdisplay; 693 sc->virt_y = sc->sc_my_mode->vdisplay; 694 sc->stride = (sc->virt_x + 7) & ~7; /* hw needs multiples of 8 */ 695 sc->max_x = sc->virt_x - 1; 696 sc->max_y = (sc->memsize * 1024) / 697 (sc->stride * (sc->bits_per_pixel / 8)) - 1; 698 699 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 700 701 mach64_init_engine(sc); 702 703 if (sc->sc_setmode) 704 mach64_modeswitch(sc, sc->sc_my_mode); 705 706 aprint_normal_dev(sc->sc_dev, 707 "initial resolution %dx%d at %d bpp\n", 708 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 709 sc->bits_per_pixel); 710 711 wsfont_init(); 712 713 #ifdef GLYPHCACHE_DEBUG 714 /* shrink the screen so we can see part of the glyph cache */ 715 sc->sc_my_mode->vdisplay -= 200; 716 #endif 717 718 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 719 sc->vd.init_screen = mach64_init_screen; 720 sc->vd.show_screen_cookie = &sc->sc_gc; 721 sc->vd.show_screen_cb = glyphcache_adapt; 722 723 sc->sc_gc.gc_bitblt = mach64_bitblt; 724 sc->sc_gc.gc_blitcookie = sc; 725 sc->sc_gc.gc_rop = MIX_SRC; 726 727 ri = &mach64_console_screen.scr_ri; 728 if (sc->sc_console) { 729 730 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 731 &defattr); 732 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 733 734 mach64_defaultscreen.textops = &ri->ri_ops; 735 mach64_defaultscreen.capabilities = ri->ri_caps; 736 mach64_defaultscreen.nrows = ri->ri_rows; 737 mach64_defaultscreen.ncols = ri->ri_cols; 738 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 739 ((sc->memsize * 1024) / sc->stride) - 740 sc->sc_my_mode->vdisplay - 5, 741 sc->stride, 742 ri->ri_font->fontwidth, 743 ri->ri_font->fontheight, 744 defattr); 745 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 746 } else { 747 /* 748 * since we're not the console we can postpone the rest 749 * until someone actually allocates a screen for us 750 */ 751 if (mach64_console_screen.scr_ri.ri_rows == 0) { 752 /* do some minimal setup to avoid weirdnesses later */ 753 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 754 &defattr); 755 } else 756 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 757 758 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 759 ((sc->memsize * 1024) / sc->stride) - 760 sc->sc_my_mode->vdisplay - 5, 761 sc->stride, 762 ri->ri_font->fontwidth, 763 ri->ri_font->fontheight, 764 defattr); 765 } 766 767 sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG]; 768 mach64_clearscreen(sc); 769 mach64_init_lut(sc); 770 771 if (sc->sc_console) 772 vcons_replay_msgbuf(&mach64_console_screen); 773 774 machfb_blank(sc, 0); /* unblank the screen */ 775 776 aa.console = sc->sc_console; 777 aa.scrdata = &mach64_screenlist; 778 aa.accessops = &sc->sc_accessops; 779 aa.accesscookie = &sc->vd; 780 781 config_found(self, &aa, wsemuldisplaydevprint); 782 #if 0 783 /* XXX 784 * turns out some firmware doesn't turn these back on when needed 785 * so we need to turn them off only when mapping vram in 786 * WSDISPLAYIO_MODE_DUMB would overlap ( unlikely but far from 787 * impossible ) 788 */ 789 if (use_mmio) { 790 /* 791 * Now that we took over, turn off the aperture registers if we 792 * don't use them. Can't do this earlier since on some hardware 793 * we use firmware calls as early console output which may in 794 * turn try to access these registers. 795 */ 796 reg = regr(sc, BUS_CNTL); 797 aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg); 798 reg |= BUS_APER_REG_DIS; 799 regw(sc, BUS_CNTL, reg); 800 } 801 #endif 802 config_found_ia(self, "drm", aux, machfb_drm_print); 803 } 804 805 static int 806 machfb_drm_print(void *aux, const char *pnp) 807 { 808 if (pnp) 809 aprint_normal("direct rendering for %s", pnp); 810 return (UNSUPP); 811 } 812 813 static void 814 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 815 long *defattr) 816 { 817 struct mach64_softc *sc = cookie; 818 struct rasops_info *ri = &scr->scr_ri; 819 820 ri->ri_depth = sc->bits_per_pixel; 821 ri->ri_width = sc->sc_my_mode->hdisplay; 822 ri->ri_height = sc->sc_my_mode->vdisplay; 823 ri->ri_stride = sc->stride; 824 ri->ri_flg = RI_CENTER | RI_FULLCLEAR; 825 if (ri->ri_depth == 8) 826 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA | 827 RI_PREFER_ALPHA; 828 829 #ifdef VCONS_DRAW_INTR 830 scr->scr_flags |= VCONS_DONT_READ; 831 #endif 832 scr->scr_flags |= VCONS_LOADFONT; 833 834 rasops_init(ri, 0, 0); 835 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE | 836 WSSCREEN_RESIZE; 837 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 838 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 839 840 /* enable acceleration */ 841 ri->ri_hw = scr; 842 ri->ri_ops.copyrows = mach64_copyrows; 843 ri->ri_ops.copycols = mach64_copycols; 844 ri->ri_ops.eraserows = mach64_eraserows; 845 ri->ri_ops.erasecols = mach64_erasecols; 846 ri->ri_ops.cursor = mach64_cursor; 847 if (FONT_IS_ALPHA(ri->ri_font)) { 848 ri->ri_ops.putchar = mach64_putchar_aa8; 849 } else 850 ri->ri_ops.putchar = mach64_putchar_mono; 851 } 852 853 static void 854 mach64_init(struct mach64_softc *sc) 855 { 856 sc->sc_blanked = 0; 857 } 858 859 static int 860 mach64_get_memsize(struct mach64_softc *sc) 861 { 862 int tmp, memsize; 863 int mem_tab[] = { 864 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 865 }; 866 tmp = regr(sc, MEM_CNTL); 867 #ifdef DIAGNOSTIC 868 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 869 #endif 870 if (sc->has_dsp) { 871 tmp &= 0x0000000f; 872 if (tmp < 8) 873 memsize = (tmp + 1) * 512; 874 else if (tmp < 12) 875 memsize = (tmp - 3) * 1024; 876 else 877 memsize = (tmp - 7) * 2048; 878 } else { 879 memsize = mem_tab[tmp & 0x07]; 880 } 881 882 return memsize; 883 } 884 885 static int 886 mach64_get_max_ramdac(struct mach64_softc *sc) 887 { 888 int i; 889 890 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 891 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 892 (mach64_chip_rev & 0x07)) 893 return 170000; 894 895 for (i = 0; i < __arraycount(mach64_info); i++) 896 if (mach64_chip_id == mach64_info[i].chip_id) 897 return mach64_info[i].ramdac_freq; 898 899 if (sc->bits_per_pixel == 8) 900 return 135000; 901 else 902 return 80000; 903 } 904 905 static int 906 mach64_ref_freq(void) 907 { 908 /* 909 * There doesn't seem to be any way to calculate the reference 910 * frequency from known values 911 */ 912 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 913 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 914 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI))) 915 return 29498; 916 else 917 return 14318; 918 } 919 920 #ifdef MACHFB_DEBUG 921 static void 922 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 923 { 924 int htotal, hdisplay, hsync_start, hsync_end; 925 int vtotal, vdisplay, vsync_start, vsync_end; 926 int gen_ctl, clk_ctl, clock; 927 int ref_freq, ref_div, mclk_fb_div, vclk_post_div, vclk_fb_div; 928 int nhsync, nvsync; 929 int post_div, dot_clock, vrefresh, vrefresh2; 930 931 hdisplay = regr(sc, CRTC_H_TOTAL_DISP); 932 hsync_end = regr(sc, CRTC_H_SYNC_STRT_WID); 933 vdisplay = regr(sc, CRTC_V_TOTAL_DISP); 934 vsync_end = regr(sc, CRTC_V_SYNC_STRT_WID); 935 gen_ctl = regr(sc, CRTC_GEN_CNTL); 936 clk_ctl = regr(sc, CLOCK_CNTL); 937 clock = clk_ctl & 3; 938 ref_div = regrb_pll(sc, PLL_REF_DIV); 939 mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 940 vclk_post_div = regrb_pll(sc, VCLK_POST_DIV); 941 vclk_fb_div = regrb_pll(sc, VCLK0_FB_DIV + clock); 942 ref_freq = mach64_ref_freq(); 943 944 aprint_normal_dev(sc->sc_dev, "CRTC registers:\n"); 945 aprint_normal("\th total: 0x%08x h sync: 0x%08x\n", 946 hdisplay, hsync_end); 947 aprint_normal("\tv total: 0x%08x v sync: 0x%08x\n", 948 vdisplay, vsync_end); 949 aprint_normal("\t g cntl: 0x%08x c cntl: 0x%08x\n", 950 gen_ctl, clk_ctl); 951 aprint_normal("\t rfreq %d rdiv: %d\n", ref_freq, ref_div); 952 aprint_normal_dev(sc->sc_dev, "PLL registers:\n"); 953 aprint_normal("\t m div: 0x%02x p div: 0x%02x v%d div: 0x%02x\n", 954 mclk_fb_div, vclk_post_div, clock, vclk_fb_div); 955 956 htotal = ((hdisplay & 0x01ff) + 1) << 3; 957 hdisplay = (((hdisplay & 0x1ff0000) >> 16) + 1) << 3; 958 if (hsync_end & CRTC_HSYNC_NEG) 959 nhsync = 1; 960 else 961 nhsync = 0; 962 hsync_start = (((hsync_end & 0xff) + 1) << 3) + 963 ((hsync_end & 0x700) >> 8); 964 hsync_end = (((hsync_end & 0x1f0000) >> 16) << 3) + hsync_start; 965 966 vtotal = (vdisplay & 0x07ff) + 1; 967 vdisplay = ((vdisplay & 0x7ff0000) >> 16) + 1; 968 if (vsync_end & CRTC_VSYNC_NEG) 969 nvsync = 1; 970 else 971 nvsync = 0; 972 vsync_start = (vsync_end & 0x07ff) + 1; 973 vsync_end = ((vsync_end & 0x1f0000) >> 16) + vsync_start; 974 975 switch ((vclk_post_div >> (clock * 2)) & 3) { 976 case 3: 977 post_div = 8; 978 break; 979 case 2: 980 post_div = 4; 981 break; 982 case 1: 983 post_div = 2; 984 break; 985 default: 986 post_div = 1; 987 break; 988 } 989 dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div); 990 vrefresh = (dot_clock * 1000) / (htotal * vtotal); 991 vrefresh2 = ((dot_clock * 1000) - (vrefresh * htotal * vtotal)) * 100 / 992 (htotal * vtotal); 993 994 aprint_normal_dev(sc->sc_dev, "Video mode:\n"); 995 aprint_normal("\t%d" "x%d @ %d.%02dHz " 996 "(%d %d %d %d %d %d %d %cH %cV)\n", 997 hdisplay, vdisplay, vrefresh, vrefresh2, dot_clock, 998 hsync_start, hsync_end, htotal, vsync_start, vsync_end, vtotal, 999 nhsync == 1 ? '-' : '+', nvsync == 1 ? '-' : '+'); 1000 1001 if (mode != NULL) { 1002 mode->dot_clock = dot_clock; 1003 mode->htotal = htotal; 1004 mode->hdisplay = hdisplay; 1005 mode->hsync_start = hsync_start; 1006 mode->hsync_end = hsync_end; 1007 mode->vtotal = vtotal; 1008 mode->vdisplay = vdisplay; 1009 mode->vsync_start = vsync_start; 1010 mode->vsync_end = vsync_end; 1011 mode->flags = 0; 1012 if (nhsync) 1013 mode->flags |= VID_NHSYNC; 1014 if (nvsync) 1015 mode->flags |= VID_NVSYNC; 1016 } 1017 } 1018 #endif 1019 1020 static int 1021 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 1022 struct videomode *mode) 1023 { 1024 1025 if (mode->dot_clock > sc->ramdac_freq) 1026 /* Clock too high. */ 1027 return 1; 1028 1029 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 1030 ((mode->htotal >> 3) - 1); 1031 crtc->h_sync_strt_wid = 1032 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 1033 ((mode->hsync_start >> 3) - 1) | ((mode->hsync_start & 7) << 8); 1034 1035 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 1036 (mode->vtotal - 1); 1037 crtc->v_sync_strt_wid = 1038 ((mode->vsync_end - mode->vsync_start) << 16) | 1039 (mode->vsync_start - 1); 1040 1041 if (mode->flags & VID_NVSYNC) 1042 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 1043 1044 switch (sc->bits_per_pixel) { 1045 case 8: 1046 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 1047 break; 1048 case 16: 1049 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 1050 break; 1051 case 32: 1052 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 1053 break; 1054 } 1055 1056 crtc->gen_cntl = 0; 1057 if (mode->flags & VID_INTERLACE) 1058 crtc->gen_cntl |= CRTC_INTERLACE_EN; 1059 1060 if (mode->flags & VID_CSYNC) 1061 crtc->gen_cntl |= CRTC_CSYNC_EN; 1062 1063 crtc->dot_clock = mode->dot_clock; 1064 1065 return 0; 1066 } 1067 1068 static void 1069 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1070 { 1071 1072 mach64_set_pll(sc, crtc->dot_clock); 1073 1074 if (sc->has_dsp) 1075 mach64_set_dsp(sc); 1076 1077 DPRINTF("\th total: 0x%08x h sync: 0x%08x\n", 1078 crtc->h_total_disp, crtc->h_sync_strt_wid); 1079 DPRINTF("\tv total: 0x%08x v sync: 0x%08x\n", 1080 crtc->v_total_disp, crtc->v_sync_strt_wid); 1081 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1082 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1083 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1084 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1085 1086 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1087 1088 regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22); 1089 1090 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1091 sc->sc_gen_cntl | CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1092 } 1093 1094 static int 1095 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1096 { 1097 struct mach64_crtcregs crtc; 1098 1099 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1100 1101 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1102 return 1; 1103 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1104 if (crtc.dot_clock == 0) { 1105 aprint_error("%s: preposterous dot clock (%d)\n", 1106 device_xname(sc->sc_dev), crtc.dot_clock); 1107 return 1; 1108 } 1109 mach64_set_crtcregs(sc, &crtc); 1110 return 0; 1111 } 1112 1113 static void 1114 mach64_reset_engine(struct mach64_softc *sc) 1115 { 1116 1117 /* Reset engine.*/ 1118 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1119 1120 /* Enable engine. */ 1121 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1122 1123 /* Ensure engine is not locked up by clearing any FIFO or 1124 host errors. */ 1125 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1126 BUS_FIFO_ERR_ACK); 1127 } 1128 1129 static void 1130 mach64_init_engine(struct mach64_softc *sc) 1131 { 1132 uint32_t pitch_value; 1133 1134 pitch_value = sc->stride; 1135 1136 if (sc->bits_per_pixel == 24) 1137 pitch_value *= 3; 1138 1139 mach64_reset_engine(sc); 1140 1141 wait_for_fifo(sc, 14); 1142 1143 regw(sc, CONTEXT_MASK, 0xffffffff); 1144 1145 regw(sc, DST_OFF_PITCH, (pitch_value >> 3) << 22); 1146 1147 /* make sure the visible area starts where we're going to draw */ 1148 regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22); 1149 1150 regw(sc, DST_Y_X, 0); 1151 regw(sc, DST_HEIGHT, 0); 1152 regw(sc, DST_BRES_ERR, 0); 1153 regw(sc, DST_BRES_INC, 0); 1154 regw(sc, DST_BRES_DEC, 0); 1155 1156 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1157 DST_Y_TOP_TO_BOTTOM); 1158 1159 regw(sc, SRC_OFF_PITCH, (pitch_value >> 3) << 22); 1160 1161 regw(sc, SRC_Y_X, 0); 1162 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1163 regw(sc, SRC_Y_X_START, 0); 1164 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1165 1166 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1167 1168 wait_for_fifo(sc, 13); 1169 regw(sc, HOST_CNTL, 0); 1170 1171 regw(sc, PAT_REG0, 0); 1172 regw(sc, PAT_REG1, 0); 1173 regw(sc, PAT_CNTL, 0); 1174 1175 regw(sc, SC_LEFT, 0); 1176 regw(sc, SC_TOP, 0); 1177 regw(sc, SC_BOTTOM, 0x3fff); 1178 regw(sc, SC_RIGHT, pitch_value - 1); 1179 1180 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1181 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1182 regw(sc, DP_WRITE_MASK, 0xffffffff); 1183 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1184 1185 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1186 1187 wait_for_fifo(sc, 3); 1188 regw(sc, CLR_CMP_CLR, 0); 1189 regw(sc, CLR_CMP_MASK, 0xffffffff); 1190 regw(sc, CLR_CMP_CNTL, 0); 1191 1192 wait_for_fifo(sc, 3); 1193 switch (sc->bits_per_pixel) { 1194 case 8: 1195 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1196 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1197 /* We want 8 bit per channel */ 1198 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1199 break; 1200 case 32: 1201 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1202 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1203 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1204 break; 1205 } 1206 regw(sc, DP_WRITE_MASK, 0xff); 1207 1208 wait_for_fifo(sc, 5); 1209 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1210 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1211 1212 wait_for_idle(sc); 1213 } 1214 1215 #if 0 1216 static void 1217 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1218 { 1219 int offset; 1220 1221 offset = ((x + y * sc->stride) * (sc->bits_per_pixel >> 3)) >> 3; 1222 1223 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1224 offset); 1225 } 1226 #endif 1227 1228 static void 1229 mach64_set_dsp(struct mach64_softc *sc) 1230 { 1231 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1232 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1233 uint32_t xclks_per_qw, xclks_per_qw_m, y; 1234 uint32_t fifo_off, fifo_on; 1235 1236 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1237 1238 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1239 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1240 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1241 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1242 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1243 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1244 dsp_loop_latency = 0; 1245 fifo_depth = 24; 1246 } else { 1247 dsp_loop_latency = 2; 1248 fifo_depth = 32; 1249 } 1250 1251 dsp_precision = 0; 1252 1253 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1254 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1255 1256 xclks_per_qw_m = (sc->mem_freq * 64 << 4) / 1257 (sc->vclk_freq * sc->bits_per_pixel); 1258 1259 DPRINTF("xclks_per_qw %d %d\n", xclks_per_qw >> 7, xclks_per_qw_m); 1260 DPRINTF("mem %dkHz v %dkHz\n", sc->mem_freq, sc->vclk_freq); 1261 1262 y = (xclks_per_qw * fifo_depth) >> 11; 1263 1264 while (y) { 1265 y >>= 1; 1266 dsp_precision++; 1267 } 1268 dsp_precision -= 5; 1269 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1270 1271 switch (sc->memtype) { 1272 case DRAM: 1273 case EDO_DRAM: 1274 case PSEUDO_EDO: 1275 if (sc->memsize > 1024) { 1276 page_size = 9; 1277 dsp_loop_latency += 6; 1278 } else { 1279 page_size = 10; 1280 if (sc->memtype == DRAM) 1281 dsp_loop_latency += 8; 1282 else 1283 dsp_loop_latency += 7; 1284 } 1285 break; 1286 case SDRAM: 1287 if (sc->memsize > 1024) { 1288 page_size = 8; 1289 dsp_loop_latency += 8; 1290 } else { 1291 page_size = 10; 1292 dsp_loop_latency += 9; 1293 } 1294 break; 1295 case SGRAM: 1296 page_size = 8; 1297 dsp_loop_latency = 8; 1298 break; 1299 default: 1300 page_size = 10; 1301 dsp_loop_latency += 9; 1302 break; 1303 } 1304 1305 if (xclks_per_qw >= (page_size << 11)) 1306 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1307 else 1308 fifo_on = (3 * page_size + 2) << 6; 1309 1310 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1311 dsp_on = fifo_on >> dsp_precision; 1312 dsp_off = fifo_off >> dsp_precision; 1313 1314 DPRINTF("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1315 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1316 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1317 "mclk_post_div = %d, vclk_post_div = %d\n", 1318 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1319 sc->mclk_fb_div, sc->vclk_fb_div, 1320 sc->mclk_post_div, sc->vclk_post_div); 1321 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1322 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1323 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1324 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1325 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1326 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1327 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1328 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1329 } 1330 1331 static void 1332 mach64_set_pll(struct mach64_softc *sc, int clock) 1333 { 1334 uint32_t q, clockreg; 1335 int clockshift = sc->sc_clock << 1; 1336 uint8_t reg, vclk_ctl; 1337 1338 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1339 #ifdef MACHFB_DEBUG 1340 printf("q = %d\n", q); 1341 #endif 1342 if (q > 25500) { 1343 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1344 q = 25500; 1345 sc->vclk_post_div = 1; 1346 sc->log2_vclk_post_div = 0; 1347 } else if (q > 12750) { 1348 sc->vclk_post_div = 1; 1349 sc->log2_vclk_post_div = 0; 1350 } else if (q > 6350) { 1351 sc->vclk_post_div = 2; 1352 sc->log2_vclk_post_div = 1; 1353 } else if (q > 3150) { 1354 sc->vclk_post_div = 4; 1355 sc->log2_vclk_post_div = 2; 1356 } else if (q >= 1600) { 1357 sc->vclk_post_div = 8; 1358 sc->log2_vclk_post_div = 3; 1359 } else { 1360 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1361 sc->vclk_post_div = 8; 1362 sc->log2_vclk_post_div = 3; 1363 } 1364 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1365 DPRINTF("post_div: %d log2_post_div: %d mclk_div: %d\n", 1366 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1367 1368 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1369 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1370 vclk_ctl |= PLL_VCLK_RESET; 1371 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1372 1373 DPRINTF("target: %d output: %d\n", clock, 1374 (2 * sc->ref_freq * sc->vclk_fb_div) / 1375 (sc->ref_div * sc->vclk_post_div)); 1376 1377 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1378 reg = regrb_pll(sc, VCLK_POST_DIV); 1379 reg &= ~(3 << clockshift); 1380 reg |= (sc->log2_vclk_post_div << clockshift); 1381 regwb_pll(sc, VCLK_POST_DIV, reg); 1382 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1383 1384 vclk_ctl &= ~PLL_VCLK_RESET; 1385 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1386 1387 clockreg = regr(sc, CLOCK_CNTL); 1388 clockreg &= ~CLOCK_SEL; 1389 clockreg |= sc->sc_clock | CLOCK_STROBE; 1390 regw(sc, CLOCK_CNTL, clockreg); 1391 sc->vclk_freq = clock; 1392 } 1393 1394 static void 1395 mach64_init_lut(struct mach64_softc *sc) 1396 { 1397 uint8_t cmap[768]; 1398 int i, idx; 1399 1400 rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap)); 1401 idx = 0; 1402 for (i = 0; i < 256; i++) { 1403 mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1], 1404 cmap[idx + 2]); 1405 idx += 3; 1406 } 1407 } 1408 1409 static int 1410 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1411 uint8_t b) 1412 { 1413 sc->sc_cmap_red[index] = r; 1414 sc->sc_cmap_green[index] = g; 1415 sc->sc_cmap_blue[index] = b; 1416 /* 1417 * writing the dac index takes a while, in theory we can poll some 1418 * register to see when it's ready - but we better avoid writing it 1419 * unnecessarily 1420 */ 1421 if (index != sc->sc_dacw) { 1422 regwb(sc, DAC_MASK, 0xff); 1423 regwb(sc, DAC_WINDEX, index); 1424 } 1425 sc->sc_dacw = index + 1; 1426 regwb(sc, DAC_DATA, r); 1427 regwb(sc, DAC_DATA, g); 1428 regwb(sc, DAC_DATA, b); 1429 return 0; 1430 } 1431 1432 static int 1433 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1434 { 1435 uint index = cm->index; 1436 uint count = cm->count; 1437 int i, error; 1438 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1439 uint8_t *r, *g, *b; 1440 1441 if (cm->index >= 256 || cm->count > 256 || 1442 (cm->index + cm->count) > 256) 1443 return EINVAL; 1444 error = copyin(cm->red, &rbuf[index], count); 1445 if (error) 1446 return error; 1447 error = copyin(cm->green, &gbuf[index], count); 1448 if (error) 1449 return error; 1450 error = copyin(cm->blue, &bbuf[index], count); 1451 if (error) 1452 return error; 1453 1454 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1455 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1456 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1457 1458 r = &sc->sc_cmap_red[index]; 1459 g = &sc->sc_cmap_green[index]; 1460 b = &sc->sc_cmap_blue[index]; 1461 1462 for (i = 0; i < count; i++) { 1463 mach64_putpalreg(sc, index, *r, *g, *b); 1464 index++; 1465 r++, g++, b++; 1466 } 1467 return 0; 1468 } 1469 1470 static int 1471 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1472 { 1473 u_int index = cm->index; 1474 u_int count = cm->count; 1475 int error; 1476 1477 if (index >= 255 || count > 256 || index + count > 256) 1478 return EINVAL; 1479 1480 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1481 if (error) 1482 return error; 1483 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1484 if (error) 1485 return error; 1486 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1487 if (error) 1488 return error; 1489 1490 return 0; 1491 } 1492 1493 static int 1494 mach64_is_console(struct mach64_softc *sc) 1495 { 1496 bool console = 0; 1497 1498 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1499 "is_console", &console); 1500 return console; 1501 } 1502 1503 /* 1504 * wsdisplay_emulops 1505 */ 1506 1507 static void 1508 mach64_cursor(void *cookie, int on, int row, int col) 1509 { 1510 struct rasops_info *ri = cookie; 1511 struct vcons_screen *scr = ri->ri_hw; 1512 struct mach64_softc *sc = scr->scr_cookie; 1513 int x, y, wi, he; 1514 1515 wi = ri->ri_font->fontwidth; 1516 he = ri->ri_font->fontheight; 1517 1518 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1519 x = ri->ri_ccol * wi + ri->ri_xorigin; 1520 y = ri->ri_crow * he + ri->ri_yorigin; 1521 if (ri->ri_flg & RI_CURSOR) { 1522 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1523 ri->ri_flg &= ~RI_CURSOR; 1524 } 1525 ri->ri_crow = row; 1526 ri->ri_ccol = col; 1527 if (on) { 1528 x = ri->ri_ccol * wi + ri->ri_xorigin; 1529 y = ri->ri_crow * he + ri->ri_yorigin; 1530 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1531 ri->ri_flg |= RI_CURSOR; 1532 } 1533 } else { 1534 scr->scr_ri.ri_crow = row; 1535 scr->scr_ri.ri_ccol = col; 1536 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1537 } 1538 } 1539 1540 #if 0 1541 static int 1542 mach64_mapchar(void *cookie, int uni, u_int *index) 1543 { 1544 return 0; 1545 } 1546 #endif 1547 1548 static void 1549 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1550 { 1551 struct rasops_info *ri = cookie; 1552 struct wsdisplay_font *font = PICK_FONT(ri, c); 1553 struct vcons_screen *scr = ri->ri_hw; 1554 struct mach64_softc *sc = scr->scr_cookie; 1555 1556 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1557 int fg, bg, uc; 1558 uint8_t *data; 1559 int x, y, wi, he; 1560 wi = font->fontwidth; 1561 he = font->fontheight; 1562 1563 if (!CHAR_IN_FONT(c, font)) 1564 return; 1565 bg = ri->ri_devcmap[(attr >> 16) & 0x0f]; 1566 fg = ri->ri_devcmap[(attr >> 24) & 0x0f]; 1567 x = ri->ri_xorigin + col * wi; 1568 y = ri->ri_yorigin + row * he; 1569 if (c == 0x20) { 1570 mach64_rectfill(sc, x, y, wi, he, bg); 1571 } else { 1572 uc = c - font->firstchar; 1573 data = (uint8_t *)font->data + uc * 1574 ri->ri_fontscale; 1575 1576 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1577 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1578 } 1579 if (attr & 1) 1580 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1581 } 1582 } 1583 1584 static void 1585 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 1586 { 1587 struct rasops_info *ri = cookie; 1588 struct wsdisplay_font *font = PICK_FONT(ri, c); 1589 struct vcons_screen *scr = ri->ri_hw; 1590 struct mach64_softc *sc = scr->scr_cookie; 1591 uint32_t bg, fg, latch = 0, bg8, fg8, pixel; 1592 int i, x, y, wi, he, r, g, b, aval; 1593 int r1, g1, b1, r0, g0, b0, fgo, bgo; 1594 uint8_t *data8; 1595 int rv = 0, cnt = 0; 1596 1597 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1598 return; 1599 1600 if (!CHAR_IN_FONT(c, font)) 1601 return; 1602 1603 wi = font->fontwidth; 1604 he = font->fontheight; 1605 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1606 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1607 x = ri->ri_xorigin + col * wi; 1608 y = ri->ri_yorigin + row * he; 1609 1610 if (c == 0x20) { 1611 mach64_rectfill(sc, x, y, wi, he, bg); 1612 if (attr & 1) 1613 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1614 return; 1615 } 1616 1617 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1618 if (rv == GC_OK) 1619 return; 1620 1621 data8 = WSFONT_GLYPH(c, font); 1622 1623 wait_for_fifo(sc, 11); 1624 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1625 regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST); 1626 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1627 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1628 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1629 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1630 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1631 regw(sc, SRC_Y_X, 0); 1632 regw(sc, SRC_WIDTH1, wi); 1633 regw(sc, DST_Y_X, (x << 16) | y); 1634 regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he); 1635 1636 /* 1637 * we need the RGB colours here, so get offsets into rasops_cmap 1638 */ 1639 fgo = ((attr >> 24) & 0xf) * 3; 1640 bgo = ((attr >> 16) & 0xf) * 3; 1641 1642 r0 = rasops_cmap[bgo]; 1643 r1 = rasops_cmap[fgo]; 1644 g0 = rasops_cmap[bgo + 1]; 1645 g1 = rasops_cmap[fgo + 1]; 1646 b0 = rasops_cmap[bgo + 2]; 1647 b1 = rasops_cmap[fgo + 2]; 1648 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 1649 bg8 = R3G3B2(r0, g0, b0); 1650 fg8 = R3G3B2(r1, g1, b1); 1651 1652 wait_for_fifo(sc, 10); 1653 1654 for (i = 0; i < ri->ri_fontscale; i++) { 1655 aval = *data8; 1656 if (aval == 0) { 1657 pixel = bg8; 1658 } else if (aval == 255) { 1659 pixel = fg8; 1660 } else { 1661 r = aval * r1 + (255 - aval) * r0; 1662 g = aval * g1 + (255 - aval) * g0; 1663 b = aval * b1 + (255 - aval) * b0; 1664 pixel = ((r & 0xe000) >> 8) | 1665 ((g & 0xe000) >> 11) | 1666 ((b & 0xc000) >> 14); 1667 } 1668 latch = (latch << 8) | pixel; 1669 /* write in 32bit chunks */ 1670 if ((i & 3) == 3) { 1671 regws(sc, HOST_DATA0, latch); 1672 /* 1673 * not strictly necessary, old data should be shifted 1674 * out 1675 */ 1676 latch = 0; 1677 cnt++; 1678 if (cnt > 8) { 1679 wait_for_fifo(sc, 10); 1680 cnt = 0; 1681 } 1682 } 1683 data8++; 1684 } 1685 /* if we have pixels left in latch write them out */ 1686 if ((i & 3) != 0) { 1687 latch = latch << ((4 - (i & 3)) << 3); 1688 regws(sc, HOST_DATA0, latch); 1689 } 1690 1691 if (rv == GC_ADD) { 1692 glyphcache_add(&sc->sc_gc, c, x, y); 1693 } else if (attr & 1) { 1694 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1695 } 1696 1697 } 1698 1699 static void 1700 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1701 { 1702 struct rasops_info *ri = cookie; 1703 struct vcons_screen *scr = ri->ri_hw; 1704 struct mach64_softc *sc = scr->scr_cookie; 1705 int32_t xs, xd, y, width, height; 1706 1707 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1708 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1709 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1710 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1711 width = ri->ri_font->fontwidth * ncols; 1712 height = ri->ri_font->fontheight; 1713 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC); 1714 } 1715 } 1716 1717 static void 1718 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1719 { 1720 struct rasops_info *ri = cookie; 1721 struct vcons_screen *scr = ri->ri_hw; 1722 struct mach64_softc *sc = scr->scr_cookie; 1723 int32_t x, y, width, height, fg, bg, ul; 1724 1725 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1726 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1727 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1728 width = ri->ri_font->fontwidth * ncols; 1729 height = ri->ri_font->fontheight; 1730 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1731 1732 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1733 } 1734 } 1735 1736 static void 1737 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1738 { 1739 struct rasops_info *ri = cookie; 1740 struct vcons_screen *scr = ri->ri_hw; 1741 struct mach64_softc *sc = scr->scr_cookie; 1742 int32_t x, ys, yd, width, height; 1743 1744 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1745 x = ri->ri_xorigin; 1746 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1747 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1748 width = ri->ri_emuwidth; 1749 height = ri->ri_font->fontheight*nrows; 1750 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC); 1751 } 1752 } 1753 1754 static void 1755 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1756 { 1757 struct rasops_info *ri = cookie; 1758 struct vcons_screen *scr = ri->ri_hw; 1759 struct mach64_softc *sc = scr->scr_cookie; 1760 int32_t x, y, width, height, fg, bg, ul; 1761 1762 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1763 if ((row == 0) && (nrows == ri->ri_rows)) { 1764 /* clear full screen */ 1765 x = 0; 1766 y = 0; 1767 width = sc->virt_x; 1768 height = sc->virt_y; 1769 } else { 1770 x = ri->ri_xorigin; 1771 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1772 width = ri->ri_emuwidth; 1773 height = ri->ri_font->fontheight * nrows; 1774 } 1775 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1776 1777 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1778 } 1779 } 1780 1781 static void 1782 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width, 1783 int height, int rop) 1784 { 1785 struct mach64_softc *sc = cookie; 1786 uint32_t dest_ctl = 0; 1787 1788 #if 0 1789 wait_for_idle(sc); 1790 #else 1791 wait_for_fifo(sc, 10); 1792 #endif 1793 1794 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1795 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1796 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1797 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1798 if (yd < ys) { 1799 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1800 } else { 1801 ys += height - 1; 1802 yd += height - 1; 1803 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1804 } 1805 if (xd < xs) { 1806 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1807 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1808 } else { 1809 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1810 xs += width - 1; 1811 xd += width - 1; 1812 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1813 } 1814 regw(sc, DST_CNTL, dest_ctl); 1815 1816 regw(sc, SRC_Y_X, (xs << 16) | ys); 1817 regw(sc, SRC_WIDTH1, width); 1818 regw(sc, DST_Y_X, (xd << 16) | yd); 1819 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1820 } 1821 1822 static void 1823 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1824 int height, uint32_t fg, uint32_t bg) 1825 { 1826 wait_for_idle(sc); 1827 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1828 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1829 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1830 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1831 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1832 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1833 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1834 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1835 regw(sc, DP_BKGD_CLR, bg); 1836 regw(sc, DP_FRGD_CLR, fg); 1837 regw(sc, SRC_Y_X, 0); 1838 regw(sc, SRC_WIDTH1, width); 1839 regw(sc, DST_Y_X, (xd << 16) | yd); 1840 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1841 /* now feed the data into the chip */ 1842 } 1843 1844 static void 1845 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1846 { 1847 int i; 1848 uint32_t latch = 0, bork; 1849 int shift = 0; 1850 int reg = 0; 1851 1852 for (i = 0; i < count; i++) { 1853 bork = data[i]; 1854 latch |= (bork << shift); 1855 if (shift == 24) { 1856 regw(sc, HOST_DATA0 + reg, latch); 1857 latch = 0; 1858 shift = 0; 1859 reg = (reg + 4) & 0x3c; 1860 } else 1861 shift += 8; 1862 } 1863 if (shift != 0) /* 24 */ 1864 regw(sc, HOST_DATA0 + reg, latch); 1865 } 1866 1867 1868 static void 1869 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1870 int colour) 1871 { 1872 wait_for_fifo(sc, 11); 1873 regw(sc, DP_FRGD_CLR, colour); 1874 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1875 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1876 regw(sc, DP_MIX, MIX_SRC << 16); 1877 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1878 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1879 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1880 1881 regw(sc, SRC_Y_X, (x << 16) | y); 1882 regw(sc, SRC_WIDTH1, width); 1883 regw(sc, DST_Y_X, (x << 16) | y); 1884 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1885 } 1886 1887 static void 1888 mach64_clearscreen(struct mach64_softc *sc) 1889 { 1890 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1891 } 1892 1893 1894 #if 0 1895 static void 1896 mach64_showpal(struct mach64_softc *sc) 1897 { 1898 int i, x = 0; 1899 1900 for (i = 0; i < 16; i++) { 1901 mach64_rectfill(sc, x, 0, 64, 64, i); 1902 x += 64; 1903 } 1904 } 1905 #endif 1906 1907 /* 1908 * wsdisplay_accessops 1909 */ 1910 1911 static int 1912 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1913 struct lwp *l) 1914 { 1915 struct vcons_data *vd = v; 1916 struct mach64_softc *sc = vd->cookie; 1917 struct wsdisplay_fbinfo *wdf; 1918 struct vcons_screen *ms = vd->active; 1919 1920 switch (cmd) { 1921 case WSDISPLAYIO_GTYPE: 1922 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1923 return 0; 1924 1925 case WSDISPLAYIO_LINEBYTES: 1926 *(u_int *)data = sc->stride * sc->bits_per_pixel / 8; 1927 return 0; 1928 1929 case WSDISPLAYIO_GINFO: 1930 wdf = (void *)data; 1931 wdf->height = sc->virt_y; 1932 wdf->width = sc->virt_x; 1933 wdf->depth = sc->bits_per_pixel; 1934 wdf->cmsize = 256; 1935 return 0; 1936 1937 case WSDISPLAYIO_GETCMAP: 1938 return mach64_getcmap(sc, 1939 (struct wsdisplay_cmap *)data); 1940 1941 case WSDISPLAYIO_PUTCMAP: 1942 return mach64_putcmap(sc, 1943 (struct wsdisplay_cmap *)data); 1944 1945 /* PCI config read/write passthrough. */ 1946 case PCI_IOC_CFGREAD: 1947 case PCI_IOC_CFGWRITE: 1948 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1949 cmd, data, flag, l); 1950 1951 case WSDISPLAYIO_GET_BUSID: 1952 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1953 sc->sc_pcitag, data); 1954 1955 case WSDISPLAYIO_SMODE: { 1956 int new_mode = *(int*)data; 1957 if (new_mode != sc->sc_mode) { 1958 sc->sc_mode = new_mode; 1959 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1960 && (ms != NULL)) 1961 { 1962 /* restore initial video mode */ 1963 mach64_init(sc); 1964 mach64_init_engine(sc); 1965 mach64_init_lut(sc); 1966 if (sc->sc_setmode) 1967 mach64_modeswitch(sc, sc->sc_my_mode); 1968 mach64_clearscreen(sc); 1969 glyphcache_wipe(&sc->sc_gc); 1970 vcons_redraw_screen(ms); 1971 } 1972 } 1973 } 1974 return 0; 1975 case WSDISPLAYIO_GET_EDID: { 1976 struct wsdisplayio_edid_info *d = data; 1977 return wsdisplayio_get_edid(sc->sc_dev, d); 1978 } 1979 1980 case WSDISPLAYIO_GET_FBINFO: { 1981 struct wsdisplayio_fbinfo *fbi = data; 1982 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1983 } 1984 } 1985 return EPASSTHROUGH; 1986 } 1987 1988 static paddr_t 1989 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1990 { 1991 struct vcons_data *vd = v; 1992 struct mach64_softc *sc = vd->cookie; 1993 paddr_t pa; 1994 1995 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 1996 /* 1997 *'regular' framebuffer mmap()ing 1998 */ 1999 if (offset < (sc->memsize * 1024)) { 2000 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, 2001 offset, prot, BUS_SPACE_MAP_LINEAR); 2002 return pa; 2003 } 2004 } else if (sc->sc_mode == WSDISPLAYIO_MODE_MAPPED) { 2005 /* 2006 * restrict all other mappings to processes with superuser 2007 * privileges 2008 */ 2009 if (kauth_authorize_machdep(kauth_cred_get(), 2010 KAUTH_MACHDEP_UNMANAGEDMEM, 2011 NULL, NULL, NULL, NULL) != 0) { 2012 return -1; 2013 } 2014 if ((offset >= sc->sc_aperbase) && 2015 (offset < (sc->sc_aperbase + sc->sc_apersize))) { 2016 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2017 BUS_SPACE_MAP_LINEAR); 2018 return pa; 2019 } 2020 2021 if ((offset >= sc->sc_regbase) && 2022 (offset < (sc->sc_regbase + sc->sc_regsize))) { 2023 pa = bus_space_mmap(sc->sc_regt, offset, 0, prot, 2024 BUS_SPACE_MAP_LINEAR); 2025 return pa; 2026 } 2027 2028 if ((offset >= sc->sc_rom.vb_base) && 2029 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 2030 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2031 BUS_SPACE_MAP_LINEAR); 2032 return pa; 2033 } 2034 2035 #ifdef PCI_MAGIC_IO_RANGE 2036 if ((offset >= PCI_MAGIC_IO_RANGE) && 2037 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 2038 return bus_space_mmap(sc->sc_iot, 2039 offset - PCI_MAGIC_IO_RANGE, 0, prot, 0); 2040 } 2041 #endif 2042 } 2043 return -1; 2044 } 2045 2046 #if 0 2047 static int 2048 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 2049 { 2050 2051 return 0; 2052 } 2053 #endif 2054 2055 void 2056 machfb_blank(struct mach64_softc *sc, int blank) 2057 { 2058 uint32_t reg; 2059 2060 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 2061 2062 switch (blank) 2063 { 2064 case 0: 2065 reg = regr(sc, CRTC_GEN_CNTL); 2066 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 2067 sc->sc_blanked = 0; 2068 break; 2069 case 1: 2070 reg = regr(sc, CRTC_GEN_CNTL); 2071 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 2072 sc->sc_blanked = 1; 2073 break; 2074 default: 2075 break; 2076 } 2077 } 2078
Indexes created Thu Oct 02 14:10:14 GMT 2025