machfb.c revision 1.103.4.1
1 /* $NetBSD: machfb.c,v 1.103.4.1 2021/03/21 21:09:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.103.4.1 2021/03/21 21:09:14 thorpej Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #include <dev/wscons/wsdisplayvar.h> 58 59 #include <dev/wscons/wsconsio.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/rasops/rasops.h> 62 #include <dev/pci/wsdisplay_pci.h> 63 64 #include <dev/wscons/wsdisplay_vconsvar.h> 65 #include <dev/wscons/wsdisplay_glyphcachevar.h> 66 67 #include "opt_wsemul.h" 68 #include "opt_machfb.h" 69 #include "opt_glyphcache.h" 70 71 #ifdef MACHFB_DEBUG 72 #define DPRINTF printf 73 #else 74 #define DPRINTF while (0) printf 75 #endif 76 77 #define MACH64_REG_SIZE 0x800 78 #define MACH64_REG_OFF 0x7ff800 79 80 #define NBARS 3 /* number of Mach64 PCI BARs */ 81 82 struct vga_bar { 83 bus_addr_t vb_base; 84 bus_size_t vb_size; 85 pcireg_t vb_type; 86 int vb_flags; 87 }; 88 89 struct mach64_softc { 90 device_t sc_dev; 91 pci_chipset_tag_t sc_pc; 92 pcitag_t sc_pcitag; 93 94 struct vga_bar sc_bars[NBARS]; 95 struct vga_bar sc_rom; 96 97 #define sc_aperbase sc_bars[0].vb_base 98 #define sc_apersize sc_bars[0].vb_size 99 100 #define sc_iobase sc_bars[1].vb_base 101 #define sc_iosize sc_bars[1].vb_size 102 103 #define sc_regbase sc_bars[2].vb_base 104 #define sc_regsize sc_bars[2].vb_size 105 106 bus_space_tag_t sc_regt; 107 bus_space_tag_t sc_memt; 108 bus_space_tag_t sc_iot; 109 bus_space_handle_t sc_regh; 110 bus_space_handle_t sc_memh; 111 #if 0 112 void *sc_aperture; /* mapped aperture vaddr */ 113 void *sc_registers; /* mapped registers vaddr */ 114 #endif 115 uint32_t sc_nbus, sc_ndev, sc_nfunc; 116 size_t memsize; 117 int memtype; 118 119 int sc_mode; 120 int sc_bg; 121 int sc_locked; 122 123 int has_dsp; 124 int bits_per_pixel; 125 int max_x; 126 int max_y; 127 int virt_x; 128 int virt_y; 129 int stride; /* in pixels */ 130 int color_depth; 131 132 int mem_freq; 133 int ramdac_freq; 134 int ref_freq; 135 int vclk_freq; 136 137 int ref_div; 138 int log2_vclk_post_div; 139 int vclk_post_div; 140 int vclk_fb_div; 141 int mclk_post_div; 142 int mclk_fb_div; 143 int sc_clock; /* which clock to use */ 144 int minref, m; 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 struct edid_info sc_ei; 150 int sc_setmode; 151 int sc_gen_cntl; 152 153 u_char sc_cmap_red[256]; 154 u_char sc_cmap_green[256]; 155 u_char sc_cmap_blue[256]; 156 int sc_dacw, sc_blanked, sc_console; 157 struct vcons_data vd; 158 struct wsdisplay_accessops sc_accessops; 159 glyphcache sc_gc; 160 }; 161 162 struct mach64_crtcregs { 163 uint32_t h_total_disp; 164 uint32_t h_sync_strt_wid; 165 uint32_t v_total_disp; 166 uint32_t v_sync_strt_wid; 167 uint32_t gen_cntl; 168 uint32_t clock_cntl; 169 uint32_t color_depth; 170 uint32_t dot_clock; 171 }; 172 173 static struct { 174 uint16_t chip_id; 175 uint32_t ramdac_freq; 176 } const mach64_info[] = { 177 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 178 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 179 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 189 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 190 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 193 #if 0 194 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 197 #endif 198 { PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI, 230000 }, 199 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 200 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 201 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 202 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 203 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 204 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 205 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 206 }; 207 208 static int mach64_chip_id, mach64_chip_rev; 209 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 210 211 static const char *mach64_gx_memtype_names[] = { 212 "DRAM", "VRAM", "VRAM", "DRAM", 213 "DRAM", "VRAM", "VRAM", "(unknown type)" 214 }; 215 216 static const char *mach64_memtype_names[] = { 217 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 218 "(unknown type)" 219 }; 220 221 extern const u_char rasops_cmap[768]; 222 223 static int mach64_match(device_t, cfdata_t, void *); 224 static void mach64_attach(device_t, device_t, void *); 225 226 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, 227 mach64_attach, NULL, NULL); 228 229 static void mach64_init(struct mach64_softc *); 230 static int mach64_get_memsize(struct mach64_softc *); 231 static int mach64_get_max_ramdac(struct mach64_softc *); 232 static int mach64_ref_freq(void); 233 234 #ifdef MACHFB_DEBUG 235 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 236 static void mach64_print_reg(struct mach64_softc *); 237 #endif 238 239 static int mach64_calc_crtcregs(struct mach64_softc *, 240 struct mach64_crtcregs *, 241 struct videomode *); 242 static void mach64_set_crtcregs(struct mach64_softc *, 243 struct mach64_crtcregs *); 244 245 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 246 static void mach64_set_dsp(struct mach64_softc *); 247 static void mach64_set_pll(struct mach64_softc *, int); 248 static void mach64_reset_engine(struct mach64_softc *); 249 static void mach64_init_engine(struct mach64_softc *); 250 #if 0 251 static void mach64_adjust_frame(struct mach64_softc *, int, int); 252 #endif 253 static void mach64_init_lut(struct mach64_softc *); 254 255 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 256 static int mach64_is_console(struct mach64_softc *); 257 258 static void mach64_cursor(void *, int, int, int); 259 #if 0 260 static int mach64_mapchar(void *, int, u_int *); 261 #endif 262 static void mach64_putchar_mono(void *, int, int, u_int, long); 263 static void mach64_putchar_aa8(void *, int, int, u_int, long); 264 static void mach64_copycols(void *, int, int, int, int); 265 static void mach64_erasecols(void *, int, int, int, long); 266 static void mach64_copyrows(void *, int, int, int); 267 static void mach64_eraserows(void *, int, int, long); 268 static void mach64_clearscreen(struct mach64_softc *); 269 270 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 271 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 272 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 273 uint8_t, uint8_t); 274 static void mach64_bitblt(void *, int, int, int, int, int, int, int); 275 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 276 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 277 uint32_t, uint32_t); 278 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 279 #if 0 280 static void mach64_showpal(struct mach64_softc *); 281 #endif 282 283 static void machfb_blank(struct mach64_softc *, int); 284 static int machfb_drm_print(void *, const char *); 285 286 static struct wsscreen_descr mach64_defaultscreen = { 287 "default", 288 80, 30, 289 NULL, 290 8, 16, 291 WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE 292 | WSSCREEN_RESIZE , 293 NULL 294 }; 295 296 static const struct wsscreen_descr *_mach64_scrlist[] = { 297 &mach64_defaultscreen, 298 }; 299 300 static struct wsscreen_list mach64_screenlist = { 301 __arraycount(_mach64_scrlist), 302 _mach64_scrlist 303 }; 304 305 static int mach64_ioctl(void *, void *, u_long, void *, int, 306 struct lwp *); 307 static paddr_t mach64_mmap(void *, void *, off_t, int); 308 309 static struct vcons_screen mach64_console_screen; 310 311 /* 312 * Inline functions for getting access to register aperture. 313 */ 314 315 static inline uint32_t 316 regr(struct mach64_softc *sc, uint32_t index) 317 { 318 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400); 319 } 320 321 static inline uint8_t 322 regrb(struct mach64_softc *sc, uint32_t index) 323 { 324 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400); 325 } 326 327 static inline void 328 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 329 { 330 bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 331 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 332 BUS_SPACE_BARRIER_WRITE); 333 } 334 335 static inline void 336 regws(struct mach64_softc *sc, uint32_t index, uint32_t data) 337 { 338 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 339 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4, 340 BUS_SPACE_BARRIER_WRITE); 341 } 342 343 static inline void 344 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 345 { 346 bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data); 347 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1, 348 BUS_SPACE_BARRIER_WRITE); 349 } 350 351 static inline void 352 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 353 { 354 uint32_t reg; 355 356 reg = regr(sc, CLOCK_CNTL); 357 reg |= PLL_WR_EN; 358 regw(sc, CLOCK_CNTL, reg); 359 reg &= ~(PLL_ADDR | PLL_DATA); 360 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 361 reg |= data << PLL_DATA_SHIFT; 362 reg |= CLOCK_STROBE; 363 regw(sc, CLOCK_CNTL, reg); 364 reg &= ~PLL_WR_EN; 365 regw(sc, CLOCK_CNTL, reg); 366 } 367 368 static inline uint8_t 369 regrb_pll(struct mach64_softc *sc, uint32_t index) 370 { 371 372 regwb(sc, CLOCK_CNTL + 1, index << 2); 373 return regrb(sc, CLOCK_CNTL + 2); 374 } 375 376 static inline void 377 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 378 { 379 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 380 continue; 381 } 382 383 static inline void 384 wait_for_idle(struct mach64_softc *sc) 385 { 386 wait_for_fifo(sc, 16); 387 while ((regr(sc, GUI_STAT) & 1) != 0) 388 continue; 389 } 390 391 static int 392 mach64_match(device_t parent, cfdata_t match, void *aux) 393 { 394 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 395 int i; 396 397 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 398 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 399 return 0; 400 401 for (i = 0; i < __arraycount(mach64_info); i++) 402 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 403 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 404 mach64_chip_rev = PCI_REVISION(pa->pa_class); 405 return 100; 406 } 407 408 return 0; 409 } 410 411 static void 412 mach64_attach(device_t parent, device_t self, void *aux) 413 { 414 struct mach64_softc *sc = device_private(self); 415 struct pci_attach_args *pa = aux; 416 struct rasops_info *ri; 417 const char *mptr = NULL; 418 prop_data_t edid_data; 419 const struct videomode *mode = NULL; 420 int bar, id, expected_id; 421 int is_gx; 422 const char **memtype_names; 423 struct wsemuldisplaydev_attach_args aa; 424 long defattr; 425 int width = 1024, height = 768; 426 pcireg_t screg; 427 uint32_t reg; 428 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 429 int use_mmio = FALSE; 430 431 sc->sc_dev = self; 432 sc->sc_pc = pa->pa_pc; 433 sc->sc_pcitag = pa->pa_tag; 434 sc->sc_dacw = -1; 435 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 436 sc->sc_nbus = pa->pa_bus; 437 sc->sc_ndev = pa->pa_device; 438 sc->sc_nfunc = pa->pa_function; 439 sc->sc_locked = 0; 440 sc->sc_iot = pa->pa_iot; 441 sc->sc_accessops.ioctl = mach64_ioctl; 442 sc->sc_accessops.mmap = mach64_mmap; 443 sc->sc_setmode = 0; 444 445 pci_aprint_devinfo(pa, "Graphics processor"); 446 #ifdef MACHFB_DEBUG 447 printf(prop_dictionary_externalize(device_properties(self))); 448 #endif 449 450 /* enable memory access */ 451 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 452 if ((screg & enables) != enables) { 453 screg |= enables; 454 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 455 PCI_COMMAND_STATUS_REG, screg); 456 } 457 for (bar = 0; bar < NBARS; bar++) { 458 reg = PCI_MAPREG_START + (bar * 4); 459 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 460 sc->sc_pcitag, reg); 461 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 462 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 463 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 464 } 465 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 466 (uint32_t)sc->sc_apersize); 467 468 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 469 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 470 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 471 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 472 sc->sc_memt = pa->pa_memt; 473 474 /* use MMIO register aperture if available */ 475 if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) { 476 if (pci_mapreg_map(pa, MACH64_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 477 0, &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase, 478 &sc->sc_regsize) == 0) { 479 480 /* 481 * the MMIO aperture maps both 1KB register blocks, but 482 * all register offsets are relative to the 2nd one so 483 * for now fix this up in MACH64_REG_OFF and the access 484 * functions 485 */ 486 aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n"); 487 use_mmio = TRUE; 488 } 489 } 490 if (!use_mmio) { 491 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, 492 sc->sc_apersize, BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 493 panic("%s: failed to map aperture", 494 device_xname(sc->sc_dev)); 495 } 496 497 sc->sc_regt = sc->sc_memt; 498 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 499 MACH64_REG_SIZE, &sc->sc_regh); 500 } 501 502 mach64_init(sc); 503 504 aprint_normal_dev(sc->sc_dev, 505 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 506 (u_int)(sc->sc_apersize / (1024 * 1024)), 507 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 508 (u_int)sc->sc_regbase); 509 510 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 511 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 512 #ifdef MACHFB_DEBUG 513 mach64_get_mode(sc, NULL); 514 mach64_print_reg(sc); 515 #endif 516 517 prop_dictionary_get_uint32(device_properties(self), "width", &width); 518 prop_dictionary_get_uint32(device_properties(self), "height", &height); 519 520 default_mode.hdisplay = width; 521 default_mode.vdisplay = height; 522 523 prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 524 "videomode", &mptr); 525 526 memset(&sc->sc_ei, 0, sizeof(sc->sc_ei)); 527 if (mptr == NULL && 528 (edid_data = prop_dictionary_get(device_properties(self), "EDID")) 529 != NULL) { 530 531 sc->sc_edid_size = uimin(1024, prop_data_size(edid_data)); 532 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 533 memcpy(sc->sc_edid_data, prop_data_value(edid_data), 534 sc->sc_edid_size); 535 536 edid_parse(sc->sc_edid_data, &sc->sc_ei); 537 538 #ifdef MACHFB_DEBUG 539 edid_print(&sc->sc_ei); 540 #endif 541 } 542 is_gx = 0; 543 switch(mach64_chip_id) { 544 case PCI_PRODUCT_ATI_MACH64_GX: 545 case PCI_PRODUCT_ATI_MACH64_CX: 546 is_gx = 1; 547 /* FALLTHROUGH */ 548 case PCI_PRODUCT_ATI_MACH64_CT: 549 sc->has_dsp = 0; 550 break; 551 case PCI_PRODUCT_ATI_MACH64_VT: 552 case PCI_PRODUCT_ATI_RAGE_II: 553 if((mach64_chip_rev & 0x07) == 0) { 554 sc->has_dsp = 0; 555 break; 556 } 557 /* FALLTHROUGH */ 558 default: 559 sc->has_dsp = 1; 560 } 561 562 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 563 564 sc->memsize = mach64_get_memsize(sc); 565 566 if(is_gx) 567 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 568 else 569 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 570 571 sc->ref_freq = mach64_ref_freq(); 572 573 reg = regr(sc, CLOCK_CNTL); 574 sc->sc_clock = reg & 3; 575 DPRINTF("using clock %d\n", sc->sc_clock); 576 577 DPRINTF("ref_freq: %d\n", sc->ref_freq); 578 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 579 DPRINTF("ref_div: %d\n", sc->ref_div); 580 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 581 DPRINTF("mclk_fb_div: %d\n", sc->mclk_fb_div); 582 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 583 (sc->ref_div * 2); 584 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 585 (sc->mem_freq * sc->ref_div); 586 sc->ramdac_freq = mach64_get_max_ramdac(sc); 587 { 588 sc->minref = sc->ramdac_freq / 510; 589 sc->m = sc->ref_freq / sc->minref; 590 DPRINTF("minref: %d m: %d\n", sc->minref, sc->m); 591 } 592 aprint_normal_dev(sc->sc_dev, 593 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 594 (u_long)sc->memsize, 595 memtype_names[sc->memtype], 596 sc->mem_freq / 1000, sc->mem_freq % 1000, 597 sc->ramdac_freq / 1000); 598 599 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 600 switch(mach64_chip_id) { 601 case PCI_PRODUCT_ATI_MACH64_GX: 602 expected_id = 0x00d7; 603 break; 604 case PCI_PRODUCT_ATI_MACH64_CX: 605 expected_id = 0x0057; 606 break; 607 default: 608 /* Most chip IDs match their PCI product ID. */ 609 expected_id = mach64_chip_id; 610 } 611 612 if (id != expected_id) { 613 aprint_error_dev(sc->sc_dev, 614 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 615 return; 616 } 617 618 sc->sc_console = mach64_is_console(sc); 619 sc->sc_gen_cntl = regr(sc, CRTC_GEN_CNTL); 620 aprint_debug("gen_cntl: %08x\n", sc->sc_gen_cntl); 621 sc->sc_gen_cntl &= CRTC_CSYNC_EN; 622 aprint_normal_dev(sc->sc_dev, "found composite sync %s\n", 623 sc->sc_gen_cntl ? "enabled" : "disabled"); 624 625 #define MODE_IS_VALID(m) ((sc->ramdac_freq >= (m)->dot_clock) && \ 626 ((m)->hdisplay <= 1280)) 627 628 /* no mode setting support on ancient chips with external clocks */ 629 sc->sc_setmode = 0; 630 if (!is_gx) { 631 /* 632 * Now pick a mode. 633 */ 634 if ((sc->sc_ei.edid_preferred_mode != NULL)) { 635 struct videomode *m = sc->sc_ei.edid_preferred_mode; 636 if (MODE_IS_VALID(m)) { 637 memcpy(&default_mode, m, 638 sizeof(struct videomode)); 639 sc->sc_setmode = 1; 640 } else { 641 aprint_normal_dev(sc->sc_dev, 642 "unable to use EDID preferred mode " 643 "(%d x %d)\n", m->hdisplay, m->vdisplay); 644 } 645 } 646 /* 647 * if we can't use the preferred mode go look for the 648 * best one we can support 649 */ 650 if (sc->sc_setmode == 0) { 651 struct videomode *m = sc->sc_ei.edid_modes; 652 653 mode = NULL; 654 sort_modes(sc->sc_ei.edid_modes, 655 &sc->sc_ei.edid_preferred_mode, 656 sc->sc_ei.edid_nmodes); 657 for (int n = 0; n < sc->sc_ei.edid_nmodes; n++) 658 if (MODE_IS_VALID(&m[n])) { 659 mode = &m[n]; 660 break; 661 } 662 if (mode != NULL) { 663 memcpy(&default_mode, mode, 664 sizeof(struct videomode)); 665 sc->sc_setmode = 1; 666 } 667 } 668 } 669 670 /* make sure my_mode points at something sensible if the above fails */ 671 if (default_mode.dot_clock == 0) { 672 sc->sc_setmode = 0; 673 mode = pick_mode_by_ref(width, height, 60); 674 if (mode != NULL) { 675 memcpy(&default_mode, mode, sizeof(default_mode)); 676 } else if ((width > 0) && (height > 0)) { 677 default_mode.hdisplay = width; 678 default_mode.vdisplay = height; 679 } else { 680 /* 681 * if we end up here we're probably dealing with 682 * uninitialized hardware - try to set 1024x768@60 and 683 * hope for the best... 684 */ 685 mode = pick_mode_by_ref(1024, 768, 60); 686 if (mode == NULL) return; 687 memcpy(&default_mode, mode, sizeof(default_mode)); 688 if (!is_gx) sc->sc_setmode = 1; 689 } 690 } 691 692 sc->sc_my_mode = &default_mode; 693 694 if ((width == sc->sc_my_mode->hdisplay) && 695 (height == sc->sc_my_mode->vdisplay)) 696 sc->sc_setmode = 0; 697 698 sc->bits_per_pixel = 8; 699 sc->virt_x = sc->sc_my_mode->hdisplay; 700 sc->virt_y = sc->sc_my_mode->vdisplay; 701 sc->stride = (sc->virt_x + 7) & ~7; /* hw needs multiples of 8 */ 702 sc->max_x = sc->virt_x - 1; 703 sc->max_y = (sc->memsize * 1024) / 704 (sc->stride * (sc->bits_per_pixel / 8)) - 1; 705 706 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 707 708 mach64_init_engine(sc); 709 710 if (sc->sc_setmode) 711 mach64_modeswitch(sc, sc->sc_my_mode); 712 713 aprint_normal_dev(sc->sc_dev, 714 "initial resolution %dx%d at %d bpp\n", 715 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 716 sc->bits_per_pixel); 717 718 wsfont_init(); 719 720 #ifdef GLYPHCACHE_DEBUG 721 /* shrink the screen so we can see part of the glyph cache */ 722 sc->sc_my_mode->vdisplay -= 200; 723 #endif 724 725 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 726 sc->vd.init_screen = mach64_init_screen; 727 sc->vd.show_screen_cookie = &sc->sc_gc; 728 sc->vd.show_screen_cb = glyphcache_adapt; 729 730 sc->sc_gc.gc_bitblt = mach64_bitblt; 731 sc->sc_gc.gc_blitcookie = sc; 732 sc->sc_gc.gc_rop = MIX_SRC; 733 734 ri = &mach64_console_screen.scr_ri; 735 if (sc->sc_console) { 736 737 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 738 &defattr); 739 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 740 741 mach64_defaultscreen.textops = &ri->ri_ops; 742 mach64_defaultscreen.capabilities = ri->ri_caps; 743 mach64_defaultscreen.nrows = ri->ri_rows; 744 mach64_defaultscreen.ncols = ri->ri_cols; 745 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 746 ((sc->memsize * 1024) / sc->stride) - 747 sc->sc_my_mode->vdisplay - 5, 748 sc->stride, 749 ri->ri_font->fontwidth, 750 ri->ri_font->fontheight, 751 defattr); 752 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 753 } else { 754 /* 755 * since we're not the console we can postpone the rest 756 * until someone actually allocates a screen for us 757 */ 758 if (mach64_console_screen.scr_ri.ri_rows == 0) { 759 /* do some minimal setup to avoid weirdnesses later */ 760 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 761 &defattr); 762 } else 763 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 764 765 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 766 ((sc->memsize * 1024) / sc->stride) - 767 sc->sc_my_mode->vdisplay - 5, 768 sc->stride, 769 ri->ri_font->fontwidth, 770 ri->ri_font->fontheight, 771 defattr); 772 } 773 774 sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG]; 775 mach64_clearscreen(sc); 776 mach64_init_lut(sc); 777 778 if (sc->sc_console) 779 vcons_replay_msgbuf(&mach64_console_screen); 780 781 machfb_blank(sc, 0); /* unblank the screen */ 782 783 aa.console = sc->sc_console; 784 aa.scrdata = &mach64_screenlist; 785 aa.accessops = &sc->sc_accessops; 786 aa.accesscookie = &sc->vd; 787 788 config_found(self, &aa, wsemuldisplaydevprint, CFARG_EOL); 789 #if 0 790 /* XXX 791 * turns out some firmware doesn't turn these back on when needed 792 * so we need to turn them off only when mapping vram in 793 * WSDISPLAYIO_MODE_DUMB would overlap ( unlikely but far from 794 * impossible ) 795 */ 796 if (use_mmio) { 797 /* 798 * Now that we took over, turn off the aperture registers if we 799 * don't use them. Can't do this earlier since on some hardware 800 * we use firmware calls as early console output which may in 801 * turn try to access these registers. 802 */ 803 reg = regr(sc, BUS_CNTL); 804 aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg); 805 reg |= BUS_APER_REG_DIS; 806 regw(sc, BUS_CNTL, reg); 807 } 808 #endif 809 config_found_ia(self, "drm", aux, machfb_drm_print); 810 } 811 812 static int 813 machfb_drm_print(void *aux, const char *pnp) 814 { 815 if (pnp) 816 aprint_normal("direct rendering for %s", pnp); 817 return (UNSUPP); 818 } 819 820 static void 821 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 822 long *defattr) 823 { 824 struct mach64_softc *sc = cookie; 825 struct rasops_info *ri = &scr->scr_ri; 826 827 ri->ri_depth = sc->bits_per_pixel; 828 ri->ri_width = sc->sc_my_mode->hdisplay; 829 ri->ri_height = sc->sc_my_mode->vdisplay; 830 ri->ri_stride = sc->stride; 831 ri->ri_flg = RI_CENTER | RI_FULLCLEAR; 832 if (ri->ri_depth == 8) 833 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA | 834 RI_PREFER_ALPHA; 835 836 #ifdef VCONS_DRAW_INTR 837 scr->scr_flags |= VCONS_DONT_READ; 838 #endif 839 scr->scr_flags |= VCONS_LOADFONT; 840 841 rasops_init(ri, 0, 0); 842 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE | 843 WSSCREEN_RESIZE; 844 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 845 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 846 847 /* enable acceleration */ 848 ri->ri_hw = scr; 849 ri->ri_ops.copyrows = mach64_copyrows; 850 ri->ri_ops.copycols = mach64_copycols; 851 ri->ri_ops.eraserows = mach64_eraserows; 852 ri->ri_ops.erasecols = mach64_erasecols; 853 ri->ri_ops.cursor = mach64_cursor; 854 if (FONT_IS_ALPHA(ri->ri_font)) { 855 ri->ri_ops.putchar = mach64_putchar_aa8; 856 } else 857 ri->ri_ops.putchar = mach64_putchar_mono; 858 } 859 860 static void 861 mach64_init(struct mach64_softc *sc) 862 { 863 sc->sc_blanked = 0; 864 } 865 866 static int 867 mach64_get_memsize(struct mach64_softc *sc) 868 { 869 int tmp, memsize; 870 int mem_tab[] = { 871 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 872 }; 873 tmp = regr(sc, MEM_CNTL); 874 #ifdef DIAGNOSTIC 875 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 876 #endif 877 if (sc->has_dsp) { 878 tmp &= 0x0000000f; 879 if (tmp < 8) 880 memsize = (tmp + 1) * 512; 881 else if (tmp < 12) 882 memsize = (tmp - 3) * 1024; 883 else 884 memsize = (tmp - 7) * 2048; 885 } else { 886 memsize = mem_tab[tmp & 0x07]; 887 } 888 889 return memsize; 890 } 891 892 static int 893 mach64_get_max_ramdac(struct mach64_softc *sc) 894 { 895 int i; 896 897 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 898 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 899 (mach64_chip_rev & 0x07)) 900 return 170000; 901 902 for (i = 0; i < __arraycount(mach64_info); i++) 903 if (mach64_chip_id == mach64_info[i].chip_id) 904 return mach64_info[i].ramdac_freq; 905 906 if (sc->bits_per_pixel == 8) 907 return 135000; 908 else 909 return 80000; 910 } 911 912 static int 913 mach64_ref_freq(void) 914 { 915 /* 916 * There doesn't seem to be any way to calculate the reference 917 * frequency from known values 918 */ 919 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 920 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 921 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI))) 922 return 29498; 923 else 924 return 14318; 925 } 926 927 #ifdef MACHFB_DEBUG 928 static void 929 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 930 { 931 int htotal, hdisplay, hsync_start, hsync_end; 932 int vtotal, vdisplay, vsync_start, vsync_end; 933 int clk_ctl, clock; 934 int ref_freq, ref_div, vclk_post_div, vclk_fb_div; 935 int nhsync, nvsync; 936 int post_div, dot_clock, vrefresh, vrefresh2; 937 938 hdisplay = regr(sc, CRTC_H_TOTAL_DISP); 939 hsync_end = regr(sc, CRTC_H_SYNC_STRT_WID); 940 vdisplay = regr(sc, CRTC_V_TOTAL_DISP); 941 vsync_end = regr(sc, CRTC_V_SYNC_STRT_WID); 942 clk_ctl = regr(sc, CLOCK_CNTL); 943 clock = clk_ctl & 3; 944 ref_div = regrb_pll(sc, PLL_REF_DIV); 945 vclk_post_div = regrb_pll(sc, VCLK_POST_DIV); 946 vclk_fb_div = regrb_pll(sc, VCLK0_FB_DIV + clock); 947 ref_freq = mach64_ref_freq(); 948 949 htotal = ((hdisplay & 0x01ff) + 1) << 3; 950 hdisplay = (((hdisplay & 0x1ff0000) >> 16) + 1) << 3; 951 if (hsync_end & CRTC_HSYNC_NEG) 952 nhsync = 1; 953 else 954 nhsync = 0; 955 hsync_start = (((hsync_end & 0xff) + 1) << 3) + 956 ((hsync_end & 0x700) >> 8); 957 hsync_end = (((hsync_end & 0x1f0000) >> 16) << 3) + hsync_start; 958 959 vtotal = (vdisplay & 0x07ff) + 1; 960 vdisplay = ((vdisplay & 0x7ff0000) >> 16) + 1; 961 if (vsync_end & CRTC_VSYNC_NEG) 962 nvsync = 1; 963 else 964 nvsync = 0; 965 vsync_start = (vsync_end & 0x07ff) + 1; 966 vsync_end = ((vsync_end & 0x1f0000) >> 16) + vsync_start; 967 968 switch ((vclk_post_div >> (clock * 2)) & 3) { 969 case 3: 970 post_div = 8; 971 break; 972 case 2: 973 post_div = 4; 974 break; 975 case 1: 976 post_div = 2; 977 break; 978 default: 979 post_div = 1; 980 break; 981 } 982 dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div); 983 vrefresh = (dot_clock * 1000) / (htotal * vtotal); 984 vrefresh2 = ((dot_clock * 1000) - (vrefresh * htotal * vtotal)) * 100 / 985 (htotal * vtotal); 986 987 aprint_normal_dev(sc->sc_dev, "Video mode:\n"); 988 aprint_normal("\t%d" "x%d @ %d.%02dHz " 989 "(%d %d %d %d %d %d %d %cH %cV)\n", 990 hdisplay, vdisplay, vrefresh, vrefresh2, dot_clock, 991 hsync_start, hsync_end, htotal, vsync_start, vsync_end, vtotal, 992 nhsync == 1 ? '-' : '+', nvsync == 1 ? '-' : '+'); 993 994 if (mode != NULL) { 995 mode->dot_clock = dot_clock; 996 mode->htotal = htotal; 997 mode->hdisplay = hdisplay; 998 mode->hsync_start = hsync_start; 999 mode->hsync_end = hsync_end; 1000 mode->vtotal = vtotal; 1001 mode->vdisplay = vdisplay; 1002 mode->vsync_start = vsync_start; 1003 mode->vsync_end = vsync_end; 1004 mode->flags = 0; 1005 if (nhsync) 1006 mode->flags |= VID_NHSYNC; 1007 if (nvsync) 1008 mode->flags |= VID_NVSYNC; 1009 } 1010 } 1011 1012 static void 1013 mach64_print_reg(struct mach64_softc *sc) 1014 { 1015 struct reglist { 1016 int offset; 1017 const char *name; 1018 }; 1019 static const struct reglist reglist_tab[] = { 1020 { 0x0000, "CRTC_H_TOTAL_DISP" }, 1021 { 0x0004, "CRTC_H_SYNC_STRT_WID" }, 1022 { 0x0008, "CRTC_V_TOTAL_DISP" }, 1023 { 0x000C, "CRTC_V_SYNC_STRT_WID" }, 1024 { 0x0010, "CRTC_VLINE_CRNT_VLINE" }, 1025 { 0x0014, "CRTC_OFF_PITCH" }, 1026 { 0x001C, "CRTC_GEN_CNTL" }, 1027 { 0x0090, "CLOCK_CNTL" }, 1028 { 0, NULL } 1029 }; 1030 static const struct reglist plllist_tab[] = { 1031 { 0x02, "PLL_REF_DIV" }, 1032 { 0x03, "PLL_GEN_CNTL" }, 1033 { 0x04, "MCLK_FB_DIV" }, 1034 { 0x05, "PLL_VCLK_CNTL" }, 1035 { 0x06, "VCLK_POST_DIV" }, 1036 { 0x07, "VCLK0_FB_DIV" }, 1037 { 0x08, "VCLK1_FB_DIV" }, 1038 { 0x09, "VCLK2_FB_DIV" }, 1039 { 0x0A, "VCLK3_FB_DIV" }, 1040 { 0x0B, "PLL_XCLK_CNTL" }, 1041 { 0x10, "LVDSPLL_CNTL0" }, 1042 { 0x11, "LVDSPLL_CNTL0" }, 1043 { 0x19, "EXT_VPLL_CNTL" }, 1044 { 0x1A, "EXT_VPLL_REF_DIV" }, 1045 { 0x1B, "EXT_VPLL_FB_DIV" }, 1046 { 0x1C, "EXT_VPLL_MSB" }, 1047 { 0, NULL } 1048 }; 1049 const struct reglist *r; 1050 1051 aprint_normal("CRTC registers\n"); 1052 for (r = reglist_tab; r->name != NULL; r++) 1053 aprint_normal("0x%04x 0x%08x %s\n", r->offset, 1054 regr(sc, r->offset), r->name); 1055 aprint_normal("PLL registers\n"); 1056 for (r = plllist_tab; r->name != NULL; r++) 1057 aprint_normal("0x%02x 0x%02x %s\n", r->offset, 1058 regrb_pll(sc, r->offset), r->name); 1059 } 1060 #endif 1061 1062 static int 1063 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 1064 struct videomode *mode) 1065 { 1066 1067 if (mode->dot_clock > sc->ramdac_freq) 1068 /* Clock too high. */ 1069 return 1; 1070 1071 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 1072 ((mode->htotal >> 3) - 1); 1073 crtc->h_sync_strt_wid = 1074 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 1075 ((mode->hsync_start >> 3) - 1) | ((mode->hsync_start & 7) << 8); 1076 1077 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 1078 (mode->vtotal - 1); 1079 crtc->v_sync_strt_wid = 1080 ((mode->vsync_end - mode->vsync_start) << 16) | 1081 (mode->vsync_start - 1); 1082 1083 if (mode->flags & VID_NVSYNC) 1084 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 1085 1086 switch (sc->bits_per_pixel) { 1087 case 8: 1088 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 1089 break; 1090 case 16: 1091 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 1092 break; 1093 case 32: 1094 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 1095 break; 1096 } 1097 1098 crtc->gen_cntl = 0; 1099 if (mode->flags & VID_INTERLACE) 1100 crtc->gen_cntl |= CRTC_INTERLACE_EN; 1101 1102 if (mode->flags & VID_CSYNC) 1103 crtc->gen_cntl |= CRTC_CSYNC_EN; 1104 1105 crtc->dot_clock = mode->dot_clock; 1106 1107 return 0; 1108 } 1109 1110 static void 1111 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1112 { 1113 1114 mach64_set_pll(sc, crtc->dot_clock); 1115 1116 if (sc->has_dsp) 1117 mach64_set_dsp(sc); 1118 1119 DPRINTF("\th total: 0x%08x h sync: 0x%08x\n", 1120 crtc->h_total_disp, crtc->h_sync_strt_wid); 1121 DPRINTF("\tv total: 0x%08x v sync: 0x%08x\n", 1122 crtc->v_total_disp, crtc->v_sync_strt_wid); 1123 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1124 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1125 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1126 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1127 1128 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1129 1130 regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22); 1131 1132 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1133 sc->sc_gen_cntl | CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1134 } 1135 1136 static int 1137 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1138 { 1139 struct mach64_crtcregs crtc; 1140 1141 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1142 1143 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1144 return 1; 1145 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1146 if (crtc.dot_clock == 0) { 1147 aprint_error("%s: preposterous dot clock (%d)\n", 1148 device_xname(sc->sc_dev), crtc.dot_clock); 1149 return 1; 1150 } 1151 mach64_set_crtcregs(sc, &crtc); 1152 return 0; 1153 } 1154 1155 static void 1156 mach64_reset_engine(struct mach64_softc *sc) 1157 { 1158 1159 /* Reset engine.*/ 1160 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1161 1162 /* Enable engine. */ 1163 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1164 1165 /* Ensure engine is not locked up by clearing any FIFO or 1166 host errors. */ 1167 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1168 BUS_FIFO_ERR_ACK); 1169 } 1170 1171 static void 1172 mach64_init_engine(struct mach64_softc *sc) 1173 { 1174 uint32_t pitch_value; 1175 1176 pitch_value = sc->stride; 1177 1178 if (sc->bits_per_pixel == 24) 1179 pitch_value *= 3; 1180 1181 mach64_reset_engine(sc); 1182 1183 wait_for_fifo(sc, 14); 1184 1185 regw(sc, CONTEXT_MASK, 0xffffffff); 1186 1187 regw(sc, DST_OFF_PITCH, (pitch_value >> 3) << 22); 1188 1189 /* make sure the visible area starts where we're going to draw */ 1190 regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22); 1191 1192 regw(sc, DST_Y_X, 0); 1193 regw(sc, DST_HEIGHT, 0); 1194 regw(sc, DST_BRES_ERR, 0); 1195 regw(sc, DST_BRES_INC, 0); 1196 regw(sc, DST_BRES_DEC, 0); 1197 1198 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1199 DST_Y_TOP_TO_BOTTOM); 1200 1201 regw(sc, SRC_OFF_PITCH, (pitch_value >> 3) << 22); 1202 1203 regw(sc, SRC_Y_X, 0); 1204 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1205 regw(sc, SRC_Y_X_START, 0); 1206 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1207 1208 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1209 1210 wait_for_fifo(sc, 13); 1211 regw(sc, HOST_CNTL, 0); 1212 1213 regw(sc, PAT_REG0, 0); 1214 regw(sc, PAT_REG1, 0); 1215 regw(sc, PAT_CNTL, 0); 1216 1217 regw(sc, SC_LEFT, 0); 1218 regw(sc, SC_TOP, 0); 1219 regw(sc, SC_BOTTOM, 0x3fff); 1220 regw(sc, SC_RIGHT, pitch_value - 1); 1221 1222 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1223 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1224 regw(sc, DP_WRITE_MASK, 0xffffffff); 1225 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1226 1227 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1228 1229 wait_for_fifo(sc, 3); 1230 regw(sc, CLR_CMP_CLR, 0); 1231 regw(sc, CLR_CMP_MASK, 0xffffffff); 1232 regw(sc, CLR_CMP_CNTL, 0); 1233 1234 wait_for_fifo(sc, 3); 1235 switch (sc->bits_per_pixel) { 1236 case 8: 1237 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1238 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1239 /* We want 8 bit per channel */ 1240 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1241 break; 1242 case 32: 1243 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1244 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1245 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1246 break; 1247 } 1248 regw(sc, DP_WRITE_MASK, 0xff); 1249 1250 wait_for_fifo(sc, 5); 1251 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1252 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1253 1254 wait_for_idle(sc); 1255 } 1256 1257 #if 0 1258 static void 1259 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1260 { 1261 int offset; 1262 1263 offset = ((x + y * sc->stride) * (sc->bits_per_pixel >> 3)) >> 3; 1264 1265 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1266 offset); 1267 } 1268 #endif 1269 1270 static void 1271 mach64_set_dsp(struct mach64_softc *sc) 1272 { 1273 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1274 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1275 uint32_t xclks_per_qw, xclks_per_qw_m, y; 1276 uint32_t fifo_off, fifo_on; 1277 1278 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1279 1280 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1281 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1282 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1283 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1284 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1285 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1286 dsp_loop_latency = 0; 1287 fifo_depth = 24; 1288 } else { 1289 dsp_loop_latency = 2; 1290 fifo_depth = 32; 1291 } 1292 1293 dsp_precision = 0; 1294 1295 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1296 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1297 1298 xclks_per_qw_m = (sc->mem_freq * 64 << 4) / 1299 (sc->vclk_freq * sc->bits_per_pixel); 1300 1301 DPRINTF("xclks_per_qw %d %d\n", xclks_per_qw >> 7, xclks_per_qw_m); 1302 DPRINTF("mem %dkHz v %dkHz\n", sc->mem_freq, sc->vclk_freq); 1303 1304 y = (xclks_per_qw * fifo_depth) >> 11; 1305 1306 while (y) { 1307 y >>= 1; 1308 dsp_precision++; 1309 } 1310 dsp_precision -= 5; 1311 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1312 1313 switch (sc->memtype) { 1314 case DRAM: 1315 case EDO_DRAM: 1316 case PSEUDO_EDO: 1317 if (sc->memsize > 1024) { 1318 page_size = 9; 1319 dsp_loop_latency += 6; 1320 } else { 1321 page_size = 10; 1322 if (sc->memtype == DRAM) 1323 dsp_loop_latency += 8; 1324 else 1325 dsp_loop_latency += 7; 1326 } 1327 break; 1328 case SDRAM: 1329 if (sc->memsize > 1024) { 1330 page_size = 8; 1331 dsp_loop_latency += 8; 1332 } else { 1333 page_size = 10; 1334 dsp_loop_latency += 9; 1335 } 1336 break; 1337 case SGRAM: 1338 page_size = 8; 1339 dsp_loop_latency = 8; 1340 break; 1341 default: 1342 page_size = 10; 1343 dsp_loop_latency += 9; 1344 break; 1345 } 1346 1347 if (xclks_per_qw >= (page_size << 11)) 1348 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1349 else 1350 fifo_on = (3 * page_size + 2) << 6; 1351 1352 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1353 dsp_on = fifo_on >> dsp_precision; 1354 dsp_off = fifo_off >> dsp_precision; 1355 1356 DPRINTF("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1357 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1358 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1359 "mclk_post_div = %d, vclk_post_div = %d\n", 1360 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1361 sc->mclk_fb_div, sc->vclk_fb_div, 1362 sc->mclk_post_div, sc->vclk_post_div); 1363 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1364 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1365 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1366 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1367 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1368 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1369 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1370 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1371 } 1372 1373 static void 1374 mach64_set_pll(struct mach64_softc *sc, int clock) 1375 { 1376 uint32_t q, clockreg; 1377 int clockshift = sc->sc_clock << 1; 1378 uint8_t reg, vclk_ctl; 1379 1380 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1381 #ifdef MACHFB_DEBUG 1382 printf("q = %d\n", q); 1383 #endif 1384 if (q > 25500) { 1385 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1386 q = 25500; 1387 sc->vclk_post_div = 1; 1388 sc->log2_vclk_post_div = 0; 1389 } else if (q > 12750) { 1390 sc->vclk_post_div = 1; 1391 sc->log2_vclk_post_div = 0; 1392 } else if (q > 6350) { 1393 sc->vclk_post_div = 2; 1394 sc->log2_vclk_post_div = 1; 1395 } else if (q > 3150) { 1396 sc->vclk_post_div = 4; 1397 sc->log2_vclk_post_div = 2; 1398 } else if (q >= 1600) { 1399 sc->vclk_post_div = 8; 1400 sc->log2_vclk_post_div = 3; 1401 } else { 1402 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1403 sc->vclk_post_div = 8; 1404 sc->log2_vclk_post_div = 3; 1405 } 1406 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1407 DPRINTF("post_div: %d log2_post_div: %d mclk_div: %d\n", 1408 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1409 1410 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1411 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1412 vclk_ctl |= PLL_VCLK_RESET; 1413 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1414 1415 DPRINTF("target: %d output: %d\n", clock, 1416 (2 * sc->ref_freq * sc->vclk_fb_div) / 1417 (sc->ref_div * sc->vclk_post_div)); 1418 1419 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1420 reg = regrb_pll(sc, VCLK_POST_DIV); 1421 reg &= ~(3 << clockshift); 1422 reg |= (sc->log2_vclk_post_div << clockshift); 1423 regwb_pll(sc, VCLK_POST_DIV, reg); 1424 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1425 1426 vclk_ctl &= ~PLL_VCLK_RESET; 1427 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1428 1429 clockreg = regr(sc, CLOCK_CNTL); 1430 clockreg &= ~CLOCK_SEL; 1431 clockreg |= sc->sc_clock | CLOCK_STROBE; 1432 regw(sc, CLOCK_CNTL, clockreg); 1433 sc->vclk_freq = clock; 1434 } 1435 1436 static void 1437 mach64_init_lut(struct mach64_softc *sc) 1438 { 1439 uint8_t cmap[768]; 1440 int i, idx; 1441 1442 rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap)); 1443 idx = 0; 1444 for (i = 0; i < 256; i++) { 1445 mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1], 1446 cmap[idx + 2]); 1447 idx += 3; 1448 } 1449 } 1450 1451 static int 1452 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1453 uint8_t b) 1454 { 1455 sc->sc_cmap_red[index] = r; 1456 sc->sc_cmap_green[index] = g; 1457 sc->sc_cmap_blue[index] = b; 1458 /* 1459 * writing the dac index takes a while, in theory we can poll some 1460 * register to see when it's ready - but we better avoid writing it 1461 * unnecessarily 1462 */ 1463 if (index != sc->sc_dacw) { 1464 regwb(sc, DAC_MASK, 0xff); 1465 regwb(sc, DAC_WINDEX, index); 1466 } 1467 sc->sc_dacw = index + 1; 1468 regwb(sc, DAC_DATA, r); 1469 regwb(sc, DAC_DATA, g); 1470 regwb(sc, DAC_DATA, b); 1471 return 0; 1472 } 1473 1474 static int 1475 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1476 { 1477 uint index = cm->index; 1478 uint count = cm->count; 1479 int i, error; 1480 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1481 uint8_t *r, *g, *b; 1482 1483 if (cm->index >= 256 || cm->count > 256 || 1484 (cm->index + cm->count) > 256) 1485 return EINVAL; 1486 error = copyin(cm->red, &rbuf[index], count); 1487 if (error) 1488 return error; 1489 error = copyin(cm->green, &gbuf[index], count); 1490 if (error) 1491 return error; 1492 error = copyin(cm->blue, &bbuf[index], count); 1493 if (error) 1494 return error; 1495 1496 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1497 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1498 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1499 1500 r = &sc->sc_cmap_red[index]; 1501 g = &sc->sc_cmap_green[index]; 1502 b = &sc->sc_cmap_blue[index]; 1503 1504 for (i = 0; i < count; i++) { 1505 mach64_putpalreg(sc, index, *r, *g, *b); 1506 index++; 1507 r++, g++, b++; 1508 } 1509 return 0; 1510 } 1511 1512 static int 1513 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1514 { 1515 u_int index = cm->index; 1516 u_int count = cm->count; 1517 int error; 1518 1519 if (index >= 255 || count > 256 || index + count > 256) 1520 return EINVAL; 1521 1522 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1523 if (error) 1524 return error; 1525 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1526 if (error) 1527 return error; 1528 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1529 if (error) 1530 return error; 1531 1532 return 0; 1533 } 1534 1535 static int 1536 mach64_is_console(struct mach64_softc *sc) 1537 { 1538 bool console = 0; 1539 1540 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1541 "is_console", &console); 1542 return console; 1543 } 1544 1545 /* 1546 * wsdisplay_emulops 1547 */ 1548 1549 static void 1550 mach64_cursor(void *cookie, int on, int row, int col) 1551 { 1552 struct rasops_info *ri = cookie; 1553 struct vcons_screen *scr = ri->ri_hw; 1554 struct mach64_softc *sc = scr->scr_cookie; 1555 int x, y, wi, he; 1556 1557 wi = ri->ri_font->fontwidth; 1558 he = ri->ri_font->fontheight; 1559 1560 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1561 x = ri->ri_ccol * wi + ri->ri_xorigin; 1562 y = ri->ri_crow * he + ri->ri_yorigin; 1563 if (ri->ri_flg & RI_CURSOR) { 1564 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1565 ri->ri_flg &= ~RI_CURSOR; 1566 } 1567 ri->ri_crow = row; 1568 ri->ri_ccol = col; 1569 if (on) { 1570 x = ri->ri_ccol * wi + ri->ri_xorigin; 1571 y = ri->ri_crow * he + ri->ri_yorigin; 1572 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1573 ri->ri_flg |= RI_CURSOR; 1574 } 1575 } else { 1576 scr->scr_ri.ri_crow = row; 1577 scr->scr_ri.ri_ccol = col; 1578 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1579 } 1580 } 1581 1582 #if 0 1583 static int 1584 mach64_mapchar(void *cookie, int uni, u_int *index) 1585 { 1586 return 0; 1587 } 1588 #endif 1589 1590 static void 1591 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1592 { 1593 struct rasops_info *ri = cookie; 1594 struct wsdisplay_font *font = PICK_FONT(ri, c); 1595 struct vcons_screen *scr = ri->ri_hw; 1596 struct mach64_softc *sc = scr->scr_cookie; 1597 1598 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1599 int fg, bg, uc; 1600 uint8_t *data; 1601 int x, y, wi, he; 1602 wi = font->fontwidth; 1603 he = font->fontheight; 1604 1605 if (!CHAR_IN_FONT(c, font)) 1606 return; 1607 bg = ri->ri_devcmap[(attr >> 16) & 0x0f]; 1608 fg = ri->ri_devcmap[(attr >> 24) & 0x0f]; 1609 x = ri->ri_xorigin + col * wi; 1610 y = ri->ri_yorigin + row * he; 1611 if (c == 0x20) { 1612 mach64_rectfill(sc, x, y, wi, he, bg); 1613 } else { 1614 uc = c - font->firstchar; 1615 data = (uint8_t *)font->data + uc * 1616 ri->ri_fontscale; 1617 1618 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1619 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1620 } 1621 if (attr & 1) 1622 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1623 } 1624 } 1625 1626 static void 1627 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 1628 { 1629 struct rasops_info *ri = cookie; 1630 struct wsdisplay_font *font = PICK_FONT(ri, c); 1631 struct vcons_screen *scr = ri->ri_hw; 1632 struct mach64_softc *sc = scr->scr_cookie; 1633 uint32_t bg, fg, latch = 0, bg8, fg8, pixel; 1634 int i, x, y, wi, he, r, g, b, aval; 1635 int r1, g1, b1, r0, g0, b0, fgo, bgo; 1636 uint8_t *data8; 1637 int rv = 0, cnt = 0; 1638 1639 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1640 return; 1641 1642 if (!CHAR_IN_FONT(c, font)) 1643 return; 1644 1645 wi = font->fontwidth; 1646 he = font->fontheight; 1647 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1648 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1649 x = ri->ri_xorigin + col * wi; 1650 y = ri->ri_yorigin + row * he; 1651 1652 if (c == 0x20) { 1653 mach64_rectfill(sc, x, y, wi, he, bg); 1654 if (attr & 1) 1655 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1656 return; 1657 } 1658 1659 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1660 if (rv == GC_OK) 1661 return; 1662 1663 data8 = WSFONT_GLYPH(c, font); 1664 1665 wait_for_fifo(sc, 11); 1666 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1667 regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST); 1668 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1669 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1670 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1671 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1672 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1673 regw(sc, SRC_Y_X, 0); 1674 regw(sc, SRC_WIDTH1, wi); 1675 regw(sc, DST_Y_X, (x << 16) | y); 1676 regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he); 1677 1678 /* 1679 * we need the RGB colours here, so get offsets into rasops_cmap 1680 */ 1681 fgo = ((attr >> 24) & 0xf) * 3; 1682 bgo = ((attr >> 16) & 0xf) * 3; 1683 1684 r0 = rasops_cmap[bgo]; 1685 r1 = rasops_cmap[fgo]; 1686 g0 = rasops_cmap[bgo + 1]; 1687 g1 = rasops_cmap[fgo + 1]; 1688 b0 = rasops_cmap[bgo + 2]; 1689 b1 = rasops_cmap[fgo + 2]; 1690 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 1691 bg8 = R3G3B2(r0, g0, b0); 1692 fg8 = R3G3B2(r1, g1, b1); 1693 1694 wait_for_fifo(sc, 10); 1695 1696 for (i = 0; i < ri->ri_fontscale; i++) { 1697 aval = *data8; 1698 if (aval == 0) { 1699 pixel = bg8; 1700 } else if (aval == 255) { 1701 pixel = fg8; 1702 } else { 1703 r = aval * r1 + (255 - aval) * r0; 1704 g = aval * g1 + (255 - aval) * g0; 1705 b = aval * b1 + (255 - aval) * b0; 1706 pixel = ((r & 0xe000) >> 8) | 1707 ((g & 0xe000) >> 11) | 1708 ((b & 0xc000) >> 14); 1709 } 1710 latch = (latch << 8) | pixel; 1711 /* write in 32bit chunks */ 1712 if ((i & 3) == 3) { 1713 regws(sc, HOST_DATA0, latch); 1714 /* 1715 * not strictly necessary, old data should be shifted 1716 * out 1717 */ 1718 latch = 0; 1719 cnt++; 1720 if (cnt > 8) { 1721 wait_for_fifo(sc, 10); 1722 cnt = 0; 1723 } 1724 } 1725 data8++; 1726 } 1727 /* if we have pixels left in latch write them out */ 1728 if ((i & 3) != 0) { 1729 latch = latch << ((4 - (i & 3)) << 3); 1730 regws(sc, HOST_DATA0, latch); 1731 } 1732 1733 if (rv == GC_ADD) { 1734 glyphcache_add(&sc->sc_gc, c, x, y); 1735 } else if (attr & 1) { 1736 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1737 } 1738 1739 } 1740 1741 static void 1742 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1743 { 1744 struct rasops_info *ri = cookie; 1745 struct vcons_screen *scr = ri->ri_hw; 1746 struct mach64_softc *sc = scr->scr_cookie; 1747 int32_t xs, xd, y, width, height; 1748 1749 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1750 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1751 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1752 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1753 width = ri->ri_font->fontwidth * ncols; 1754 height = ri->ri_font->fontheight; 1755 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC); 1756 } 1757 } 1758 1759 static void 1760 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1761 { 1762 struct rasops_info *ri = cookie; 1763 struct vcons_screen *scr = ri->ri_hw; 1764 struct mach64_softc *sc = scr->scr_cookie; 1765 int32_t x, y, width, height, fg, bg, ul; 1766 1767 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1768 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1769 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1770 width = ri->ri_font->fontwidth * ncols; 1771 height = ri->ri_font->fontheight; 1772 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1773 1774 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1775 } 1776 } 1777 1778 static void 1779 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1780 { 1781 struct rasops_info *ri = cookie; 1782 struct vcons_screen *scr = ri->ri_hw; 1783 struct mach64_softc *sc = scr->scr_cookie; 1784 int32_t x, ys, yd, width, height; 1785 1786 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1787 x = ri->ri_xorigin; 1788 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1789 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1790 width = ri->ri_emuwidth; 1791 height = ri->ri_font->fontheight*nrows; 1792 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC); 1793 } 1794 } 1795 1796 static void 1797 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1798 { 1799 struct rasops_info *ri = cookie; 1800 struct vcons_screen *scr = ri->ri_hw; 1801 struct mach64_softc *sc = scr->scr_cookie; 1802 int32_t x, y, width, height, fg, bg, ul; 1803 1804 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1805 if ((row == 0) && (nrows == ri->ri_rows)) { 1806 /* clear full screen */ 1807 x = 0; 1808 y = 0; 1809 width = sc->virt_x; 1810 height = sc->virt_y; 1811 } else { 1812 x = ri->ri_xorigin; 1813 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1814 width = ri->ri_emuwidth; 1815 height = ri->ri_font->fontheight * nrows; 1816 } 1817 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1818 1819 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1820 } 1821 } 1822 1823 static void 1824 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width, 1825 int height, int rop) 1826 { 1827 struct mach64_softc *sc = cookie; 1828 uint32_t dest_ctl = 0; 1829 1830 #if 0 1831 wait_for_idle(sc); 1832 #else 1833 wait_for_fifo(sc, 10); 1834 #endif 1835 1836 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1837 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1838 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1839 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1840 if (yd < ys) { 1841 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1842 } else { 1843 ys += height - 1; 1844 yd += height - 1; 1845 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1846 } 1847 if (xd < xs) { 1848 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1849 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1850 } else { 1851 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1852 xs += width - 1; 1853 xd += width - 1; 1854 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1855 } 1856 regw(sc, DST_CNTL, dest_ctl); 1857 1858 regw(sc, SRC_Y_X, (xs << 16) | ys); 1859 regw(sc, SRC_WIDTH1, width); 1860 regw(sc, DST_Y_X, (xd << 16) | yd); 1861 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1862 } 1863 1864 static void 1865 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1866 int height, uint32_t fg, uint32_t bg) 1867 { 1868 wait_for_idle(sc); 1869 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1870 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1871 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1872 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1873 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1874 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1875 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1876 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1877 regw(sc, DP_BKGD_CLR, bg); 1878 regw(sc, DP_FRGD_CLR, fg); 1879 regw(sc, SRC_Y_X, 0); 1880 regw(sc, SRC_WIDTH1, width); 1881 regw(sc, DST_Y_X, (xd << 16) | yd); 1882 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1883 /* now feed the data into the chip */ 1884 } 1885 1886 static void 1887 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1888 { 1889 int i; 1890 uint32_t latch = 0, bork; 1891 int shift = 0; 1892 int reg = 0; 1893 1894 for (i = 0; i < count; i++) { 1895 bork = data[i]; 1896 latch |= (bork << shift); 1897 if (shift == 24) { 1898 regw(sc, HOST_DATA0 + reg, latch); 1899 latch = 0; 1900 shift = 0; 1901 reg = (reg + 4) & 0x3c; 1902 } else 1903 shift += 8; 1904 } 1905 if (shift != 0) /* 24 */ 1906 regw(sc, HOST_DATA0 + reg, latch); 1907 } 1908 1909 1910 static void 1911 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1912 int colour) 1913 { 1914 wait_for_fifo(sc, 11); 1915 regw(sc, DP_FRGD_CLR, colour); 1916 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1917 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1918 regw(sc, DP_MIX, MIX_SRC << 16); 1919 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1920 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1921 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1922 1923 regw(sc, SRC_Y_X, (x << 16) | y); 1924 regw(sc, SRC_WIDTH1, width); 1925 regw(sc, DST_Y_X, (x << 16) | y); 1926 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1927 } 1928 1929 static void 1930 mach64_clearscreen(struct mach64_softc *sc) 1931 { 1932 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1933 } 1934 1935 1936 #if 0 1937 static void 1938 mach64_showpal(struct mach64_softc *sc) 1939 { 1940 int i, x = 0; 1941 1942 for (i = 0; i < 16; i++) { 1943 mach64_rectfill(sc, x, 0, 64, 64, i); 1944 x += 64; 1945 } 1946 } 1947 #endif 1948 1949 /* 1950 * wsdisplay_accessops 1951 */ 1952 1953 static int 1954 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1955 struct lwp *l) 1956 { 1957 struct vcons_data *vd = v; 1958 struct mach64_softc *sc = vd->cookie; 1959 struct wsdisplay_fbinfo *wdf; 1960 struct vcons_screen *ms = vd->active; 1961 1962 switch (cmd) { 1963 case WSDISPLAYIO_GTYPE: 1964 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1965 return 0; 1966 1967 case WSDISPLAYIO_LINEBYTES: 1968 *(u_int *)data = sc->stride * sc->bits_per_pixel / 8; 1969 return 0; 1970 1971 case WSDISPLAYIO_GINFO: 1972 wdf = (void *)data; 1973 wdf->height = sc->virt_y; 1974 wdf->width = sc->virt_x; 1975 wdf->depth = sc->bits_per_pixel; 1976 wdf->cmsize = 256; 1977 return 0; 1978 1979 case WSDISPLAYIO_GETCMAP: 1980 return mach64_getcmap(sc, 1981 (struct wsdisplay_cmap *)data); 1982 1983 case WSDISPLAYIO_PUTCMAP: 1984 return mach64_putcmap(sc, 1985 (struct wsdisplay_cmap *)data); 1986 1987 /* PCI config read/write passthrough. */ 1988 case PCI_IOC_CFGREAD: 1989 case PCI_IOC_CFGWRITE: 1990 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1991 cmd, data, flag, l); 1992 1993 case WSDISPLAYIO_GET_BUSID: 1994 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1995 sc->sc_pcitag, data); 1996 1997 case WSDISPLAYIO_SMODE: { 1998 int new_mode = *(int*)data; 1999 if (new_mode != sc->sc_mode) { 2000 sc->sc_mode = new_mode; 2001 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 2002 && (ms != NULL)) 2003 { 2004 /* restore initial video mode */ 2005 mach64_init(sc); 2006 mach64_init_engine(sc); 2007 mach64_init_lut(sc); 2008 if (sc->sc_setmode) 2009 mach64_modeswitch(sc, sc->sc_my_mode); 2010 mach64_clearscreen(sc); 2011 glyphcache_wipe(&sc->sc_gc); 2012 vcons_redraw_screen(ms); 2013 } 2014 } 2015 } 2016 return 0; 2017 case WSDISPLAYIO_GET_EDID: { 2018 struct wsdisplayio_edid_info *d = data; 2019 return wsdisplayio_get_edid(sc->sc_dev, d); 2020 } 2021 2022 case WSDISPLAYIO_GET_FBINFO: { 2023 struct wsdisplayio_fbinfo *fbi = data; 2024 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 2025 } 2026 } 2027 return EPASSTHROUGH; 2028 } 2029 2030 static paddr_t 2031 mach64_mmap(void *v, void *vs, off_t offset, int prot) 2032 { 2033 struct vcons_data *vd = v; 2034 struct mach64_softc *sc = vd->cookie; 2035 paddr_t pa; 2036 2037 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 2038 /* 2039 *'regular' framebuffer mmap()ing 2040 */ 2041 if (offset < (sc->memsize * 1024)) { 2042 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, 2043 offset, prot, BUS_SPACE_MAP_LINEAR); 2044 return pa; 2045 } 2046 } else if (sc->sc_mode == WSDISPLAYIO_MODE_MAPPED) { 2047 /* 2048 * restrict all other mappings to processes with superuser 2049 * privileges 2050 */ 2051 if (kauth_authorize_machdep(kauth_cred_get(), 2052 KAUTH_MACHDEP_UNMANAGEDMEM, 2053 NULL, NULL, NULL, NULL) != 0) { 2054 return -1; 2055 } 2056 if ((offset >= sc->sc_aperbase) && 2057 (offset < (sc->sc_aperbase + sc->sc_apersize))) { 2058 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2059 BUS_SPACE_MAP_LINEAR); 2060 return pa; 2061 } 2062 2063 if ((offset >= sc->sc_regbase) && 2064 (offset < (sc->sc_regbase + sc->sc_regsize))) { 2065 pa = bus_space_mmap(sc->sc_regt, offset, 0, prot, 2066 BUS_SPACE_MAP_LINEAR); 2067 return pa; 2068 } 2069 2070 if ((offset >= sc->sc_rom.vb_base) && 2071 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 2072 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2073 BUS_SPACE_MAP_LINEAR); 2074 return pa; 2075 } 2076 2077 #ifdef PCI_MAGIC_IO_RANGE 2078 if ((offset >= PCI_MAGIC_IO_RANGE) && 2079 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 2080 return bus_space_mmap(sc->sc_iot, 2081 offset - PCI_MAGIC_IO_RANGE, 0, prot, 0); 2082 } 2083 #endif 2084 } 2085 return -1; 2086 } 2087 2088 #if 0 2089 static int 2090 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 2091 { 2092 2093 return 0; 2094 } 2095 #endif 2096 2097 void 2098 machfb_blank(struct mach64_softc *sc, int blank) 2099 { 2100 uint32_t reg; 2101 2102 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 2103 2104 switch (blank) 2105 { 2106 case 0: 2107 reg = regr(sc, CRTC_GEN_CNTL); 2108 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 2109 sc->sc_blanked = 0; 2110 break; 2111 case 1: 2112 reg = regr(sc, CRTC_GEN_CNTL); 2113 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 2114 sc->sc_blanked = 1; 2115 break; 2116 default: 2117 break; 2118 } 2119 } 2120
Indexes created Thu Oct 02 14:10:14 GMT 2025