machfb.c revision 1.105
1 /* $NetBSD: machfb.c,v 1.105 2021/06/21 03:19:21 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.105 2021/06/21 03:19:21 christos Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #include <dev/wscons/wsdisplayvar.h> 58 59 #include <dev/wscons/wsconsio.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/rasops/rasops.h> 62 #include <dev/pci/wsdisplay_pci.h> 63 64 #include <dev/wscons/wsdisplay_vconsvar.h> 65 #include <dev/wscons/wsdisplay_glyphcachevar.h> 66 67 #include "opt_wsemul.h" 68 #include "opt_machfb.h" 69 #include "opt_glyphcache.h" 70 71 #ifdef MACHFB_DEBUG 72 #define DPRINTF printf 73 #else 74 #define DPRINTF while (0) printf 75 #endif 76 77 #define MACH64_REG_SIZE 0x800 78 #define MACH64_REG_OFF 0x7ff800 79 80 #define NBARS 3 /* number of Mach64 PCI BARs */ 81 82 struct vga_bar { 83 bus_addr_t vb_base; 84 bus_size_t vb_size; 85 pcireg_t vb_type; 86 int vb_flags; 87 }; 88 89 struct mach64_softc { 90 device_t sc_dev; 91 pci_chipset_tag_t sc_pc; 92 pcitag_t sc_pcitag; 93 94 struct vga_bar sc_bars[NBARS]; 95 struct vga_bar sc_rom; 96 97 #define sc_aperbase sc_bars[0].vb_base 98 #define sc_apersize sc_bars[0].vb_size 99 100 #define sc_iobase sc_bars[1].vb_base 101 #define sc_iosize sc_bars[1].vb_size 102 103 #define sc_regbase sc_bars[2].vb_base 104 #define sc_regsize sc_bars[2].vb_size 105 106 bus_space_tag_t sc_regt; 107 bus_space_tag_t sc_memt; 108 bus_space_tag_t sc_iot; 109 bus_space_handle_t sc_regh; 110 bus_space_handle_t sc_memh; 111 #if 0 112 void *sc_aperture; /* mapped aperture vaddr */ 113 void *sc_registers; /* mapped registers vaddr */ 114 #endif 115 uint32_t sc_nbus, sc_ndev, sc_nfunc; 116 size_t memsize; 117 int memtype; 118 119 int sc_mode; 120 int sc_bg; 121 int sc_locked; 122 123 int has_dsp; 124 int bits_per_pixel; 125 int max_x; 126 int max_y; 127 int virt_x; 128 int virt_y; 129 int stride; /* in pixels */ 130 int color_depth; 131 132 int mem_freq; 133 int ramdac_freq; 134 int ref_freq; 135 int vclk_freq; 136 137 int ref_div; 138 int log2_vclk_post_div; 139 int vclk_post_div; 140 int vclk_fb_div; 141 int mclk_post_div; 142 int mclk_fb_div; 143 int sc_clock; /* which clock to use */ 144 int minref, m; 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 struct edid_info sc_ei; 150 int sc_setmode; 151 int sc_gen_cntl; 152 153 u_char sc_cmap_red[256]; 154 u_char sc_cmap_green[256]; 155 u_char sc_cmap_blue[256]; 156 int sc_dacw, sc_blanked, sc_console; 157 struct vcons_data vd; 158 struct wsdisplay_accessops sc_accessops; 159 glyphcache sc_gc; 160 }; 161 162 struct mach64_crtcregs { 163 uint32_t h_total_disp; 164 uint32_t h_sync_strt_wid; 165 uint32_t v_total_disp; 166 uint32_t v_sync_strt_wid; 167 uint32_t gen_cntl; 168 uint32_t clock_cntl; 169 uint32_t color_depth; 170 uint32_t dot_clock; 171 }; 172 173 static struct { 174 uint16_t chip_id; 175 uint32_t ramdac_freq; 176 } const mach64_info[] = { 177 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 178 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 179 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 189 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 190 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 193 #if 0 194 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 197 #endif 198 { PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI, 230000 }, 199 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 200 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 201 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 202 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 203 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 204 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 205 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 206 }; 207 208 static int mach64_chip_id, mach64_chip_rev; 209 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 210 211 static const char *mach64_gx_memtype_names[] = { 212 "DRAM", "VRAM", "VRAM", "DRAM", 213 "DRAM", "VRAM", "VRAM", "(unknown type)" 214 }; 215 216 static const char *mach64_memtype_names[] = { 217 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 218 "(unknown type)" 219 }; 220 221 extern const u_char rasops_cmap[768]; 222 223 static int mach64_match(device_t, cfdata_t, void *); 224 static void mach64_attach(device_t, device_t, void *); 225 226 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, 227 mach64_attach, NULL, NULL); 228 229 static void mach64_init(struct mach64_softc *); 230 static int mach64_get_memsize(struct mach64_softc *); 231 static int mach64_get_max_ramdac(struct mach64_softc *); 232 static int mach64_ref_freq(void); 233 234 #ifdef MACHFB_DEBUG 235 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 236 static void mach64_print_reg(struct mach64_softc *); 237 #endif 238 239 static int mach64_calc_crtcregs(struct mach64_softc *, 240 struct mach64_crtcregs *, 241 struct videomode *); 242 static void mach64_set_crtcregs(struct mach64_softc *, 243 struct mach64_crtcregs *); 244 245 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 246 static void mach64_set_dsp(struct mach64_softc *); 247 static void mach64_set_pll(struct mach64_softc *, int); 248 static void mach64_reset_engine(struct mach64_softc *); 249 static void mach64_init_engine(struct mach64_softc *); 250 #if 0 251 static void mach64_adjust_frame(struct mach64_softc *, int, int); 252 #endif 253 static void mach64_init_lut(struct mach64_softc *); 254 255 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 256 static int mach64_is_console(struct mach64_softc *); 257 258 static void mach64_cursor(void *, int, int, int); 259 #if 0 260 static int mach64_mapchar(void *, int, u_int *); 261 #endif 262 static void mach64_putchar_mono(void *, int, int, u_int, long); 263 static void mach64_putchar_aa8(void *, int, int, u_int, long); 264 static void mach64_copycols(void *, int, int, int, int); 265 static void mach64_erasecols(void *, int, int, int, long); 266 static void mach64_copyrows(void *, int, int, int); 267 static void mach64_eraserows(void *, int, int, long); 268 static void mach64_clearscreen(struct mach64_softc *); 269 270 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 271 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 272 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 273 uint8_t, uint8_t); 274 static void mach64_bitblt(void *, int, int, int, int, int, int, int); 275 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 276 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 277 uint32_t, uint32_t); 278 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 279 #if 0 280 static void mach64_showpal(struct mach64_softc *); 281 #endif 282 283 static void machfb_blank(struct mach64_softc *, int); 284 static int machfb_drm_print(void *, const char *); 285 286 static struct wsscreen_descr mach64_defaultscreen = { 287 "default", 288 80, 30, 289 NULL, 290 8, 16, 291 WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE 292 | WSSCREEN_RESIZE , 293 NULL 294 }; 295 296 static const struct wsscreen_descr *_mach64_scrlist[] = { 297 &mach64_defaultscreen, 298 }; 299 300 static struct wsscreen_list mach64_screenlist = { 301 __arraycount(_mach64_scrlist), 302 _mach64_scrlist 303 }; 304 305 static int mach64_ioctl(void *, void *, u_long, void *, int, 306 struct lwp *); 307 static paddr_t mach64_mmap(void *, void *, off_t, int); 308 309 static struct vcons_screen mach64_console_screen; 310 311 /* 312 * Inline functions for getting access to register aperture. 313 */ 314 315 static inline uint32_t 316 regr(struct mach64_softc *sc, uint32_t index) 317 { 318 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400); 319 } 320 321 static inline uint8_t 322 regrb(struct mach64_softc *sc, uint32_t index) 323 { 324 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400); 325 } 326 327 static inline void 328 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 329 { 330 bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 331 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 332 BUS_SPACE_BARRIER_WRITE); 333 } 334 335 static inline void 336 regws(struct mach64_softc *sc, uint32_t index, uint32_t data) 337 { 338 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 339 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4, 340 BUS_SPACE_BARRIER_WRITE); 341 } 342 343 static inline void 344 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 345 { 346 bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data); 347 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1, 348 BUS_SPACE_BARRIER_WRITE); 349 } 350 351 static inline void 352 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 353 { 354 uint32_t reg; 355 356 reg = regr(sc, CLOCK_CNTL); 357 reg |= PLL_WR_EN; 358 regw(sc, CLOCK_CNTL, reg); 359 reg &= ~(PLL_ADDR | PLL_DATA); 360 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 361 reg |= data << PLL_DATA_SHIFT; 362 reg |= CLOCK_STROBE; 363 regw(sc, CLOCK_CNTL, reg); 364 reg &= ~PLL_WR_EN; 365 regw(sc, CLOCK_CNTL, reg); 366 } 367 368 static inline uint8_t 369 regrb_pll(struct mach64_softc *sc, uint32_t index) 370 { 371 372 regwb(sc, CLOCK_CNTL + 1, index << 2); 373 return regrb(sc, CLOCK_CNTL + 2); 374 } 375 376 static inline void 377 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 378 { 379 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 380 continue; 381 } 382 383 static inline void 384 wait_for_idle(struct mach64_softc *sc) 385 { 386 wait_for_fifo(sc, 16); 387 while ((regr(sc, GUI_STAT) & 1) != 0) 388 continue; 389 } 390 391 static int 392 mach64_match(device_t parent, cfdata_t match, void *aux) 393 { 394 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 395 int i; 396 397 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 398 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 399 return 0; 400 401 for (i = 0; i < __arraycount(mach64_info); i++) 402 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 403 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 404 mach64_chip_rev = PCI_REVISION(pa->pa_class); 405 return 100; 406 } 407 408 return 0; 409 } 410 411 static void 412 mach64_attach(device_t parent, device_t self, void *aux) 413 { 414 struct mach64_softc *sc = device_private(self); 415 struct pci_attach_args *pa = aux; 416 struct rasops_info *ri; 417 const char *mptr = NULL; 418 prop_data_t edid_data; 419 const struct videomode *mode = NULL; 420 int bar, id, expected_id; 421 int is_gx; 422 const char **memtype_names; 423 struct wsemuldisplaydev_attach_args aa; 424 long defattr; 425 int width = 1024, height = 768; 426 pcireg_t screg; 427 uint32_t reg; 428 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 429 int use_mmio = FALSE; 430 431 sc->sc_dev = self; 432 sc->sc_pc = pa->pa_pc; 433 sc->sc_pcitag = pa->pa_tag; 434 sc->sc_dacw = -1; 435 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 436 sc->sc_nbus = pa->pa_bus; 437 sc->sc_ndev = pa->pa_device; 438 sc->sc_nfunc = pa->pa_function; 439 sc->sc_locked = 0; 440 sc->sc_iot = pa->pa_iot; 441 sc->sc_accessops.ioctl = mach64_ioctl; 442 sc->sc_accessops.mmap = mach64_mmap; 443 sc->sc_setmode = 0; 444 445 pci_aprint_devinfo(pa, "Graphics processor"); 446 #ifdef MACHFB_DEBUG 447 printf(prop_dictionary_externalize(device_properties(self))); 448 #endif 449 450 /* enable memory access */ 451 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 452 if ((screg & enables) != enables) { 453 screg |= enables; 454 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 455 PCI_COMMAND_STATUS_REG, screg); 456 } 457 for (bar = 0; bar < NBARS; bar++) { 458 reg = PCI_MAPREG_START + (bar * 4); 459 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 460 sc->sc_pcitag, reg); 461 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 462 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 463 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 464 } 465 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 466 (uint32_t)sc->sc_apersize); 467 468 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 469 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 470 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 471 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 472 sc->sc_memt = pa->pa_memt; 473 474 /* use MMIO register aperture if available */ 475 if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) { 476 if (pci_mapreg_map(pa, MACH64_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 477 0, &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase, 478 &sc->sc_regsize) == 0) { 479 480 /* 481 * the MMIO aperture maps both 1KB register blocks, but 482 * all register offsets are relative to the 2nd one so 483 * for now fix this up in MACH64_REG_OFF and the access 484 * functions 485 */ 486 aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n"); 487 use_mmio = TRUE; 488 } 489 } 490 if (!use_mmio) { 491 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, 492 sc->sc_apersize, BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 493 panic("%s: failed to map aperture", 494 device_xname(sc->sc_dev)); 495 } 496 497 sc->sc_regt = sc->sc_memt; 498 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 499 MACH64_REG_SIZE, &sc->sc_regh); 500 } 501 502 mach64_init(sc); 503 504 aprint_normal_dev(sc->sc_dev, 505 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 506 (u_int)(sc->sc_apersize / (1024 * 1024)), 507 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 508 (u_int)sc->sc_regbase); 509 510 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 511 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 512 #ifdef MACHFB_DEBUG 513 mach64_get_mode(sc, NULL); 514 mach64_print_reg(sc); 515 #endif 516 517 prop_dictionary_get_uint32(device_properties(self), "width", &width); 518 prop_dictionary_get_uint32(device_properties(self), "height", &height); 519 520 default_mode.hdisplay = width; 521 default_mode.vdisplay = height; 522 523 prop_dictionary_get_string(device_properties(sc->sc_dev), 524 "videomode", &mptr); 525 526 memset(&sc->sc_ei, 0, sizeof(sc->sc_ei)); 527 if (mptr == NULL && 528 (edid_data = prop_dictionary_get(device_properties(self), "EDID")) 529 != NULL) { 530 531 sc->sc_edid_size = uimin(1024, prop_data_size(edid_data)); 532 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 533 memcpy(sc->sc_edid_data, prop_data_value(edid_data), 534 sc->sc_edid_size); 535 536 edid_parse(sc->sc_edid_data, &sc->sc_ei); 537 538 #ifdef MACHFB_DEBUG 539 edid_print(&sc->sc_ei); 540 #endif 541 } 542 is_gx = 0; 543 switch(mach64_chip_id) { 544 case PCI_PRODUCT_ATI_MACH64_GX: 545 case PCI_PRODUCT_ATI_MACH64_CX: 546 is_gx = 1; 547 /* FALLTHROUGH */ 548 case PCI_PRODUCT_ATI_MACH64_CT: 549 sc->has_dsp = 0; 550 break; 551 case PCI_PRODUCT_ATI_MACH64_VT: 552 case PCI_PRODUCT_ATI_RAGE_II: 553 if((mach64_chip_rev & 0x07) == 0) { 554 sc->has_dsp = 0; 555 break; 556 } 557 /* FALLTHROUGH */ 558 default: 559 sc->has_dsp = 1; 560 } 561 562 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 563 564 sc->memsize = mach64_get_memsize(sc); 565 566 if(is_gx) 567 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 568 else 569 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 570 571 sc->ref_freq = mach64_ref_freq(); 572 573 reg = regr(sc, CLOCK_CNTL); 574 sc->sc_clock = reg & 3; 575 DPRINTF("using clock %d\n", sc->sc_clock); 576 577 DPRINTF("ref_freq: %d\n", sc->ref_freq); 578 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 579 DPRINTF("ref_div: %d\n", sc->ref_div); 580 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 581 DPRINTF("mclk_fb_div: %d\n", sc->mclk_fb_div); 582 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 583 (sc->ref_div * 2); 584 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 585 (sc->mem_freq * sc->ref_div); 586 sc->ramdac_freq = mach64_get_max_ramdac(sc); 587 { 588 sc->minref = sc->ramdac_freq / 510; 589 sc->m = sc->ref_freq / sc->minref; 590 DPRINTF("minref: %d m: %d\n", sc->minref, sc->m); 591 } 592 aprint_normal_dev(sc->sc_dev, 593 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 594 (u_long)sc->memsize, 595 memtype_names[sc->memtype], 596 sc->mem_freq / 1000, sc->mem_freq % 1000, 597 sc->ramdac_freq / 1000); 598 599 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 600 switch(mach64_chip_id) { 601 case PCI_PRODUCT_ATI_MACH64_GX: 602 expected_id = 0x00d7; 603 break; 604 case PCI_PRODUCT_ATI_MACH64_CX: 605 expected_id = 0x0057; 606 break; 607 default: 608 /* Most chip IDs match their PCI product ID. */ 609 expected_id = mach64_chip_id; 610 } 611 612 if (id != expected_id) { 613 aprint_error_dev(sc->sc_dev, 614 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 615 return; 616 } 617 618 sc->sc_console = mach64_is_console(sc); 619 sc->sc_gen_cntl = regr(sc, CRTC_GEN_CNTL); 620 aprint_debug("gen_cntl: %08x\n", sc->sc_gen_cntl); 621 sc->sc_gen_cntl &= CRTC_CSYNC_EN; 622 aprint_normal_dev(sc->sc_dev, "found composite sync %s\n", 623 sc->sc_gen_cntl ? "enabled" : "disabled"); 624 625 #define MODE_IS_VALID(m) ((sc->ramdac_freq >= (m)->dot_clock) && \ 626 ((m)->hdisplay <= 1280)) 627 628 /* no mode setting support on ancient chips with external clocks */ 629 sc->sc_setmode = 0; 630 if (!is_gx) { 631 /* 632 * Now pick a mode. 633 */ 634 if ((sc->sc_ei.edid_preferred_mode != NULL)) { 635 struct videomode *m = sc->sc_ei.edid_preferred_mode; 636 if (MODE_IS_VALID(m)) { 637 memcpy(&default_mode, m, 638 sizeof(struct videomode)); 639 sc->sc_setmode = 1; 640 } else { 641 aprint_normal_dev(sc->sc_dev, 642 "unable to use EDID preferred mode " 643 "(%d x %d)\n", m->hdisplay, m->vdisplay); 644 } 645 } 646 /* 647 * if we can't use the preferred mode go look for the 648 * best one we can support 649 */ 650 if (sc->sc_setmode == 0) { 651 struct videomode *m = sc->sc_ei.edid_modes; 652 653 mode = NULL; 654 sort_modes(sc->sc_ei.edid_modes, 655 &sc->sc_ei.edid_preferred_mode, 656 sc->sc_ei.edid_nmodes); 657 for (int n = 0; n < sc->sc_ei.edid_nmodes; n++) 658 if (MODE_IS_VALID(&m[n])) { 659 mode = &m[n]; 660 break; 661 } 662 if (mode != NULL) { 663 memcpy(&default_mode, mode, 664 sizeof(struct videomode)); 665 sc->sc_setmode = 1; 666 } 667 } 668 } 669 670 /* make sure my_mode points at something sensible if the above fails */ 671 if (default_mode.dot_clock == 0) { 672 sc->sc_setmode = 0; 673 mode = pick_mode_by_ref(width, height, 60); 674 if (mode != NULL) { 675 memcpy(&default_mode, mode, sizeof(default_mode)); 676 } else if ((width > 0) && (height > 0)) { 677 default_mode.hdisplay = width; 678 default_mode.vdisplay = height; 679 } else { 680 /* 681 * if we end up here we're probably dealing with 682 * uninitialized hardware - try to set 1024x768@60 and 683 * hope for the best... 684 */ 685 mode = pick_mode_by_ref(1024, 768, 60); 686 if (mode == NULL) return; 687 memcpy(&default_mode, mode, sizeof(default_mode)); 688 if (!is_gx) sc->sc_setmode = 1; 689 } 690 } 691 692 sc->sc_my_mode = &default_mode; 693 694 if ((width == sc->sc_my_mode->hdisplay) && 695 (height == sc->sc_my_mode->vdisplay)) 696 sc->sc_setmode = 0; 697 698 sc->bits_per_pixel = 8; 699 sc->virt_x = sc->sc_my_mode->hdisplay; 700 sc->virt_y = sc->sc_my_mode->vdisplay; 701 sc->stride = (sc->virt_x + 7) & ~7; /* hw needs multiples of 8 */ 702 sc->max_x = sc->virt_x - 1; 703 sc->max_y = (sc->memsize * 1024) / 704 (sc->stride * (sc->bits_per_pixel / 8)) - 1; 705 706 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 707 708 mach64_init_engine(sc); 709 710 if (sc->sc_setmode) 711 mach64_modeswitch(sc, sc->sc_my_mode); 712 713 aprint_normal_dev(sc->sc_dev, 714 "initial resolution %dx%d at %d bpp\n", 715 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 716 sc->bits_per_pixel); 717 718 wsfont_init(); 719 720 #ifdef GLYPHCACHE_DEBUG 721 /* shrink the screen so we can see part of the glyph cache */ 722 sc->sc_my_mode->vdisplay -= 200; 723 #endif 724 725 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 726 sc->vd.init_screen = mach64_init_screen; 727 sc->vd.show_screen_cookie = &sc->sc_gc; 728 sc->vd.show_screen_cb = glyphcache_adapt; 729 730 sc->sc_gc.gc_bitblt = mach64_bitblt; 731 sc->sc_gc.gc_blitcookie = sc; 732 sc->sc_gc.gc_rop = MIX_SRC; 733 734 ri = &mach64_console_screen.scr_ri; 735 if (sc->sc_console) { 736 737 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 738 &defattr); 739 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 740 741 mach64_defaultscreen.textops = &ri->ri_ops; 742 mach64_defaultscreen.capabilities = ri->ri_caps; 743 mach64_defaultscreen.nrows = ri->ri_rows; 744 mach64_defaultscreen.ncols = ri->ri_cols; 745 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 746 ((sc->memsize * 1024) / sc->stride) - 747 sc->sc_my_mode->vdisplay - 5, 748 sc->stride, 749 ri->ri_font->fontwidth, 750 ri->ri_font->fontheight, 751 defattr); 752 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 753 } else { 754 /* 755 * since we're not the console we can postpone the rest 756 * until someone actually allocates a screen for us 757 */ 758 if (mach64_console_screen.scr_ri.ri_rows == 0) { 759 /* do some minimal setup to avoid weirdnesses later */ 760 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 761 &defattr); 762 } else 763 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 764 765 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 766 ((sc->memsize * 1024) / sc->stride) - 767 sc->sc_my_mode->vdisplay - 5, 768 sc->stride, 769 ri->ri_font->fontwidth, 770 ri->ri_font->fontheight, 771 defattr); 772 } 773 774 sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG]; 775 mach64_clearscreen(sc); 776 mach64_init_lut(sc); 777 778 if (sc->sc_console) 779 vcons_replay_msgbuf(&mach64_console_screen); 780 781 machfb_blank(sc, 0); /* unblank the screen */ 782 783 aa.console = sc->sc_console; 784 aa.scrdata = &mach64_screenlist; 785 aa.accessops = &sc->sc_accessops; 786 aa.accesscookie = &sc->vd; 787 788 config_found(self, &aa, wsemuldisplaydevprint, 789 CFARG_IATTR, "wsemuldisplaydev", 790 CFARG_EOL); 791 #if 0 792 /* XXX 793 * turns out some firmware doesn't turn these back on when needed 794 * so we need to turn them off only when mapping vram in 795 * WSDISPLAYIO_MODE_DUMB would overlap ( unlikely but far from 796 * impossible ) 797 */ 798 if (use_mmio) { 799 /* 800 * Now that we took over, turn off the aperture registers if we 801 * don't use them. Can't do this earlier since on some hardware 802 * we use firmware calls as early console output which may in 803 * turn try to access these registers. 804 */ 805 reg = regr(sc, BUS_CNTL); 806 aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg); 807 reg |= BUS_APER_REG_DIS; 808 regw(sc, BUS_CNTL, reg); 809 } 810 #endif 811 config_found(self, aux, machfb_drm_print, 812 CFARG_IATTR, "drm", 813 CFARG_EOL); 814 } 815 816 static int 817 machfb_drm_print(void *aux, const char *pnp) 818 { 819 if (pnp) 820 aprint_normal("direct rendering for %s", pnp); 821 return (UNSUPP); 822 } 823 824 static void 825 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 826 long *defattr) 827 { 828 struct mach64_softc *sc = cookie; 829 struct rasops_info *ri = &scr->scr_ri; 830 831 ri->ri_depth = sc->bits_per_pixel; 832 ri->ri_width = sc->sc_my_mode->hdisplay; 833 ri->ri_height = sc->sc_my_mode->vdisplay; 834 ri->ri_stride = sc->stride; 835 ri->ri_flg = RI_CENTER | RI_FULLCLEAR; 836 if (ri->ri_depth == 8) 837 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA | 838 RI_PREFER_ALPHA; 839 840 #ifdef VCONS_DRAW_INTR 841 scr->scr_flags |= VCONS_DONT_READ; 842 #endif 843 scr->scr_flags |= VCONS_LOADFONT; 844 845 rasops_init(ri, 0, 0); 846 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE | 847 WSSCREEN_RESIZE; 848 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 849 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 850 851 /* enable acceleration */ 852 ri->ri_hw = scr; 853 ri->ri_ops.copyrows = mach64_copyrows; 854 ri->ri_ops.copycols = mach64_copycols; 855 ri->ri_ops.eraserows = mach64_eraserows; 856 ri->ri_ops.erasecols = mach64_erasecols; 857 ri->ri_ops.cursor = mach64_cursor; 858 if (FONT_IS_ALPHA(ri->ri_font)) { 859 ri->ri_ops.putchar = mach64_putchar_aa8; 860 } else 861 ri->ri_ops.putchar = mach64_putchar_mono; 862 } 863 864 static void 865 mach64_init(struct mach64_softc *sc) 866 { 867 sc->sc_blanked = 0; 868 } 869 870 static int 871 mach64_get_memsize(struct mach64_softc *sc) 872 { 873 int tmp, memsize; 874 int mem_tab[] = { 875 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 876 }; 877 tmp = regr(sc, MEM_CNTL); 878 #ifdef DIAGNOSTIC 879 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 880 #endif 881 if (sc->has_dsp) { 882 tmp &= 0x0000000f; 883 if (tmp < 8) 884 memsize = (tmp + 1) * 512; 885 else if (tmp < 12) 886 memsize = (tmp - 3) * 1024; 887 else 888 memsize = (tmp - 7) * 2048; 889 } else { 890 memsize = mem_tab[tmp & 0x07]; 891 } 892 893 return memsize; 894 } 895 896 static int 897 mach64_get_max_ramdac(struct mach64_softc *sc) 898 { 899 int i; 900 901 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 902 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 903 (mach64_chip_rev & 0x07)) 904 return 170000; 905 906 for (i = 0; i < __arraycount(mach64_info); i++) 907 if (mach64_chip_id == mach64_info[i].chip_id) 908 return mach64_info[i].ramdac_freq; 909 910 if (sc->bits_per_pixel == 8) 911 return 135000; 912 else 913 return 80000; 914 } 915 916 static int 917 mach64_ref_freq(void) 918 { 919 /* 920 * There doesn't seem to be any way to calculate the reference 921 * frequency from known values 922 */ 923 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 924 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 925 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI))) 926 return 29498; 927 else 928 return 14318; 929 } 930 931 #ifdef MACHFB_DEBUG 932 static void 933 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 934 { 935 int htotal, hdisplay, hsync_start, hsync_end; 936 int vtotal, vdisplay, vsync_start, vsync_end; 937 int clk_ctl, clock; 938 int ref_freq, ref_div, vclk_post_div, vclk_fb_div; 939 int nhsync, nvsync; 940 int post_div, dot_clock, vrefresh, vrefresh2; 941 942 hdisplay = regr(sc, CRTC_H_TOTAL_DISP); 943 hsync_end = regr(sc, CRTC_H_SYNC_STRT_WID); 944 vdisplay = regr(sc, CRTC_V_TOTAL_DISP); 945 vsync_end = regr(sc, CRTC_V_SYNC_STRT_WID); 946 clk_ctl = regr(sc, CLOCK_CNTL); 947 clock = clk_ctl & 3; 948 ref_div = regrb_pll(sc, PLL_REF_DIV); 949 vclk_post_div = regrb_pll(sc, VCLK_POST_DIV); 950 vclk_fb_div = regrb_pll(sc, VCLK0_FB_DIV + clock); 951 ref_freq = mach64_ref_freq(); 952 953 htotal = ((hdisplay & 0x01ff) + 1) << 3; 954 hdisplay = (((hdisplay & 0x1ff0000) >> 16) + 1) << 3; 955 if (hsync_end & CRTC_HSYNC_NEG) 956 nhsync = 1; 957 else 958 nhsync = 0; 959 hsync_start = (((hsync_end & 0xff) + 1) << 3) + 960 ((hsync_end & 0x700) >> 8); 961 hsync_end = (((hsync_end & 0x1f0000) >> 16) << 3) + hsync_start; 962 963 vtotal = (vdisplay & 0x07ff) + 1; 964 vdisplay = ((vdisplay & 0x7ff0000) >> 16) + 1; 965 if (vsync_end & CRTC_VSYNC_NEG) 966 nvsync = 1; 967 else 968 nvsync = 0; 969 vsync_start = (vsync_end & 0x07ff) + 1; 970 vsync_end = ((vsync_end & 0x1f0000) >> 16) + vsync_start; 971 972 switch ((vclk_post_div >> (clock * 2)) & 3) { 973 case 3: 974 post_div = 8; 975 break; 976 case 2: 977 post_div = 4; 978 break; 979 case 1: 980 post_div = 2; 981 break; 982 default: 983 post_div = 1; 984 break; 985 } 986 dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div); 987 vrefresh = (dot_clock * 1000) / (htotal * vtotal); 988 vrefresh2 = ((dot_clock * 1000) - (vrefresh * htotal * vtotal)) * 100 / 989 (htotal * vtotal); 990 991 aprint_normal_dev(sc->sc_dev, "Video mode:\n"); 992 aprint_normal("\t%d" "x%d @ %d.%02dHz " 993 "(%d %d %d %d %d %d %d %cH %cV)\n", 994 hdisplay, vdisplay, vrefresh, vrefresh2, dot_clock, 995 hsync_start, hsync_end, htotal, vsync_start, vsync_end, vtotal, 996 nhsync == 1 ? '-' : '+', nvsync == 1 ? '-' : '+'); 997 998 if (mode != NULL) { 999 mode->dot_clock = dot_clock; 1000 mode->htotal = htotal; 1001 mode->hdisplay = hdisplay; 1002 mode->hsync_start = hsync_start; 1003 mode->hsync_end = hsync_end; 1004 mode->vtotal = vtotal; 1005 mode->vdisplay = vdisplay; 1006 mode->vsync_start = vsync_start; 1007 mode->vsync_end = vsync_end; 1008 mode->flags = 0; 1009 if (nhsync) 1010 mode->flags |= VID_NHSYNC; 1011 if (nvsync) 1012 mode->flags |= VID_NVSYNC; 1013 } 1014 } 1015 1016 static void 1017 mach64_print_reg(struct mach64_softc *sc) 1018 { 1019 struct reglist { 1020 int offset; 1021 const char *name; 1022 }; 1023 static const struct reglist reglist_tab[] = { 1024 { 0x0000, "CRTC_H_TOTAL_DISP" }, 1025 { 0x0004, "CRTC_H_SYNC_STRT_WID" }, 1026 { 0x0008, "CRTC_V_TOTAL_DISP" }, 1027 { 0x000C, "CRTC_V_SYNC_STRT_WID" }, 1028 { 0x0010, "CRTC_VLINE_CRNT_VLINE" }, 1029 { 0x0014, "CRTC_OFF_PITCH" }, 1030 { 0x001C, "CRTC_GEN_CNTL" }, 1031 { 0x0090, "CLOCK_CNTL" }, 1032 { 0, NULL } 1033 }; 1034 static const struct reglist plllist_tab[] = { 1035 { 0x02, "PLL_REF_DIV" }, 1036 { 0x03, "PLL_GEN_CNTL" }, 1037 { 0x04, "MCLK_FB_DIV" }, 1038 { 0x05, "PLL_VCLK_CNTL" }, 1039 { 0x06, "VCLK_POST_DIV" }, 1040 { 0x07, "VCLK0_FB_DIV" }, 1041 { 0x08, "VCLK1_FB_DIV" }, 1042 { 0x09, "VCLK2_FB_DIV" }, 1043 { 0x0A, "VCLK3_FB_DIV" }, 1044 { 0x0B, "PLL_XCLK_CNTL" }, 1045 { 0x10, "LVDSPLL_CNTL0" }, 1046 { 0x11, "LVDSPLL_CNTL0" }, 1047 { 0x19, "EXT_VPLL_CNTL" }, 1048 { 0x1A, "EXT_VPLL_REF_DIV" }, 1049 { 0x1B, "EXT_VPLL_FB_DIV" }, 1050 { 0x1C, "EXT_VPLL_MSB" }, 1051 { 0, NULL } 1052 }; 1053 const struct reglist *r; 1054 1055 aprint_normal("CRTC registers\n"); 1056 for (r = reglist_tab; r->name != NULL; r++) 1057 aprint_normal("0x%04x 0x%08x %s\n", r->offset, 1058 regr(sc, r->offset), r->name); 1059 aprint_normal("PLL registers\n"); 1060 for (r = plllist_tab; r->name != NULL; r++) 1061 aprint_normal("0x%02x 0x%02x %s\n", r->offset, 1062 regrb_pll(sc, r->offset), r->name); 1063 } 1064 #endif 1065 1066 static int 1067 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 1068 struct videomode *mode) 1069 { 1070 1071 if (mode->dot_clock > sc->ramdac_freq) 1072 /* Clock too high. */ 1073 return 1; 1074 1075 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 1076 ((mode->htotal >> 3) - 1); 1077 crtc->h_sync_strt_wid = 1078 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 1079 ((mode->hsync_start >> 3) - 1) | ((mode->hsync_start & 7) << 8); 1080 1081 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 1082 (mode->vtotal - 1); 1083 crtc->v_sync_strt_wid = 1084 ((mode->vsync_end - mode->vsync_start) << 16) | 1085 (mode->vsync_start - 1); 1086 1087 if (mode->flags & VID_NVSYNC) 1088 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 1089 1090 switch (sc->bits_per_pixel) { 1091 case 8: 1092 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 1093 break; 1094 case 16: 1095 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 1096 break; 1097 case 32: 1098 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 1099 break; 1100 } 1101 1102 crtc->gen_cntl = 0; 1103 if (mode->flags & VID_INTERLACE) 1104 crtc->gen_cntl |= CRTC_INTERLACE_EN; 1105 1106 if (mode->flags & VID_CSYNC) 1107 crtc->gen_cntl |= CRTC_CSYNC_EN; 1108 1109 crtc->dot_clock = mode->dot_clock; 1110 1111 return 0; 1112 } 1113 1114 static void 1115 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1116 { 1117 1118 mach64_set_pll(sc, crtc->dot_clock); 1119 1120 if (sc->has_dsp) 1121 mach64_set_dsp(sc); 1122 1123 DPRINTF("\th total: 0x%08x h sync: 0x%08x\n", 1124 crtc->h_total_disp, crtc->h_sync_strt_wid); 1125 DPRINTF("\tv total: 0x%08x v sync: 0x%08x\n", 1126 crtc->v_total_disp, crtc->v_sync_strt_wid); 1127 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1128 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1129 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1130 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1131 1132 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1133 1134 regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22); 1135 1136 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1137 sc->sc_gen_cntl | CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1138 } 1139 1140 static int 1141 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1142 { 1143 struct mach64_crtcregs crtc; 1144 1145 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1146 1147 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1148 return 1; 1149 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1150 if (crtc.dot_clock == 0) { 1151 aprint_error("%s: preposterous dot clock (%d)\n", 1152 device_xname(sc->sc_dev), crtc.dot_clock); 1153 return 1; 1154 } 1155 mach64_set_crtcregs(sc, &crtc); 1156 return 0; 1157 } 1158 1159 static void 1160 mach64_reset_engine(struct mach64_softc *sc) 1161 { 1162 1163 /* Reset engine.*/ 1164 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1165 1166 /* Enable engine. */ 1167 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1168 1169 /* Ensure engine is not locked up by clearing any FIFO or 1170 host errors. */ 1171 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1172 BUS_FIFO_ERR_ACK); 1173 } 1174 1175 static void 1176 mach64_init_engine(struct mach64_softc *sc) 1177 { 1178 uint32_t pitch_value; 1179 1180 pitch_value = sc->stride; 1181 1182 if (sc->bits_per_pixel == 24) 1183 pitch_value *= 3; 1184 1185 mach64_reset_engine(sc); 1186 1187 wait_for_fifo(sc, 14); 1188 1189 regw(sc, CONTEXT_MASK, 0xffffffff); 1190 1191 regw(sc, DST_OFF_PITCH, (pitch_value >> 3) << 22); 1192 1193 /* make sure the visible area starts where we're going to draw */ 1194 regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22); 1195 1196 regw(sc, DST_Y_X, 0); 1197 regw(sc, DST_HEIGHT, 0); 1198 regw(sc, DST_BRES_ERR, 0); 1199 regw(sc, DST_BRES_INC, 0); 1200 regw(sc, DST_BRES_DEC, 0); 1201 1202 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1203 DST_Y_TOP_TO_BOTTOM); 1204 1205 regw(sc, SRC_OFF_PITCH, (pitch_value >> 3) << 22); 1206 1207 regw(sc, SRC_Y_X, 0); 1208 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1209 regw(sc, SRC_Y_X_START, 0); 1210 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1211 1212 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1213 1214 wait_for_fifo(sc, 13); 1215 regw(sc, HOST_CNTL, 0); 1216 1217 regw(sc, PAT_REG0, 0); 1218 regw(sc, PAT_REG1, 0); 1219 regw(sc, PAT_CNTL, 0); 1220 1221 regw(sc, SC_LEFT, 0); 1222 regw(sc, SC_TOP, 0); 1223 regw(sc, SC_BOTTOM, 0x3fff); 1224 regw(sc, SC_RIGHT, pitch_value - 1); 1225 1226 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1227 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1228 regw(sc, DP_WRITE_MASK, 0xffffffff); 1229 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1230 1231 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1232 1233 wait_for_fifo(sc, 3); 1234 regw(sc, CLR_CMP_CLR, 0); 1235 regw(sc, CLR_CMP_MASK, 0xffffffff); 1236 regw(sc, CLR_CMP_CNTL, 0); 1237 1238 wait_for_fifo(sc, 3); 1239 switch (sc->bits_per_pixel) { 1240 case 8: 1241 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1242 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1243 /* We want 8 bit per channel */ 1244 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1245 break; 1246 case 32: 1247 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1248 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1249 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1250 break; 1251 } 1252 regw(sc, DP_WRITE_MASK, 0xff); 1253 1254 wait_for_fifo(sc, 5); 1255 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1256 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1257 1258 wait_for_idle(sc); 1259 } 1260 1261 #if 0 1262 static void 1263 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1264 { 1265 int offset; 1266 1267 offset = ((x + y * sc->stride) * (sc->bits_per_pixel >> 3)) >> 3; 1268 1269 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1270 offset); 1271 } 1272 #endif 1273 1274 static void 1275 mach64_set_dsp(struct mach64_softc *sc) 1276 { 1277 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1278 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1279 uint32_t xclks_per_qw, xclks_per_qw_m, y; 1280 uint32_t fifo_off, fifo_on; 1281 1282 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1283 1284 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1285 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1286 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1287 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1288 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1289 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1290 dsp_loop_latency = 0; 1291 fifo_depth = 24; 1292 } else { 1293 dsp_loop_latency = 2; 1294 fifo_depth = 32; 1295 } 1296 1297 dsp_precision = 0; 1298 1299 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1300 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1301 1302 xclks_per_qw_m = (sc->mem_freq * 64 << 4) / 1303 (sc->vclk_freq * sc->bits_per_pixel); 1304 1305 DPRINTF("xclks_per_qw %d %d\n", xclks_per_qw >> 7, xclks_per_qw_m); 1306 DPRINTF("mem %dkHz v %dkHz\n", sc->mem_freq, sc->vclk_freq); 1307 1308 y = (xclks_per_qw * fifo_depth) >> 11; 1309 1310 while (y) { 1311 y >>= 1; 1312 dsp_precision++; 1313 } 1314 dsp_precision -= 5; 1315 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1316 1317 switch (sc->memtype) { 1318 case DRAM: 1319 case EDO_DRAM: 1320 case PSEUDO_EDO: 1321 if (sc->memsize > 1024) { 1322 page_size = 9; 1323 dsp_loop_latency += 6; 1324 } else { 1325 page_size = 10; 1326 if (sc->memtype == DRAM) 1327 dsp_loop_latency += 8; 1328 else 1329 dsp_loop_latency += 7; 1330 } 1331 break; 1332 case SDRAM: 1333 if (sc->memsize > 1024) { 1334 page_size = 8; 1335 dsp_loop_latency += 8; 1336 } else { 1337 page_size = 10; 1338 dsp_loop_latency += 9; 1339 } 1340 break; 1341 case SGRAM: 1342 page_size = 8; 1343 dsp_loop_latency = 8; 1344 break; 1345 default: 1346 page_size = 10; 1347 dsp_loop_latency += 9; 1348 break; 1349 } 1350 1351 if (xclks_per_qw >= (page_size << 11)) 1352 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1353 else 1354 fifo_on = (3 * page_size + 2) << 6; 1355 1356 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1357 dsp_on = fifo_on >> dsp_precision; 1358 dsp_off = fifo_off >> dsp_precision; 1359 1360 DPRINTF("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1361 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1362 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1363 "mclk_post_div = %d, vclk_post_div = %d\n", 1364 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1365 sc->mclk_fb_div, sc->vclk_fb_div, 1366 sc->mclk_post_div, sc->vclk_post_div); 1367 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1368 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1369 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1370 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1371 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1372 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1373 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1374 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1375 } 1376 1377 static void 1378 mach64_set_pll(struct mach64_softc *sc, int clock) 1379 { 1380 uint32_t q, clockreg; 1381 int clockshift = sc->sc_clock << 1; 1382 uint8_t reg, vclk_ctl; 1383 1384 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1385 #ifdef MACHFB_DEBUG 1386 printf("q = %d\n", q); 1387 #endif 1388 if (q > 25500) { 1389 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1390 q = 25500; 1391 sc->vclk_post_div = 1; 1392 sc->log2_vclk_post_div = 0; 1393 } else if (q > 12750) { 1394 sc->vclk_post_div = 1; 1395 sc->log2_vclk_post_div = 0; 1396 } else if (q > 6350) { 1397 sc->vclk_post_div = 2; 1398 sc->log2_vclk_post_div = 1; 1399 } else if (q > 3150) { 1400 sc->vclk_post_div = 4; 1401 sc->log2_vclk_post_div = 2; 1402 } else if (q >= 1600) { 1403 sc->vclk_post_div = 8; 1404 sc->log2_vclk_post_div = 3; 1405 } else { 1406 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1407 sc->vclk_post_div = 8; 1408 sc->log2_vclk_post_div = 3; 1409 } 1410 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1411 DPRINTF("post_div: %d log2_post_div: %d mclk_div: %d\n", 1412 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1413 1414 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1415 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1416 vclk_ctl |= PLL_VCLK_RESET; 1417 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1418 1419 DPRINTF("target: %d output: %d\n", clock, 1420 (2 * sc->ref_freq * sc->vclk_fb_div) / 1421 (sc->ref_div * sc->vclk_post_div)); 1422 1423 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1424 reg = regrb_pll(sc, VCLK_POST_DIV); 1425 reg &= ~(3 << clockshift); 1426 reg |= (sc->log2_vclk_post_div << clockshift); 1427 regwb_pll(sc, VCLK_POST_DIV, reg); 1428 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1429 1430 vclk_ctl &= ~PLL_VCLK_RESET; 1431 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1432 1433 clockreg = regr(sc, CLOCK_CNTL); 1434 clockreg &= ~CLOCK_SEL; 1435 clockreg |= sc->sc_clock | CLOCK_STROBE; 1436 regw(sc, CLOCK_CNTL, clockreg); 1437 sc->vclk_freq = clock; 1438 } 1439 1440 static void 1441 mach64_init_lut(struct mach64_softc *sc) 1442 { 1443 uint8_t cmap[768]; 1444 int i, idx; 1445 1446 rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap)); 1447 idx = 0; 1448 for (i = 0; i < 256; i++) { 1449 mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1], 1450 cmap[idx + 2]); 1451 idx += 3; 1452 } 1453 } 1454 1455 static int 1456 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1457 uint8_t b) 1458 { 1459 sc->sc_cmap_red[index] = r; 1460 sc->sc_cmap_green[index] = g; 1461 sc->sc_cmap_blue[index] = b; 1462 /* 1463 * writing the dac index takes a while, in theory we can poll some 1464 * register to see when it's ready - but we better avoid writing it 1465 * unnecessarily 1466 */ 1467 if (index != sc->sc_dacw) { 1468 regwb(sc, DAC_MASK, 0xff); 1469 regwb(sc, DAC_WINDEX, index); 1470 } 1471 sc->sc_dacw = index + 1; 1472 regwb(sc, DAC_DATA, r); 1473 regwb(sc, DAC_DATA, g); 1474 regwb(sc, DAC_DATA, b); 1475 return 0; 1476 } 1477 1478 static int 1479 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1480 { 1481 uint index = cm->index; 1482 uint count = cm->count; 1483 int i, error; 1484 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1485 uint8_t *r, *g, *b; 1486 1487 if (cm->index >= 256 || cm->count > 256 || 1488 (cm->index + cm->count) > 256) 1489 return EINVAL; 1490 error = copyin(cm->red, &rbuf[index], count); 1491 if (error) 1492 return error; 1493 error = copyin(cm->green, &gbuf[index], count); 1494 if (error) 1495 return error; 1496 error = copyin(cm->blue, &bbuf[index], count); 1497 if (error) 1498 return error; 1499 1500 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1501 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1502 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1503 1504 r = &sc->sc_cmap_red[index]; 1505 g = &sc->sc_cmap_green[index]; 1506 b = &sc->sc_cmap_blue[index]; 1507 1508 for (i = 0; i < count; i++) { 1509 mach64_putpalreg(sc, index, *r, *g, *b); 1510 index++; 1511 r++, g++, b++; 1512 } 1513 return 0; 1514 } 1515 1516 static int 1517 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1518 { 1519 u_int index = cm->index; 1520 u_int count = cm->count; 1521 int error; 1522 1523 if (index >= 255 || count > 256 || index + count > 256) 1524 return EINVAL; 1525 1526 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1527 if (error) 1528 return error; 1529 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1530 if (error) 1531 return error; 1532 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1533 if (error) 1534 return error; 1535 1536 return 0; 1537 } 1538 1539 static int 1540 mach64_is_console(struct mach64_softc *sc) 1541 { 1542 bool console = 0; 1543 1544 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1545 "is_console", &console); 1546 return console; 1547 } 1548 1549 /* 1550 * wsdisplay_emulops 1551 */ 1552 1553 static void 1554 mach64_cursor(void *cookie, int on, int row, int col) 1555 { 1556 struct rasops_info *ri = cookie; 1557 struct vcons_screen *scr = ri->ri_hw; 1558 struct mach64_softc *sc = scr->scr_cookie; 1559 int x, y, wi, he; 1560 1561 wi = ri->ri_font->fontwidth; 1562 he = ri->ri_font->fontheight; 1563 1564 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1565 x = ri->ri_ccol * wi + ri->ri_xorigin; 1566 y = ri->ri_crow * he + ri->ri_yorigin; 1567 if (ri->ri_flg & RI_CURSOR) { 1568 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1569 ri->ri_flg &= ~RI_CURSOR; 1570 } 1571 ri->ri_crow = row; 1572 ri->ri_ccol = col; 1573 if (on) { 1574 x = ri->ri_ccol * wi + ri->ri_xorigin; 1575 y = ri->ri_crow * he + ri->ri_yorigin; 1576 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1577 ri->ri_flg |= RI_CURSOR; 1578 } 1579 } else { 1580 scr->scr_ri.ri_crow = row; 1581 scr->scr_ri.ri_ccol = col; 1582 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1583 } 1584 } 1585 1586 #if 0 1587 static int 1588 mach64_mapchar(void *cookie, int uni, u_int *index) 1589 { 1590 return 0; 1591 } 1592 #endif 1593 1594 static void 1595 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1596 { 1597 struct rasops_info *ri = cookie; 1598 struct wsdisplay_font *font = PICK_FONT(ri, c); 1599 struct vcons_screen *scr = ri->ri_hw; 1600 struct mach64_softc *sc = scr->scr_cookie; 1601 1602 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1603 int fg, bg, uc; 1604 uint8_t *data; 1605 int x, y, wi, he; 1606 wi = font->fontwidth; 1607 he = font->fontheight; 1608 1609 if (!CHAR_IN_FONT(c, font)) 1610 return; 1611 bg = ri->ri_devcmap[(attr >> 16) & 0x0f]; 1612 fg = ri->ri_devcmap[(attr >> 24) & 0x0f]; 1613 x = ri->ri_xorigin + col * wi; 1614 y = ri->ri_yorigin + row * he; 1615 if (c == 0x20) { 1616 mach64_rectfill(sc, x, y, wi, he, bg); 1617 } else { 1618 uc = c - font->firstchar; 1619 data = (uint8_t *)font->data + uc * 1620 ri->ri_fontscale; 1621 1622 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1623 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1624 } 1625 if (attr & 1) 1626 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1627 } 1628 } 1629 1630 static void 1631 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 1632 { 1633 struct rasops_info *ri = cookie; 1634 struct wsdisplay_font *font = PICK_FONT(ri, c); 1635 struct vcons_screen *scr = ri->ri_hw; 1636 struct mach64_softc *sc = scr->scr_cookie; 1637 uint32_t bg, fg, latch = 0, bg8, fg8, pixel; 1638 int i, x, y, wi, he, r, g, b, aval; 1639 int r1, g1, b1, r0, g0, b0, fgo, bgo; 1640 uint8_t *data8; 1641 int rv = 0, cnt = 0; 1642 1643 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1644 return; 1645 1646 if (!CHAR_IN_FONT(c, font)) 1647 return; 1648 1649 wi = font->fontwidth; 1650 he = font->fontheight; 1651 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1652 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1653 x = ri->ri_xorigin + col * wi; 1654 y = ri->ri_yorigin + row * he; 1655 1656 if (c == 0x20) { 1657 mach64_rectfill(sc, x, y, wi, he, bg); 1658 if (attr & 1) 1659 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1660 return; 1661 } 1662 1663 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1664 if (rv == GC_OK) 1665 return; 1666 1667 data8 = WSFONT_GLYPH(c, font); 1668 1669 wait_for_fifo(sc, 11); 1670 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1671 regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST); 1672 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1673 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1674 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1675 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1676 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1677 regw(sc, SRC_Y_X, 0); 1678 regw(sc, SRC_WIDTH1, wi); 1679 regw(sc, DST_Y_X, (x << 16) | y); 1680 regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he); 1681 1682 /* 1683 * we need the RGB colours here, so get offsets into rasops_cmap 1684 */ 1685 fgo = ((attr >> 24) & 0xf) * 3; 1686 bgo = ((attr >> 16) & 0xf) * 3; 1687 1688 r0 = rasops_cmap[bgo]; 1689 r1 = rasops_cmap[fgo]; 1690 g0 = rasops_cmap[bgo + 1]; 1691 g1 = rasops_cmap[fgo + 1]; 1692 b0 = rasops_cmap[bgo + 2]; 1693 b1 = rasops_cmap[fgo + 2]; 1694 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 1695 bg8 = R3G3B2(r0, g0, b0); 1696 fg8 = R3G3B2(r1, g1, b1); 1697 1698 wait_for_fifo(sc, 10); 1699 1700 for (i = 0; i < ri->ri_fontscale; i++) { 1701 aval = *data8; 1702 if (aval == 0) { 1703 pixel = bg8; 1704 } else if (aval == 255) { 1705 pixel = fg8; 1706 } else { 1707 r = aval * r1 + (255 - aval) * r0; 1708 g = aval * g1 + (255 - aval) * g0; 1709 b = aval * b1 + (255 - aval) * b0; 1710 pixel = ((r & 0xe000) >> 8) | 1711 ((g & 0xe000) >> 11) | 1712 ((b & 0xc000) >> 14); 1713 } 1714 latch = (latch << 8) | pixel; 1715 /* write in 32bit chunks */ 1716 if ((i & 3) == 3) { 1717 regws(sc, HOST_DATA0, latch); 1718 /* 1719 * not strictly necessary, old data should be shifted 1720 * out 1721 */ 1722 latch = 0; 1723 cnt++; 1724 if (cnt > 8) { 1725 wait_for_fifo(sc, 10); 1726 cnt = 0; 1727 } 1728 } 1729 data8++; 1730 } 1731 /* if we have pixels left in latch write them out */ 1732 if ((i & 3) != 0) { 1733 latch = latch << ((4 - (i & 3)) << 3); 1734 regws(sc, HOST_DATA0, latch); 1735 } 1736 1737 if (rv == GC_ADD) { 1738 glyphcache_add(&sc->sc_gc, c, x, y); 1739 } else if (attr & 1) { 1740 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1741 } 1742 1743 } 1744 1745 static void 1746 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1747 { 1748 struct rasops_info *ri = cookie; 1749 struct vcons_screen *scr = ri->ri_hw; 1750 struct mach64_softc *sc = scr->scr_cookie; 1751 int32_t xs, xd, y, width, height; 1752 1753 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1754 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1755 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1756 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1757 width = ri->ri_font->fontwidth * ncols; 1758 height = ri->ri_font->fontheight; 1759 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC); 1760 } 1761 } 1762 1763 static void 1764 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1765 { 1766 struct rasops_info *ri = cookie; 1767 struct vcons_screen *scr = ri->ri_hw; 1768 struct mach64_softc *sc = scr->scr_cookie; 1769 int32_t x, y, width, height, fg, bg, ul; 1770 1771 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1772 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1773 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1774 width = ri->ri_font->fontwidth * ncols; 1775 height = ri->ri_font->fontheight; 1776 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1777 1778 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1779 } 1780 } 1781 1782 static void 1783 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1784 { 1785 struct rasops_info *ri = cookie; 1786 struct vcons_screen *scr = ri->ri_hw; 1787 struct mach64_softc *sc = scr->scr_cookie; 1788 int32_t x, ys, yd, width, height; 1789 1790 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1791 x = ri->ri_xorigin; 1792 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1793 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1794 width = ri->ri_emuwidth; 1795 height = ri->ri_font->fontheight*nrows; 1796 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC); 1797 } 1798 } 1799 1800 static void 1801 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1802 { 1803 struct rasops_info *ri = cookie; 1804 struct vcons_screen *scr = ri->ri_hw; 1805 struct mach64_softc *sc = scr->scr_cookie; 1806 int32_t x, y, width, height, fg, bg, ul; 1807 1808 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1809 if ((row == 0) && (nrows == ri->ri_rows)) { 1810 /* clear full screen */ 1811 x = 0; 1812 y = 0; 1813 width = sc->virt_x; 1814 height = sc->virt_y; 1815 } else { 1816 x = ri->ri_xorigin; 1817 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1818 width = ri->ri_emuwidth; 1819 height = ri->ri_font->fontheight * nrows; 1820 } 1821 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1822 1823 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1824 } 1825 } 1826 1827 static void 1828 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width, 1829 int height, int rop) 1830 { 1831 struct mach64_softc *sc = cookie; 1832 uint32_t dest_ctl = 0; 1833 1834 #if 0 1835 wait_for_idle(sc); 1836 #else 1837 wait_for_fifo(sc, 10); 1838 #endif 1839 1840 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1841 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1842 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1843 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1844 if (yd < ys) { 1845 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1846 } else { 1847 ys += height - 1; 1848 yd += height - 1; 1849 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1850 } 1851 if (xd < xs) { 1852 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1853 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1854 } else { 1855 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1856 xs += width - 1; 1857 xd += width - 1; 1858 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1859 } 1860 regw(sc, DST_CNTL, dest_ctl); 1861 1862 regw(sc, SRC_Y_X, (xs << 16) | ys); 1863 regw(sc, SRC_WIDTH1, width); 1864 regw(sc, DST_Y_X, (xd << 16) | yd); 1865 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1866 } 1867 1868 static void 1869 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1870 int height, uint32_t fg, uint32_t bg) 1871 { 1872 wait_for_idle(sc); 1873 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1874 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1875 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1876 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1877 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1878 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1879 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1880 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1881 regw(sc, DP_BKGD_CLR, bg); 1882 regw(sc, DP_FRGD_CLR, fg); 1883 regw(sc, SRC_Y_X, 0); 1884 regw(sc, SRC_WIDTH1, width); 1885 regw(sc, DST_Y_X, (xd << 16) | yd); 1886 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1887 /* now feed the data into the chip */ 1888 } 1889 1890 static void 1891 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1892 { 1893 int i; 1894 uint32_t latch = 0, bork; 1895 int shift = 0; 1896 int reg = 0; 1897 1898 for (i = 0; i < count; i++) { 1899 bork = data[i]; 1900 latch |= (bork << shift); 1901 if (shift == 24) { 1902 regw(sc, HOST_DATA0 + reg, latch); 1903 latch = 0; 1904 shift = 0; 1905 reg = (reg + 4) & 0x3c; 1906 } else 1907 shift += 8; 1908 } 1909 if (shift != 0) /* 24 */ 1910 regw(sc, HOST_DATA0 + reg, latch); 1911 } 1912 1913 1914 static void 1915 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1916 int colour) 1917 { 1918 wait_for_fifo(sc, 11); 1919 regw(sc, DP_FRGD_CLR, colour); 1920 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1921 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1922 regw(sc, DP_MIX, MIX_SRC << 16); 1923 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1924 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1925 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1926 1927 regw(sc, SRC_Y_X, (x << 16) | y); 1928 regw(sc, SRC_WIDTH1, width); 1929 regw(sc, DST_Y_X, (x << 16) | y); 1930 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1931 } 1932 1933 static void 1934 mach64_clearscreen(struct mach64_softc *sc) 1935 { 1936 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1937 } 1938 1939 1940 #if 0 1941 static void 1942 mach64_showpal(struct mach64_softc *sc) 1943 { 1944 int i, x = 0; 1945 1946 for (i = 0; i < 16; i++) { 1947 mach64_rectfill(sc, x, 0, 64, 64, i); 1948 x += 64; 1949 } 1950 } 1951 #endif 1952 1953 /* 1954 * wsdisplay_accessops 1955 */ 1956 1957 static int 1958 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1959 struct lwp *l) 1960 { 1961 struct vcons_data *vd = v; 1962 struct mach64_softc *sc = vd->cookie; 1963 struct wsdisplay_fbinfo *wdf; 1964 struct vcons_screen *ms = vd->active; 1965 1966 switch (cmd) { 1967 case WSDISPLAYIO_GTYPE: 1968 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1969 return 0; 1970 1971 case WSDISPLAYIO_LINEBYTES: 1972 *(u_int *)data = sc->stride * sc->bits_per_pixel / 8; 1973 return 0; 1974 1975 case WSDISPLAYIO_GINFO: 1976 wdf = (void *)data; 1977 wdf->height = sc->virt_y; 1978 wdf->width = sc->virt_x; 1979 wdf->depth = sc->bits_per_pixel; 1980 wdf->cmsize = 256; 1981 return 0; 1982 1983 case WSDISPLAYIO_GETCMAP: 1984 return mach64_getcmap(sc, 1985 (struct wsdisplay_cmap *)data); 1986 1987 case WSDISPLAYIO_PUTCMAP: 1988 return mach64_putcmap(sc, 1989 (struct wsdisplay_cmap *)data); 1990 1991 /* PCI config read/write passthrough. */ 1992 case PCI_IOC_CFGREAD: 1993 case PCI_IOC_CFGWRITE: 1994 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1995 cmd, data, flag, l); 1996 1997 case WSDISPLAYIO_GET_BUSID: 1998 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1999 sc->sc_pcitag, data); 2000 2001 case WSDISPLAYIO_SMODE: { 2002 int new_mode = *(int*)data; 2003 if (new_mode != sc->sc_mode) { 2004 sc->sc_mode = new_mode; 2005 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 2006 && (ms != NULL)) 2007 { 2008 /* restore initial video mode */ 2009 mach64_init(sc); 2010 mach64_init_engine(sc); 2011 mach64_init_lut(sc); 2012 if (sc->sc_setmode) 2013 mach64_modeswitch(sc, sc->sc_my_mode); 2014 mach64_clearscreen(sc); 2015 glyphcache_wipe(&sc->sc_gc); 2016 vcons_redraw_screen(ms); 2017 } 2018 } 2019 } 2020 return 0; 2021 case WSDISPLAYIO_GET_EDID: { 2022 struct wsdisplayio_edid_info *d = data; 2023 return wsdisplayio_get_edid(sc->sc_dev, d); 2024 } 2025 2026 case WSDISPLAYIO_GET_FBINFO: { 2027 struct wsdisplayio_fbinfo *fbi = data; 2028 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 2029 } 2030 } 2031 return EPASSTHROUGH; 2032 } 2033 2034 static paddr_t 2035 mach64_mmap(void *v, void *vs, off_t offset, int prot) 2036 { 2037 struct vcons_data *vd = v; 2038 struct mach64_softc *sc = vd->cookie; 2039 paddr_t pa; 2040 2041 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 2042 /* 2043 *'regular' framebuffer mmap()ing 2044 */ 2045 if (offset < (sc->memsize * 1024)) { 2046 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, 2047 offset, prot, BUS_SPACE_MAP_LINEAR); 2048 return pa; 2049 } 2050 } else if (sc->sc_mode == WSDISPLAYIO_MODE_MAPPED) { 2051 /* 2052 * restrict all other mappings to processes with superuser 2053 * privileges 2054 */ 2055 if (kauth_authorize_machdep(kauth_cred_get(), 2056 KAUTH_MACHDEP_UNMANAGEDMEM, 2057 NULL, NULL, NULL, NULL) != 0) { 2058 return -1; 2059 } 2060 if ((offset >= sc->sc_aperbase) && 2061 (offset < (sc->sc_aperbase + sc->sc_apersize))) { 2062 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2063 BUS_SPACE_MAP_LINEAR); 2064 return pa; 2065 } 2066 2067 if ((offset >= sc->sc_regbase) && 2068 (offset < (sc->sc_regbase + sc->sc_regsize))) { 2069 pa = bus_space_mmap(sc->sc_regt, offset, 0, prot, 2070 BUS_SPACE_MAP_LINEAR); 2071 return pa; 2072 } 2073 2074 if ((offset >= sc->sc_rom.vb_base) && 2075 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 2076 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2077 BUS_SPACE_MAP_LINEAR); 2078 return pa; 2079 } 2080 2081 #ifdef PCI_MAGIC_IO_RANGE 2082 if ((offset >= PCI_MAGIC_IO_RANGE) && 2083 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 2084 return bus_space_mmap(sc->sc_iot, 2085 offset - PCI_MAGIC_IO_RANGE, 0, prot, 0); 2086 } 2087 #endif 2088 } 2089 return -1; 2090 } 2091 2092 #if 0 2093 static int 2094 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 2095 { 2096 2097 return 0; 2098 } 2099 #endif 2100 2101 void 2102 machfb_blank(struct mach64_softc *sc, int blank) 2103 { 2104 uint32_t reg; 2105 2106 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 2107 2108 switch (blank) 2109 { 2110 case 0: 2111 reg = regr(sc, CRTC_GEN_CNTL); 2112 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 2113 sc->sc_blanked = 0; 2114 break; 2115 case 1: 2116 reg = regr(sc, CRTC_GEN_CNTL); 2117 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 2118 sc->sc_blanked = 1; 2119 break; 2120 default: 2121 break; 2122 } 2123 } 2124
Indexes created Thu Oct 02 14:10:14 GMT 2025