machfb.c revision 1.106
1 /* $NetBSD: machfb.c,v 1.106 2021/08/07 16:19:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.106 2021/08/07 16:19:14 thorpej Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #include <dev/wscons/wsdisplayvar.h> 58 59 #include <dev/wscons/wsconsio.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/rasops/rasops.h> 62 #include <dev/pci/wsdisplay_pci.h> 63 64 #include <dev/wscons/wsdisplay_vconsvar.h> 65 #include <dev/wscons/wsdisplay_glyphcachevar.h> 66 67 #include "opt_wsemul.h" 68 #include "opt_machfb.h" 69 #include "opt_glyphcache.h" 70 71 #ifdef MACHFB_DEBUG 72 #define DPRINTF printf 73 #else 74 #define DPRINTF while (0) printf 75 #endif 76 77 #define MACH64_REG_SIZE 0x800 78 #define MACH64_REG_OFF 0x7ff800 79 80 #define NBARS 3 /* number of Mach64 PCI BARs */ 81 82 struct vga_bar { 83 bus_addr_t vb_base; 84 bus_size_t vb_size; 85 pcireg_t vb_type; 86 int vb_flags; 87 }; 88 89 struct mach64_softc { 90 device_t sc_dev; 91 pci_chipset_tag_t sc_pc; 92 pcitag_t sc_pcitag; 93 94 struct vga_bar sc_bars[NBARS]; 95 struct vga_bar sc_rom; 96 97 #define sc_aperbase sc_bars[0].vb_base 98 #define sc_apersize sc_bars[0].vb_size 99 100 #define sc_iobase sc_bars[1].vb_base 101 #define sc_iosize sc_bars[1].vb_size 102 103 #define sc_regbase sc_bars[2].vb_base 104 #define sc_regsize sc_bars[2].vb_size 105 106 bus_space_tag_t sc_regt; 107 bus_space_tag_t sc_memt; 108 bus_space_tag_t sc_iot; 109 bus_space_handle_t sc_regh; 110 bus_space_handle_t sc_memh; 111 #if 0 112 void *sc_aperture; /* mapped aperture vaddr */ 113 void *sc_registers; /* mapped registers vaddr */ 114 #endif 115 uint32_t sc_nbus, sc_ndev, sc_nfunc; 116 size_t memsize; 117 int memtype; 118 119 int sc_mode; 120 int sc_bg; 121 int sc_locked; 122 123 int has_dsp; 124 int bits_per_pixel; 125 int max_x; 126 int max_y; 127 int virt_x; 128 int virt_y; 129 int stride; /* in pixels */ 130 int color_depth; 131 132 int mem_freq; 133 int ramdac_freq; 134 int ref_freq; 135 int vclk_freq; 136 137 int ref_div; 138 int log2_vclk_post_div; 139 int vclk_post_div; 140 int vclk_fb_div; 141 int mclk_post_div; 142 int mclk_fb_div; 143 int sc_clock; /* which clock to use */ 144 int minref, m; 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 struct edid_info sc_ei; 150 int sc_setmode; 151 int sc_gen_cntl; 152 153 u_char sc_cmap_red[256]; 154 u_char sc_cmap_green[256]; 155 u_char sc_cmap_blue[256]; 156 int sc_dacw, sc_blanked, sc_console; 157 struct vcons_data vd; 158 struct wsdisplay_accessops sc_accessops; 159 glyphcache sc_gc; 160 }; 161 162 struct mach64_crtcregs { 163 uint32_t h_total_disp; 164 uint32_t h_sync_strt_wid; 165 uint32_t v_total_disp; 166 uint32_t v_sync_strt_wid; 167 uint32_t gen_cntl; 168 uint32_t clock_cntl; 169 uint32_t color_depth; 170 uint32_t dot_clock; 171 }; 172 173 static struct { 174 uint16_t chip_id; 175 uint32_t ramdac_freq; 176 } const mach64_info[] = { 177 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 178 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 179 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 189 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 190 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 193 #if 0 194 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 197 #endif 198 { PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI, 230000 }, 199 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 200 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 201 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 202 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 203 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 204 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 205 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 206 }; 207 208 static int mach64_chip_id, mach64_chip_rev; 209 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 210 211 static const char *mach64_gx_memtype_names[] = { 212 "DRAM", "VRAM", "VRAM", "DRAM", 213 "DRAM", "VRAM", "VRAM", "(unknown type)" 214 }; 215 216 static const char *mach64_memtype_names[] = { 217 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 218 "(unknown type)" 219 }; 220 221 extern const u_char rasops_cmap[768]; 222 223 static int mach64_match(device_t, cfdata_t, void *); 224 static void mach64_attach(device_t, device_t, void *); 225 226 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, 227 mach64_attach, NULL, NULL); 228 229 static void mach64_init(struct mach64_softc *); 230 static int mach64_get_memsize(struct mach64_softc *); 231 static int mach64_get_max_ramdac(struct mach64_softc *); 232 static int mach64_ref_freq(void); 233 234 #ifdef MACHFB_DEBUG 235 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 236 static void mach64_print_reg(struct mach64_softc *); 237 #endif 238 239 static int mach64_calc_crtcregs(struct mach64_softc *, 240 struct mach64_crtcregs *, 241 struct videomode *); 242 static void mach64_set_crtcregs(struct mach64_softc *, 243 struct mach64_crtcregs *); 244 245 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 246 static void mach64_set_dsp(struct mach64_softc *); 247 static void mach64_set_pll(struct mach64_softc *, int); 248 static void mach64_reset_engine(struct mach64_softc *); 249 static void mach64_init_engine(struct mach64_softc *); 250 #if 0 251 static void mach64_adjust_frame(struct mach64_softc *, int, int); 252 #endif 253 static void mach64_init_lut(struct mach64_softc *); 254 255 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 256 static int mach64_is_console(struct mach64_softc *); 257 258 static void mach64_cursor(void *, int, int, int); 259 #if 0 260 static int mach64_mapchar(void *, int, u_int *); 261 #endif 262 static void mach64_putchar_mono(void *, int, int, u_int, long); 263 static void mach64_putchar_aa8(void *, int, int, u_int, long); 264 static void mach64_copycols(void *, int, int, int, int); 265 static void mach64_erasecols(void *, int, int, int, long); 266 static void mach64_copyrows(void *, int, int, int); 267 static void mach64_eraserows(void *, int, int, long); 268 static void mach64_clearscreen(struct mach64_softc *); 269 270 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 271 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 272 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 273 uint8_t, uint8_t); 274 static void mach64_bitblt(void *, int, int, int, int, int, int, int); 275 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 276 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 277 uint32_t, uint32_t); 278 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 279 #if 0 280 static void mach64_showpal(struct mach64_softc *); 281 #endif 282 283 static void machfb_blank(struct mach64_softc *, int); 284 static int machfb_drm_print(void *, const char *); 285 286 static struct wsscreen_descr mach64_defaultscreen = { 287 "default", 288 80, 30, 289 NULL, 290 8, 16, 291 WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE 292 | WSSCREEN_RESIZE , 293 NULL 294 }; 295 296 static const struct wsscreen_descr *_mach64_scrlist[] = { 297 &mach64_defaultscreen, 298 }; 299 300 static struct wsscreen_list mach64_screenlist = { 301 __arraycount(_mach64_scrlist), 302 _mach64_scrlist 303 }; 304 305 static int mach64_ioctl(void *, void *, u_long, void *, int, 306 struct lwp *); 307 static paddr_t mach64_mmap(void *, void *, off_t, int); 308 309 static struct vcons_screen mach64_console_screen; 310 311 /* 312 * Inline functions for getting access to register aperture. 313 */ 314 315 static inline uint32_t 316 regr(struct mach64_softc *sc, uint32_t index) 317 { 318 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400); 319 } 320 321 static inline uint8_t 322 regrb(struct mach64_softc *sc, uint32_t index) 323 { 324 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400); 325 } 326 327 static inline void 328 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 329 { 330 bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 331 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 332 BUS_SPACE_BARRIER_WRITE); 333 } 334 335 static inline void 336 regws(struct mach64_softc *sc, uint32_t index, uint32_t data) 337 { 338 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 339 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4, 340 BUS_SPACE_BARRIER_WRITE); 341 } 342 343 static inline void 344 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 345 { 346 bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data); 347 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1, 348 BUS_SPACE_BARRIER_WRITE); 349 } 350 351 static inline void 352 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 353 { 354 uint32_t reg; 355 356 reg = regr(sc, CLOCK_CNTL); 357 reg |= PLL_WR_EN; 358 regw(sc, CLOCK_CNTL, reg); 359 reg &= ~(PLL_ADDR | PLL_DATA); 360 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 361 reg |= data << PLL_DATA_SHIFT; 362 reg |= CLOCK_STROBE; 363 regw(sc, CLOCK_CNTL, reg); 364 reg &= ~PLL_WR_EN; 365 regw(sc, CLOCK_CNTL, reg); 366 } 367 368 static inline uint8_t 369 regrb_pll(struct mach64_softc *sc, uint32_t index) 370 { 371 372 regwb(sc, CLOCK_CNTL + 1, index << 2); 373 return regrb(sc, CLOCK_CNTL + 2); 374 } 375 376 static inline void 377 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 378 { 379 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 380 continue; 381 } 382 383 static inline void 384 wait_for_idle(struct mach64_softc *sc) 385 { 386 wait_for_fifo(sc, 16); 387 while ((regr(sc, GUI_STAT) & 1) != 0) 388 continue; 389 } 390 391 static int 392 mach64_match(device_t parent, cfdata_t match, void *aux) 393 { 394 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 395 int i; 396 397 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 398 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 399 return 0; 400 401 for (i = 0; i < __arraycount(mach64_info); i++) 402 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 403 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 404 mach64_chip_rev = PCI_REVISION(pa->pa_class); 405 return 100; 406 } 407 408 return 0; 409 } 410 411 static void 412 mach64_attach(device_t parent, device_t self, void *aux) 413 { 414 struct mach64_softc *sc = device_private(self); 415 struct pci_attach_args *pa = aux; 416 struct rasops_info *ri; 417 const char *mptr = NULL; 418 prop_data_t edid_data; 419 const struct videomode *mode = NULL; 420 int bar, id, expected_id; 421 int is_gx; 422 const char **memtype_names; 423 struct wsemuldisplaydev_attach_args aa; 424 long defattr; 425 int width = 1024, height = 768; 426 pcireg_t screg; 427 uint32_t reg; 428 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 429 int use_mmio = FALSE; 430 431 sc->sc_dev = self; 432 sc->sc_pc = pa->pa_pc; 433 sc->sc_pcitag = pa->pa_tag; 434 sc->sc_dacw = -1; 435 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 436 sc->sc_nbus = pa->pa_bus; 437 sc->sc_ndev = pa->pa_device; 438 sc->sc_nfunc = pa->pa_function; 439 sc->sc_locked = 0; 440 sc->sc_iot = pa->pa_iot; 441 sc->sc_accessops.ioctl = mach64_ioctl; 442 sc->sc_accessops.mmap = mach64_mmap; 443 sc->sc_setmode = 0; 444 445 pci_aprint_devinfo(pa, "Graphics processor"); 446 #ifdef MACHFB_DEBUG 447 printf(prop_dictionary_externalize(device_properties(self))); 448 #endif 449 450 /* enable memory access */ 451 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 452 if ((screg & enables) != enables) { 453 screg |= enables; 454 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 455 PCI_COMMAND_STATUS_REG, screg); 456 } 457 for (bar = 0; bar < NBARS; bar++) { 458 reg = PCI_MAPREG_START + (bar * 4); 459 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 460 sc->sc_pcitag, reg); 461 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 462 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 463 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 464 } 465 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 466 (uint32_t)sc->sc_apersize); 467 468 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 469 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 470 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 471 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 472 sc->sc_memt = pa->pa_memt; 473 474 /* use MMIO register aperture if available */ 475 if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) { 476 if (pci_mapreg_map(pa, MACH64_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 477 0, &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase, 478 &sc->sc_regsize) == 0) { 479 480 /* 481 * the MMIO aperture maps both 1KB register blocks, but 482 * all register offsets are relative to the 2nd one so 483 * for now fix this up in MACH64_REG_OFF and the access 484 * functions 485 */ 486 aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n"); 487 use_mmio = TRUE; 488 } 489 } 490 if (!use_mmio) { 491 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, 492 sc->sc_apersize, BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 493 panic("%s: failed to map aperture", 494 device_xname(sc->sc_dev)); 495 } 496 497 sc->sc_regt = sc->sc_memt; 498 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 499 MACH64_REG_SIZE, &sc->sc_regh); 500 } 501 502 mach64_init(sc); 503 504 aprint_normal_dev(sc->sc_dev, 505 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 506 (u_int)(sc->sc_apersize / (1024 * 1024)), 507 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 508 (u_int)sc->sc_regbase); 509 510 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 511 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 512 #ifdef MACHFB_DEBUG 513 mach64_get_mode(sc, NULL); 514 mach64_print_reg(sc); 515 #endif 516 517 prop_dictionary_get_uint32(device_properties(self), "width", &width); 518 prop_dictionary_get_uint32(device_properties(self), "height", &height); 519 520 default_mode.hdisplay = width; 521 default_mode.vdisplay = height; 522 523 prop_dictionary_get_string(device_properties(sc->sc_dev), 524 "videomode", &mptr); 525 526 memset(&sc->sc_ei, 0, sizeof(sc->sc_ei)); 527 if (mptr == NULL && 528 (edid_data = prop_dictionary_get(device_properties(self), "EDID")) 529 != NULL) { 530 531 sc->sc_edid_size = uimin(1024, prop_data_size(edid_data)); 532 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 533 memcpy(sc->sc_edid_data, prop_data_value(edid_data), 534 sc->sc_edid_size); 535 536 edid_parse(sc->sc_edid_data, &sc->sc_ei); 537 538 #ifdef MACHFB_DEBUG 539 edid_print(&sc->sc_ei); 540 #endif 541 } 542 is_gx = 0; 543 switch(mach64_chip_id) { 544 case PCI_PRODUCT_ATI_MACH64_GX: 545 case PCI_PRODUCT_ATI_MACH64_CX: 546 is_gx = 1; 547 /* FALLTHROUGH */ 548 case PCI_PRODUCT_ATI_MACH64_CT: 549 sc->has_dsp = 0; 550 break; 551 case PCI_PRODUCT_ATI_MACH64_VT: 552 case PCI_PRODUCT_ATI_RAGE_II: 553 if((mach64_chip_rev & 0x07) == 0) { 554 sc->has_dsp = 0; 555 break; 556 } 557 /* FALLTHROUGH */ 558 default: 559 sc->has_dsp = 1; 560 } 561 562 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 563 564 sc->memsize = mach64_get_memsize(sc); 565 566 if(is_gx) 567 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 568 else 569 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 570 571 sc->ref_freq = mach64_ref_freq(); 572 573 reg = regr(sc, CLOCK_CNTL); 574 sc->sc_clock = reg & 3; 575 DPRINTF("using clock %d\n", sc->sc_clock); 576 577 DPRINTF("ref_freq: %d\n", sc->ref_freq); 578 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 579 DPRINTF("ref_div: %d\n", sc->ref_div); 580 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 581 DPRINTF("mclk_fb_div: %d\n", sc->mclk_fb_div); 582 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 583 (sc->ref_div * 2); 584 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 585 (sc->mem_freq * sc->ref_div); 586 sc->ramdac_freq = mach64_get_max_ramdac(sc); 587 { 588 sc->minref = sc->ramdac_freq / 510; 589 sc->m = sc->ref_freq / sc->minref; 590 DPRINTF("minref: %d m: %d\n", sc->minref, sc->m); 591 } 592 aprint_normal_dev(sc->sc_dev, 593 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 594 (u_long)sc->memsize, 595 memtype_names[sc->memtype], 596 sc->mem_freq / 1000, sc->mem_freq % 1000, 597 sc->ramdac_freq / 1000); 598 599 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 600 switch(mach64_chip_id) { 601 case PCI_PRODUCT_ATI_MACH64_GX: 602 expected_id = 0x00d7; 603 break; 604 case PCI_PRODUCT_ATI_MACH64_CX: 605 expected_id = 0x0057; 606 break; 607 default: 608 /* Most chip IDs match their PCI product ID. */ 609 expected_id = mach64_chip_id; 610 } 611 612 if (id != expected_id) { 613 aprint_error_dev(sc->sc_dev, 614 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 615 return; 616 } 617 618 sc->sc_console = mach64_is_console(sc); 619 sc->sc_gen_cntl = regr(sc, CRTC_GEN_CNTL); 620 aprint_debug("gen_cntl: %08x\n", sc->sc_gen_cntl); 621 sc->sc_gen_cntl &= CRTC_CSYNC_EN; 622 aprint_normal_dev(sc->sc_dev, "found composite sync %s\n", 623 sc->sc_gen_cntl ? "enabled" : "disabled"); 624 625 #define MODE_IS_VALID(m) ((sc->ramdac_freq >= (m)->dot_clock) && \ 626 ((m)->hdisplay <= 1280)) 627 628 /* no mode setting support on ancient chips with external clocks */ 629 sc->sc_setmode = 0; 630 if (!is_gx) { 631 /* 632 * Now pick a mode. 633 */ 634 if ((sc->sc_ei.edid_preferred_mode != NULL)) { 635 struct videomode *m = sc->sc_ei.edid_preferred_mode; 636 if (MODE_IS_VALID(m)) { 637 memcpy(&default_mode, m, 638 sizeof(struct videomode)); 639 sc->sc_setmode = 1; 640 } else { 641 aprint_normal_dev(sc->sc_dev, 642 "unable to use EDID preferred mode " 643 "(%d x %d)\n", m->hdisplay, m->vdisplay); 644 } 645 } 646 /* 647 * if we can't use the preferred mode go look for the 648 * best one we can support 649 */ 650 if (sc->sc_setmode == 0) { 651 struct videomode *m = sc->sc_ei.edid_modes; 652 653 mode = NULL; 654 sort_modes(sc->sc_ei.edid_modes, 655 &sc->sc_ei.edid_preferred_mode, 656 sc->sc_ei.edid_nmodes); 657 for (int n = 0; n < sc->sc_ei.edid_nmodes; n++) 658 if (MODE_IS_VALID(&m[n])) { 659 mode = &m[n]; 660 break; 661 } 662 if (mode != NULL) { 663 memcpy(&default_mode, mode, 664 sizeof(struct videomode)); 665 sc->sc_setmode = 1; 666 } 667 } 668 } 669 670 /* make sure my_mode points at something sensible if the above fails */ 671 if (default_mode.dot_clock == 0) { 672 sc->sc_setmode = 0; 673 mode = pick_mode_by_ref(width, height, 60); 674 if (mode != NULL) { 675 memcpy(&default_mode, mode, sizeof(default_mode)); 676 } else if ((width > 0) && (height > 0)) { 677 default_mode.hdisplay = width; 678 default_mode.vdisplay = height; 679 } else { 680 /* 681 * if we end up here we're probably dealing with 682 * uninitialized hardware - try to set 1024x768@60 and 683 * hope for the best... 684 */ 685 mode = pick_mode_by_ref(1024, 768, 60); 686 if (mode == NULL) return; 687 memcpy(&default_mode, mode, sizeof(default_mode)); 688 if (!is_gx) sc->sc_setmode = 1; 689 } 690 } 691 692 sc->sc_my_mode = &default_mode; 693 694 if ((width == sc->sc_my_mode->hdisplay) && 695 (height == sc->sc_my_mode->vdisplay)) 696 sc->sc_setmode = 0; 697 698 sc->bits_per_pixel = 8; 699 sc->virt_x = sc->sc_my_mode->hdisplay; 700 sc->virt_y = sc->sc_my_mode->vdisplay; 701 sc->stride = (sc->virt_x + 7) & ~7; /* hw needs multiples of 8 */ 702 sc->max_x = sc->virt_x - 1; 703 sc->max_y = (sc->memsize * 1024) / 704 (sc->stride * (sc->bits_per_pixel / 8)) - 1; 705 706 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 707 708 mach64_init_engine(sc); 709 710 if (sc->sc_setmode) 711 mach64_modeswitch(sc, sc->sc_my_mode); 712 713 aprint_normal_dev(sc->sc_dev, 714 "initial resolution %dx%d at %d bpp\n", 715 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 716 sc->bits_per_pixel); 717 718 wsfont_init(); 719 720 #ifdef GLYPHCACHE_DEBUG 721 /* shrink the screen so we can see part of the glyph cache */ 722 sc->sc_my_mode->vdisplay -= 200; 723 #endif 724 725 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 726 sc->vd.init_screen = mach64_init_screen; 727 sc->vd.show_screen_cookie = &sc->sc_gc; 728 sc->vd.show_screen_cb = glyphcache_adapt; 729 730 sc->sc_gc.gc_bitblt = mach64_bitblt; 731 sc->sc_gc.gc_blitcookie = sc; 732 sc->sc_gc.gc_rop = MIX_SRC; 733 734 ri = &mach64_console_screen.scr_ri; 735 if (sc->sc_console) { 736 737 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 738 &defattr); 739 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 740 741 mach64_defaultscreen.textops = &ri->ri_ops; 742 mach64_defaultscreen.capabilities = ri->ri_caps; 743 mach64_defaultscreen.nrows = ri->ri_rows; 744 mach64_defaultscreen.ncols = ri->ri_cols; 745 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 746 ((sc->memsize * 1024) / sc->stride) - 747 sc->sc_my_mode->vdisplay - 5, 748 sc->stride, 749 ri->ri_font->fontwidth, 750 ri->ri_font->fontheight, 751 defattr); 752 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 753 } else { 754 /* 755 * since we're not the console we can postpone the rest 756 * until someone actually allocates a screen for us 757 */ 758 if (mach64_console_screen.scr_ri.ri_rows == 0) { 759 /* do some minimal setup to avoid weirdnesses later */ 760 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 761 &defattr); 762 } else 763 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 764 765 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 766 ((sc->memsize * 1024) / sc->stride) - 767 sc->sc_my_mode->vdisplay - 5, 768 sc->stride, 769 ri->ri_font->fontwidth, 770 ri->ri_font->fontheight, 771 defattr); 772 } 773 774 sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG]; 775 mach64_clearscreen(sc); 776 mach64_init_lut(sc); 777 778 if (sc->sc_console) 779 vcons_replay_msgbuf(&mach64_console_screen); 780 781 machfb_blank(sc, 0); /* unblank the screen */ 782 783 aa.console = sc->sc_console; 784 aa.scrdata = &mach64_screenlist; 785 aa.accessops = &sc->sc_accessops; 786 aa.accesscookie = &sc->vd; 787 788 config_found(self, &aa, wsemuldisplaydevprint, 789 CFARGS(.iattr = "wsemuldisplaydev")); 790 #if 0 791 /* XXX 792 * turns out some firmware doesn't turn these back on when needed 793 * so we need to turn them off only when mapping vram in 794 * WSDISPLAYIO_MODE_DUMB would overlap ( unlikely but far from 795 * impossible ) 796 */ 797 if (use_mmio) { 798 /* 799 * Now that we took over, turn off the aperture registers if we 800 * don't use them. Can't do this earlier since on some hardware 801 * we use firmware calls as early console output which may in 802 * turn try to access these registers. 803 */ 804 reg = regr(sc, BUS_CNTL); 805 aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg); 806 reg |= BUS_APER_REG_DIS; 807 regw(sc, BUS_CNTL, reg); 808 } 809 #endif 810 config_found(self, aux, machfb_drm_print, 811 CFARGS(.iattr = "drm")); 812 } 813 814 static int 815 machfb_drm_print(void *aux, const char *pnp) 816 { 817 if (pnp) 818 aprint_normal("direct rendering for %s", pnp); 819 return (UNSUPP); 820 } 821 822 static void 823 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 824 long *defattr) 825 { 826 struct mach64_softc *sc = cookie; 827 struct rasops_info *ri = &scr->scr_ri; 828 829 ri->ri_depth = sc->bits_per_pixel; 830 ri->ri_width = sc->sc_my_mode->hdisplay; 831 ri->ri_height = sc->sc_my_mode->vdisplay; 832 ri->ri_stride = sc->stride; 833 ri->ri_flg = RI_CENTER | RI_FULLCLEAR; 834 if (ri->ri_depth == 8) 835 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA | 836 RI_PREFER_ALPHA; 837 838 #ifdef VCONS_DRAW_INTR 839 scr->scr_flags |= VCONS_DONT_READ; 840 #endif 841 scr->scr_flags |= VCONS_LOADFONT; 842 843 rasops_init(ri, 0, 0); 844 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE | 845 WSSCREEN_RESIZE; 846 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 847 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 848 849 /* enable acceleration */ 850 ri->ri_hw = scr; 851 ri->ri_ops.copyrows = mach64_copyrows; 852 ri->ri_ops.copycols = mach64_copycols; 853 ri->ri_ops.eraserows = mach64_eraserows; 854 ri->ri_ops.erasecols = mach64_erasecols; 855 ri->ri_ops.cursor = mach64_cursor; 856 if (FONT_IS_ALPHA(ri->ri_font)) { 857 ri->ri_ops.putchar = mach64_putchar_aa8; 858 } else 859 ri->ri_ops.putchar = mach64_putchar_mono; 860 } 861 862 static void 863 mach64_init(struct mach64_softc *sc) 864 { 865 sc->sc_blanked = 0; 866 } 867 868 static int 869 mach64_get_memsize(struct mach64_softc *sc) 870 { 871 int tmp, memsize; 872 int mem_tab[] = { 873 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 874 }; 875 tmp = regr(sc, MEM_CNTL); 876 #ifdef DIAGNOSTIC 877 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 878 #endif 879 if (sc->has_dsp) { 880 tmp &= 0x0000000f; 881 if (tmp < 8) 882 memsize = (tmp + 1) * 512; 883 else if (tmp < 12) 884 memsize = (tmp - 3) * 1024; 885 else 886 memsize = (tmp - 7) * 2048; 887 } else { 888 memsize = mem_tab[tmp & 0x07]; 889 } 890 891 return memsize; 892 } 893 894 static int 895 mach64_get_max_ramdac(struct mach64_softc *sc) 896 { 897 int i; 898 899 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 900 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 901 (mach64_chip_rev & 0x07)) 902 return 170000; 903 904 for (i = 0; i < __arraycount(mach64_info); i++) 905 if (mach64_chip_id == mach64_info[i].chip_id) 906 return mach64_info[i].ramdac_freq; 907 908 if (sc->bits_per_pixel == 8) 909 return 135000; 910 else 911 return 80000; 912 } 913 914 static int 915 mach64_ref_freq(void) 916 { 917 /* 918 * There doesn't seem to be any way to calculate the reference 919 * frequency from known values 920 */ 921 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 922 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 923 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI))) 924 return 29498; 925 else 926 return 14318; 927 } 928 929 #ifdef MACHFB_DEBUG 930 static void 931 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 932 { 933 int htotal, hdisplay, hsync_start, hsync_end; 934 int vtotal, vdisplay, vsync_start, vsync_end; 935 int clk_ctl, clock; 936 int ref_freq, ref_div, vclk_post_div, vclk_fb_div; 937 int nhsync, nvsync; 938 int post_div, dot_clock, vrefresh, vrefresh2; 939 940 hdisplay = regr(sc, CRTC_H_TOTAL_DISP); 941 hsync_end = regr(sc, CRTC_H_SYNC_STRT_WID); 942 vdisplay = regr(sc, CRTC_V_TOTAL_DISP); 943 vsync_end = regr(sc, CRTC_V_SYNC_STRT_WID); 944 clk_ctl = regr(sc, CLOCK_CNTL); 945 clock = clk_ctl & 3; 946 ref_div = regrb_pll(sc, PLL_REF_DIV); 947 vclk_post_div = regrb_pll(sc, VCLK_POST_DIV); 948 vclk_fb_div = regrb_pll(sc, VCLK0_FB_DIV + clock); 949 ref_freq = mach64_ref_freq(); 950 951 htotal = ((hdisplay & 0x01ff) + 1) << 3; 952 hdisplay = (((hdisplay & 0x1ff0000) >> 16) + 1) << 3; 953 if (hsync_end & CRTC_HSYNC_NEG) 954 nhsync = 1; 955 else 956 nhsync = 0; 957 hsync_start = (((hsync_end & 0xff) + 1) << 3) + 958 ((hsync_end & 0x700) >> 8); 959 hsync_end = (((hsync_end & 0x1f0000) >> 16) << 3) + hsync_start; 960 961 vtotal = (vdisplay & 0x07ff) + 1; 962 vdisplay = ((vdisplay & 0x7ff0000) >> 16) + 1; 963 if (vsync_end & CRTC_VSYNC_NEG) 964 nvsync = 1; 965 else 966 nvsync = 0; 967 vsync_start = (vsync_end & 0x07ff) + 1; 968 vsync_end = ((vsync_end & 0x1f0000) >> 16) + vsync_start; 969 970 switch ((vclk_post_div >> (clock * 2)) & 3) { 971 case 3: 972 post_div = 8; 973 break; 974 case 2: 975 post_div = 4; 976 break; 977 case 1: 978 post_div = 2; 979 break; 980 default: 981 post_div = 1; 982 break; 983 } 984 dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div); 985 vrefresh = (dot_clock * 1000) / (htotal * vtotal); 986 vrefresh2 = ((dot_clock * 1000) - (vrefresh * htotal * vtotal)) * 100 / 987 (htotal * vtotal); 988 989 aprint_normal_dev(sc->sc_dev, "Video mode:\n"); 990 aprint_normal("\t%d" "x%d @ %d.%02dHz " 991 "(%d %d %d %d %d %d %d %cH %cV)\n", 992 hdisplay, vdisplay, vrefresh, vrefresh2, dot_clock, 993 hsync_start, hsync_end, htotal, vsync_start, vsync_end, vtotal, 994 nhsync == 1 ? '-' : '+', nvsync == 1 ? '-' : '+'); 995 996 if (mode != NULL) { 997 mode->dot_clock = dot_clock; 998 mode->htotal = htotal; 999 mode->hdisplay = hdisplay; 1000 mode->hsync_start = hsync_start; 1001 mode->hsync_end = hsync_end; 1002 mode->vtotal = vtotal; 1003 mode->vdisplay = vdisplay; 1004 mode->vsync_start = vsync_start; 1005 mode->vsync_end = vsync_end; 1006 mode->flags = 0; 1007 if (nhsync) 1008 mode->flags |= VID_NHSYNC; 1009 if (nvsync) 1010 mode->flags |= VID_NVSYNC; 1011 } 1012 } 1013 1014 static void 1015 mach64_print_reg(struct mach64_softc *sc) 1016 { 1017 struct reglist { 1018 int offset; 1019 const char *name; 1020 }; 1021 static const struct reglist reglist_tab[] = { 1022 { 0x0000, "CRTC_H_TOTAL_DISP" }, 1023 { 0x0004, "CRTC_H_SYNC_STRT_WID" }, 1024 { 0x0008, "CRTC_V_TOTAL_DISP" }, 1025 { 0x000C, "CRTC_V_SYNC_STRT_WID" }, 1026 { 0x0010, "CRTC_VLINE_CRNT_VLINE" }, 1027 { 0x0014, "CRTC_OFF_PITCH" }, 1028 { 0x001C, "CRTC_GEN_CNTL" }, 1029 { 0x0090, "CLOCK_CNTL" }, 1030 { 0, NULL } 1031 }; 1032 static const struct reglist plllist_tab[] = { 1033 { 0x02, "PLL_REF_DIV" }, 1034 { 0x03, "PLL_GEN_CNTL" }, 1035 { 0x04, "MCLK_FB_DIV" }, 1036 { 0x05, "PLL_VCLK_CNTL" }, 1037 { 0x06, "VCLK_POST_DIV" }, 1038 { 0x07, "VCLK0_FB_DIV" }, 1039 { 0x08, "VCLK1_FB_DIV" }, 1040 { 0x09, "VCLK2_FB_DIV" }, 1041 { 0x0A, "VCLK3_FB_DIV" }, 1042 { 0x0B, "PLL_XCLK_CNTL" }, 1043 { 0x10, "LVDSPLL_CNTL0" }, 1044 { 0x11, "LVDSPLL_CNTL0" }, 1045 { 0x19, "EXT_VPLL_CNTL" }, 1046 { 0x1A, "EXT_VPLL_REF_DIV" }, 1047 { 0x1B, "EXT_VPLL_FB_DIV" }, 1048 { 0x1C, "EXT_VPLL_MSB" }, 1049 { 0, NULL } 1050 }; 1051 const struct reglist *r; 1052 1053 aprint_normal("CRTC registers\n"); 1054 for (r = reglist_tab; r->name != NULL; r++) 1055 aprint_normal("0x%04x 0x%08x %s\n", r->offset, 1056 regr(sc, r->offset), r->name); 1057 aprint_normal("PLL registers\n"); 1058 for (r = plllist_tab; r->name != NULL; r++) 1059 aprint_normal("0x%02x 0x%02x %s\n", r->offset, 1060 regrb_pll(sc, r->offset), r->name); 1061 } 1062 #endif 1063 1064 static int 1065 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 1066 struct videomode *mode) 1067 { 1068 1069 if (mode->dot_clock > sc->ramdac_freq) 1070 /* Clock too high. */ 1071 return 1; 1072 1073 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 1074 ((mode->htotal >> 3) - 1); 1075 crtc->h_sync_strt_wid = 1076 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 1077 ((mode->hsync_start >> 3) - 1) | ((mode->hsync_start & 7) << 8); 1078 1079 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 1080 (mode->vtotal - 1); 1081 crtc->v_sync_strt_wid = 1082 ((mode->vsync_end - mode->vsync_start) << 16) | 1083 (mode->vsync_start - 1); 1084 1085 if (mode->flags & VID_NVSYNC) 1086 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 1087 1088 switch (sc->bits_per_pixel) { 1089 case 8: 1090 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 1091 break; 1092 case 16: 1093 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 1094 break; 1095 case 32: 1096 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 1097 break; 1098 } 1099 1100 crtc->gen_cntl = 0; 1101 if (mode->flags & VID_INTERLACE) 1102 crtc->gen_cntl |= CRTC_INTERLACE_EN; 1103 1104 if (mode->flags & VID_CSYNC) 1105 crtc->gen_cntl |= CRTC_CSYNC_EN; 1106 1107 crtc->dot_clock = mode->dot_clock; 1108 1109 return 0; 1110 } 1111 1112 static void 1113 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1114 { 1115 1116 mach64_set_pll(sc, crtc->dot_clock); 1117 1118 if (sc->has_dsp) 1119 mach64_set_dsp(sc); 1120 1121 DPRINTF("\th total: 0x%08x h sync: 0x%08x\n", 1122 crtc->h_total_disp, crtc->h_sync_strt_wid); 1123 DPRINTF("\tv total: 0x%08x v sync: 0x%08x\n", 1124 crtc->v_total_disp, crtc->v_sync_strt_wid); 1125 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1126 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1127 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1128 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1129 1130 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1131 1132 regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22); 1133 1134 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1135 sc->sc_gen_cntl | CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1136 } 1137 1138 static int 1139 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1140 { 1141 struct mach64_crtcregs crtc; 1142 1143 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1144 1145 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1146 return 1; 1147 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1148 if (crtc.dot_clock == 0) { 1149 aprint_error("%s: preposterous dot clock (%d)\n", 1150 device_xname(sc->sc_dev), crtc.dot_clock); 1151 return 1; 1152 } 1153 mach64_set_crtcregs(sc, &crtc); 1154 return 0; 1155 } 1156 1157 static void 1158 mach64_reset_engine(struct mach64_softc *sc) 1159 { 1160 1161 /* Reset engine.*/ 1162 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1163 1164 /* Enable engine. */ 1165 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1166 1167 /* Ensure engine is not locked up by clearing any FIFO or 1168 host errors. */ 1169 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1170 BUS_FIFO_ERR_ACK); 1171 } 1172 1173 static void 1174 mach64_init_engine(struct mach64_softc *sc) 1175 { 1176 uint32_t pitch_value; 1177 1178 pitch_value = sc->stride; 1179 1180 if (sc->bits_per_pixel == 24) 1181 pitch_value *= 3; 1182 1183 mach64_reset_engine(sc); 1184 1185 wait_for_fifo(sc, 14); 1186 1187 regw(sc, CONTEXT_MASK, 0xffffffff); 1188 1189 regw(sc, DST_OFF_PITCH, (pitch_value >> 3) << 22); 1190 1191 /* make sure the visible area starts where we're going to draw */ 1192 regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22); 1193 1194 regw(sc, DST_Y_X, 0); 1195 regw(sc, DST_HEIGHT, 0); 1196 regw(sc, DST_BRES_ERR, 0); 1197 regw(sc, DST_BRES_INC, 0); 1198 regw(sc, DST_BRES_DEC, 0); 1199 1200 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1201 DST_Y_TOP_TO_BOTTOM); 1202 1203 regw(sc, SRC_OFF_PITCH, (pitch_value >> 3) << 22); 1204 1205 regw(sc, SRC_Y_X, 0); 1206 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1207 regw(sc, SRC_Y_X_START, 0); 1208 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1209 1210 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1211 1212 wait_for_fifo(sc, 13); 1213 regw(sc, HOST_CNTL, 0); 1214 1215 regw(sc, PAT_REG0, 0); 1216 regw(sc, PAT_REG1, 0); 1217 regw(sc, PAT_CNTL, 0); 1218 1219 regw(sc, SC_LEFT, 0); 1220 regw(sc, SC_TOP, 0); 1221 regw(sc, SC_BOTTOM, 0x3fff); 1222 regw(sc, SC_RIGHT, pitch_value - 1); 1223 1224 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1225 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1226 regw(sc, DP_WRITE_MASK, 0xffffffff); 1227 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1228 1229 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1230 1231 wait_for_fifo(sc, 3); 1232 regw(sc, CLR_CMP_CLR, 0); 1233 regw(sc, CLR_CMP_MASK, 0xffffffff); 1234 regw(sc, CLR_CMP_CNTL, 0); 1235 1236 wait_for_fifo(sc, 3); 1237 switch (sc->bits_per_pixel) { 1238 case 8: 1239 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1240 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1241 /* We want 8 bit per channel */ 1242 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1243 break; 1244 case 32: 1245 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1246 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1247 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1248 break; 1249 } 1250 regw(sc, DP_WRITE_MASK, 0xff); 1251 1252 wait_for_fifo(sc, 5); 1253 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1254 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1255 1256 wait_for_idle(sc); 1257 } 1258 1259 #if 0 1260 static void 1261 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1262 { 1263 int offset; 1264 1265 offset = ((x + y * sc->stride) * (sc->bits_per_pixel >> 3)) >> 3; 1266 1267 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1268 offset); 1269 } 1270 #endif 1271 1272 static void 1273 mach64_set_dsp(struct mach64_softc *sc) 1274 { 1275 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1276 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1277 uint32_t xclks_per_qw, xclks_per_qw_m, y; 1278 uint32_t fifo_off, fifo_on; 1279 1280 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1281 1282 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1283 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1284 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1285 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1286 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1287 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1288 dsp_loop_latency = 0; 1289 fifo_depth = 24; 1290 } else { 1291 dsp_loop_latency = 2; 1292 fifo_depth = 32; 1293 } 1294 1295 dsp_precision = 0; 1296 1297 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1298 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1299 1300 xclks_per_qw_m = (sc->mem_freq * 64 << 4) / 1301 (sc->vclk_freq * sc->bits_per_pixel); 1302 1303 DPRINTF("xclks_per_qw %d %d\n", xclks_per_qw >> 7, xclks_per_qw_m); 1304 DPRINTF("mem %dkHz v %dkHz\n", sc->mem_freq, sc->vclk_freq); 1305 1306 y = (xclks_per_qw * fifo_depth) >> 11; 1307 1308 while (y) { 1309 y >>= 1; 1310 dsp_precision++; 1311 } 1312 dsp_precision -= 5; 1313 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1314 1315 switch (sc->memtype) { 1316 case DRAM: 1317 case EDO_DRAM: 1318 case PSEUDO_EDO: 1319 if (sc->memsize > 1024) { 1320 page_size = 9; 1321 dsp_loop_latency += 6; 1322 } else { 1323 page_size = 10; 1324 if (sc->memtype == DRAM) 1325 dsp_loop_latency += 8; 1326 else 1327 dsp_loop_latency += 7; 1328 } 1329 break; 1330 case SDRAM: 1331 if (sc->memsize > 1024) { 1332 page_size = 8; 1333 dsp_loop_latency += 8; 1334 } else { 1335 page_size = 10; 1336 dsp_loop_latency += 9; 1337 } 1338 break; 1339 case SGRAM: 1340 page_size = 8; 1341 dsp_loop_latency = 8; 1342 break; 1343 default: 1344 page_size = 10; 1345 dsp_loop_latency += 9; 1346 break; 1347 } 1348 1349 if (xclks_per_qw >= (page_size << 11)) 1350 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1351 else 1352 fifo_on = (3 * page_size + 2) << 6; 1353 1354 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1355 dsp_on = fifo_on >> dsp_precision; 1356 dsp_off = fifo_off >> dsp_precision; 1357 1358 DPRINTF("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1359 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1360 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1361 "mclk_post_div = %d, vclk_post_div = %d\n", 1362 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1363 sc->mclk_fb_div, sc->vclk_fb_div, 1364 sc->mclk_post_div, sc->vclk_post_div); 1365 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1366 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1367 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1368 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1369 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1370 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1371 DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF)); 1372 DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG)); 1373 } 1374 1375 static void 1376 mach64_set_pll(struct mach64_softc *sc, int clock) 1377 { 1378 uint32_t q, clockreg; 1379 int clockshift = sc->sc_clock << 1; 1380 uint8_t reg, vclk_ctl; 1381 1382 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1383 #ifdef MACHFB_DEBUG 1384 printf("q = %d\n", q); 1385 #endif 1386 if (q > 25500) { 1387 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1388 q = 25500; 1389 sc->vclk_post_div = 1; 1390 sc->log2_vclk_post_div = 0; 1391 } else if (q > 12750) { 1392 sc->vclk_post_div = 1; 1393 sc->log2_vclk_post_div = 0; 1394 } else if (q > 6350) { 1395 sc->vclk_post_div = 2; 1396 sc->log2_vclk_post_div = 1; 1397 } else if (q > 3150) { 1398 sc->vclk_post_div = 4; 1399 sc->log2_vclk_post_div = 2; 1400 } else if (q >= 1600) { 1401 sc->vclk_post_div = 8; 1402 sc->log2_vclk_post_div = 3; 1403 } else { 1404 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1405 sc->vclk_post_div = 8; 1406 sc->log2_vclk_post_div = 3; 1407 } 1408 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1409 DPRINTF("post_div: %d log2_post_div: %d mclk_div: %d\n", 1410 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1411 1412 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1413 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1414 vclk_ctl |= PLL_VCLK_RESET; 1415 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1416 1417 DPRINTF("target: %d output: %d\n", clock, 1418 (2 * sc->ref_freq * sc->vclk_fb_div) / 1419 (sc->ref_div * sc->vclk_post_div)); 1420 1421 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1422 reg = regrb_pll(sc, VCLK_POST_DIV); 1423 reg &= ~(3 << clockshift); 1424 reg |= (sc->log2_vclk_post_div << clockshift); 1425 regwb_pll(sc, VCLK_POST_DIV, reg); 1426 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1427 1428 vclk_ctl &= ~PLL_VCLK_RESET; 1429 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1430 1431 clockreg = regr(sc, CLOCK_CNTL); 1432 clockreg &= ~CLOCK_SEL; 1433 clockreg |= sc->sc_clock | CLOCK_STROBE; 1434 regw(sc, CLOCK_CNTL, clockreg); 1435 sc->vclk_freq = clock; 1436 } 1437 1438 static void 1439 mach64_init_lut(struct mach64_softc *sc) 1440 { 1441 uint8_t cmap[768]; 1442 int i, idx; 1443 1444 rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap)); 1445 idx = 0; 1446 for (i = 0; i < 256; i++) { 1447 mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1], 1448 cmap[idx + 2]); 1449 idx += 3; 1450 } 1451 } 1452 1453 static int 1454 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1455 uint8_t b) 1456 { 1457 sc->sc_cmap_red[index] = r; 1458 sc->sc_cmap_green[index] = g; 1459 sc->sc_cmap_blue[index] = b; 1460 /* 1461 * writing the dac index takes a while, in theory we can poll some 1462 * register to see when it's ready - but we better avoid writing it 1463 * unnecessarily 1464 */ 1465 if (index != sc->sc_dacw) { 1466 regwb(sc, DAC_MASK, 0xff); 1467 regwb(sc, DAC_WINDEX, index); 1468 } 1469 sc->sc_dacw = index + 1; 1470 regwb(sc, DAC_DATA, r); 1471 regwb(sc, DAC_DATA, g); 1472 regwb(sc, DAC_DATA, b); 1473 return 0; 1474 } 1475 1476 static int 1477 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1478 { 1479 uint index = cm->index; 1480 uint count = cm->count; 1481 int i, error; 1482 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1483 uint8_t *r, *g, *b; 1484 1485 if (cm->index >= 256 || cm->count > 256 || 1486 (cm->index + cm->count) > 256) 1487 return EINVAL; 1488 error = copyin(cm->red, &rbuf[index], count); 1489 if (error) 1490 return error; 1491 error = copyin(cm->green, &gbuf[index], count); 1492 if (error) 1493 return error; 1494 error = copyin(cm->blue, &bbuf[index], count); 1495 if (error) 1496 return error; 1497 1498 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1499 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1500 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1501 1502 r = &sc->sc_cmap_red[index]; 1503 g = &sc->sc_cmap_green[index]; 1504 b = &sc->sc_cmap_blue[index]; 1505 1506 for (i = 0; i < count; i++) { 1507 mach64_putpalreg(sc, index, *r, *g, *b); 1508 index++; 1509 r++, g++, b++; 1510 } 1511 return 0; 1512 } 1513 1514 static int 1515 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1516 { 1517 u_int index = cm->index; 1518 u_int count = cm->count; 1519 int error; 1520 1521 if (index >= 255 || count > 256 || index + count > 256) 1522 return EINVAL; 1523 1524 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1525 if (error) 1526 return error; 1527 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1528 if (error) 1529 return error; 1530 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1531 if (error) 1532 return error; 1533 1534 return 0; 1535 } 1536 1537 static int 1538 mach64_is_console(struct mach64_softc *sc) 1539 { 1540 bool console = 0; 1541 1542 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1543 "is_console", &console); 1544 return console; 1545 } 1546 1547 /* 1548 * wsdisplay_emulops 1549 */ 1550 1551 static void 1552 mach64_cursor(void *cookie, int on, int row, int col) 1553 { 1554 struct rasops_info *ri = cookie; 1555 struct vcons_screen *scr = ri->ri_hw; 1556 struct mach64_softc *sc = scr->scr_cookie; 1557 int x, y, wi, he; 1558 1559 wi = ri->ri_font->fontwidth; 1560 he = ri->ri_font->fontheight; 1561 1562 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1563 x = ri->ri_ccol * wi + ri->ri_xorigin; 1564 y = ri->ri_crow * he + ri->ri_yorigin; 1565 if (ri->ri_flg & RI_CURSOR) { 1566 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1567 ri->ri_flg &= ~RI_CURSOR; 1568 } 1569 ri->ri_crow = row; 1570 ri->ri_ccol = col; 1571 if (on) { 1572 x = ri->ri_ccol * wi + ri->ri_xorigin; 1573 y = ri->ri_crow * he + ri->ri_yorigin; 1574 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1575 ri->ri_flg |= RI_CURSOR; 1576 } 1577 } else { 1578 scr->scr_ri.ri_crow = row; 1579 scr->scr_ri.ri_ccol = col; 1580 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1581 } 1582 } 1583 1584 #if 0 1585 static int 1586 mach64_mapchar(void *cookie, int uni, u_int *index) 1587 { 1588 return 0; 1589 } 1590 #endif 1591 1592 static void 1593 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1594 { 1595 struct rasops_info *ri = cookie; 1596 struct wsdisplay_font *font = PICK_FONT(ri, c); 1597 struct vcons_screen *scr = ri->ri_hw; 1598 struct mach64_softc *sc = scr->scr_cookie; 1599 1600 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1601 int fg, bg, uc; 1602 uint8_t *data; 1603 int x, y, wi, he; 1604 wi = font->fontwidth; 1605 he = font->fontheight; 1606 1607 if (!CHAR_IN_FONT(c, font)) 1608 return; 1609 bg = ri->ri_devcmap[(attr >> 16) & 0x0f]; 1610 fg = ri->ri_devcmap[(attr >> 24) & 0x0f]; 1611 x = ri->ri_xorigin + col * wi; 1612 y = ri->ri_yorigin + row * he; 1613 if (c == 0x20) { 1614 mach64_rectfill(sc, x, y, wi, he, bg); 1615 } else { 1616 uc = c - font->firstchar; 1617 data = (uint8_t *)font->data + uc * 1618 ri->ri_fontscale; 1619 1620 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1621 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1622 } 1623 if (attr & 1) 1624 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1625 } 1626 } 1627 1628 static void 1629 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 1630 { 1631 struct rasops_info *ri = cookie; 1632 struct wsdisplay_font *font = PICK_FONT(ri, c); 1633 struct vcons_screen *scr = ri->ri_hw; 1634 struct mach64_softc *sc = scr->scr_cookie; 1635 uint32_t bg, fg, latch = 0, bg8, fg8, pixel; 1636 int i, x, y, wi, he, r, g, b, aval; 1637 int r1, g1, b1, r0, g0, b0, fgo, bgo; 1638 uint8_t *data8; 1639 int rv = 0, cnt = 0; 1640 1641 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1642 return; 1643 1644 if (!CHAR_IN_FONT(c, font)) 1645 return; 1646 1647 wi = font->fontwidth; 1648 he = font->fontheight; 1649 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1650 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1651 x = ri->ri_xorigin + col * wi; 1652 y = ri->ri_yorigin + row * he; 1653 1654 if (c == 0x20) { 1655 mach64_rectfill(sc, x, y, wi, he, bg); 1656 if (attr & 1) 1657 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1658 return; 1659 } 1660 1661 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1662 if (rv == GC_OK) 1663 return; 1664 1665 data8 = WSFONT_GLYPH(c, font); 1666 1667 wait_for_fifo(sc, 11); 1668 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1669 regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST); 1670 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1671 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1672 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1673 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1674 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1675 regw(sc, SRC_Y_X, 0); 1676 regw(sc, SRC_WIDTH1, wi); 1677 regw(sc, DST_Y_X, (x << 16) | y); 1678 regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he); 1679 1680 /* 1681 * we need the RGB colours here, so get offsets into rasops_cmap 1682 */ 1683 fgo = ((attr >> 24) & 0xf) * 3; 1684 bgo = ((attr >> 16) & 0xf) * 3; 1685 1686 r0 = rasops_cmap[bgo]; 1687 r1 = rasops_cmap[fgo]; 1688 g0 = rasops_cmap[bgo + 1]; 1689 g1 = rasops_cmap[fgo + 1]; 1690 b0 = rasops_cmap[bgo + 2]; 1691 b1 = rasops_cmap[fgo + 2]; 1692 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 1693 bg8 = R3G3B2(r0, g0, b0); 1694 fg8 = R3G3B2(r1, g1, b1); 1695 1696 wait_for_fifo(sc, 10); 1697 1698 for (i = 0; i < ri->ri_fontscale; i++) { 1699 aval = *data8; 1700 if (aval == 0) { 1701 pixel = bg8; 1702 } else if (aval == 255) { 1703 pixel = fg8; 1704 } else { 1705 r = aval * r1 + (255 - aval) * r0; 1706 g = aval * g1 + (255 - aval) * g0; 1707 b = aval * b1 + (255 - aval) * b0; 1708 pixel = ((r & 0xe000) >> 8) | 1709 ((g & 0xe000) >> 11) | 1710 ((b & 0xc000) >> 14); 1711 } 1712 latch = (latch << 8) | pixel; 1713 /* write in 32bit chunks */ 1714 if ((i & 3) == 3) { 1715 regws(sc, HOST_DATA0, latch); 1716 /* 1717 * not strictly necessary, old data should be shifted 1718 * out 1719 */ 1720 latch = 0; 1721 cnt++; 1722 if (cnt > 8) { 1723 wait_for_fifo(sc, 10); 1724 cnt = 0; 1725 } 1726 } 1727 data8++; 1728 } 1729 /* if we have pixels left in latch write them out */ 1730 if ((i & 3) != 0) { 1731 latch = latch << ((4 - (i & 3)) << 3); 1732 regws(sc, HOST_DATA0, latch); 1733 } 1734 1735 if (rv == GC_ADD) { 1736 glyphcache_add(&sc->sc_gc, c, x, y); 1737 } else if (attr & 1) { 1738 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1739 } 1740 1741 } 1742 1743 static void 1744 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1745 { 1746 struct rasops_info *ri = cookie; 1747 struct vcons_screen *scr = ri->ri_hw; 1748 struct mach64_softc *sc = scr->scr_cookie; 1749 int32_t xs, xd, y, width, height; 1750 1751 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1752 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1753 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1754 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1755 width = ri->ri_font->fontwidth * ncols; 1756 height = ri->ri_font->fontheight; 1757 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC); 1758 } 1759 } 1760 1761 static void 1762 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1763 { 1764 struct rasops_info *ri = cookie; 1765 struct vcons_screen *scr = ri->ri_hw; 1766 struct mach64_softc *sc = scr->scr_cookie; 1767 int32_t x, y, width, height, fg, bg, ul; 1768 1769 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1770 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1771 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1772 width = ri->ri_font->fontwidth * ncols; 1773 height = ri->ri_font->fontheight; 1774 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1775 1776 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1777 } 1778 } 1779 1780 static void 1781 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1782 { 1783 struct rasops_info *ri = cookie; 1784 struct vcons_screen *scr = ri->ri_hw; 1785 struct mach64_softc *sc = scr->scr_cookie; 1786 int32_t x, ys, yd, width, height; 1787 1788 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1789 x = ri->ri_xorigin; 1790 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1791 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1792 width = ri->ri_emuwidth; 1793 height = ri->ri_font->fontheight*nrows; 1794 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC); 1795 } 1796 } 1797 1798 static void 1799 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1800 { 1801 struct rasops_info *ri = cookie; 1802 struct vcons_screen *scr = ri->ri_hw; 1803 struct mach64_softc *sc = scr->scr_cookie; 1804 int32_t x, y, width, height, fg, bg, ul; 1805 1806 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1807 if ((row == 0) && (nrows == ri->ri_rows)) { 1808 /* clear full screen */ 1809 x = 0; 1810 y = 0; 1811 width = sc->virt_x; 1812 height = sc->virt_y; 1813 } else { 1814 x = ri->ri_xorigin; 1815 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1816 width = ri->ri_emuwidth; 1817 height = ri->ri_font->fontheight * nrows; 1818 } 1819 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1820 1821 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1822 } 1823 } 1824 1825 static void 1826 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width, 1827 int height, int rop) 1828 { 1829 struct mach64_softc *sc = cookie; 1830 uint32_t dest_ctl = 0; 1831 1832 #if 0 1833 wait_for_idle(sc); 1834 #else 1835 wait_for_fifo(sc, 10); 1836 #endif 1837 1838 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1839 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1840 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1841 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1842 if (yd < ys) { 1843 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1844 } else { 1845 ys += height - 1; 1846 yd += height - 1; 1847 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1848 } 1849 if (xd < xs) { 1850 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1851 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1852 } else { 1853 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1854 xs += width - 1; 1855 xd += width - 1; 1856 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1857 } 1858 regw(sc, DST_CNTL, dest_ctl); 1859 1860 regw(sc, SRC_Y_X, (xs << 16) | ys); 1861 regw(sc, SRC_WIDTH1, width); 1862 regw(sc, DST_Y_X, (xd << 16) | yd); 1863 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1864 } 1865 1866 static void 1867 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1868 int height, uint32_t fg, uint32_t bg) 1869 { 1870 wait_for_idle(sc); 1871 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1872 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1873 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1874 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1875 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1876 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1877 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1878 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1879 regw(sc, DP_BKGD_CLR, bg); 1880 regw(sc, DP_FRGD_CLR, fg); 1881 regw(sc, SRC_Y_X, 0); 1882 regw(sc, SRC_WIDTH1, width); 1883 regw(sc, DST_Y_X, (xd << 16) | yd); 1884 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1885 /* now feed the data into the chip */ 1886 } 1887 1888 static void 1889 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1890 { 1891 int i; 1892 uint32_t latch = 0, bork; 1893 int shift = 0; 1894 int reg = 0; 1895 1896 for (i = 0; i < count; i++) { 1897 bork = data[i]; 1898 latch |= (bork << shift); 1899 if (shift == 24) { 1900 regw(sc, HOST_DATA0 + reg, latch); 1901 latch = 0; 1902 shift = 0; 1903 reg = (reg + 4) & 0x3c; 1904 } else 1905 shift += 8; 1906 } 1907 if (shift != 0) /* 24 */ 1908 regw(sc, HOST_DATA0 + reg, latch); 1909 } 1910 1911 1912 static void 1913 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1914 int colour) 1915 { 1916 wait_for_fifo(sc, 11); 1917 regw(sc, DP_FRGD_CLR, colour); 1918 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1919 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1920 regw(sc, DP_MIX, MIX_SRC << 16); 1921 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1922 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1923 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1924 1925 regw(sc, SRC_Y_X, (x << 16) | y); 1926 regw(sc, SRC_WIDTH1, width); 1927 regw(sc, DST_Y_X, (x << 16) | y); 1928 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1929 } 1930 1931 static void 1932 mach64_clearscreen(struct mach64_softc *sc) 1933 { 1934 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1935 } 1936 1937 1938 #if 0 1939 static void 1940 mach64_showpal(struct mach64_softc *sc) 1941 { 1942 int i, x = 0; 1943 1944 for (i = 0; i < 16; i++) { 1945 mach64_rectfill(sc, x, 0, 64, 64, i); 1946 x += 64; 1947 } 1948 } 1949 #endif 1950 1951 /* 1952 * wsdisplay_accessops 1953 */ 1954 1955 static int 1956 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1957 struct lwp *l) 1958 { 1959 struct vcons_data *vd = v; 1960 struct mach64_softc *sc = vd->cookie; 1961 struct wsdisplay_fbinfo *wdf; 1962 struct vcons_screen *ms = vd->active; 1963 1964 switch (cmd) { 1965 case WSDISPLAYIO_GTYPE: 1966 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1967 return 0; 1968 1969 case WSDISPLAYIO_LINEBYTES: 1970 *(u_int *)data = sc->stride * sc->bits_per_pixel / 8; 1971 return 0; 1972 1973 case WSDISPLAYIO_GINFO: 1974 wdf = (void *)data; 1975 wdf->height = sc->virt_y; 1976 wdf->width = sc->virt_x; 1977 wdf->depth = sc->bits_per_pixel; 1978 wdf->cmsize = 256; 1979 return 0; 1980 1981 case WSDISPLAYIO_GETCMAP: 1982 return mach64_getcmap(sc, 1983 (struct wsdisplay_cmap *)data); 1984 1985 case WSDISPLAYIO_PUTCMAP: 1986 return mach64_putcmap(sc, 1987 (struct wsdisplay_cmap *)data); 1988 1989 /* PCI config read/write passthrough. */ 1990 case PCI_IOC_CFGREAD: 1991 case PCI_IOC_CFGWRITE: 1992 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1993 cmd, data, flag, l); 1994 1995 case WSDISPLAYIO_GET_BUSID: 1996 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1997 sc->sc_pcitag, data); 1998 1999 case WSDISPLAYIO_SMODE: { 2000 int new_mode = *(int*)data; 2001 if (new_mode != sc->sc_mode) { 2002 sc->sc_mode = new_mode; 2003 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 2004 && (ms != NULL)) 2005 { 2006 /* restore initial video mode */ 2007 mach64_init(sc); 2008 mach64_init_engine(sc); 2009 mach64_init_lut(sc); 2010 if (sc->sc_setmode) 2011 mach64_modeswitch(sc, sc->sc_my_mode); 2012 mach64_clearscreen(sc); 2013 glyphcache_wipe(&sc->sc_gc); 2014 vcons_redraw_screen(ms); 2015 } 2016 } 2017 } 2018 return 0; 2019 case WSDISPLAYIO_GET_EDID: { 2020 struct wsdisplayio_edid_info *d = data; 2021 return wsdisplayio_get_edid(sc->sc_dev, d); 2022 } 2023 2024 case WSDISPLAYIO_GET_FBINFO: { 2025 struct wsdisplayio_fbinfo *fbi = data; 2026 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 2027 } 2028 } 2029 return EPASSTHROUGH; 2030 } 2031 2032 static paddr_t 2033 mach64_mmap(void *v, void *vs, off_t offset, int prot) 2034 { 2035 struct vcons_data *vd = v; 2036 struct mach64_softc *sc = vd->cookie; 2037 paddr_t pa; 2038 2039 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 2040 /* 2041 *'regular' framebuffer mmap()ing 2042 */ 2043 if (offset < (sc->memsize * 1024)) { 2044 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, 2045 offset, prot, BUS_SPACE_MAP_LINEAR); 2046 return pa; 2047 } 2048 } else if (sc->sc_mode == WSDISPLAYIO_MODE_MAPPED) { 2049 /* 2050 * restrict all other mappings to processes with superuser 2051 * privileges 2052 */ 2053 if (kauth_authorize_machdep(kauth_cred_get(), 2054 KAUTH_MACHDEP_UNMANAGEDMEM, 2055 NULL, NULL, NULL, NULL) != 0) { 2056 return -1; 2057 } 2058 if ((offset >= sc->sc_aperbase) && 2059 (offset < (sc->sc_aperbase + sc->sc_apersize))) { 2060 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2061 BUS_SPACE_MAP_LINEAR); 2062 return pa; 2063 } 2064 2065 if ((offset >= sc->sc_regbase) && 2066 (offset < (sc->sc_regbase + sc->sc_regsize))) { 2067 pa = bus_space_mmap(sc->sc_regt, offset, 0, prot, 2068 BUS_SPACE_MAP_LINEAR); 2069 return pa; 2070 } 2071 2072 if ((offset >= sc->sc_rom.vb_base) && 2073 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 2074 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 2075 BUS_SPACE_MAP_LINEAR); 2076 return pa; 2077 } 2078 2079 #ifdef PCI_MAGIC_IO_RANGE 2080 if ((offset >= PCI_MAGIC_IO_RANGE) && 2081 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 2082 return bus_space_mmap(sc->sc_iot, 2083 offset - PCI_MAGIC_IO_RANGE, 0, prot, 0); 2084 } 2085 #endif 2086 } 2087 return -1; 2088 } 2089 2090 #if 0 2091 static int 2092 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 2093 { 2094 2095 return 0; 2096 } 2097 #endif 2098 2099 void 2100 machfb_blank(struct mach64_softc *sc, int blank) 2101 { 2102 uint32_t reg; 2103 2104 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 2105 2106 switch (blank) 2107 { 2108 case 0: 2109 reg = regr(sc, CRTC_GEN_CNTL); 2110 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 2111 sc->sc_blanked = 0; 2112 break; 2113 case 1: 2114 reg = regr(sc, CRTC_GEN_CNTL); 2115 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 2116 sc->sc_blanked = 1; 2117 break; 2118 default: 2119 break; 2120 } 2121 } 2122
Indexes created Thu Oct 02 14:10:14 GMT 2025