machfb.c revision 1.14.2.2
1 /* $NetBSD: machfb.c,v 1.14.2.2 2004/08/03 10:49:09 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: machfb.c,v 1.14.2.2 2004/08/03 10:49:09 skrll Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/callout.h> 43 44 #ifdef __sparc__ 45 #include <machine/promlib.h> 46 #endif 47 48 #include <dev/ic/videomode.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 #include <dev/pci/pciio.h> 54 #include <dev/pci/machfbreg.h> 55 56 #include <dev/wscons/wsdisplayvar.h> 57 #include <dev/wscons/wsconsio.h> 58 #include <dev/wsfont/wsfont.h> 59 #include <dev/rasops/rasops.h> 60 61 #define MACH64_REG_SIZE 1024 62 #define MACH64_REG_OFF 0x7ffc00 63 64 #define NBARS 3 /* number of Mach64 PCI BARs */ 65 66 struct vga_bar { 67 bus_addr_t vb_base; 68 bus_size_t vb_size; 69 pcireg_t vb_type; 70 int vb_flags; 71 }; 72 73 struct mach64_softc { 74 struct device sc_dev; 75 pci_chipset_tag_t sc_pc; 76 pcitag_t sc_pcitag; 77 78 struct vga_bar sc_bars[NBARS]; 79 struct vga_bar sc_rom; 80 81 #define sc_aperbase sc_bars[0].vb_base 82 #define sc_apersize sc_bars[0].vb_size 83 84 #define sc_iobase sc_bars[1].vb_base 85 #define sc_iosize sc_bars[1].vb_size 86 87 #define sc_regbase sc_bars[2].vb_base 88 #define sc_regsize sc_bars[2].vb_size 89 90 bus_space_tag_t sc_regt; 91 bus_space_tag_t sc_memt; 92 bus_space_handle_t sc_regh; 93 bus_space_handle_t sc_memh; 94 95 size_t memsize; 96 int memtype; 97 98 int has_dsp; 99 int bits_per_pixel; 100 int max_x, max_y; 101 int virt_x, virt_y; 102 int color_depth; 103 104 int mem_freq; 105 int ramdac_freq; 106 int ref_freq; 107 108 int ref_div; 109 int log2_vclk_post_div; 110 int vclk_post_div; 111 int vclk_fb_div; 112 int mclk_post_div; 113 int mclk_fb_div; 114 115 struct mach64screen *wanted; 116 struct mach64screen *active; 117 void (*switchcb)(void *, int, int); 118 void *switchcbarg; 119 struct callout switch_callout; 120 LIST_HEAD(, mach64screen) screens; 121 const struct wsscreen_descr *currenttype; 122 }; 123 124 struct mach64screen { 125 struct rasops_info ri; 126 LIST_ENTRY(mach64screen) next; 127 struct mach64_softc *sc; 128 const struct wsscreen_descr *type; 129 int active; 130 u_int16_t *mem; 131 int dispoffset; 132 int mindispoffset; 133 int maxdispoffset; 134 135 int cursoron; 136 int cursorcol; 137 int cursorrow; 138 u_int16_t cursortmp; 139 }; 140 141 struct mach64_crtcregs { 142 u_int32_t h_total_disp; 143 u_int32_t h_sync_strt_wid; 144 u_int32_t v_total_disp; 145 u_int32_t v_sync_strt_wid; 146 u_int32_t gen_cntl; 147 u_int32_t clock_cntl; 148 u_int32_t color_depth; 149 u_int32_t dot_clock; 150 }; 151 152 struct { 153 u_int16_t chip_id; 154 u_int32_t ramdac_freq; 155 } mach64_info[] = { 156 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 157 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 158 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 159 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 160 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 161 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 162 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 163 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 164 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 165 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 166 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 167 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 168 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 169 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 176 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 177 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 178 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 179 }; 180 181 static int mach64_chip_id, mach64_chip_rev; 182 static struct videomode default_mode; 183 static struct mach64screen mach64_console_screen; 184 185 static char *mach64_memtype_names[] = { 186 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 187 "(unknown type)" 188 }; 189 190 struct videomode mach64_modes[] = { 191 /* 640x400 @ 70 Hz, 31.5 kHz */ 192 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 193 /* 640x480 @ 72 Hz, 36.5 kHz */ 194 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 195 /* 800x600 @ 72 Hz, 48.0 kHz */ 196 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 197 VID_PHSYNC | VID_PVSYNC }, 198 /* 1024x768 @ 70 Hz, 56.5 kHz */ 199 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 200 VID_NHSYNC | VID_NVSYNC }, 201 /* 1152x864 @ 70 Hz, 62.4 kHz */ 202 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 203 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 204 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 205 VID_NHSYNC | VID_NVSYNC } 206 }; 207 208 /* FIXME values are wrong! */ 209 const u_char mach64_cmap[16 * 3] = { 210 0x00, 0x00, 0x00, /* black */ 211 0x7f, 0x00, 0x00, /* red */ 212 0x00, 0x7f, 0x00, /* green */ 213 0x7f, 0x7f, 0x00, /* brown */ 214 0x00, 0x00, 0x7f, /* blue */ 215 0x7f, 0x00, 0x7f, /* magenta */ 216 0x00, 0x7f, 0x7f, /* cyan */ 217 0xff, 0xff, 0xff, /* white */ 218 219 0x7f, 0x7f, 0x7f, /* black */ 220 0xff, 0x00, 0x00, /* red */ 221 0x00, 0xff, 0x00, /* green */ 222 0xff, 0xff, 0x00, /* brown */ 223 0x00, 0x00, 0xff, /* blue */ 224 0xff, 0x00, 0xff, /* magenta */ 225 0x00, 0xff, 0xff, /* cyan */ 226 0xff, 0xff, 0xff, /* white */ 227 }; 228 229 int mach64_match(struct device *, struct cfdata *, void *); 230 void mach64_attach(struct device *, struct device *, void *); 231 232 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 233 NULL, NULL); 234 235 void mach64_init(struct mach64_softc *); 236 int mach64_get_memsize(struct mach64_softc *); 237 int mach64_get_max_ramdac(struct mach64_softc *); 238 void mach64_get_mode(struct mach64_softc *, struct videomode *); 239 int mach64_calc_crtcregs(struct mach64_softc *, struct mach64_crtcregs *, 240 struct videomode *); 241 void mach64_set_crtcregs(struct mach64_softc *, struct mach64_crtcregs *); 242 int mach64_modeswitch(struct mach64_softc *, struct videomode *); 243 void mach64_set_dsp(struct mach64_softc *); 244 void mach64_set_pll(struct mach64_softc *, int); 245 void mach64_reset_engine(struct mach64_softc *); 246 void mach64_init_engine(struct mach64_softc *); 247 void mach64_adjust_frame(struct mach64_softc *, int, int); 248 void mach64_init_lut(struct mach64_softc *); 249 void mach64_switch_screen(struct mach64_softc *); 250 void mach64_init_screen(struct mach64_softc *, struct mach64screen *, 251 const struct wsscreen_descr *, int, long *, int); 252 void mach64_restore_screen(struct mach64screen *, 253 const struct wsscreen_descr *, u_int16_t *); 254 int mach64_set_screentype(struct mach64_softc *, 255 const struct wsscreen_descr *); 256 int mach64_is_console(struct pci_attach_args *); 257 258 void mach64_cursor(void *, int, int, int); 259 int mach64_mapchar(void *, int, u_int *); 260 void mach64_putchar(void *, int, int, u_int, long); 261 void mach64_copycols(void *, int, int, int, int); 262 void mach64_erasecols(void *, int, int, int, long); 263 void mach64_copyrows(void *, int, int, int); 264 void mach64_eraserows(void *, int, int, long); 265 int mach64_allocattr(void *, int, int, int, long *); 266 267 #if 0 268 const struct wsdisplay_emulops mach64_emulops = { 269 mach64_cursor, 270 mach64_mapchar, 271 mach64_putchar, 272 mach64_copycols, 273 mach64_erasecols, 274 mach64_copyrows, 275 mach64_eraserows, 276 mach64_allocattr, 277 }; 278 #endif 279 280 struct wsscreen_descr mach64_defaultscreen = { 281 "default", 282 0, 0, 283 &mach64_console_screen.ri.ri_ops, 284 8, 16, 285 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 286 &default_mode 287 }, mach64_80x25_screen = { 288 "80x25", 80, 25, 289 &mach64_console_screen.ri.ri_ops, 290 8, 16, 291 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 292 &mach64_modes[0] 293 }, mach64_80x30_screen = { 294 "80x30", 80, 30, 295 &mach64_console_screen.ri.ri_ops, 296 8, 16, 297 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 298 &mach64_modes[1] 299 }, mach64_80x40_screen = { 300 "80x40", 80, 40, 301 &mach64_console_screen.ri.ri_ops, 302 8, 10, 303 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 304 &mach64_modes[0] 305 }, mach64_80x50_screen = { 306 "80x50", 80, 50, 307 &mach64_console_screen.ri.ri_ops, 308 8, 8, 309 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 310 &mach64_modes[0] 311 }, mach64_100x37_screen = { 312 "100x37", 100, 37, 313 &mach64_console_screen.ri.ri_ops, 314 8, 16, 315 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 316 &mach64_modes[2] 317 }, mach64_128x48_screen = { 318 "128x48", 128, 48, 319 &mach64_console_screen.ri.ri_ops, 320 8, 16, 321 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 322 &mach64_modes[3] 323 }, mach64_144x54_screen = { 324 "144x54", 144, 54, 325 &mach64_console_screen.ri.ri_ops, 326 8, 16, 327 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 328 &mach64_modes[4] 329 }, mach64_160x64_screen = { 330 "160x54", 160, 64, 331 &mach64_console_screen.ri.ri_ops, 332 8, 16, 333 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 334 &mach64_modes[5] 335 }; 336 337 const struct wsscreen_descr *_mach64_scrlist[] = { 338 &mach64_defaultscreen, 339 &mach64_80x25_screen, 340 &mach64_80x30_screen, 341 &mach64_80x40_screen, 342 &mach64_80x50_screen, 343 &mach64_100x37_screen, 344 &mach64_128x48_screen, 345 &mach64_144x54_screen, 346 &mach64_160x64_screen 347 }; 348 349 struct wsscreen_list mach64_screenlist = { 350 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 351 _mach64_scrlist 352 }; 353 354 int mach64_ioctl(void *, u_long, caddr_t, int, struct lwp *); 355 paddr_t mach64_mmap(void *, off_t, int); 356 int mach64_alloc_screen(void *, const struct wsscreen_descr *, void **, 357 int *, int *, long *); 358 void mach64_free_screen(void *, void *); 359 int mach64_show_screen(void *, void *, int, void (*)(void *, int, int), 360 void *); 361 int mach64_load_font(void *, void *, struct wsdisplay_font *); 362 363 struct wsdisplay_accessops mach64_accessops = { 364 mach64_ioctl, 365 mach64_mmap, 366 mach64_alloc_screen, 367 mach64_free_screen, 368 mach64_show_screen, 369 NULL 370 }; 371 372 /* 373 * Inline functions for getting access to register aperture. 374 */ 375 static inline u_int32_t regr(struct mach64_softc *, u_int32_t); 376 static inline u_int8_t regrb(struct mach64_softc *, u_int32_t); 377 static inline void regw(struct mach64_softc *, u_int32_t, u_int32_t); 378 static inline void regwb(struct mach64_softc *, u_int32_t, u_int8_t); 379 static inline void regwb_pll(struct mach64_softc *, u_int32_t, u_int8_t); 380 381 static inline u_int32_t 382 regr(struct mach64_softc *sc, u_int32_t index) 383 { 384 385 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 386 } 387 388 static inline u_int8_t 389 regrb(struct mach64_softc *sc, u_int32_t index) 390 { 391 392 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 393 } 394 395 static inline void 396 regw(struct mach64_softc *sc, u_int32_t index, u_int32_t data) 397 { 398 399 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 400 } 401 402 static inline void 403 regwb(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 404 { 405 406 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 407 } 408 409 static inline void 410 regwb_pll(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 411 { 412 413 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 414 regwb(sc, CLOCK_CNTL + 2, data); 415 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 416 } 417 418 static inline void 419 wait_for_fifo(struct mach64_softc *sc, u_int8_t v) 420 { 421 422 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 423 ; 424 } 425 426 static inline void 427 wait_for_idle(struct mach64_softc *sc) 428 { 429 430 wait_for_fifo(sc, 16); 431 while ((regr(sc, GUI_STAT) & 1) != 0) 432 ; 433 } 434 435 int 436 mach64_match(struct device *parent, struct cfdata *match, void *aux) 437 { 438 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 439 int i; 440 441 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 442 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 443 return 0; 444 445 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 446 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 447 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 448 mach64_chip_rev = PCI_REVISION(pa->pa_class); 449 return 1; 450 } 451 452 return 0; 453 } 454 455 void 456 mach64_attach(struct device *parent, struct device *self, void *aux) 457 { 458 struct mach64_softc *sc = (void *)self; 459 struct pci_attach_args *pa = aux; 460 char devinfo[256]; 461 int bar, reg, id; 462 struct wsemuldisplaydev_attach_args aa; 463 long defattr; 464 int setmode, console; 465 466 sc->sc_pc = pa->pa_pc; 467 sc->sc_pcitag = pa->pa_tag; 468 469 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 470 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 471 472 for (bar = 0; bar < NBARS; bar++) { 473 reg = PCI_MAPREG_START + (bar * 4); 474 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 475 sc->sc_pcitag, reg); 476 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 477 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 478 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 479 } 480 sc->sc_memt = pa->pa_memt; 481 482 mach64_init(sc); 483 484 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 485 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 486 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 487 (u_int)sc->sc_regbase); 488 489 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 490 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 491 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 492 (mach64_chip_rev & 0x07) == 0)) 493 sc->has_dsp = 0; 494 else 495 sc->has_dsp = 1; 496 497 sc->memsize = mach64_get_memsize(sc); 498 if (sc->memsize == 8192) 499 /* The last page is used as register aperture. */ 500 sc->memsize -= 4; 501 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 502 503 /* XXX is there any way to calculate reference frequency from 504 known values? */ 505 if (mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) 506 sc->ref_freq = 29498; 507 else 508 sc->ref_freq = 14318; 509 510 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 511 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 512 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 513 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 514 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 515 (sc->ref_div * 2); 516 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 517 (sc->mem_freq * sc->ref_div); 518 sc->ramdac_freq = mach64_get_max_ramdac(sc); 519 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 520 sc->sc_dev.dv_xname, (u_long)sc->memsize, 521 mach64_memtype_names[sc->memtype], 522 sc->mem_freq / 1000, sc->mem_freq % 1000, 523 sc->ramdac_freq / 1000); 524 525 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 526 if (id != mach64_chip_id) { 527 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 528 sc->sc_dev.dv_xname, id, mach64_chip_id); 529 return; 530 } 531 532 console = mach64_is_console(pa); 533 534 #ifdef __sparc__ 535 if (console) { 536 mach64_get_mode(sc, &default_mode); 537 setmode = 0; 538 } else { 539 memcpy(&default_mode, &mach64_modes[4], sizeof(struct videomode)); 540 setmode = 1; 541 } 542 #else 543 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)); 544 setmode = 1; 545 #endif 546 547 sc->bits_per_pixel = 8; 548 sc->virt_x = default_mode.hdisplay; 549 sc->virt_y = default_mode.vdisplay; 550 sc->max_x = sc->virt_x - 1; 551 sc->max_y = (sc->memsize * 1024) / 552 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 553 554 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 555 556 mach64_init_engine(sc); 557 #if 0 558 mach64_adjust_frame(0, 0); 559 if (sc->bits_per_pixel == 8) 560 mach64_init_lut(sc); 561 #endif 562 563 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 564 default_mode.hdisplay, default_mode.vdisplay, 565 sc->bits_per_pixel); 566 567 mach64_console_screen.ri.ri_hw = sc; 568 mach64_console_screen.ri.ri_depth = sc->bits_per_pixel; 569 mach64_console_screen.ri.ri_bits = (void*)(u_long)sc->sc_aperbase; 570 mach64_console_screen.ri.ri_width = default_mode.hdisplay; 571 mach64_console_screen.ri.ri_height = default_mode.vdisplay; 572 mach64_console_screen.ri.ri_stride = mach64_console_screen.ri.ri_width; 573 mach64_console_screen.ri.ri_flg = RI_CLEAR; 574 575 rasops_init(&mach64_console_screen.ri, mach64_console_screen.ri.ri_height / 16, 576 mach64_console_screen.ri.ri_width / 8); 577 578 mach64_defaultscreen.nrows = mach64_console_screen.ri.ri_rows; 579 mach64_defaultscreen.ncols = mach64_console_screen.ri.ri_cols; 580 581 mach64_console_screen.ri.ri_ops.allocattr(&mach64_console_screen.ri, 0, 0, 0, 582 &defattr); 583 584 /* Initialize fonts */ 585 wsfont_init(); 586 587 if (console) { 588 mach64_init_screen(sc, &mach64_console_screen, 589 &mach64_defaultscreen, 1, &defattr, setmode); 590 wsdisplay_cnattach(&mach64_defaultscreen, &mach64_console_screen.ri, 591 0, 0, defattr); 592 } 593 594 aa.console = console; 595 aa.scrdata = &mach64_screenlist; 596 aa.accessops = &mach64_accessops; 597 aa.accesscookie = sc; 598 599 config_found(self, &aa, wsemuldisplaydevprint); 600 } 601 602 void 603 mach64_init_screen(struct mach64_softc *sc, struct mach64screen *scr, 604 const struct wsscreen_descr *type, int existing, long *attrp, int setmode) 605 { 606 607 scr->sc = sc; 608 scr->type = type; 609 scr->mindispoffset = 0; 610 scr->maxdispoffset = sc->memsize * 1024; 611 scr->dispoffset = 0; 612 scr->cursorcol = 0; 613 scr->cursorrow = 0; 614 615 scr->mem = (u_int16_t *)malloc(type->nrows * type->ncols * 2, 616 M_DEVBUF, M_WAITOK); 617 if (existing) { 618 scr->active = 1; 619 620 if (setmode && mach64_set_screentype(sc, type)) { 621 panic("%s: failed to switch video mode", 622 sc->sc_dev.dv_xname); 623 } 624 } else { 625 scr->active = 0; 626 } 627 628 LIST_INSERT_HEAD(&sc->screens, scr, next); 629 } 630 631 void 632 mach64_init(struct mach64_softc *sc) 633 { 634 u_int32_t *p32, saved_value; 635 u_int8_t *p; 636 int need_swap; 637 638 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 639 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 640 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 641 } 642 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 643 644 sc->sc_regt = sc->sc_memt; 645 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 646 sc->sc_regsize, &sc->sc_regh); 647 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 648 649 /* 650 * Test wether the aperture is byte swapped or not 651 */ 652 p32 = (u_int32_t*)(u_long)sc->sc_aperbase; 653 saved_value = *p32; 654 p = (u_int8_t*)(u_long)sc->sc_aperbase; 655 *p32 = 0x12345678; 656 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 657 need_swap = 0; 658 else 659 need_swap = 1; 660 if (need_swap) { 661 sc->sc_aperbase += 0x800000; 662 sc->sc_apersize -= 0x800000; 663 } 664 *p32 = saved_value; 665 666 LIST_INIT(&sc->screens); 667 sc->active = NULL; 668 sc->currenttype = &mach64_defaultscreen; 669 callout_init(&sc->switch_callout); 670 } 671 672 int 673 mach64_get_memsize(struct mach64_softc *sc) 674 { 675 int tmp, memsize; 676 int mem_tab[] = { 677 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 678 }; 679 680 tmp = regr(sc, MEM_CNTL); 681 if (sc->has_dsp) { 682 tmp &= 0x0000000f; 683 if (tmp < 8) 684 memsize = (tmp + 1) * 512; 685 else if (tmp < 12) 686 memsize = (tmp - 3) * 1024; 687 else 688 memsize = (tmp - 7) * 2048; 689 } else { 690 memsize = mem_tab[tmp & 0x07]; 691 } 692 693 return memsize; 694 } 695 696 int 697 mach64_get_max_ramdac(struct mach64_softc *sc) 698 { 699 int i; 700 701 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 702 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 703 (mach64_chip_rev & 0x07)) 704 return 170000; 705 706 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 707 if (mach64_chip_id == mach64_info[i].chip_id) 708 return mach64_info[i].ramdac_freq; 709 710 if (sc->bits_per_pixel == 8) 711 return 135000; 712 else 713 return 80000; 714 } 715 716 void 717 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 718 { 719 struct mach64_crtcregs crtc; 720 721 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 722 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 723 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 724 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 725 726 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 727 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 728 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 729 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 730 mode->hsync_start; 731 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 732 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 733 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 734 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 735 736 #ifdef MACH64_DEBUG 737 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 738 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 739 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 740 #endif 741 } 742 743 int 744 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 745 struct videomode *mode) 746 { 747 748 if (mode->dot_clock > sc->ramdac_freq) 749 /* Clock too high. */ 750 return 1; 751 752 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 753 ((mode->htotal >> 3) - 1); 754 crtc->h_sync_strt_wid = 755 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 756 ((mode->hsync_start >> 3) - 1); 757 758 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 759 (mode->vtotal - 1); 760 crtc->v_sync_strt_wid = 761 ((mode->vsync_end - mode->vsync_start) << 16) | 762 (mode->vsync_start - 1); 763 764 if (mode->flags & VID_NVSYNC) 765 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 766 767 switch (sc->bits_per_pixel) { 768 case 8: 769 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 770 break; 771 case 16: 772 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 773 break; 774 case 32: 775 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 776 break; 777 } 778 779 crtc->gen_cntl = 0; 780 if (mode->flags & VID_INTERLACE) 781 crtc->gen_cntl |= CRTC_INTERLACE_EN; 782 if (mode->flags & VID_CSYNC) 783 crtc->gen_cntl |= CRTC_CSYNC_EN; 784 785 crtc->dot_clock = mode->dot_clock; 786 787 return 0; 788 } 789 790 void 791 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 792 { 793 794 mach64_set_pll(sc, crtc->dot_clock); 795 796 if (sc->has_dsp) 797 mach64_set_dsp(sc); 798 799 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 800 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 801 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 802 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 803 804 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 805 806 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 807 808 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 809 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 810 } 811 812 int 813 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 814 { 815 struct mach64_crtcregs crtc; 816 817 if (mach64_calc_crtcregs(sc, &crtc, mode)) 818 return 1; 819 820 mach64_set_crtcregs(sc, &crtc); 821 return 0; 822 } 823 824 void 825 mach64_reset_engine(struct mach64_softc *sc) 826 { 827 828 /* Reset engine.*/ 829 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 830 831 /* Enable engine. */ 832 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 833 834 /* Ensure engine is not locked up by clearing any FIFO or 835 host errors. */ 836 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 837 BUS_FIFO_ERR_ACK); 838 } 839 840 void 841 mach64_init_engine(struct mach64_softc *sc) 842 { 843 u_int32_t pitch_value; 844 845 pitch_value = sc->virt_x; 846 847 if (sc->bits_per_pixel == 24) 848 pitch_value *= 3; 849 850 mach64_reset_engine(sc); 851 852 wait_for_fifo(sc, 14); 853 854 regw(sc, CONTEXT_MASK, 0xffffffff); 855 856 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 857 858 regw(sc, DST_Y_X, 0); 859 regw(sc, DST_HEIGHT, 0); 860 regw(sc, DST_BRES_ERR, 0); 861 regw(sc, DST_BRES_INC, 0); 862 regw(sc, DST_BRES_DEC, 0); 863 864 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 865 DST_Y_TOP_TO_BOTTOM); 866 867 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 868 869 regw(sc, SRC_Y_X, 0); 870 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 871 regw(sc, SRC_Y_X_START, 0); 872 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 873 874 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 875 876 wait_for_fifo(sc, 13); 877 regw(sc, HOST_CNTL, 0); 878 879 regw(sc, PAT_REG0, 0); 880 regw(sc, PAT_REG1, 0); 881 regw(sc, PAT_CNTL, 0); 882 883 regw(sc, SC_LEFT, 0); 884 regw(sc, SC_TOP, 0); 885 regw(sc, SC_BOTTOM, default_mode.vdisplay - 1); 886 regw(sc, SC_RIGHT, pitch_value - 1); 887 888 regw(sc, DP_BKGD_CLR, 0); 889 regw(sc, DP_FRGD_CLR, 0xffffffff); 890 regw(sc, DP_WRITE_MASK, 0xffffffff); 891 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 892 893 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 894 895 wait_for_fifo(sc, 3); 896 regw(sc, CLR_CMP_CLR, 0); 897 regw(sc, CLR_CMP_MASK, 0xffffffff); 898 regw(sc, CLR_CMP_CNTL, 0); 899 900 wait_for_fifo(sc, 2); 901 switch (sc->bits_per_pixel) { 902 case 8: 903 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 904 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 905 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) & ~DAC_8BIT_EN); 906 break; 907 #if 0 908 case 32: 909 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 910 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 911 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 912 break; 913 #endif 914 } 915 916 wait_for_fifo(sc, 5); 917 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 918 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 919 920 wait_for_idle(sc); 921 } 922 923 void 924 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 925 { 926 int offset; 927 928 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 929 930 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 931 offset); 932 } 933 934 void 935 mach64_set_dsp(struct mach64_softc *sc) 936 { 937 u_int32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 938 u_int32_t dsp_off, dsp_on, dsp_xclks_per_qw; 939 u_int32_t xclks_per_qw, y; 940 u_int32_t fifo_off, fifo_on; 941 942 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 943 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 944 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 945 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 946 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 947 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 948 dsp_loop_latency = 0; 949 fifo_depth = 24; 950 } else { 951 dsp_loop_latency = 2; 952 fifo_depth = 32; 953 } 954 955 dsp_precision = 0; 956 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 957 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 958 y = (xclks_per_qw * fifo_depth) >> 11; 959 while (y) { 960 y >>= 1; 961 dsp_precision++; 962 } 963 dsp_precision -= 5; 964 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 965 966 switch (sc->memtype) { 967 case DRAM: 968 case EDO_DRAM: 969 case PSEUDO_EDO: 970 if (sc->memsize > 1024) { 971 page_size = 9; 972 dsp_loop_latency += 6; 973 } else { 974 page_size = 10; 975 if (sc->memtype == DRAM) 976 dsp_loop_latency += 8; 977 else 978 dsp_loop_latency += 7; 979 } 980 break; 981 case SDRAM: 982 case SGRAM: 983 if (sc->memsize > 1024) { 984 page_size = 8; 985 dsp_loop_latency += 8; 986 } else { 987 page_size = 10; 988 dsp_loop_latency += 9; 989 } 990 break; 991 default: 992 page_size = 10; 993 dsp_loop_latency += 9; 994 break; 995 } 996 997 if (xclks_per_qw >= (page_size << 11)) 998 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 999 else 1000 fifo_on = (3 * page_size + 2) << 6; 1001 1002 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1003 dsp_on = fifo_on >> dsp_precision; 1004 dsp_off = fifo_off >> dsp_precision; 1005 1006 #ifdef MACH64_DEBUG 1007 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1008 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1009 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1010 "mclk_post_div = %d, vclk_post_div = %d\n", 1011 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1012 sc->mclk_fb_div, sc->vclk_fb_div, 1013 sc->mclk_post_div, sc->vclk_post_div); 1014 #endif 1015 1016 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1017 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1018 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1019 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1020 } 1021 1022 void 1023 mach64_set_pll(struct mach64_softc *sc, int clock) 1024 { 1025 int q; 1026 1027 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1028 #ifdef MACH64_DEBUG 1029 printf("q = %d\n", q); 1030 #endif 1031 if (q > 25500) { 1032 printf("Warning: q > 25500\n"); 1033 q = 25500; 1034 sc->vclk_post_div = 1; 1035 sc->log2_vclk_post_div = 0; 1036 } else if (q > 12750) { 1037 sc->vclk_post_div = 1; 1038 sc->log2_vclk_post_div = 0; 1039 } else if (q > 6350) { 1040 sc->vclk_post_div = 2; 1041 sc->log2_vclk_post_div = 1; 1042 } else if (q > 3150) { 1043 sc->vclk_post_div = 4; 1044 sc->log2_vclk_post_div = 2; 1045 } else if (q >= 1600) { 1046 sc->vclk_post_div = 8; 1047 sc->log2_vclk_post_div = 3; 1048 } else { 1049 printf("Warning: q < 1600\n"); 1050 sc->vclk_post_div = 8; 1051 sc->log2_vclk_post_div = 3; 1052 } 1053 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1054 1055 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1056 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1057 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1058 } 1059 1060 void 1061 mach64_init_lut(struct mach64_softc *sc) 1062 { 1063 int i; 1064 1065 regwb(sc, DAC_REGS, 0); 1066 1067 for (i = 0; i < 16; i++) { 1068 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3]); 1069 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3 + 1]); 1070 regwb(sc, DAC_REGS + 1, mach64_cmap[i + 3 + 2]); 1071 } 1072 } 1073 1074 void 1075 mach64_switch_screen(struct mach64_softc *sc) 1076 { 1077 struct mach64screen *scr, *oldscr; 1078 const struct wsscreen_descr *type; 1079 1080 scr = sc->wanted; 1081 if (!scr) { 1082 printf("mach64_switch_screen: disappeared\n"); 1083 (*sc->switchcb)(sc->switchcbarg, EIO, 0); 1084 return; 1085 } 1086 type = scr->type; 1087 oldscr = sc->active; /* can be NULL! */ 1088 #ifdef DIAGNOSTIC 1089 if (oldscr) { 1090 if (!oldscr->active) 1091 panic("mach64_switch_screen: not active"); 1092 if (oldscr->type != sc->currenttype) 1093 panic("mach64_switch_screen: bad type"); 1094 } 1095 #endif 1096 if (scr == oldscr) 1097 return; 1098 1099 #ifdef DIAGNOSTIC 1100 if (scr->active) 1101 panic("mach64_switch_screen: active"); 1102 #endif 1103 1104 if (oldscr) 1105 oldscr->active = 0; 1106 1107 if (sc->currenttype != type) { 1108 mach64_set_screentype(sc, type); 1109 sc->currenttype = type; 1110 } 1111 1112 scr->dispoffset = scr->mindispoffset; 1113 1114 if (!oldscr || (scr->dispoffset != oldscr->dispoffset)) { 1115 1116 } 1117 1118 /* Clear the entire screen. */ 1119 1120 scr->active = 1; 1121 mach64_restore_screen(scr, type, scr->mem); 1122 1123 sc->active = scr; 1124 1125 mach64_cursor(scr, scr->cursoron, scr->cursorrow, scr->cursorcol); 1126 1127 sc->wanted = 0; 1128 if (sc->switchcb) 1129 (*sc->switchcb)(sc->switchcbarg, 0, 0); 1130 } 1131 1132 void 1133 mach64_restore_screen(struct mach64screen *scr, 1134 const struct wsscreen_descr *type, u_int16_t *mem) 1135 { 1136 1137 } 1138 1139 int 1140 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1141 { 1142 struct mach64_crtcregs regs; 1143 1144 if (mach64_calc_crtcregs(sc, ®s, 1145 (struct videomode *)des->modecookie)) 1146 return 1; 1147 1148 mach64_set_crtcregs(sc, ®s); 1149 return 0; 1150 } 1151 1152 int 1153 mach64_is_console(struct pci_attach_args *pa) 1154 { 1155 #ifdef __sparc__ 1156 int node; 1157 1158 node = PCITAG_NODE(pa->pa_tag); 1159 if (node == -1) 1160 return 0; 1161 1162 return (node == prom_instance_to_package(prom_stdout())); 1163 #else 1164 return 1; 1165 #endif 1166 } 1167 1168 /* 1169 * wsdisplay_emulops 1170 */ 1171 1172 void 1173 mach64_cursor(void *cookie, int on, int row, int col) 1174 { 1175 1176 } 1177 1178 #if 0 1179 int 1180 mach64_mapchar(void *cookie, int uni, u_int *index) 1181 { 1182 1183 return 0; 1184 } 1185 1186 void 1187 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1188 { 1189 1190 } 1191 1192 void 1193 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1194 { 1195 1196 } 1197 1198 void 1199 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1200 { 1201 1202 } 1203 1204 void 1205 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1206 { 1207 1208 } 1209 1210 int 1211 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1212 { 1213 1214 return 0; 1215 } 1216 #endif 1217 1218 void 1219 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1220 { 1221 1222 } 1223 1224 /* 1225 * wsdisplay_accessops 1226 */ 1227 1228 int 1229 mach64_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct lwp *l) 1230 { 1231 1232 return ENOTTY; 1233 } 1234 1235 paddr_t 1236 mach64_mmap(void *v, off_t offset, int prot) 1237 { 1238 1239 return -1; 1240 } 1241 1242 int 1243 mach64_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 1244 int *curxp, int *curyp, long *defattrp) 1245 { 1246 struct mach64_softc *sc = v; 1247 struct mach64screen *scr; 1248 1249 scr = malloc(sizeof(struct mach64screen), M_DEVBUF, M_WAITOK|M_ZERO); 1250 mach64_init_screen(sc, scr, type, 0, defattrp, sc->active == NULL); 1251 rasops_init(&scr->ri, mach64_console_screen.ri.ri_height / 16, 1252 mach64_console_screen.ri.ri_width / 8); 1253 1254 scr->mem = malloc(type->ncols * type->nrows * 2, M_DEVBUF, 1255 M_WAITOK); 1256 mach64_eraserows(sc, 0, type->nrows, *defattrp); 1257 if (sc->active == NULL) { 1258 scr->active = 1; 1259 sc->active = scr; 1260 sc->currenttype = type; 1261 } 1262 1263 *cookiep = scr; 1264 *curxp = scr->cursorcol; 1265 *curyp = scr->cursorrow; 1266 1267 return 0; 1268 } 1269 1270 void 1271 mach64_free_screen(void *v, void *cookie) 1272 { 1273 struct mach64_softc *sc = v; 1274 struct mach64screen *scr = cookie; 1275 1276 LIST_REMOVE(scr, next); 1277 if (scr != &mach64_console_screen) 1278 free(scr, M_DEVBUF); 1279 else 1280 panic("mach64_free_screen: console"); 1281 1282 if (sc->active == scr) 1283 sc->active = 0; 1284 } 1285 1286 int 1287 mach64_show_screen(void *v, void *cookie, int waitok, 1288 void (*cb)(void *, int, int), void *cbarg) 1289 { 1290 struct mach64_softc *sc = v; 1291 struct mach64screen *scr, *oldscr; 1292 1293 scr = cookie; 1294 oldscr = sc->active; 1295 if (scr == oldscr) 1296 return 0; 1297 1298 sc->wanted = scr; 1299 sc->switchcb = cb; 1300 sc->switchcbarg = cbarg; 1301 if (cb) { 1302 callout_reset(&sc->switch_callout, 0, 1303 (void(*)(void *))mach64_switch_screen, sc); 1304 return EAGAIN; 1305 } 1306 1307 mach64_switch_screen(sc); 1308 1309 return 0; 1310 } 1311 1312 #if 0 1313 int 1314 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1315 { 1316 1317 return 0; 1318 } 1319 #endif 1320
Indexes created Thu Oct 02 14:10:14 GMT 2025