machfb.c revision 1.23.2.1
1 /* $NetBSD: machfb.c,v 1.23.2.1 2005/06/08 11:42:17 tron Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: machfb.c,v 1.23.2.1 2005/06/08 11:42:17 tron Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/callout.h> 43 44 #ifdef __sparc__ 45 #include <machine/promlib.h> 46 #endif 47 48 #ifdef __powerpc__ 49 #include <dev/ofw/openfirm.h> 50 #include <dev/ofw/ofw_pci.h> 51 #endif 52 53 #include <dev/ic/videomode.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 #include <dev/pci/pciio.h> 59 #include <dev/pci/machfbreg.h> 60 61 #include <dev/wscons/wsdisplayvar.h> 62 #include <dev/wscons/wsconsio.h> 63 #include <dev/wsfont/wsfont.h> 64 #include <dev/rasops/rasops.h> 65 66 #define MACH64_REG_SIZE 1024 67 #define MACH64_REG_OFF 0x7ffc00 68 69 #define NBARS 3 /* number of Mach64 PCI BARs */ 70 71 struct vga_bar { 72 bus_addr_t vb_base; 73 pcireg_t vb_busaddr; 74 bus_size_t vb_size; 75 pcireg_t vb_type; 76 int vb_flags; 77 }; 78 79 struct mach64_softc { 80 struct device sc_dev; 81 pci_chipset_tag_t sc_pc; 82 pcitag_t sc_pcitag; 83 84 struct vga_bar sc_bars[NBARS]; 85 struct vga_bar sc_rom; 86 87 #define sc_aperbase sc_bars[0].vb_base 88 #define sc_apersize sc_bars[0].vb_size 89 #define sc_aperphys sc_bars[0].vb_busaddr 90 91 #define sc_iobase sc_bars[1].vb_base 92 #define sc_iosize sc_bars[1].vb_size 93 94 #define sc_regbase sc_bars[2].vb_base 95 #define sc_regsize sc_bars[2].vb_size 96 #define sc_regphys sc_bars[2].vb_busaddr 97 98 bus_space_tag_t sc_regt; 99 bus_space_tag_t sc_memt; 100 bus_space_handle_t sc_regh; 101 bus_space_handle_t sc_memh; 102 103 size_t memsize; 104 int memtype; 105 106 int sc_mode; 107 int sc_bg; 108 109 int has_dsp; 110 int bits_per_pixel; 111 int max_x, max_y; 112 int virt_x, virt_y; 113 int color_depth; 114 115 int mem_freq; 116 int ramdac_freq; 117 int ref_freq; 118 119 int ref_div; 120 int log2_vclk_post_div; 121 int vclk_post_div; 122 int vclk_fb_div; 123 int mclk_post_div; 124 int mclk_fb_div; 125 126 struct mach64screen *wanted; 127 struct mach64screen *active; 128 void (*switchcb)(void *, int, int); 129 void *switchcbarg; 130 struct callout switch_callout; 131 LIST_HEAD(, mach64screen) screens; 132 const struct wsscreen_descr *currenttype; 133 u_char sc_cmap_red[256]; 134 u_char sc_cmap_green[256]; 135 u_char sc_cmap_blue[256]; 136 int sc_dacw; 137 }; 138 139 struct mach64screen { 140 struct rasops_info ri; 141 LIST_ENTRY(mach64screen) next; 142 struct mach64_softc *sc; 143 const struct wsscreen_descr *type; 144 int active; 145 u_int *chars; 146 long *attrs; 147 int dispoffset; 148 int mindispoffset; 149 int maxdispoffset; 150 151 int cursoron; 152 int cursorcol; 153 int cursorrow; 154 int cursordrawn; 155 }; 156 157 struct mach64_crtcregs { 158 u_int32_t h_total_disp; 159 u_int32_t h_sync_strt_wid; 160 u_int32_t v_total_disp; 161 u_int32_t v_sync_strt_wid; 162 u_int32_t gen_cntl; 163 u_int32_t clock_cntl; 164 u_int32_t color_depth; 165 u_int32_t dot_clock; 166 }; 167 168 struct { 169 u_int16_t chip_id; 170 u_int32_t ramdac_freq; 171 } mach64_info[] = { 172 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 173 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 181 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 182 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 189 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 190 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 192 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 193 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 194 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 195 }; 196 197 static int mach64_chip_id, mach64_chip_rev; 198 static struct videomode default_mode; 199 static struct mach64screen mach64_console_screen; 200 201 static char *mach64_memtype_names[] = { 202 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 203 "(unknown type)" 204 }; 205 206 struct videomode mach64_modes[] = { 207 /* 640x400 @ 70 Hz, 31.5 kHz */ 208 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 209 /* 640x480 @ 72 Hz, 36.5 kHz */ 210 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 211 /* 800x600 @ 72 Hz, 48.0 kHz */ 212 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 213 VID_PHSYNC | VID_PVSYNC }, 214 /* 1024x768 @ 70 Hz, 56.5 kHz */ 215 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 216 VID_NHSYNC | VID_NVSYNC }, 217 /* 1152x864 @ 70 Hz, 62.4 kHz */ 218 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 219 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 220 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 221 VID_NHSYNC | VID_NVSYNC } 222 }; 223 224 extern const u_char rasops_cmap[768]; 225 226 int mach64_match(struct device *, struct cfdata *, void *); 227 void mach64_attach(struct device *, struct device *, void *); 228 229 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 230 NULL, NULL); 231 232 void mach64_init(struct mach64_softc *); 233 int mach64_get_memsize(struct mach64_softc *); 234 int mach64_get_max_ramdac(struct mach64_softc *); 235 void mach64_get_mode(struct mach64_softc *, struct videomode *); 236 int mach64_calc_crtcregs(struct mach64_softc *, struct mach64_crtcregs *, 237 struct videomode *); 238 void mach64_set_crtcregs(struct mach64_softc *, struct mach64_crtcregs *); 239 int mach64_modeswitch(struct mach64_softc *, struct videomode *); 240 void mach64_set_dsp(struct mach64_softc *); 241 void mach64_set_pll(struct mach64_softc *, int); 242 void mach64_reset_engine(struct mach64_softc *); 243 void mach64_init_engine(struct mach64_softc *); 244 void mach64_adjust_frame(struct mach64_softc *, int, int); 245 void mach64_init_lut(struct mach64_softc *); 246 void mach64_switch_screen(struct mach64_softc *); 247 void mach64_init_screen(struct mach64_softc *, struct mach64screen *, 248 const struct wsscreen_descr *, int, long *, int); 249 void mach64_restore_screen(struct mach64screen *, 250 const struct wsscreen_descr *, u_int *); 251 int mach64_set_screentype(struct mach64_softc *, 252 const struct wsscreen_descr *); 253 int mach64_is_console(struct pci_attach_args *); 254 255 void mach64_cursor(void *, int, int, int); 256 int mach64_mapchar(void *, int, u_int *); 257 void mach64_putchar(void *, int, int, u_int, long); 258 void mach64_copycols(void *, int, int, int, int); 259 void mach64_erasecols(void *, int, int, int, long); 260 void mach64_copyrows(void *, int, int, int); 261 void mach64_eraserows(void *, int, int, long); 262 int mach64_allocattr(void *, int, int, int, long *); 263 void mach64_clearscreen(struct mach64_softc *); 264 265 void mach64_scroll(void *, void *, int); 266 267 int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 268 int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 269 int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, uint8_t, uint8_t); 270 void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, int, int, int) ; 271 void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 272 void mach64_setup_mono(struct mach64_softc *, int, int, int, int, uint32_t, uint32_t); 273 void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 274 void mach64_showpal(struct mach64_softc *); 275 int mach64_getwschar(void *, struct wsdisplay_char *); 276 int mach64_putwschar(void *, struct wsdisplay_char *); 277 278 void set_address(struct rasops_info *, bus_addr_t); 279 280 #if 0 281 const struct wsdisplay_emulops mach64_emulops = { 282 mach64_cursor, 283 mach64_mapchar, 284 mach64_putchar, 285 mach64_copycols, 286 mach64_erasecols, 287 mach64_copyrows, 288 mach64_eraserows, 289 mach64_allocattr, 290 }; 291 #endif 292 293 struct wsscreen_descr mach64_defaultscreen = { 294 "default", 295 0, 0, 296 &mach64_console_screen.ri.ri_ops, 297 8, 16, 298 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 299 &default_mode 300 }, mach64_80x25_screen = { 301 "80x25", 80, 25, 302 &mach64_console_screen.ri.ri_ops, 303 8, 16, 304 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 305 &mach64_modes[0] 306 }, mach64_80x30_screen = { 307 "80x30", 80, 30, 308 &mach64_console_screen.ri.ri_ops, 309 8, 16, 310 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 311 &mach64_modes[1] 312 }, mach64_80x40_screen = { 313 "80x40", 80, 40, 314 &mach64_console_screen.ri.ri_ops, 315 8, 10, 316 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 317 &mach64_modes[0] 318 }, mach64_80x50_screen = { 319 "80x50", 80, 50, 320 &mach64_console_screen.ri.ri_ops, 321 8, 8, 322 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 323 &mach64_modes[0] 324 }, mach64_100x37_screen = { 325 "100x37", 100, 37, 326 &mach64_console_screen.ri.ri_ops, 327 8, 16, 328 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 329 &mach64_modes[2] 330 }, mach64_128x48_screen = { 331 "128x48", 128, 48, 332 &mach64_console_screen.ri.ri_ops, 333 8, 16, 334 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 335 &mach64_modes[3] 336 }, mach64_144x54_screen = { 337 "144x54", 144, 54, 338 &mach64_console_screen.ri.ri_ops, 339 8, 16, 340 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 341 &mach64_modes[4] 342 }, mach64_160x64_screen = { 343 "160x54", 160, 64, 344 &mach64_console_screen.ri.ri_ops, 345 8, 16, 346 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 347 &mach64_modes[5] 348 }; 349 350 const struct wsscreen_descr *_mach64_scrlist[] = { 351 &mach64_defaultscreen, 352 &mach64_80x25_screen, 353 &mach64_80x30_screen, 354 &mach64_80x40_screen, 355 &mach64_80x50_screen, 356 &mach64_100x37_screen, 357 &mach64_128x48_screen, 358 &mach64_144x54_screen, 359 &mach64_160x64_screen 360 }; 361 362 struct wsscreen_list mach64_screenlist = { 363 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 364 _mach64_scrlist 365 }; 366 367 int mach64_ioctl(void *, u_long, caddr_t, int, struct proc *); 368 paddr_t mach64_mmap(void *, off_t, int); 369 int mach64_alloc_screen(void *, const struct wsscreen_descr *, void **, 370 int *, int *, long *); 371 void mach64_free_screen(void *, void *); 372 int mach64_show_screen(void *, void *, int, void (*)(void *, int, int), 373 void *); 374 int mach64_load_font(void *, void *, struct wsdisplay_font *); 375 376 struct wsdisplay_accessops mach64_accessops = { 377 mach64_ioctl, 378 mach64_mmap, 379 mach64_alloc_screen, 380 mach64_free_screen, 381 mach64_show_screen, 382 NULL, /* load_font */ 383 NULL, /* polls */ 384 mach64_getwschar, /* getwschar */ 385 mach64_putwschar, /* putwschar */ 386 NULL, /* scroll */ 387 NULL, /* getborder */ 388 NULL /* setborder */ 389 }; 390 391 /* 392 * Inline functions for getting access to register aperture. 393 */ 394 static inline u_int32_t regr(struct mach64_softc *, u_int32_t); 395 static inline u_int8_t regrb(struct mach64_softc *, u_int32_t); 396 static inline void regw(struct mach64_softc *, u_int32_t, u_int32_t); 397 static inline void regwb(struct mach64_softc *, u_int32_t, u_int8_t); 398 static inline void regwb_pll(struct mach64_softc *, u_int32_t, u_int8_t); 399 400 static inline u_int32_t 401 regr(struct mach64_softc *sc, u_int32_t index) 402 { 403 404 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 405 } 406 407 static inline u_int8_t 408 regrb(struct mach64_softc *sc, u_int32_t index) 409 { 410 411 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 412 } 413 414 static inline void 415 regw(struct mach64_softc *sc, u_int32_t index, u_int32_t data) 416 { 417 418 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 419 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, BUS_SPACE_BARRIER_WRITE); 420 } 421 422 static inline void 423 regwb(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 424 { 425 426 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 427 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, BUS_SPACE_BARRIER_WRITE); 428 } 429 430 static inline void 431 regwb_pll(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 432 { 433 434 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 435 regwb(sc, CLOCK_CNTL + 2, data); 436 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 437 } 438 439 static inline void 440 wait_for_fifo(struct mach64_softc *sc, u_int8_t v) 441 { 442 443 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 444 ; 445 } 446 447 static inline void 448 wait_for_idle(struct mach64_softc *sc) 449 { 450 451 wait_for_fifo(sc, 16); 452 while ((regr(sc, GUI_STAT) & 1) != 0) 453 ; 454 } 455 456 int 457 mach64_match(struct device *parent, struct cfdata *match, void *aux) 458 { 459 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 460 int i; 461 462 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 463 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 464 return 0; 465 466 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 467 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 468 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 469 mach64_chip_rev = PCI_REVISION(pa->pa_class); 470 return 100; 471 } 472 473 return 0; 474 } 475 476 void 477 mach64_attach(struct device *parent, struct device *self, void *aux) 478 { 479 struct mach64_softc *sc = (void *)self; 480 struct pci_attach_args *pa = aux; 481 char devinfo[256]; 482 int bar, reg, id; 483 struct wsemuldisplaydev_attach_args aa; 484 long defattr; 485 int setmode, console; 486 pcireg_t screg; 487 488 sc->sc_pc = pa->pa_pc; 489 sc->sc_pcitag = pa->pa_tag; 490 sc->sc_dacw=-1; 491 sc->sc_mode=WSDISPLAYIO_MODE_EMUL; 492 493 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 494 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 495 496 /* enable memory and IO access */ 497 screg=pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 498 screg|=PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 499 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 500 501 /* enable memory and IO access */ 502 screg=pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 503 screg|=PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 504 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 505 506 for (bar = 0; bar < NBARS; bar++) { 507 reg = PCI_MAPREG_START + (bar * 4); 508 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 509 sc->sc_pcitag, reg); 510 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 511 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 512 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 513 sc->sc_bars[bar].vb_busaddr=pci_conf_read(sc->sc_pc, sc->sc_pcitag, reg)&0xfffffff0; 514 } 515 sc->sc_memt = pa->pa_memt; 516 517 mach64_init(sc); 518 519 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 520 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 521 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 522 (u_int)sc->sc_regphys); 523 524 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 525 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 526 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 527 (mach64_chip_rev & 0x07) == 0)) 528 sc->has_dsp = 0; 529 else 530 sc->has_dsp = 1; 531 532 sc->memsize = mach64_get_memsize(sc); 533 if (sc->memsize == 8192) 534 /* The last page is used as register aperture. */ 535 sc->memsize -= 4; 536 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 537 538 /* XXX is there any way to calculate reference frequency from 539 known values? */ 540 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 541 ((mach64_chip_id>=PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 542 (mach64_chip_id<=PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 543 printf("ref_freq=29.498MHz\n"); 544 sc->ref_freq = 29498; 545 } else 546 sc->ref_freq = 14318; 547 548 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 549 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 550 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 551 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 552 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 553 (sc->ref_div * 2); 554 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 555 (sc->mem_freq * sc->ref_div); 556 sc->ramdac_freq = mach64_get_max_ramdac(sc); 557 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 558 sc->sc_dev.dv_xname, (u_long)sc->memsize, 559 mach64_memtype_names[sc->memtype], 560 sc->mem_freq / 1000, sc->mem_freq % 1000, 561 sc->ramdac_freq / 1000); 562 563 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 564 if (id != mach64_chip_id) { 565 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 566 sc->sc_dev.dv_xname, id, mach64_chip_id); 567 return; 568 } 569 570 console = mach64_is_console(pa); 571 572 #if defined(__sparc__) || defined(__powerpc__) 573 if (console) { 574 mach64_get_mode(sc, &default_mode); 575 setmode = 0; 576 } else { 577 memcpy(&default_mode, &mach64_modes[4], sizeof(struct videomode)); 578 setmode = 1; 579 } 580 #else 581 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)); 582 setmode = 1; 583 #endif 584 585 sc->bits_per_pixel = 8; 586 sc->virt_x = default_mode.hdisplay; 587 sc->virt_y = default_mode.vdisplay; 588 sc->max_x = sc->virt_x - 1; 589 sc->max_y = (sc->memsize * 1024) / 590 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 591 592 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 593 594 mach64_init_engine(sc); 595 #if 0 596 mach64_adjust_frame(0, 0); 597 if (sc->bits_per_pixel == 8) 598 mach64_init_lut(sc); 599 #endif 600 601 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 602 default_mode.hdisplay, default_mode.vdisplay, 603 sc->bits_per_pixel); 604 605 mach64_console_screen.ri.ri_hw = &mach64_console_screen; 606 mach64_console_screen.ri.ri_depth = sc->bits_per_pixel; 607 mach64_console_screen.ri.ri_width = default_mode.hdisplay; 608 mach64_console_screen.ri.ri_height = default_mode.vdisplay; 609 mach64_console_screen.ri.ri_stride = mach64_console_screen.ri.ri_width; 610 611 mach64_console_screen.ri.ri_bits=(void *)(uintptr_t)sc->sc_aperbase; 612 613 mach64_console_screen.ri.ri_flg = RI_CENTER; 614 mach64_console_screen.active=1; 615 sc->active=&mach64_console_screen; 616 617 rasops_init(&mach64_console_screen.ri, mach64_console_screen.ri.ri_height / 16, 618 mach64_console_screen.ri.ri_width / 8); /* XXX width/height are nonsense */ 619 rasops_reconfig(&mach64_console_screen.ri, 620 mach64_console_screen.ri.ri_height / mach64_console_screen.ri.ri_font->fontheight, 621 mach64_console_screen.ri.ri_width / mach64_console_screen.ri.ri_font->fontwidth); 622 623 set_address(&mach64_console_screen.ri,sc->sc_aperbase); 624 625 626 /* enable acceleration */ 627 mach64_console_screen.ri.ri_ops.copyrows=mach64_copyrows; 628 mach64_console_screen.ri.ri_ops.eraserows=mach64_eraserows; 629 mach64_console_screen.ri.ri_ops.copycols=mach64_copycols; 630 mach64_console_screen.ri.ri_ops.erasecols=mach64_erasecols; 631 mach64_console_screen.ri.ri_ops.putchar=mach64_putchar; 632 mach64_console_screen.ri.ri_ops.cursor=mach64_cursor; 633 634 mach64_defaultscreen.nrows = mach64_console_screen.ri.ri_rows; 635 mach64_defaultscreen.ncols = mach64_console_screen.ri.ri_cols; 636 637 mach64_allocattr(&mach64_console_screen.ri, WS_DEFAULT_FG, WS_DEFAULT_BG, 0, 638 &defattr); 639 640 sc->sc_bg=WS_DEFAULT_BG; 641 642 643 /* really necessary? */ 644 mach64_defaultscreen.capabilities=mach64_console_screen.ri.ri_caps; 645 mach64_defaultscreen.textops=&mach64_console_screen.ri.ri_ops; 646 647 /* Initialize fonts */ 648 /* XXX shouldn't that happen /before/ we call rasops_init()? */ 649 wsfont_init(); 650 651 if (console) { 652 mach64_init_screen(sc, &mach64_console_screen, 653 &mach64_defaultscreen, 1, &defattr, setmode); 654 wsdisplay_cnattach(&mach64_defaultscreen, &mach64_console_screen.ri, 655 0, 0, defattr); 656 } 657 658 mach64_init_lut(sc); 659 mach64_clearscreen(sc); 660 661 aa.console = console; 662 aa.scrdata = &mach64_screenlist; 663 aa.accessops = &mach64_accessops; 664 aa.accesscookie = sc; 665 666 config_found(self, &aa, wsemuldisplaydevprint); 667 } 668 669 void 670 mach64_init_screen(struct mach64_softc *sc, struct mach64screen *scr, 671 const struct wsscreen_descr *type, int existing, long *attrp, int setmode) 672 { 673 struct rasops_info *ri=&scr->ri; 674 int cnt; 675 scr->sc = sc; 676 scr->type = type; 677 scr->mindispoffset = 0; 678 scr->maxdispoffset = sc->memsize * 1024; 679 scr->dispoffset = 0; 680 scr->cursorcol = 0; 681 scr->cursorrow = 0; 682 683 cnt=type->nrows * type->ncols; 684 scr->attrs=(long *)malloc((cnt)*(sizeof(long)+sizeof(u_int)), 685 M_DEVBUF, M_WAITOK); 686 scr->chars=(u_int *)&scr->attrs[cnt]; 687 /* we allocate both chars and attributes in one chunk, attributes first because 688 they have the (potentially) bigger alignment */ 689 690 ri->ri_depth = sc->bits_per_pixel; 691 ri->ri_width = default_mode.hdisplay; 692 ri->ri_height = default_mode.vdisplay; 693 ri->ri_stride = ri->ri_width; 694 ri->ri_flg = RI_CENTER; 695 696 if (existing) { 697 scr->active = 1; 698 ri->ri_flg|=RI_CLEAR; 699 if (setmode && mach64_set_screentype(sc, type)) { 700 panic("%s: failed to switch video mode", 701 sc->sc_dev.dv_xname); 702 } 703 } else { 704 scr->active = 0; 705 } 706 707 LIST_INSERT_HEAD(&sc->screens, scr, next); 708 } 709 710 void 711 mach64_init(struct mach64_softc *sc) 712 { 713 u_int32_t *p32, saved_value; 714 u_int8_t *p; 715 int need_swap; 716 717 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 718 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 719 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 720 } 721 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 722 723 sc->sc_regt = sc->sc_memt; 724 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 725 sc->sc_regsize, &sc->sc_regh); 726 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 727 728 /* 729 * Test wether the aperture is byte swapped or not 730 */ 731 p32 = (u_int32_t*)(u_long)sc->sc_aperbase; 732 saved_value = *p32; 733 p = (u_int8_t*)(u_long)sc->sc_aperbase; 734 *p32 = 0x12345678; 735 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 736 need_swap = 0; 737 else 738 need_swap = 1; 739 if (need_swap) { 740 sc->sc_aperbase += 0x800000; 741 sc->sc_apersize -= 0x800000; 742 } 743 *p32 = saved_value; 744 745 LIST_INIT(&sc->screens); 746 sc->active = NULL; 747 sc->currenttype = &mach64_defaultscreen; 748 callout_init(&sc->switch_callout); 749 } 750 751 int 752 mach64_get_memsize(struct mach64_softc *sc) 753 { 754 int tmp, memsize; 755 int mem_tab[] = { 756 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 757 }; 758 759 tmp = regr(sc, MEM_CNTL); 760 printf("memctl: %08x\n",tmp); 761 if (sc->has_dsp) { 762 tmp &= 0x0000000f; 763 if (tmp < 8) 764 memsize = (tmp + 1) * 512; 765 else if (tmp < 12) 766 memsize = (tmp - 3) * 1024; 767 else 768 memsize = (tmp - 7) * 2048; 769 } else { 770 memsize = mem_tab[tmp & 0x07]; 771 } 772 773 return memsize; 774 } 775 776 int 777 mach64_get_max_ramdac(struct mach64_softc *sc) 778 { 779 int i; 780 781 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 782 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 783 (mach64_chip_rev & 0x07)) 784 return 170000; 785 786 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 787 if (mach64_chip_id == mach64_info[i].chip_id) 788 return mach64_info[i].ramdac_freq; 789 790 if (sc->bits_per_pixel == 8) 791 return 135000; 792 else 793 return 80000; 794 } 795 796 void 797 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 798 { 799 struct mach64_crtcregs crtc; 800 801 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 802 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 803 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 804 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 805 806 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 807 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 808 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 809 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 810 mode->hsync_start; 811 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 812 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 813 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 814 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 815 816 #ifdef DEBUG_MACHFB 817 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 818 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 819 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 820 #endif 821 } 822 823 int 824 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 825 struct videomode *mode) 826 { 827 828 if (mode->dot_clock > sc->ramdac_freq) 829 /* Clock too high. */ 830 return 1; 831 832 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 833 ((mode->htotal >> 3) - 1); 834 crtc->h_sync_strt_wid = 835 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 836 ((mode->hsync_start >> 3) - 1); 837 838 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 839 (mode->vtotal - 1); 840 crtc->v_sync_strt_wid = 841 ((mode->vsync_end - mode->vsync_start) << 16) | 842 (mode->vsync_start - 1); 843 844 if (mode->flags & VID_NVSYNC) 845 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 846 847 switch (sc->bits_per_pixel) { 848 case 8: 849 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 850 break; 851 case 16: 852 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 853 break; 854 case 32: 855 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 856 break; 857 } 858 859 crtc->gen_cntl = 0; 860 if (mode->flags & VID_INTERLACE) 861 crtc->gen_cntl |= CRTC_INTERLACE_EN; 862 if (mode->flags & VID_CSYNC) 863 crtc->gen_cntl |= CRTC_CSYNC_EN; 864 865 crtc->dot_clock = mode->dot_clock; 866 867 return 0; 868 } 869 870 void 871 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 872 { 873 874 mach64_set_pll(sc, crtc->dot_clock); 875 876 if (sc->has_dsp) 877 mach64_set_dsp(sc); 878 879 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 880 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 881 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 882 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 883 884 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 885 886 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 887 888 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 889 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 890 } 891 892 int 893 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 894 { 895 struct mach64_crtcregs crtc; 896 897 if (mach64_calc_crtcregs(sc, &crtc, mode)) 898 return 1; 899 900 mach64_set_crtcregs(sc, &crtc); 901 return 0; 902 } 903 904 void 905 mach64_reset_engine(struct mach64_softc *sc) 906 { 907 908 /* Reset engine.*/ 909 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 910 911 /* Enable engine. */ 912 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 913 914 /* Ensure engine is not locked up by clearing any FIFO or 915 host errors. */ 916 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 917 BUS_FIFO_ERR_ACK); 918 } 919 920 void 921 mach64_init_engine(struct mach64_softc *sc) 922 { 923 u_int32_t pitch_value; 924 925 pitch_value = sc->virt_x; 926 927 if (sc->bits_per_pixel == 24) 928 pitch_value *= 3; 929 930 mach64_reset_engine(sc); 931 932 wait_for_fifo(sc, 14); 933 934 regw(sc, CONTEXT_MASK, 0xffffffff); 935 936 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 937 938 regw(sc, DST_Y_X, 0); 939 regw(sc, DST_HEIGHT, 0); 940 regw(sc, DST_BRES_ERR, 0); 941 regw(sc, DST_BRES_INC, 0); 942 regw(sc, DST_BRES_DEC, 0); 943 944 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 945 DST_Y_TOP_TO_BOTTOM); 946 947 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 948 949 regw(sc, SRC_Y_X, 0); 950 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 951 regw(sc, SRC_Y_X_START, 0); 952 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 953 954 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 955 956 wait_for_fifo(sc, 13); 957 regw(sc, HOST_CNTL, 0); 958 959 regw(sc, PAT_REG0, 0); 960 regw(sc, PAT_REG1, 0); 961 regw(sc, PAT_CNTL, 0); 962 963 regw(sc, SC_LEFT, 0); 964 regw(sc, SC_TOP, 0); 965 regw(sc, SC_BOTTOM, default_mode.vdisplay - 1); 966 regw(sc, SC_RIGHT, pitch_value - 1); 967 968 regw(sc, DP_BKGD_CLR, 0); 969 regw(sc, DP_FRGD_CLR, 0xffffffff); 970 regw(sc, DP_WRITE_MASK, 0xffffffff); 971 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 972 973 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 974 975 wait_for_fifo(sc, 3); 976 regw(sc, CLR_CMP_CLR, 0); 977 regw(sc, CLR_CMP_MASK, 0xffffffff); 978 regw(sc, CLR_CMP_CNTL, 0); 979 980 wait_for_fifo(sc, 2); 981 switch (sc->bits_per_pixel) { 982 case 8: 983 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 984 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 985 /* XXX huh? We /want/ an 8 bit per channel palette! */ 986 /*regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) & ~DAC_8BIT_EN);*/ 987 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 988 break; 989 #if 0 990 case 32: 991 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 992 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 993 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 994 break; 995 #endif 996 } 997 998 wait_for_fifo(sc, 5); 999 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1000 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1001 1002 wait_for_idle(sc); 1003 } 1004 1005 void 1006 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1007 { 1008 int offset; 1009 1010 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1011 1012 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1013 offset); 1014 } 1015 1016 void 1017 mach64_set_dsp(struct mach64_softc *sc) 1018 { 1019 u_int32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1020 u_int32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1021 u_int32_t xclks_per_qw, y; 1022 u_int32_t fifo_off, fifo_on; 1023 1024 printf("initializing the DSP\n"); 1025 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1026 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1027 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1028 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1029 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1030 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1031 dsp_loop_latency = 0; 1032 fifo_depth = 24; 1033 } else { 1034 dsp_loop_latency = 2; 1035 fifo_depth = 32; 1036 } 1037 1038 dsp_precision = 0; 1039 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1040 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1041 y = (xclks_per_qw * fifo_depth) >> 11; 1042 while (y) { 1043 y >>= 1; 1044 dsp_precision++; 1045 } 1046 dsp_precision -= 5; 1047 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1048 1049 switch (sc->memtype) { 1050 case DRAM: 1051 case EDO_DRAM: 1052 case PSEUDO_EDO: 1053 if (sc->memsize > 1024) { 1054 page_size = 9; 1055 dsp_loop_latency += 6; 1056 } else { 1057 page_size = 10; 1058 if (sc->memtype == DRAM) 1059 dsp_loop_latency += 8; 1060 else 1061 dsp_loop_latency += 7; 1062 } 1063 break; 1064 case SDRAM: 1065 case SGRAM: 1066 if (sc->memsize > 1024) { 1067 page_size = 8; 1068 dsp_loop_latency += 8; 1069 } else { 1070 page_size = 10; 1071 dsp_loop_latency += 9; 1072 } 1073 break; 1074 default: 1075 page_size = 10; 1076 dsp_loop_latency += 9; 1077 break; 1078 } 1079 1080 if (xclks_per_qw >= (page_size << 11)) 1081 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1082 else 1083 fifo_on = (3 * page_size + 2) << 6; 1084 1085 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1086 dsp_on = fifo_on >> dsp_precision; 1087 dsp_off = fifo_off >> dsp_precision; 1088 1089 #ifdef DEBUG_MACHFB 1090 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1091 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1092 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1093 "mclk_post_div = %d, vclk_post_div = %d\n", 1094 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1095 sc->mclk_fb_div, sc->vclk_fb_div, 1096 sc->mclk_post_div, sc->vclk_post_div); 1097 #endif 1098 1099 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1100 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1101 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1102 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1103 } 1104 1105 void 1106 mach64_set_pll(struct mach64_softc *sc, int clock) 1107 { 1108 int q; 1109 1110 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1111 #ifdef DEBUG_MACHFB 1112 printf("q = %d\n", q); 1113 #endif 1114 if (q > 25500) { 1115 printf("Warning: q > 25500\n"); 1116 q = 25500; 1117 sc->vclk_post_div = 1; 1118 sc->log2_vclk_post_div = 0; 1119 } else if (q > 12750) { 1120 sc->vclk_post_div = 1; 1121 sc->log2_vclk_post_div = 0; 1122 } else if (q > 6350) { 1123 sc->vclk_post_div = 2; 1124 sc->log2_vclk_post_div = 1; 1125 } else if (q > 3150) { 1126 sc->vclk_post_div = 4; 1127 sc->log2_vclk_post_div = 2; 1128 } else if (q >= 1600) { 1129 sc->vclk_post_div = 8; 1130 sc->log2_vclk_post_div = 3; 1131 } else { 1132 printf("Warning: q < 1600\n"); 1133 sc->vclk_post_div = 8; 1134 sc->log2_vclk_post_div = 3; 1135 } 1136 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1137 1138 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1139 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1140 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1141 } 1142 1143 void 1144 mach64_init_lut(struct mach64_softc *sc) 1145 { 1146 int i,idx; 1147 idx=0; 1148 for(i=0;i<256;i++) { 1149 mach64_putpalreg(sc,i,rasops_cmap[idx],rasops_cmap[idx+1],rasops_cmap[idx+2]); 1150 idx+=3; 1151 } 1152 } 1153 1154 int 1155 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, uint8_t b) 1156 { 1157 sc->sc_cmap_red[index]=r; 1158 sc->sc_cmap_green[index]=g; 1159 sc->sc_cmap_blue[index]=b; 1160 /* writing the dac index takes a while, in theory we can poll some register 1161 to see when it's ready - but we better avoid writing it unnecessarily */ 1162 if(index!=sc->sc_dacw) 1163 { 1164 regwb(sc, DAC_MASK, 0xff); 1165 regwb(sc, DAC_WINDEX, index); 1166 } 1167 sc->sc_dacw=index+1; 1168 regwb(sc, DAC_DATA, r); 1169 regwb(sc, DAC_DATA, g); 1170 regwb(sc, DAC_DATA, b); 1171 return 0; 1172 } 1173 1174 int 1175 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1176 { 1177 u_int index = cm->index; 1178 u_int count = cm->count; 1179 int i, error; 1180 u_char rbuf[256], gbuf[256], bbuf[256]; 1181 u_char *r, *g, *b; 1182 1183 printf("putcmap: %d %d\n",index, count); 1184 if (cm->index >= 256 || cm->count > 256 || 1185 (cm->index + cm->count) > 256) 1186 return EINVAL; 1187 error = copyin(cm->red, &rbuf[index], count); 1188 if (error) 1189 return error; 1190 error = copyin(cm->green, &gbuf[index], count); 1191 if (error) 1192 return error; 1193 error = copyin(cm->blue, &bbuf[index], count); 1194 if (error) 1195 return error; 1196 1197 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1198 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1199 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1200 1201 r = &sc->sc_cmap_red[index]; 1202 g = &sc->sc_cmap_green[index]; 1203 b = &sc->sc_cmap_blue[index]; 1204 1205 for (i = 0; i < count; i++) { 1206 mach64_putpalreg(sc,index,*r, *g, *b); 1207 index++; 1208 r++, g++, b++; 1209 } 1210 return 0; 1211 } 1212 1213 int 1214 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1215 { 1216 u_int index = cm->index; 1217 u_int count = cm->count; 1218 int error; 1219 1220 if (index >= 255 || count > 256 || index + count > 256) 1221 return EINVAL; 1222 1223 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1224 if (error) 1225 return error; 1226 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1227 if (error) 1228 return error; 1229 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1230 if (error) 1231 return error; 1232 1233 return 0; 1234 } 1235 1236 int 1237 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1238 { 1239 struct mach64_crtcregs regs; 1240 1241 if (mach64_calc_crtcregs(sc, ®s, 1242 (struct videomode *)des->modecookie)) 1243 return 1; 1244 1245 mach64_set_crtcregs(sc, ®s); 1246 return 0; 1247 } 1248 1249 int 1250 mach64_is_console(struct pci_attach_args *pa) 1251 { 1252 #ifdef __sparc__ 1253 int node; 1254 1255 node = PCITAG_NODE(pa->pa_tag); 1256 if (node == -1) 1257 return 0; 1258 1259 return (node == prom_instance_to_package(prom_stdout())); 1260 #elif defined(__powerpc__) 1261 /* check if we're the /chosen console device */ 1262 int chosen, stdout, node, us; 1263 us=pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1264 chosen = OF_finddevice("/chosen"); 1265 OF_getprop(chosen, "stdout", &stdout, 4); 1266 node = OF_instance_to_package(stdout); 1267 return(us==node); 1268 #else 1269 return 1; 1270 #endif 1271 } 1272 1273 /* 1274 * wsdisplay_emulops 1275 */ 1276 1277 void 1278 mach64_cursor(void *cookie, int on, int row, int col) 1279 { 1280 struct rasops_info *ri=cookie; 1281 struct mach64screen *scr=ri->ri_hw; 1282 struct mach64_softc *sc=scr->sc; 1283 int x,y,wi=ri->ri_font->fontwidth,he=ri->ri_font->fontheight; 1284 if(scr->active) { 1285 x=scr->cursorcol*wi+ri->ri_xorigin; 1286 y=scr->cursorrow*he+ri->ri_yorigin; 1287 if(scr->cursordrawn) { 1288 mach64_bitblt(sc,x,y,x,y,wi,he,MIX_NOT_SRC,0xff); 1289 scr->cursordrawn=0; 1290 } 1291 scr->cursorrow=row; 1292 scr->cursorcol=col; 1293 if((scr->cursoron=on)!=0) 1294 { 1295 x=scr->cursorcol*wi+ri->ri_xorigin; 1296 y=scr->cursorrow*he+ri->ri_yorigin; 1297 mach64_bitblt(sc,x,y,x,y,wi,he,MIX_NOT_SRC,0xff); 1298 scr->cursordrawn=1; 1299 } 1300 } else { 1301 scr->cursoron=on; 1302 scr->cursorrow=row; 1303 scr->cursorcol=col; 1304 scr->cursordrawn=0; 1305 } 1306 } 1307 1308 #if 0 1309 int 1310 mach64_mapchar(void *cookie, int uni, u_int *index) 1311 { 1312 1313 return 0; 1314 } 1315 #endif 1316 1317 void 1318 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1319 { 1320 struct rasops_info *ri=cookie; 1321 struct mach64screen *scr=ri->ri_hw; 1322 struct mach64_softc *sc=scr->sc; 1323 int offset=ri->ri_cols*row+col; 1324 scr->attrs[offset]=attr; 1325 scr->chars[offset]=c; 1326 if((scr->active) && (sc->sc_mode==WSDISPLAYIO_MODE_EMUL)) { 1327 int fg,bg,uc; 1328 uint8_t *data; 1329 int x,y,wi=ri->ri_font->fontwidth,he=ri->ri_font->fontheight; 1330 1331 /*scr->putchar(cookie,row,col,c,attr);*/ 1332 if (!CHAR_IN_FONT(c, ri->ri_font)) 1333 return; 1334 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1335 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1336 x=ri->ri_xorigin+col*wi; 1337 y=ri->ri_yorigin+row*he; 1338 if(c==0x20) { 1339 mach64_rectfill(sc,x,y,wi,he,bg); 1340 } else { 1341 uc = c-ri->ri_font->firstchar; 1342 data = (uint8_t *)ri->ri_font->data + uc * ri->ri_fontscale; 1343 1344 mach64_setup_mono(sc,x,y,wi,he,fg,bg); 1345 mach64_feed_bytes(sc,ri->ri_fontscale,data); 1346 } 1347 } 1348 } 1349 1350 1351 void 1352 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1353 { 1354 struct rasops_info *ri=cookie; 1355 struct mach64screen *scr=ri->ri_hw; 1356 struct mach64_softc *sc=scr->sc; 1357 int32_t xs,xd,y,width,height; 1358 1359 int from=srccol+row*ri->ri_cols; 1360 int to=dstcol+row*ri->ri_cols; 1361 memmove(&scr->attrs[to],&scr->attrs[from],ncols*sizeof(long)); 1362 memmove(&scr->chars[to],&scr->chars[from],ncols*sizeof(u_int)); 1363 1364 if((scr->active) && (sc->sc_mode==WSDISPLAYIO_MODE_EMUL)) { 1365 xs=ri->ri_xorigin+ri->ri_font->fontwidth*srccol; 1366 xd=ri->ri_xorigin+ri->ri_font->fontwidth*dstcol; 1367 y=ri->ri_yorigin+ri->ri_font->fontheight*row; 1368 width=ri->ri_font->fontwidth*ncols; 1369 height=ri->ri_font->fontheight; 1370 mach64_bitblt(sc,xs,y,xd,y,width,height,MIX_SRC,0xff); 1371 } 1372 } 1373 1374 void 1375 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1376 { 1377 struct rasops_info *ri=cookie; 1378 struct mach64screen *scr=ri->ri_hw; 1379 struct mach64_softc *sc=scr->sc; 1380 int32_t x,y,width,height,fg,bg,ul;; 1381 1382 int start=startcol+row*ri->ri_cols; 1383 int end=start+ncols, i; 1384 for(i=start;i<end;i++) { 1385 scr->attrs[i]=fillattr; 1386 scr->chars[i]=0x20; 1387 } 1388 if((scr->active) && (sc->sc_mode==WSDISPLAYIO_MODE_EMUL)) { 1389 x=ri->ri_xorigin+ri->ri_font->fontwidth*startcol; 1390 y=ri->ri_yorigin+ri->ri_font->fontheight*row; 1391 width=ri->ri_font->fontwidth*ncols; 1392 height=ri->ri_font->fontheight; 1393 rasops_unpack_attr(fillattr,&fg,&bg,&ul); 1394 1395 mach64_rectfill(sc,x,y,width,height,bg); 1396 } 1397 } 1398 1399 void 1400 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1401 { 1402 struct rasops_info *ri=cookie; 1403 struct mach64screen *scr=ri->ri_hw; 1404 struct mach64_softc *sc=scr->sc; 1405 int32_t x,ys,yd,width,height; 1406 1407 int from=ri->ri_cols*srcrow, to=ri->ri_cols*dstrow, len=ri->ri_cols*nrows; 1408 memmove(&scr->attrs[to],&scr->attrs[from],len*sizeof(long)); 1409 memmove(&scr->chars[to],&scr->chars[from],len*sizeof(u_int)); 1410 1411 if((scr->active) && (sc->sc_mode==WSDISPLAYIO_MODE_EMUL)) { 1412 x=ri->ri_xorigin; 1413 ys=ri->ri_yorigin+ri->ri_font->fontheight*srcrow; 1414 yd=ri->ri_yorigin+ri->ri_font->fontheight*dstrow; 1415 width=ri->ri_emuwidth; 1416 height=ri->ri_font->fontheight*nrows; 1417 mach64_bitblt(sc,x,ys,x,yd,width,height,MIX_SRC,0xff); 1418 } 1419 } 1420 1421 void 1422 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1423 { 1424 struct rasops_info *ri=cookie; 1425 struct mach64screen *scr=ri->ri_hw; 1426 struct mach64_softc *sc=scr->sc; 1427 int32_t x,y,width,height,fg,bg,ul; 1428 1429 int start=ri->ri_cols*row, end=ri->ri_cols*(row+nrows),i; 1430 for(i=start;i<end;i++) { 1431 scr->attrs[i]=fillattr; 1432 scr->chars[i]=0x20; 1433 } 1434 1435 if((scr->active) && (sc->sc_mode==WSDISPLAYIO_MODE_EMUL)) { 1436 x=ri->ri_xorigin; 1437 y=ri->ri_yorigin+ri->ri_font->fontheight*row; 1438 width=ri->ri_emuwidth; 1439 height=ri->ri_font->fontheight*nrows; 1440 rasops_unpack_attr(fillattr,&fg,&bg,&ul); 1441 1442 mach64_rectfill(sc,x,y,width,height,bg); 1443 } 1444 } 1445 1446 void 1447 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1448 { 1449 uint32_t dest_ctl=0; 1450 wait_for_idle(sc); 1451 regw(sc,DP_WRITE_MASK,mask); /* XXX only good for 8 bit */ 1452 regw(sc,DP_PIX_WIDTH,DST_8BPP|SRC_8BPP|HOST_8BPP); 1453 regw(sc,DP_SRC,FRGD_SRC_BLIT); 1454 regw(sc,DP_MIX,(rop&0xffff)<<16); 1455 regw(sc,CLR_CMP_CNTL,0); /* no transparency */ 1456 if(yd<ys) { 1457 dest_ctl=DST_Y_TOP_TO_BOTTOM; 1458 } else { 1459 ys+=height-1; 1460 yd+=height-1; 1461 dest_ctl=DST_Y_BOTTOM_TO_TOP; 1462 } 1463 if(xd<xs) { 1464 dest_ctl|=DST_X_LEFT_TO_RIGHT; 1465 regw(sc,SRC_CNTL,SRC_LINE_X_LEFT_TO_RIGHT); 1466 } else { 1467 dest_ctl|=DST_X_RIGHT_TO_LEFT; 1468 xs+=width-1; 1469 xd+=width-1; 1470 regw(sc,SRC_CNTL,SRC_LINE_X_RIGHT_TO_LEFT); 1471 } 1472 regw(sc,DST_CNTL,dest_ctl); 1473 1474 regw(sc,SRC_Y_X,(xs<<16)|ys); 1475 regw(sc,SRC_WIDTH1,width); 1476 regw(sc,DST_Y_X,(xd<<16)|yd); 1477 regw(sc,DST_HEIGHT_WIDTH,(width<<16)|height); 1478 } 1479 1480 void 1481 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, int height, uint32_t fg, 1482 uint32_t bg) 1483 { 1484 wait_for_idle(sc); 1485 regw(sc,DP_WRITE_MASK,0xff); /* XXX only good for 8 bit */ 1486 regw(sc,DP_PIX_WIDTH,DST_8BPP|SRC_1BPP|HOST_1BPP); 1487 regw(sc,DP_SRC,MONO_SRC_HOST|BKGD_SRC_BKGD_CLR|FRGD_SRC_FRGD_CLR); 1488 regw(sc,DP_MIX,((MIX_SRC&0xffff)<<16)|MIX_SRC); 1489 regw(sc,CLR_CMP_CNTL,0); /* no transparency */ 1490 regw(sc,SRC_CNTL,SRC_LINE_X_LEFT_TO_RIGHT); 1491 regw(sc,DST_CNTL,DST_Y_TOP_TO_BOTTOM|DST_X_LEFT_TO_RIGHT); 1492 regw(sc,HOST_CNTL,HOST_BYTE_ALIGN); 1493 regw(sc,DP_BKGD_CLR,bg); 1494 regw(sc,DP_FRGD_CLR,fg); 1495 regw(sc,SRC_Y_X,0); 1496 regw(sc,SRC_WIDTH1,width); 1497 regw(sc,DST_Y_X,(xd<<16)|yd); 1498 regw(sc,DST_HEIGHT_WIDTH,(width<<16)|height); 1499 /* now feed the data into the chip */ 1500 } 1501 1502 void 1503 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1504 { 1505 int i; 1506 uint32_t latch=0, bork; 1507 int shift=0; 1508 int reg=0; 1509 for(i=0;i<count;i++) { 1510 bork=data[i]; 1511 latch|=(bork<<shift); 1512 if(shift==24) { 1513 regw(sc,HOST_DATA0+reg,latch); 1514 latch=0; 1515 shift=0; 1516 reg=(reg+4)&0x3c; 1517 } else 1518 shift+=8; 1519 } 1520 if(shift!=0) /* 24 */ 1521 regw(sc,HOST_DATA0+reg,latch); 1522 } 1523 1524 1525 void 1526 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, int colour) 1527 { 1528 wait_for_idle(sc); 1529 regw(sc,DP_WRITE_MASK,0xff); 1530 regw(sc,DP_FRGD_CLR,colour); 1531 regw(sc,DP_PIX_WIDTH,DST_8BPP|SRC_8BPP|HOST_8BPP); 1532 regw(sc,DP_SRC,FRGD_SRC_FRGD_CLR); 1533 regw(sc,DP_MIX,(MIX_SRC)<<16); 1534 regw(sc,CLR_CMP_CNTL,0); /* no transparency */ 1535 regw(sc,SRC_CNTL,SRC_LINE_X_LEFT_TO_RIGHT); 1536 regw(sc,DST_CNTL,DST_X_LEFT_TO_RIGHT|DST_Y_TOP_TO_BOTTOM); 1537 1538 regw(sc,SRC_Y_X,(x<<16)|y); 1539 regw(sc,SRC_WIDTH1,width); 1540 regw(sc,DST_Y_X,(x<<16)|y); 1541 regw(sc,DST_HEIGHT_WIDTH,(width<<16)|height); 1542 } 1543 1544 void 1545 mach64_clearscreen(struct mach64_softc *sc) 1546 { 1547 mach64_rectfill(sc,0,0,sc->virt_x,sc->virt_y,sc->sc_bg); 1548 } 1549 1550 1551 void 1552 mach64_showpal(struct mach64_softc *sc) 1553 { 1554 int i,x=0; 1555 for (i=0;i<16;i++) { 1556 mach64_rectfill(sc,x,0,64,64,i); 1557 x+=64; 1558 } 1559 } 1560 1561 int 1562 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1563 { 1564 if((fg==0)&&(bg==0)) 1565 { 1566 fg=WS_DEFAULT_FG; 1567 bg=WS_DEFAULT_BG; 1568 } 1569 *attrp=(fg&0xf)<<24|(bg&0xf)<<16|(flags&0xff)<<8; 1570 return 0; 1571 } 1572 1573 /* 1574 * wsdisplay_accessops 1575 */ 1576 1577 int 1578 mach64_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 1579 { 1580 /* we'll probably need to add more stuff here */ 1581 struct mach64_softc *sc = v; 1582 struct wsdisplay_fbinfo *wdf; 1583 struct mach64screen *ms=sc->active; 1584 switch (cmd) { 1585 case WSDISPLAYIO_GTYPE: 1586 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; /* XXX ? */ 1587 return 0; 1588 1589 case WSDISPLAYIO_GINFO: 1590 wdf = (void *)data; 1591 wdf->height = ms->ri.ri_height; 1592 wdf->width = ms->ri.ri_width; 1593 wdf->depth = ms->ri.ri_depth; 1594 wdf->cmsize = 256; 1595 return 0; 1596 case WSDISPLAYIO_GETCMAP: 1597 return mach64_getcmap(sc, (struct wsdisplay_cmap *)data); 1598 1599 case WSDISPLAYIO_PUTCMAP: 1600 return mach64_putcmap(sc, (struct wsdisplay_cmap *)data); 1601 /* PCI config read/write passthrough. */ 1602 case PCI_IOC_CFGREAD: 1603 case PCI_IOC_CFGWRITE: 1604 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1605 cmd, data, flag, p)); 1606 case WSDISPLAYIO_SMODE: 1607 { 1608 int new_mode=*(int*)data; 1609 if(new_mode!=sc->sc_mode) 1610 { 1611 sc->sc_mode=new_mode; 1612 if(new_mode==WSDISPLAYIO_MODE_EMUL) 1613 { 1614 /* we'll probably want to reset the console into a known state here 1615 just in case the Xserver crashed or didn't properly clean up after 1616 itself for whetever reason */ 1617 mach64_restore_screen(ms, ms->type, ms->chars); 1618 mach64_cursor(ms, ms->cursoron, ms->cursorrow, ms->cursorcol); 1619 } 1620 } 1621 } 1622 return 0; 1623 case WSDISPLAYIO_GETWSCHAR: 1624 return mach64_getwschar(sc,(struct wsdisplay_char *)data); 1625 case WSDISPLAYIO_PUTWSCHAR: 1626 return mach64_putwschar(sc,(struct wsdisplay_char *)data); 1627 } 1628 return EPASSTHROUGH; 1629 } 1630 1631 paddr_t 1632 mach64_mmap(void *v, off_t offset, int prot) 1633 { 1634 struct mach64_softc *sc = v; 1635 paddr_t pa; 1636 /* 'regular' framebuffer mmap()ing */ 1637 if(offset<sc->sc_apersize) { 1638 pa = bus_space_mmap(sc->sc_memt,sc->sc_aperbase+offset,0,prot,BUS_SPACE_MAP_LINEAR); 1639 return pa; 1640 } 1641 #if 0 1642 /* allow XFree86 to mmap() PCI space as if the BARs contain physical addresses */ 1643 if((offset>0x80000000) && (offset<=0xffffffff)) { 1644 pa = bus_space_mmap(sc->sc_memt,offset,0,prot,BUS_SPACE_MAP_LINEAR); 1645 return pa; 1646 } 1647 #endif 1648 1649 if((offset>=sc->sc_aperphys) && (offset<(sc->sc_aperphys+sc->sc_apersize))) { 1650 pa = bus_space_mmap(sc->sc_memt,offset,0,prot,BUS_SPACE_MAP_LINEAR); 1651 return pa; 1652 } 1653 1654 if((offset>=sc->sc_regphys) && (offset<(sc->sc_regphys+sc->sc_regsize))) { 1655 pa = bus_space_mmap(sc->sc_memt,offset,0,prot,BUS_SPACE_MAP_LINEAR); 1656 return pa; 1657 } 1658 1659 return -1; 1660 } 1661 1662 int 1663 mach64_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 1664 int *curxp, int *curyp, long *defattrp) 1665 { 1666 struct mach64_softc *sc = v; 1667 struct mach64screen *scr; 1668 struct rasops_info *ri; 1669 int cnt=type->nrows * type->ncols; 1670 1671 scr = malloc(sizeof(struct mach64screen), M_DEVBUF, M_WAITOK|M_ZERO); 1672 mach64_init_screen(sc, scr, type, 0, defattrp, sc->active == NULL); 1673 ri=&scr->ri; 1674 1675 ri->ri_hw=scr; 1676 /*ri->ri_bits=(void *)sc->sc_aperbase;*/ 1677 rasops_init(ri, mach64_console_screen.ri.ri_height / 8, 1678 mach64_console_screen.ri.ri_width / 8); 1679 1680 rasops_reconfig(ri, ri->ri_height / ri->ri_font->fontheight, 1681 ri->ri_width / ri->ri_font->fontwidth); 1682 set_address(ri,sc->sc_aperbase); 1683 mach64_allocattr(ri,WS_DEFAULT_FG,WS_DEFAULT_BG,0,defattrp); 1684 1685 scr->ri.ri_ops.copyrows=mach64_copyrows; 1686 scr->ri.ri_ops.eraserows=mach64_eraserows; 1687 scr->ri.ri_ops.copycols=mach64_copycols; 1688 scr->ri.ri_ops.erasecols=mach64_erasecols; 1689 scr->ri.ri_ops.putchar=mach64_putchar; 1690 scr->ri.ri_ops.cursor=mach64_cursor; 1691 1692 scr->attrs=(long *)malloc((cnt)*(sizeof(long)+sizeof(u_int)), 1693 M_DEVBUF, M_WAITOK); 1694 scr->chars=(u_int *)&scr->attrs[cnt]; 1695 mach64_eraserows(ri, 0, ri->ri_rows, *defattrp); 1696 1697 if (sc->active == NULL) { 1698 scr->active = 1; 1699 sc->active = scr; 1700 sc->currenttype = type; 1701 } 1702 1703 *cookiep = scr; 1704 *curxp = scr->cursorcol; 1705 *curyp = scr->cursorrow; 1706 1707 return 0; 1708 } 1709 1710 void 1711 mach64_free_screen(void *v, void *cookie) 1712 { 1713 struct mach64_softc *sc = v; 1714 struct mach64screen *scr = cookie; 1715 1716 LIST_REMOVE(scr, next); 1717 if (scr != &mach64_console_screen) { 1718 free(scr->attrs,M_DEVBUF); 1719 free(scr, M_DEVBUF); 1720 } else 1721 panic("mach64_free_screen: console"); 1722 1723 if (sc->active == scr) 1724 sc->active = 0; 1725 } 1726 1727 int 1728 mach64_show_screen(void *v, void *cookie, int waitok, 1729 void (*cb)(void *, int, int), void *cbarg) 1730 { 1731 struct mach64_softc *sc = v; 1732 struct mach64screen *scr, *oldscr; 1733 1734 scr = cookie; 1735 oldscr = sc->active; 1736 if (scr == oldscr) 1737 return 0; 1738 1739 sc->wanted = scr; 1740 sc->switchcb = cb; 1741 sc->switchcbarg = cbarg; 1742 if (cb) { 1743 callout_reset(&sc->switch_callout, 0, 1744 (void(*)(void *))mach64_switch_screen, sc); 1745 return EAGAIN; 1746 } 1747 1748 mach64_switch_screen(sc); 1749 1750 return 0; 1751 } 1752 1753 void 1754 mach64_switch_screen(struct mach64_softc *sc) 1755 { 1756 struct mach64screen *scr, *oldscr; 1757 const struct wsscreen_descr *type; 1758 1759 scr = sc->wanted; 1760 if (!scr) { 1761 printf("mach64_switch_screen: disappeared\n"); 1762 (*sc->switchcb)(sc->switchcbarg, EIO, 0); 1763 return; 1764 } 1765 type = scr->type; 1766 oldscr = sc->active; /* can be NULL! */ 1767 #ifdef DIAGNOSTIC 1768 if (oldscr) { 1769 if (!oldscr->active) 1770 panic("mach64_switch_screen: not active"); 1771 if (oldscr->type != sc->currenttype) 1772 panic("mach64_switch_screen: bad type"); 1773 } 1774 #endif 1775 if (scr == oldscr) 1776 return; 1777 1778 #ifdef DIAGNOSTIC 1779 /* XXX: this one bites us at reboot */ 1780 /* if (scr->active) 1781 panic("mach64_switch_screen: active");*/ 1782 #endif 1783 1784 if (oldscr) 1785 oldscr->active = 0; 1786 1787 if (sc->currenttype != type) { 1788 mach64_set_screentype(sc, type); 1789 sc->currenttype = type; 1790 } 1791 1792 scr->dispoffset = scr->mindispoffset; 1793 1794 if (!oldscr || (scr->dispoffset != oldscr->dispoffset)) { 1795 1796 } 1797 1798 /* Clear the entire screen. */ 1799 1800 scr->active = 1; 1801 mach64_restore_screen(scr, type, scr->chars); 1802 1803 sc->active = scr; 1804 1805 scr->ri.ri_ops.cursor(scr, scr->cursoron, scr->cursorrow, scr->cursorcol); 1806 1807 sc->wanted = 0; 1808 if (sc->switchcb) 1809 (*sc->switchcb)(sc->switchcbarg, 0, 0); 1810 } 1811 1812 void 1813 mach64_restore_screen(struct mach64screen *scr, 1814 const struct wsscreen_descr *type, u_int *mem) 1815 { 1816 int i, j, offset=0; 1817 /*struct rasops_info *ri=&scr->ri;*/ 1818 u_int *charptr=scr->chars; 1819 long *attrptr=scr->attrs; 1820 mach64_clearscreen(scr->sc); 1821 for (i = 0; i < scr->ri.ri_rows; i++) { 1822 for (j = 0; j < scr->ri.ri_cols; j++) { 1823 mach64_putchar(scr, i, j, charptr[offset], attrptr[offset]); 1824 offset++; 1825 } 1826 } 1827 scr->cursordrawn=0; 1828 } 1829 1830 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1831 void 1832 set_address(struct rasops_info *ri, bus_addr_t fb) 1833 { 1834 /*printf(" %d %d %d\n",ri->ri_xorigin,ri->ri_yorigin,ri->ri_stride);*/ 1835 ri->ri_bits=(void *)((u_long)fb+ri->ri_stride*ri->ri_yorigin+ri->ri_xorigin); 1836 } 1837 1838 int 1839 mach64_getwschar(void *cookie, struct wsdisplay_char *wsc) 1840 { 1841 struct mach64_softc *sc=cookie; 1842 struct mach64screen *scr=sc->active; 1843 int fg,bg,fl; 1844 if(scr){ 1845 if((wsc->col>=0) && (wsc->col<scr->ri.ri_cols) && (wsc->row>=0) && 1846 (wsc->row<scr->ri.ri_rows)) { 1847 int pos=scr->ri.ri_cols*wsc->row+wsc->col; 1848 wsc->letter=scr->chars[pos]; 1849 rasops_unpack_attr(scr->attrs[pos],&fg, &bg, &fl); 1850 wsc->foreground=fg; 1851 wsc->background=bg; 1852 wsc->flags=fl; 1853 return 0; 1854 } 1855 } 1856 return EINVAL; 1857 } 1858 1859 int 1860 mach64_putwschar(void *cookie, struct wsdisplay_char *wsc) 1861 { 1862 struct mach64_softc *sc=cookie; 1863 struct mach64screen *scr=sc->active; 1864 long attr; 1865 if(scr){ 1866 if((wsc->col>=0) && (wsc->col<scr->ri.ri_cols) && (wsc->row>=0) && 1867 (wsc->row<scr->ri.ri_rows)) { 1868 mach64_allocattr(&scr->ri,wsc->foreground, wsc->background, wsc->flags,&attr); 1869 mach64_putchar(&scr->ri,wsc->row, wsc->col, wsc->letter,attr); 1870 return 0; 1871 } 1872 } 1873 return EINVAL; 1874 } 1875 1876 #if 0 1877 int 1878 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1879 { 1880 1881 return 0; 1882 } 1883 #endif 1884 1885
Indexes created Thu Oct 02 14:10:14 GMT 2025