machfb.c revision 1.23.2.2
1 /* $NetBSD: machfb.c,v 1.23.2.2 2005/06/08 11:45:53 tron Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, 36 "$NetBSD: machfb.c,v 1.23.2.2 2005/06/08 11:45:53 tron Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/callout.h> 44 45 #ifdef __sparc__ 46 #include <machine/promlib.h> 47 #endif 48 49 #ifdef __powerpc__ 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_pci.h> 52 #endif 53 54 #include <dev/ic/videomode.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 #include <dev/pci/pciio.h> 60 #include <dev/pci/machfbreg.h> 61 62 #include <dev/wscons/wsdisplayvar.h> 63 #include <dev/wscons/wsconsio.h> 64 #include <dev/wsfont/wsfont.h> 65 #include <dev/rasops/rasops.h> 66 67 #define MACH64_REG_SIZE 1024 68 #define MACH64_REG_OFF 0x7ffc00 69 70 #define NBARS 3 /* number of Mach64 PCI BARs */ 71 72 struct vga_bar { 73 bus_addr_t vb_base; 74 pcireg_t vb_busaddr; 75 bus_size_t vb_size; 76 pcireg_t vb_type; 77 int vb_flags; 78 }; 79 80 struct mach64_softc { 81 struct device sc_dev; 82 pci_chipset_tag_t sc_pc; 83 pcitag_t sc_pcitag; 84 85 struct vga_bar sc_bars[NBARS]; 86 struct vga_bar sc_rom; 87 88 #define sc_aperbase sc_bars[0].vb_base 89 #define sc_apersize sc_bars[0].vb_size 90 #define sc_aperphys sc_bars[0].vb_busaddr 91 92 #define sc_iobase sc_bars[1].vb_base 93 #define sc_iosize sc_bars[1].vb_size 94 95 #define sc_regbase sc_bars[2].vb_base 96 #define sc_regsize sc_bars[2].vb_size 97 #define sc_regphys sc_bars[2].vb_busaddr 98 99 bus_space_tag_t sc_regt; 100 bus_space_tag_t sc_memt; 101 bus_space_handle_t sc_regh; 102 bus_space_handle_t sc_memh; 103 104 size_t memsize; 105 int memtype; 106 107 int sc_mode; 108 int sc_bg; 109 110 int has_dsp; 111 int bits_per_pixel; 112 int max_x; 113 int max_y; 114 int virt_x; 115 int virt_y; 116 int color_depth; 117 118 int mem_freq; 119 int ramdac_freq; 120 int ref_freq; 121 122 int ref_div; 123 int log2_vclk_post_div; 124 int vclk_post_div; 125 int vclk_fb_div; 126 int mclk_post_div; 127 int mclk_fb_div; 128 129 struct mach64screen *wanted; 130 struct mach64screen *active; 131 void (*switchcb)(void *, int, int); 132 void *switchcbarg; 133 struct callout switch_callout; 134 LIST_HEAD(, mach64screen) screens; 135 const struct wsscreen_descr *currenttype; 136 u_char sc_cmap_red[256]; 137 u_char sc_cmap_green[256]; 138 u_char sc_cmap_blue[256]; 139 int sc_dacw; 140 }; 141 142 struct mach64screen { 143 struct rasops_info ri; 144 LIST_ENTRY(mach64screen) next; 145 struct mach64_softc *sc; 146 const struct wsscreen_descr *type; 147 int active; 148 u_int *chars; 149 long *attrs; 150 int dispoffset; 151 int mindispoffset; 152 int maxdispoffset; 153 154 int cursoron; 155 int cursorcol; 156 int cursorrow; 157 int cursordrawn; 158 }; 159 160 struct mach64_crtcregs { 161 u_int32_t h_total_disp; 162 u_int32_t h_sync_strt_wid; 163 u_int32_t v_total_disp; 164 u_int32_t v_sync_strt_wid; 165 u_int32_t gen_cntl; 166 u_int32_t clock_cntl; 167 u_int32_t color_depth; 168 u_int32_t dot_clock; 169 }; 170 171 struct { 172 u_int16_t chip_id; 173 u_int32_t ramdac_freq; 174 } mach64_info[] = { 175 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 184 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 189 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 193 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 195 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 196 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 197 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 198 }; 199 200 static int mach64_chip_id, mach64_chip_rev; 201 static struct videomode default_mode; 202 static struct mach64screen mach64_console_screen; 203 204 static char *mach64_memtype_names[] = { 205 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 206 "(unknown type)" 207 }; 208 209 struct videomode mach64_modes[] = { 210 /* 640x400 @ 70 Hz, 31.5 kHz */ 211 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 212 /* 640x480 @ 72 Hz, 36.5 kHz */ 213 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 214 /* 800x600 @ 72 Hz, 48.0 kHz */ 215 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 216 VID_PHSYNC | VID_PVSYNC }, 217 /* 1024x768 @ 70 Hz, 56.5 kHz */ 218 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 219 VID_NHSYNC | VID_NVSYNC }, 220 /* 1152x864 @ 70 Hz, 62.4 kHz */ 221 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 222 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 223 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 224 VID_NHSYNC | VID_NVSYNC } 225 }; 226 227 extern const u_char rasops_cmap[768]; 228 229 int mach64_match(struct device *, struct cfdata *, void *); 230 void mach64_attach(struct device *, struct device *, void *); 231 232 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 233 NULL, NULL); 234 235 void mach64_init(struct mach64_softc *); 236 int mach64_get_memsize(struct mach64_softc *); 237 int mach64_get_max_ramdac(struct mach64_softc *); 238 void mach64_get_mode(struct mach64_softc *, struct videomode *); 239 int mach64_calc_crtcregs(struct mach64_softc *, struct mach64_crtcregs *, 240 struct videomode *); 241 void mach64_set_crtcregs(struct mach64_softc *, struct mach64_crtcregs *); 242 int mach64_modeswitch(struct mach64_softc *, struct videomode *); 243 void mach64_set_dsp(struct mach64_softc *); 244 void mach64_set_pll(struct mach64_softc *, int); 245 void mach64_reset_engine(struct mach64_softc *); 246 void mach64_init_engine(struct mach64_softc *); 247 void mach64_adjust_frame(struct mach64_softc *, int, int); 248 void mach64_init_lut(struct mach64_softc *); 249 void mach64_switch_screen(struct mach64_softc *); 250 void mach64_init_screen(struct mach64_softc *, struct mach64screen *, 251 const struct wsscreen_descr *, int, long *, int); 252 void mach64_restore_screen(struct mach64screen *, 253 const struct wsscreen_descr *, u_int *); 254 int mach64_set_screentype(struct mach64_softc *, 255 const struct wsscreen_descr *); 256 int mach64_is_console(struct pci_attach_args *); 257 258 void mach64_cursor(void *, int, int, int); 259 int mach64_mapchar(void *, int, u_int *); 260 void mach64_putchar(void *, int, int, u_int, long); 261 void mach64_copycols(void *, int, int, int, int); 262 void mach64_erasecols(void *, int, int, int, long); 263 void mach64_copyrows(void *, int, int, int); 264 void mach64_eraserows(void *, int, int, long); 265 int mach64_allocattr(void *, int, int, int, long *); 266 void mach64_clearscreen(struct mach64_softc *); 267 268 void mach64_scroll(void *, void *, int); 269 270 int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 271 int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 272 int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, uint8_t, 273 uint8_t); 274 void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, int, int, 275 int) ; 276 void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 277 void mach64_setup_mono(struct mach64_softc *, int, int, int, int, uint32_t, 278 uint32_t); 279 void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 280 void mach64_showpal(struct mach64_softc *); 281 int mach64_getwschar(void *, struct wsdisplay_char *); 282 int mach64_putwschar(void *, struct wsdisplay_char *); 283 284 void set_address(struct rasops_info *, bus_addr_t); 285 286 #if 0 287 const struct wsdisplay_emulops mach64_emulops = { 288 mach64_cursor, 289 mach64_mapchar, 290 mach64_putchar, 291 mach64_copycols, 292 mach64_erasecols, 293 mach64_copyrows, 294 mach64_eraserows, 295 mach64_allocattr, 296 }; 297 #endif 298 299 struct wsscreen_descr mach64_defaultscreen = { 300 "default", 301 0, 0, 302 &mach64_console_screen.ri.ri_ops, 303 8, 16, 304 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 305 &default_mode 306 }, mach64_80x25_screen = { 307 "80x25", 80, 25, 308 &mach64_console_screen.ri.ri_ops, 309 8, 16, 310 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 311 &mach64_modes[0] 312 }, mach64_80x30_screen = { 313 "80x30", 80, 30, 314 &mach64_console_screen.ri.ri_ops, 315 8, 16, 316 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 317 &mach64_modes[1] 318 }, mach64_80x40_screen = { 319 "80x40", 80, 40, 320 &mach64_console_screen.ri.ri_ops, 321 8, 10, 322 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 323 &mach64_modes[0] 324 }, mach64_80x50_screen = { 325 "80x50", 80, 50, 326 &mach64_console_screen.ri.ri_ops, 327 8, 8, 328 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 329 &mach64_modes[0] 330 }, mach64_100x37_screen = { 331 "100x37", 100, 37, 332 &mach64_console_screen.ri.ri_ops, 333 8, 16, 334 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 335 &mach64_modes[2] 336 }, mach64_128x48_screen = { 337 "128x48", 128, 48, 338 &mach64_console_screen.ri.ri_ops, 339 8, 16, 340 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 341 &mach64_modes[3] 342 }, mach64_144x54_screen = { 343 "144x54", 144, 54, 344 &mach64_console_screen.ri.ri_ops, 345 8, 16, 346 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 347 &mach64_modes[4] 348 }, mach64_160x64_screen = { 349 "160x54", 160, 64, 350 &mach64_console_screen.ri.ri_ops, 351 8, 16, 352 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 353 &mach64_modes[5] 354 }; 355 356 const struct wsscreen_descr *_mach64_scrlist[] = { 357 &mach64_defaultscreen, 358 &mach64_80x25_screen, 359 &mach64_80x30_screen, 360 &mach64_80x40_screen, 361 &mach64_80x50_screen, 362 &mach64_100x37_screen, 363 &mach64_128x48_screen, 364 &mach64_144x54_screen, 365 &mach64_160x64_screen 366 }; 367 368 struct wsscreen_list mach64_screenlist = { 369 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 370 _mach64_scrlist 371 }; 372 373 int mach64_ioctl(void *, u_long, caddr_t, int, struct proc *); 374 paddr_t mach64_mmap(void *, off_t, int); 375 int mach64_alloc_screen(void *, const struct wsscreen_descr *, void **, 376 int *, int *, long *); 377 void mach64_free_screen(void *, void *); 378 int mach64_show_screen(void *, void *, int, void (*)(void *, int, int), 379 void *); 380 int mach64_load_font(void *, void *, struct wsdisplay_font *); 381 382 struct wsdisplay_accessops mach64_accessops = { 383 mach64_ioctl, 384 mach64_mmap, 385 mach64_alloc_screen, 386 mach64_free_screen, 387 mach64_show_screen, 388 NULL, /* load_font */ 389 NULL, /* polls */ 390 mach64_getwschar, /* getwschar */ 391 mach64_putwschar, /* putwschar */ 392 NULL, /* scroll */ 393 NULL, /* getborder */ 394 NULL /* setborder */ 395 }; 396 397 /* 398 * Inline functions for getting access to register aperture. 399 */ 400 static inline u_int32_t regr(struct mach64_softc *, u_int32_t); 401 static inline u_int8_t regrb(struct mach64_softc *, u_int32_t); 402 static inline void regw(struct mach64_softc *, u_int32_t, u_int32_t); 403 static inline void regwb(struct mach64_softc *, u_int32_t, u_int8_t); 404 static inline void regwb_pll(struct mach64_softc *, u_int32_t, u_int8_t); 405 406 static inline u_int32_t 407 regr(struct mach64_softc *sc, u_int32_t index) 408 { 409 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 410 } 411 412 static inline u_int8_t 413 regrb(struct mach64_softc *sc, u_int32_t index) 414 { 415 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 416 } 417 418 static inline void 419 regw(struct mach64_softc *sc, u_int32_t index, u_int32_t data) 420 { 421 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 422 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 423 BUS_SPACE_BARRIER_WRITE); 424 } 425 426 static inline void 427 regwb(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 428 { 429 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 430 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 431 BUS_SPACE_BARRIER_WRITE); 432 } 433 434 static inline void 435 regwb_pll(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 436 { 437 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 438 regwb(sc, CLOCK_CNTL + 2, data); 439 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 440 } 441 442 static inline void 443 wait_for_fifo(struct mach64_softc *sc, u_int8_t v) 444 { 445 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 446 ; 447 } 448 449 static inline void 450 wait_for_idle(struct mach64_softc *sc) 451 { 452 wait_for_fifo(sc, 16); 453 while ((regr(sc, GUI_STAT) & 1) != 0) 454 ; 455 } 456 457 int 458 mach64_match(struct device *parent, struct cfdata *match, void *aux) 459 { 460 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 461 int i; 462 463 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 464 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 465 return 0; 466 467 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 468 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 469 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 470 mach64_chip_rev = PCI_REVISION(pa->pa_class); 471 return 100; 472 } 473 474 return 0; 475 } 476 477 void 478 mach64_attach(struct device *parent, struct device *self, void *aux) 479 { 480 struct mach64_softc *sc = (void *)self; 481 struct pci_attach_args *pa = aux; 482 char devinfo[256]; 483 int bar, reg, id; 484 struct wsemuldisplaydev_attach_args aa; 485 long defattr; 486 int setmode, console; 487 pcireg_t screg; 488 489 sc->sc_pc = pa->pa_pc; 490 sc->sc_pcitag = pa->pa_tag; 491 sc->sc_dacw=-1; 492 sc->sc_mode=WSDISPLAYIO_MODE_EMUL; 493 494 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 495 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 496 497 /* enable memory and IO access */ 498 screg=pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 499 screg|=PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 500 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 501 502 /* enable memory and IO access */ 503 screg=pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 504 screg|=PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 505 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 506 507 for (bar = 0; bar < NBARS; bar++) { 508 reg = PCI_MAPREG_START + (bar * 4); 509 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 510 sc->sc_pcitag, reg); 511 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 512 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 513 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 514 sc->sc_bars[bar].vb_busaddr=pci_conf_read(sc->sc_pc, 515 sc->sc_pcitag, reg)&0xfffffff0; 516 } 517 sc->sc_memt = pa->pa_memt; 518 519 mach64_init(sc); 520 521 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 522 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 523 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 524 (u_int)sc->sc_regphys); 525 526 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 527 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 528 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 529 (mach64_chip_rev & 0x07) == 0)) 530 sc->has_dsp = 0; 531 else 532 sc->has_dsp = 1; 533 534 sc->memsize = mach64_get_memsize(sc); 535 if (sc->memsize == 8192) 536 /* The last page is used as register aperture. */ 537 sc->memsize -= 4; 538 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 539 540 /* XXX is there any way to calculate reference frequency from 541 known values? */ 542 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 543 ((mach64_chip_id>=PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 544 (mach64_chip_id<=PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 545 printf("ref_freq=29.498MHz\n"); 546 sc->ref_freq = 29498; 547 } else 548 sc->ref_freq = 14318; 549 550 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 551 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 552 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 553 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 554 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 555 (sc->ref_div * 2); 556 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 557 (sc->mem_freq * sc->ref_div); 558 sc->ramdac_freq = mach64_get_max_ramdac(sc); 559 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 560 sc->sc_dev.dv_xname, (u_long)sc->memsize, 561 mach64_memtype_names[sc->memtype], 562 sc->mem_freq / 1000, sc->mem_freq % 1000, 563 sc->ramdac_freq / 1000); 564 565 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 566 if (id != mach64_chip_id) { 567 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 568 sc->sc_dev.dv_xname, id, mach64_chip_id); 569 return; 570 } 571 572 console = mach64_is_console(pa); 573 574 #if defined(__sparc__) || defined(__powerpc__) 575 if (console) { 576 mach64_get_mode(sc, &default_mode); 577 setmode = 0; 578 } else { 579 memcpy(&default_mode, &mach64_modes[4], sizeof(struct 580 videomode)); 581 setmode = 1; 582 } 583 #else 584 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)); 585 setmode = 1; 586 #endif 587 588 sc->bits_per_pixel = 8; 589 sc->virt_x = default_mode.hdisplay; 590 sc->virt_y = default_mode.vdisplay; 591 sc->max_x = sc->virt_x - 1; 592 sc->max_y = (sc->memsize * 1024) / 593 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 594 595 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 596 597 mach64_init_engine(sc); 598 #if 0 599 mach64_adjust_frame(0, 0); 600 if (sc->bits_per_pixel == 8) 601 mach64_init_lut(sc); 602 #endif 603 604 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 605 default_mode.hdisplay, default_mode.vdisplay, 606 sc->bits_per_pixel); 607 608 mach64_console_screen.ri.ri_hw = &mach64_console_screen; 609 mach64_console_screen.ri.ri_depth = sc->bits_per_pixel; 610 mach64_console_screen.ri.ri_width = default_mode.hdisplay; 611 mach64_console_screen.ri.ri_height = default_mode.vdisplay; 612 mach64_console_screen.ri.ri_stride = mach64_console_screen.ri.ri_width; 613 614 mach64_console_screen.ri.ri_bits=(void *)(uintptr_t)sc->sc_aperbase; 615 616 mach64_console_screen.ri.ri_flg = RI_CENTER; 617 mach64_console_screen.active=1; 618 sc->active=&mach64_console_screen; 619 620 /* XXX width/height are nonsense, we only want to pick a font */ 621 rasops_init(&mach64_console_screen.ri, 622 mach64_console_screen.ri.ri_height / 16, 623 mach64_console_screen.ri.ri_width / 8); 624 625 /* now get the real values */ 626 rasops_reconfig(&mach64_console_screen.ri, 627 mach64_console_screen.ri.ri_height / 628 mach64_console_screen.ri.ri_font->fontheight, 629 mach64_console_screen.ri.ri_width / 630 mach64_console_screen.ri.ri_font->fontwidth); 631 632 set_address(&mach64_console_screen.ri,sc->sc_aperbase); 633 634 /* enable acceleration */ 635 mach64_console_screen.ri.ri_ops.copyrows=mach64_copyrows; 636 mach64_console_screen.ri.ri_ops.eraserows=mach64_eraserows; 637 mach64_console_screen.ri.ri_ops.copycols=mach64_copycols; 638 mach64_console_screen.ri.ri_ops.erasecols=mach64_erasecols; 639 mach64_console_screen.ri.ri_ops.putchar=mach64_putchar; 640 mach64_console_screen.ri.ri_ops.cursor=mach64_cursor; 641 642 mach64_defaultscreen.nrows = mach64_console_screen.ri.ri_rows; 643 mach64_defaultscreen.ncols = mach64_console_screen.ri.ri_cols; 644 645 mach64_allocattr(&mach64_console_screen.ri, WS_DEFAULT_FG, 646 WS_DEFAULT_BG, 0, &defattr); 647 648 sc->sc_bg=WS_DEFAULT_BG; 649 650 /* really necessary? */ 651 mach64_defaultscreen.capabilities=mach64_console_screen.ri.ri_caps; 652 mach64_defaultscreen.textops=&mach64_console_screen.ri.ri_ops; 653 654 /* Initialize fonts */ 655 /* XXX shouldn't that happen /before/ we call rasops_init()? */ 656 wsfont_init(); 657 658 if (console) { 659 mach64_init_screen(sc, &mach64_console_screen, 660 &mach64_defaultscreen, 1, &defattr, setmode); 661 wsdisplay_cnattach(&mach64_defaultscreen, 662 &mach64_console_screen.ri, 0, 0, defattr); 663 } 664 665 mach64_init_lut(sc); 666 mach64_clearscreen(sc); 667 668 aa.console = console; 669 aa.scrdata = &mach64_screenlist; 670 aa.accessops = &mach64_accessops; 671 aa.accesscookie = sc; 672 673 config_found(self, &aa, wsemuldisplaydevprint); 674 } 675 676 void 677 mach64_init_screen(struct mach64_softc *sc, struct mach64screen *scr, 678 const struct wsscreen_descr *type, int existing, long *attrp, int setmode) 679 { 680 struct rasops_info *ri=&scr->ri; 681 int cnt; 682 scr->sc = sc; 683 scr->type = type; 684 scr->mindispoffset = 0; 685 scr->maxdispoffset = sc->memsize * 1024; 686 scr->dispoffset = 0; 687 scr->cursorcol = 0; 688 scr->cursorrow = 0; 689 690 cnt=type->nrows * type->ncols; 691 scr->attrs=(long *)malloc(cnt * (sizeof(long) + sizeof(u_int)), 692 M_DEVBUF, M_WAITOK); 693 scr->chars=(u_int *)&scr->attrs[cnt]; 694 695 /* 696 * we allocate both chars and attributes in one chunk, attributes first 697 * because they have the (potentially) bigger alignment 698 */ 699 ri->ri_depth = sc->bits_per_pixel; 700 ri->ri_width = default_mode.hdisplay; 701 ri->ri_height = default_mode.vdisplay; 702 ri->ri_stride = ri->ri_width; 703 ri->ri_flg = RI_CENTER; 704 705 if (existing) { 706 scr->active = 1; 707 ri->ri_flg|=RI_CLEAR; 708 if (setmode && mach64_set_screentype(sc, type)) { 709 panic("%s: failed to switch video mode", 710 sc->sc_dev.dv_xname); 711 } 712 } else { 713 scr->active = 0; 714 } 715 716 LIST_INSERT_HEAD(&sc->screens, scr, next); 717 } 718 719 void 720 mach64_init(struct mach64_softc *sc) 721 { 722 u_int32_t *p32, saved_value; 723 u_int8_t *p; 724 int need_swap; 725 726 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 727 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 728 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 729 } 730 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 731 732 sc->sc_regt = sc->sc_memt; 733 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 734 sc->sc_regsize, &sc->sc_regh); 735 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 736 737 /* 738 * Test wether the aperture is byte swapped or not 739 */ 740 p32 = (u_int32_t*)(u_long)sc->sc_aperbase; 741 saved_value = *p32; 742 p = (u_int8_t*)(u_long)sc->sc_aperbase; 743 *p32 = 0x12345678; 744 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 745 need_swap = 0; 746 else 747 need_swap = 1; 748 if (need_swap) { 749 sc->sc_aperbase += 0x800000; 750 sc->sc_apersize -= 0x800000; 751 } 752 *p32 = saved_value; 753 754 LIST_INIT(&sc->screens); 755 sc->active = NULL; 756 sc->currenttype = &mach64_defaultscreen; 757 callout_init(&sc->switch_callout); 758 } 759 760 int 761 mach64_get_memsize(struct mach64_softc *sc) 762 { 763 int tmp, memsize; 764 int mem_tab[] = { 765 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 766 }; 767 768 tmp = regr(sc, MEM_CNTL); 769 printf("memctl: %08x\n",tmp); 770 if (sc->has_dsp) { 771 tmp &= 0x0000000f; 772 if (tmp < 8) 773 memsize = (tmp + 1) * 512; 774 else if (tmp < 12) 775 memsize = (tmp - 3) * 1024; 776 else 777 memsize = (tmp - 7) * 2048; 778 } else { 779 memsize = mem_tab[tmp & 0x07]; 780 } 781 782 return memsize; 783 } 784 785 int 786 mach64_get_max_ramdac(struct mach64_softc *sc) 787 { 788 int i; 789 790 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 791 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 792 (mach64_chip_rev & 0x07)) 793 return 170000; 794 795 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 796 if (mach64_chip_id == mach64_info[i].chip_id) 797 return mach64_info[i].ramdac_freq; 798 799 if (sc->bits_per_pixel == 8) 800 return 135000; 801 else 802 return 80000; 803 } 804 805 void 806 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 807 { 808 struct mach64_crtcregs crtc; 809 810 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 811 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 812 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 813 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 814 815 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 816 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 817 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 818 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 819 mode->hsync_start; 820 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 821 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 822 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 823 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 824 825 #ifdef DEBUG_MACHFB 826 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 827 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 828 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 829 #endif 830 } 831 832 int 833 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 834 struct videomode *mode) 835 { 836 837 if (mode->dot_clock > sc->ramdac_freq) 838 /* Clock too high. */ 839 return 1; 840 841 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 842 ((mode->htotal >> 3) - 1); 843 crtc->h_sync_strt_wid = 844 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 845 ((mode->hsync_start >> 3) - 1); 846 847 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 848 (mode->vtotal - 1); 849 crtc->v_sync_strt_wid = 850 ((mode->vsync_end - mode->vsync_start) << 16) | 851 (mode->vsync_start - 1); 852 853 if (mode->flags & VID_NVSYNC) 854 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 855 856 switch (sc->bits_per_pixel) { 857 case 8: 858 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 859 break; 860 case 16: 861 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 862 break; 863 case 32: 864 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 865 break; 866 } 867 868 crtc->gen_cntl = 0; 869 if (mode->flags & VID_INTERLACE) 870 crtc->gen_cntl |= CRTC_INTERLACE_EN; 871 if (mode->flags & VID_CSYNC) 872 crtc->gen_cntl |= CRTC_CSYNC_EN; 873 874 crtc->dot_clock = mode->dot_clock; 875 876 return 0; 877 } 878 879 void 880 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 881 { 882 883 mach64_set_pll(sc, crtc->dot_clock); 884 885 if (sc->has_dsp) 886 mach64_set_dsp(sc); 887 888 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 889 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 890 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 891 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 892 893 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 894 895 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 896 897 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 898 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 899 } 900 901 int 902 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 903 { 904 struct mach64_crtcregs crtc; 905 906 if (mach64_calc_crtcregs(sc, &crtc, mode)) 907 return 1; 908 909 mach64_set_crtcregs(sc, &crtc); 910 return 0; 911 } 912 913 void 914 mach64_reset_engine(struct mach64_softc *sc) 915 { 916 917 /* Reset engine.*/ 918 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 919 920 /* Enable engine. */ 921 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 922 923 /* Ensure engine is not locked up by clearing any FIFO or 924 host errors. */ 925 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 926 BUS_FIFO_ERR_ACK); 927 } 928 929 void 930 mach64_init_engine(struct mach64_softc *sc) 931 { 932 u_int32_t pitch_value; 933 934 pitch_value = sc->virt_x; 935 936 if (sc->bits_per_pixel == 24) 937 pitch_value *= 3; 938 939 mach64_reset_engine(sc); 940 941 wait_for_fifo(sc, 14); 942 943 regw(sc, CONTEXT_MASK, 0xffffffff); 944 945 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 946 947 regw(sc, DST_Y_X, 0); 948 regw(sc, DST_HEIGHT, 0); 949 regw(sc, DST_BRES_ERR, 0); 950 regw(sc, DST_BRES_INC, 0); 951 regw(sc, DST_BRES_DEC, 0); 952 953 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 954 DST_Y_TOP_TO_BOTTOM); 955 956 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 957 958 regw(sc, SRC_Y_X, 0); 959 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 960 regw(sc, SRC_Y_X_START, 0); 961 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 962 963 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 964 965 wait_for_fifo(sc, 13); 966 regw(sc, HOST_CNTL, 0); 967 968 regw(sc, PAT_REG0, 0); 969 regw(sc, PAT_REG1, 0); 970 regw(sc, PAT_CNTL, 0); 971 972 regw(sc, SC_LEFT, 0); 973 regw(sc, SC_TOP, 0); 974 regw(sc, SC_BOTTOM, default_mode.vdisplay - 1); 975 regw(sc, SC_RIGHT, pitch_value - 1); 976 977 regw(sc, DP_BKGD_CLR, 0); 978 regw(sc, DP_FRGD_CLR, 0xffffffff); 979 regw(sc, DP_WRITE_MASK, 0xffffffff); 980 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 981 982 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 983 984 wait_for_fifo(sc, 3); 985 regw(sc, CLR_CMP_CLR, 0); 986 regw(sc, CLR_CMP_MASK, 0xffffffff); 987 regw(sc, CLR_CMP_CNTL, 0); 988 989 wait_for_fifo(sc, 2); 990 switch (sc->bits_per_pixel) { 991 case 8: 992 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 993 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 994 /* We want 8 bit per channel */ 995 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 996 break; 997 #if 0 998 case 32: 999 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 1000 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1001 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1002 break; 1003 #endif 1004 } 1005 1006 wait_for_fifo(sc, 5); 1007 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1008 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1009 1010 wait_for_idle(sc); 1011 } 1012 1013 void 1014 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1015 { 1016 int offset; 1017 1018 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1019 1020 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1021 offset); 1022 } 1023 1024 void 1025 mach64_set_dsp(struct mach64_softc *sc) 1026 { 1027 u_int32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1028 u_int32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1029 u_int32_t xclks_per_qw, y; 1030 u_int32_t fifo_off, fifo_on; 1031 1032 printf("initializing the DSP\n"); 1033 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1034 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1035 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1036 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1037 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1038 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1039 dsp_loop_latency = 0; 1040 fifo_depth = 24; 1041 } else { 1042 dsp_loop_latency = 2; 1043 fifo_depth = 32; 1044 } 1045 1046 dsp_precision = 0; 1047 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1048 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1049 y = (xclks_per_qw * fifo_depth) >> 11; 1050 while (y) { 1051 y >>= 1; 1052 dsp_precision++; 1053 } 1054 dsp_precision -= 5; 1055 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1056 1057 switch (sc->memtype) { 1058 case DRAM: 1059 case EDO_DRAM: 1060 case PSEUDO_EDO: 1061 if (sc->memsize > 1024) { 1062 page_size = 9; 1063 dsp_loop_latency += 6; 1064 } else { 1065 page_size = 10; 1066 if (sc->memtype == DRAM) 1067 dsp_loop_latency += 8; 1068 else 1069 dsp_loop_latency += 7; 1070 } 1071 break; 1072 case SDRAM: 1073 case SGRAM: 1074 if (sc->memsize > 1024) { 1075 page_size = 8; 1076 dsp_loop_latency += 8; 1077 } else { 1078 page_size = 10; 1079 dsp_loop_latency += 9; 1080 } 1081 break; 1082 default: 1083 page_size = 10; 1084 dsp_loop_latency += 9; 1085 break; 1086 } 1087 1088 if (xclks_per_qw >= (page_size << 11)) 1089 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1090 else 1091 fifo_on = (3 * page_size + 2) << 6; 1092 1093 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1094 dsp_on = fifo_on >> dsp_precision; 1095 dsp_off = fifo_off >> dsp_precision; 1096 1097 #ifdef DEBUG_MACHFB 1098 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1099 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1100 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1101 "mclk_post_div = %d, vclk_post_div = %d\n", 1102 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1103 sc->mclk_fb_div, sc->vclk_fb_div, 1104 sc->mclk_post_div, sc->vclk_post_div); 1105 #endif 1106 1107 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1108 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1109 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1110 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1111 } 1112 1113 void 1114 mach64_set_pll(struct mach64_softc *sc, int clock) 1115 { 1116 int q; 1117 1118 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1119 #ifdef DEBUG_MACHFB 1120 printf("q = %d\n", q); 1121 #endif 1122 if (q > 25500) { 1123 printf("Warning: q > 25500\n"); 1124 q = 25500; 1125 sc->vclk_post_div = 1; 1126 sc->log2_vclk_post_div = 0; 1127 } else if (q > 12750) { 1128 sc->vclk_post_div = 1; 1129 sc->log2_vclk_post_div = 0; 1130 } else if (q > 6350) { 1131 sc->vclk_post_div = 2; 1132 sc->log2_vclk_post_div = 1; 1133 } else if (q > 3150) { 1134 sc->vclk_post_div = 4; 1135 sc->log2_vclk_post_div = 2; 1136 } else if (q >= 1600) { 1137 sc->vclk_post_div = 8; 1138 sc->log2_vclk_post_div = 3; 1139 } else { 1140 printf("Warning: q < 1600\n"); 1141 sc->vclk_post_div = 8; 1142 sc->log2_vclk_post_div = 3; 1143 } 1144 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1145 1146 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1147 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1148 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1149 } 1150 1151 void 1152 mach64_init_lut(struct mach64_softc *sc) 1153 { 1154 int i,idx; 1155 idx=0; 1156 for(i=0;i<256;i++) { 1157 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx+1], 1158 rasops_cmap[idx+2]); 1159 idx+=3; 1160 } 1161 } 1162 1163 int 1164 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, uint8_t b) 1165 { 1166 sc->sc_cmap_red[index]=r; 1167 sc->sc_cmap_green[index]=g; 1168 sc->sc_cmap_blue[index]=b; 1169 /* 1170 * writing the dac index takes a while, in theory we can poll some 1171 * register to see when it's ready - but we better avoid writing it 1172 * unnecessarily 1173 */ 1174 if(index!=sc->sc_dacw) 1175 { 1176 regwb(sc, DAC_MASK, 0xff); 1177 regwb(sc, DAC_WINDEX, index); 1178 } 1179 sc->sc_dacw=index+1; 1180 regwb(sc, DAC_DATA, r); 1181 regwb(sc, DAC_DATA, g); 1182 regwb(sc, DAC_DATA, b); 1183 return 0; 1184 } 1185 1186 int 1187 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1188 { 1189 u_int index = cm->index; 1190 u_int count = cm->count; 1191 int i, error; 1192 u_char rbuf[256], gbuf[256], bbuf[256]; 1193 u_char *r, *g, *b; 1194 1195 printf("putcmap: %d %d\n",index, count); 1196 if (cm->index >= 256 || cm->count > 256 || 1197 (cm->index + cm->count) > 256) 1198 return EINVAL; 1199 error = copyin(cm->red, &rbuf[index], count); 1200 if (error) 1201 return error; 1202 error = copyin(cm->green, &gbuf[index], count); 1203 if (error) 1204 return error; 1205 error = copyin(cm->blue, &bbuf[index], count); 1206 if (error) 1207 return error; 1208 1209 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1210 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1211 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1212 1213 r = &sc->sc_cmap_red[index]; 1214 g = &sc->sc_cmap_green[index]; 1215 b = &sc->sc_cmap_blue[index]; 1216 1217 for (i = 0; i < count; i++) { 1218 mach64_putpalreg(sc,index,*r, *g, *b); 1219 index++; 1220 r++, g++, b++; 1221 } 1222 return 0; 1223 } 1224 1225 int 1226 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1227 { 1228 u_int index = cm->index; 1229 u_int count = cm->count; 1230 int error; 1231 1232 if (index >= 255 || count > 256 || index + count > 256) 1233 return EINVAL; 1234 1235 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1236 if (error) 1237 return error; 1238 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1239 if (error) 1240 return error; 1241 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1242 if (error) 1243 return error; 1244 1245 return 0; 1246 } 1247 1248 int 1249 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1250 { 1251 struct mach64_crtcregs regs; 1252 1253 if (mach64_calc_crtcregs(sc, ®s, 1254 (struct videomode *)des->modecookie)) 1255 return 1; 1256 1257 mach64_set_crtcregs(sc, ®s); 1258 return 0; 1259 } 1260 1261 int 1262 mach64_is_console(struct pci_attach_args *pa) 1263 { 1264 #ifdef __sparc__ 1265 int node; 1266 1267 node = PCITAG_NODE(pa->pa_tag); 1268 if (node == -1) 1269 return 0; 1270 1271 return (node == prom_instance_to_package(prom_stdout())); 1272 #elif defined(__powerpc__) 1273 /* check if we're the /chosen console device */ 1274 int chosen, stdout, node, us; 1275 us=pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1276 chosen = OF_finddevice("/chosen"); 1277 OF_getprop(chosen, "stdout", &stdout, 4); 1278 node = OF_instance_to_package(stdout); 1279 return(us == node); 1280 #else 1281 return 1; 1282 #endif 1283 } 1284 1285 /* 1286 * wsdisplay_emulops 1287 */ 1288 1289 void 1290 mach64_cursor(void *cookie, int on, int row, int col) 1291 { 1292 struct rasops_info *ri=cookie; 1293 struct mach64screen *scr=ri->ri_hw; 1294 struct mach64_softc *sc=scr->sc; 1295 int x,y,wi=ri->ri_font->fontwidth,he=ri->ri_font->fontheight; 1296 if(scr->active) { 1297 x=scr->cursorcol*wi+ri->ri_xorigin; 1298 y=scr->cursorrow*he+ri->ri_yorigin; 1299 if(scr->cursordrawn) { 1300 mach64_bitblt(sc,x,y,x,y,wi,he,MIX_NOT_SRC,0xff); 1301 scr->cursordrawn=0; 1302 } 1303 scr->cursorrow=row; 1304 scr->cursorcol=col; 1305 if((scr->cursoron=on)!=0) 1306 { 1307 x=scr->cursorcol*wi+ri->ri_xorigin; 1308 y=scr->cursorrow*he+ri->ri_yorigin; 1309 mach64_bitblt(sc,x,y,x,y,wi,he,MIX_NOT_SRC,0xff); 1310 scr->cursordrawn=1; 1311 } 1312 } else { 1313 scr->cursoron=on; 1314 scr->cursorrow=row; 1315 scr->cursorcol=col; 1316 scr->cursordrawn=0; 1317 } 1318 } 1319 1320 #if 0 1321 int 1322 mach64_mapchar(void *cookie, int uni, u_int *index) 1323 { 1324 1325 return 0; 1326 } 1327 #endif 1328 1329 void 1330 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1331 { 1332 struct rasops_info *ri=cookie; 1333 struct mach64screen *scr=ri->ri_hw; 1334 struct mach64_softc *sc=scr->sc; 1335 int offset=ri->ri_cols*row+col; 1336 scr->attrs[offset]=attr; 1337 scr->chars[offset]=c; 1338 if((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1339 int fg,bg,uc; 1340 uint8_t *data; 1341 int x,y,wi=ri->ri_font->fontwidth,he=ri->ri_font->fontheight; 1342 1343 /*scr->putchar(cookie,row,col,c,attr);*/ 1344 if (!CHAR_IN_FONT(c, ri->ri_font)) 1345 return; 1346 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1347 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1348 x=ri->ri_xorigin+col*wi; 1349 y=ri->ri_yorigin+row*he; 1350 if(c == 0x20) { 1351 mach64_rectfill(sc,x,y,wi,he,bg); 1352 } else { 1353 uc = c-ri->ri_font->firstchar; 1354 data = (uint8_t *)ri->ri_font->data + uc * 1355 ri->ri_fontscale; 1356 1357 mach64_setup_mono(sc,x,y,wi,he,fg,bg); 1358 mach64_feed_bytes(sc,ri->ri_fontscale,data); 1359 } 1360 } 1361 } 1362 1363 1364 void 1365 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1366 { 1367 struct rasops_info *ri=cookie; 1368 struct mach64screen *scr=ri->ri_hw; 1369 struct mach64_softc *sc=scr->sc; 1370 int32_t xs,xd,y,width,height; 1371 1372 int from=srccol+row*ri->ri_cols; 1373 int to=dstcol+row*ri->ri_cols; 1374 memmove(&scr->attrs[to],&scr->attrs[from],ncols*sizeof(long)); 1375 memmove(&scr->chars[to],&scr->chars[from],ncols*sizeof(u_int)); 1376 1377 if((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1378 xs=ri->ri_xorigin+ri->ri_font->fontwidth*srccol; 1379 xd=ri->ri_xorigin+ri->ri_font->fontwidth*dstcol; 1380 y=ri->ri_yorigin+ri->ri_font->fontheight*row; 1381 width=ri->ri_font->fontwidth*ncols; 1382 height=ri->ri_font->fontheight; 1383 mach64_bitblt(sc,xs,y,xd,y,width,height,MIX_SRC,0xff); 1384 } 1385 } 1386 1387 void 1388 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1389 { 1390 struct rasops_info *ri=cookie; 1391 struct mach64screen *scr=ri->ri_hw; 1392 struct mach64_softc *sc=scr->sc; 1393 int32_t x,y,width,height,fg,bg,ul;; 1394 1395 int start=startcol+row*ri->ri_cols; 1396 int end=start+ncols, i; 1397 for(i=start;i<end;i++) { 1398 scr->attrs[i]=fillattr; 1399 scr->chars[i]=0x20; 1400 } 1401 if((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1402 x=ri->ri_xorigin+ri->ri_font->fontwidth*startcol; 1403 y=ri->ri_yorigin+ri->ri_font->fontheight*row; 1404 width=ri->ri_font->fontwidth*ncols; 1405 height=ri->ri_font->fontheight; 1406 rasops_unpack_attr(fillattr,&fg,&bg,&ul); 1407 1408 mach64_rectfill(sc,x,y,width,height,bg); 1409 } 1410 } 1411 1412 void 1413 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1414 { 1415 struct rasops_info *ri=cookie; 1416 struct mach64screen *scr=ri->ri_hw; 1417 struct mach64_softc *sc=scr->sc; 1418 int32_t x, ys, yd, width, height; 1419 1420 int from, to, len; 1421 from=ri->ri_cols*srcrow; 1422 to=ri->ri_cols*dstrow; 1423 len=ri->ri_cols*nrows; 1424 1425 memmove(&scr->attrs[to],&scr->attrs[from],len*sizeof(long)); 1426 memmove(&scr->chars[to],&scr->chars[from],len*sizeof(u_int)); 1427 1428 if((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1429 x=ri->ri_xorigin; 1430 ys=ri->ri_yorigin+ri->ri_font->fontheight*srcrow; 1431 yd=ri->ri_yorigin+ri->ri_font->fontheight*dstrow; 1432 width=ri->ri_emuwidth; 1433 height=ri->ri_font->fontheight*nrows; 1434 mach64_bitblt(sc,x,ys,x,yd,width,height,MIX_SRC,0xff); 1435 } 1436 } 1437 1438 void 1439 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1440 { 1441 struct rasops_info *ri=cookie; 1442 struct mach64screen *scr=ri->ri_hw; 1443 struct mach64_softc *sc=scr->sc; 1444 int32_t x,y,width,height,fg,bg,ul; 1445 1446 int start=ri->ri_cols*row, end=ri->ri_cols*(row+nrows),i; 1447 for(i=start;i<end;i++) { 1448 scr->attrs[i]=fillattr; 1449 scr->chars[i]=0x20; 1450 } 1451 1452 if((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1453 x=ri->ri_xorigin; 1454 y=ri->ri_yorigin+ri->ri_font->fontheight*row; 1455 width=ri->ri_emuwidth; 1456 height=ri->ri_font->fontheight*nrows; 1457 rasops_unpack_attr(fillattr,&fg,&bg,&ul); 1458 1459 mach64_rectfill(sc,x,y,width,height,bg); 1460 } 1461 } 1462 1463 void 1464 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1465 { 1466 uint32_t dest_ctl=0; 1467 wait_for_idle(sc); 1468 regw(sc,DP_WRITE_MASK,mask); /* XXX only good for 8 bit */ 1469 regw(sc,DP_PIX_WIDTH,DST_8BPP|SRC_8BPP|HOST_8BPP); 1470 regw(sc,DP_SRC,FRGD_SRC_BLIT); 1471 regw(sc,DP_MIX,(rop&0xffff)<<16); 1472 regw(sc,CLR_CMP_CNTL,0); /* no transparency */ 1473 if(yd<ys) { 1474 dest_ctl=DST_Y_TOP_TO_BOTTOM; 1475 } else { 1476 ys+=height-1; 1477 yd+=height-1; 1478 dest_ctl=DST_Y_BOTTOM_TO_TOP; 1479 } 1480 if(xd<xs) { 1481 dest_ctl|=DST_X_LEFT_TO_RIGHT; 1482 regw(sc,SRC_CNTL,SRC_LINE_X_LEFT_TO_RIGHT); 1483 } else { 1484 dest_ctl|=DST_X_RIGHT_TO_LEFT; 1485 xs+=width-1; 1486 xd+=width-1; 1487 regw(sc,SRC_CNTL,SRC_LINE_X_RIGHT_TO_LEFT); 1488 } 1489 regw(sc,DST_CNTL,dest_ctl); 1490 1491 regw(sc,SRC_Y_X,(xs<<16)|ys); 1492 regw(sc,SRC_WIDTH1,width); 1493 regw(sc,DST_Y_X,(xd<<16)|yd); 1494 regw(sc,DST_HEIGHT_WIDTH,(width<<16)|height); 1495 } 1496 1497 void 1498 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1499 int height, uint32_t fg, uint32_t bg) 1500 { 1501 wait_for_idle(sc); 1502 regw(sc,DP_WRITE_MASK,0xff); /* XXX only good for 8 bit */ 1503 regw(sc,DP_PIX_WIDTH,DST_8BPP|SRC_1BPP|HOST_1BPP); 1504 regw(sc,DP_SRC,MONO_SRC_HOST|BKGD_SRC_BKGD_CLR|FRGD_SRC_FRGD_CLR); 1505 regw(sc,DP_MIX,((MIX_SRC&0xffff)<<16)|MIX_SRC); 1506 regw(sc,CLR_CMP_CNTL,0); /* no transparency */ 1507 regw(sc,SRC_CNTL,SRC_LINE_X_LEFT_TO_RIGHT); 1508 regw(sc,DST_CNTL,DST_Y_TOP_TO_BOTTOM|DST_X_LEFT_TO_RIGHT); 1509 regw(sc,HOST_CNTL,HOST_BYTE_ALIGN); 1510 regw(sc,DP_BKGD_CLR,bg); 1511 regw(sc,DP_FRGD_CLR,fg); 1512 regw(sc,SRC_Y_X,0); 1513 regw(sc,SRC_WIDTH1,width); 1514 regw(sc,DST_Y_X,(xd<<16)|yd); 1515 regw(sc,DST_HEIGHT_WIDTH,(width<<16)|height); 1516 /* now feed the data into the chip */ 1517 } 1518 1519 void 1520 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1521 { 1522 int i; 1523 uint32_t latch=0, bork; 1524 int shift=0; 1525 int reg=0; 1526 for(i=0;i<count;i++) { 1527 bork=data[i]; 1528 latch|=(bork<<shift); 1529 if(shift == 24) { 1530 regw(sc,HOST_DATA0+reg,latch); 1531 latch=0; 1532 shift=0; 1533 reg=(reg+4)&0x3c; 1534 } else 1535 shift+=8; 1536 } 1537 if(shift!=0) /* 24 */ 1538 regw(sc,HOST_DATA0+reg,latch); 1539 } 1540 1541 1542 void 1543 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1544 int colour) 1545 { 1546 wait_for_idle(sc); 1547 regw(sc,DP_WRITE_MASK,0xff); 1548 regw(sc,DP_FRGD_CLR,colour); 1549 regw(sc,DP_PIX_WIDTH,DST_8BPP|SRC_8BPP|HOST_8BPP); 1550 regw(sc,DP_SRC,FRGD_SRC_FRGD_CLR); 1551 regw(sc,DP_MIX,(MIX_SRC)<<16); 1552 regw(sc,CLR_CMP_CNTL,0); /* no transparency */ 1553 regw(sc,SRC_CNTL,SRC_LINE_X_LEFT_TO_RIGHT); 1554 regw(sc,DST_CNTL,DST_X_LEFT_TO_RIGHT|DST_Y_TOP_TO_BOTTOM); 1555 1556 regw(sc,SRC_Y_X,(x<<16)|y); 1557 regw(sc,SRC_WIDTH1,width); 1558 regw(sc,DST_Y_X,(x<<16)|y); 1559 regw(sc,DST_HEIGHT_WIDTH,(width<<16)|height); 1560 } 1561 1562 void 1563 mach64_clearscreen(struct mach64_softc *sc) 1564 { 1565 mach64_rectfill(sc,0,0,sc->virt_x,sc->virt_y,sc->sc_bg); 1566 } 1567 1568 1569 void 1570 mach64_showpal(struct mach64_softc *sc) 1571 { 1572 int i,x=0; 1573 for (i=0;i<16;i++) { 1574 mach64_rectfill(sc,x,0,64,64,i); 1575 x+=64; 1576 } 1577 } 1578 1579 int 1580 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1581 { 1582 if((fg == 0)&&(bg == 0)) 1583 { 1584 fg=WS_DEFAULT_FG; 1585 bg=WS_DEFAULT_BG; 1586 } 1587 *attrp=(fg&0xf)<<24|(bg&0xf)<<16|(flags&0xff)<<8; 1588 return 0; 1589 } 1590 1591 /* 1592 * wsdisplay_accessops 1593 */ 1594 1595 int 1596 mach64_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 1597 { 1598 struct mach64_softc *sc = v; 1599 struct wsdisplay_fbinfo *wdf; 1600 struct mach64screen *ms=sc->active; 1601 switch (cmd) { 1602 case WSDISPLAYIO_GTYPE: 1603 /* XXX is this the right type to return? */ 1604 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1605 return 0; 1606 1607 case WSDISPLAYIO_GINFO: 1608 wdf = (void *)data; 1609 wdf->height = ms->ri.ri_height; 1610 wdf->width = ms->ri.ri_width; 1611 wdf->depth = ms->ri.ri_depth; 1612 wdf->cmsize = 256; 1613 return 0; 1614 case WSDISPLAYIO_GETCMAP: 1615 return mach64_getcmap(sc, 1616 (struct wsdisplay_cmap *)data); 1617 1618 case WSDISPLAYIO_PUTCMAP: 1619 return mach64_putcmap(sc, 1620 (struct wsdisplay_cmap *)data); 1621 /* PCI config read/write passthrough. */ 1622 case PCI_IOC_CFGREAD: 1623 case PCI_IOC_CFGWRITE: 1624 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1625 cmd, data, flag, p)); 1626 case WSDISPLAYIO_SMODE: 1627 { 1628 int new_mode=*(int*)data; 1629 if(new_mode!=sc->sc_mode) 1630 { 1631 sc->sc_mode=new_mode; 1632 if(new_mode == WSDISPLAYIO_MODE_EMUL) 1633 { 1634 /* 1635 * reset a few things the 1636 * Xserver might have screwed up 1637 */ 1638 mach64_restore_screen(ms, 1639 ms->type, ms->chars); 1640 mach64_cursor(ms, ms->cursoron, 1641 ms->cursorrow, 1642 ms->cursorcol); 1643 } 1644 } 1645 } 1646 return 0; 1647 case WSDISPLAYIO_GETWSCHAR: 1648 return mach64_getwschar(sc, 1649 (struct wsdisplay_char *)data); 1650 case WSDISPLAYIO_PUTWSCHAR: 1651 return mach64_putwschar(sc, 1652 (struct wsdisplay_char *)data); 1653 } 1654 return EPASSTHROUGH; 1655 } 1656 1657 paddr_t 1658 mach64_mmap(void *v, off_t offset, int prot) 1659 { 1660 struct mach64_softc *sc = v; 1661 paddr_t pa; 1662 /* 'regular' framebuffer mmap()ing */ 1663 if(offset<sc->sc_apersize) { 1664 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase+offset, 0, 1665 prot, BUS_SPACE_MAP_LINEAR); 1666 return pa; 1667 } 1668 #if 0 1669 /* evil hack to allow mmap()ing other devices as well */ 1670 if((offset>0x80000000) && (offset<=0xffffffff)) { 1671 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1672 BUS_SPACE_MAP_LINEAR); 1673 return pa; 1674 } 1675 #endif 1676 1677 if((offset>=sc->sc_aperphys) && 1678 (offset<(sc->sc_aperphys+sc->sc_apersize))) { 1679 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1680 BUS_SPACE_MAP_LINEAR); 1681 return pa; 1682 } 1683 1684 if((offset>=sc->sc_regphys) && 1685 (offset<(sc->sc_regphys+sc->sc_regsize))) { 1686 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1687 BUS_SPACE_MAP_LINEAR); 1688 return pa; 1689 } 1690 1691 return -1; 1692 } 1693 1694 int 1695 mach64_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 1696 int *curxp, int *curyp, long *defattrp) 1697 { 1698 struct mach64_softc *sc = v; 1699 struct mach64screen *scr; 1700 struct rasops_info *ri; 1701 int cnt=type->nrows * type->ncols; 1702 1703 scr = malloc(sizeof(struct mach64screen), M_DEVBUF, M_WAITOK|M_ZERO); 1704 mach64_init_screen(sc, scr, type, 0, defattrp, sc->active == NULL); 1705 ri=&scr->ri; 1706 1707 ri->ri_hw=scr; 1708 /*ri->ri_bits=(void *)sc->sc_aperbase;*/ 1709 rasops_init(ri, mach64_console_screen.ri.ri_height / 8, 1710 mach64_console_screen.ri.ri_width / 8); 1711 1712 rasops_reconfig(ri, ri->ri_height / ri->ri_font->fontheight, 1713 ri->ri_width / ri->ri_font->fontwidth); 1714 set_address(ri,sc->sc_aperbase); 1715 mach64_allocattr(ri,WS_DEFAULT_FG,WS_DEFAULT_BG,0,defattrp); 1716 1717 scr->ri.ri_ops.copyrows=mach64_copyrows; 1718 scr->ri.ri_ops.eraserows=mach64_eraserows; 1719 scr->ri.ri_ops.copycols=mach64_copycols; 1720 scr->ri.ri_ops.erasecols=mach64_erasecols; 1721 scr->ri.ri_ops.putchar=mach64_putchar; 1722 scr->ri.ri_ops.cursor=mach64_cursor; 1723 1724 scr->attrs=(long *)malloc((cnt)*(sizeof(long)+sizeof(u_int)), 1725 M_DEVBUF, M_WAITOK); 1726 scr->chars=(u_int *)&scr->attrs[cnt]; 1727 mach64_eraserows(ri, 0, ri->ri_rows, *defattrp); 1728 1729 if (sc->active == NULL) { 1730 scr->active = 1; 1731 sc->active = scr; 1732 sc->currenttype = type; 1733 } 1734 1735 *cookiep = scr; 1736 *curxp = scr->cursorcol; 1737 *curyp = scr->cursorrow; 1738 1739 return 0; 1740 } 1741 1742 void 1743 mach64_free_screen(void *v, void *cookie) 1744 { 1745 struct mach64_softc *sc = v; 1746 struct mach64screen *scr = cookie; 1747 1748 LIST_REMOVE(scr, next); 1749 if (scr != &mach64_console_screen) { 1750 free(scr->attrs,M_DEVBUF); 1751 free(scr, M_DEVBUF); 1752 } else 1753 panic("mach64_free_screen: console"); 1754 1755 if (sc->active == scr) 1756 sc->active = 0; 1757 } 1758 1759 int 1760 mach64_show_screen(void *v, void *cookie, int waitok, 1761 void (*cb)(void *, int, int), void *cbarg) 1762 { 1763 struct mach64_softc *sc = v; 1764 struct mach64screen *scr, *oldscr; 1765 1766 scr = cookie; 1767 oldscr = sc->active; 1768 if (scr == oldscr) 1769 return 0; 1770 1771 sc->wanted = scr; 1772 sc->switchcb = cb; 1773 sc->switchcbarg = cbarg; 1774 if (cb) { 1775 callout_reset(&sc->switch_callout, 0, 1776 (void(*)(void *))mach64_switch_screen, sc); 1777 return EAGAIN; 1778 } 1779 1780 mach64_switch_screen(sc); 1781 1782 return 0; 1783 } 1784 1785 void 1786 mach64_switch_screen(struct mach64_softc *sc) 1787 { 1788 struct mach64screen *scr, *oldscr; 1789 const struct wsscreen_descr *type; 1790 1791 scr = sc->wanted; 1792 if (!scr) { 1793 printf("mach64_switch_screen: disappeared\n"); 1794 (*sc->switchcb)(sc->switchcbarg, EIO, 0); 1795 return; 1796 } 1797 type = scr->type; 1798 oldscr = sc->active; /* can be NULL! */ 1799 #ifdef DIAGNOSTIC 1800 if (oldscr) { 1801 if (!oldscr->active) 1802 panic("mach64_switch_screen: not active"); 1803 if (oldscr->type != sc->currenttype) 1804 panic("mach64_switch_screen: bad type"); 1805 } 1806 #endif 1807 if (scr == oldscr) 1808 return; 1809 1810 #ifdef DIAGNOSTIC 1811 /* XXX: this one bites us at reboot */ 1812 /* if (scr->active) 1813 panic("mach64_switch_screen: active");*/ 1814 #endif 1815 1816 if (oldscr) 1817 oldscr->active = 0; 1818 1819 if (sc->currenttype != type) { 1820 mach64_set_screentype(sc, type); 1821 sc->currenttype = type; 1822 } 1823 1824 scr->dispoffset = scr->mindispoffset; 1825 1826 if (!oldscr || (scr->dispoffset != oldscr->dispoffset)) { 1827 1828 } 1829 1830 /* Clear the entire screen. */ 1831 1832 scr->active = 1; 1833 mach64_restore_screen(scr, type, scr->chars); 1834 1835 sc->active = scr; 1836 1837 scr->ri.ri_ops.cursor(scr, scr->cursoron, scr->cursorrow, 1838 scr->cursorcol); 1839 1840 sc->wanted = 0; 1841 if (sc->switchcb) 1842 (*sc->switchcb)(sc->switchcbarg, 0, 0); 1843 } 1844 1845 void 1846 mach64_restore_screen(struct mach64screen *scr, 1847 const struct wsscreen_descr *type, u_int *mem) 1848 { 1849 int i, j, offset=0; 1850 /*struct rasops_info *ri=&scr->ri;*/ 1851 u_int *charptr=scr->chars; 1852 long *attrptr=scr->attrs; 1853 mach64_clearscreen(scr->sc); 1854 for (i = 0; i < scr->ri.ri_rows; i++) { 1855 for (j = 0; j < scr->ri.ri_cols; j++) { 1856 mach64_putchar(scr, i, j, charptr[offset], 1857 attrptr[offset]); 1858 offset++; 1859 } 1860 } 1861 scr->cursordrawn=0; 1862 } 1863 1864 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1865 void 1866 set_address(struct rasops_info *ri, bus_addr_t fb) 1867 { 1868 /*printf(" %d %d %d\n",ri->ri_xorigin,ri->ri_yorigin,ri->ri_stride);*/ 1869 ri->ri_bits = (void *)((u_long)fb + ri->ri_stride * ri->ri_yorigin + 1870 ri->ri_xorigin); 1871 } 1872 1873 int 1874 mach64_getwschar(void *cookie, struct wsdisplay_char *wsc) 1875 { 1876 struct mach64_softc *sc=cookie; 1877 struct mach64screen *scr=sc->active; 1878 int fg,bg,fl; 1879 if(scr){ 1880 if((wsc->col>=0) && (wsc->col<scr->ri.ri_cols) && 1881 (wsc->row>=0) && (wsc->row<scr->ri.ri_rows)) { 1882 int pos = scr->ri.ri_cols * wsc->row + wsc->col; 1883 wsc->letter=scr->chars[pos]; 1884 rasops_unpack_attr(scr->attrs[pos], &fg, &bg, &fl); 1885 wsc->foreground=fg; 1886 wsc->background=bg; 1887 wsc->flags=fl; 1888 return 0; 1889 } 1890 } 1891 return EINVAL; 1892 } 1893 1894 int 1895 mach64_putwschar(void *cookie, struct wsdisplay_char *wsc) 1896 { 1897 struct mach64_softc *sc=cookie; 1898 struct mach64screen *scr=sc->active; 1899 long attr; 1900 if(scr){ 1901 if((wsc->col>=0) && (wsc->col<scr->ri.ri_cols) && 1902 (wsc->row>=0) && (wsc->row<scr->ri.ri_rows)) { 1903 mach64_allocattr(&scr->ri,wsc->foreground, 1904 wsc->background, wsc->flags,&attr); 1905 mach64_putchar(&scr->ri,wsc->row, wsc->col, 1906 wsc->letter,attr); 1907 return 0; 1908 } 1909 } 1910 return EINVAL; 1911 } 1912 1913 #if 0 1914 int 1915 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1916 { 1917 1918 return 0; 1919 } 1920 #endif 1921 1922
Indexes created Thu Oct 02 14:10:14 GMT 2025