machfb.c revision 1.26
1 /* $NetBSD: machfb.c,v 1.26 2005/05/02 16:02:43 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, 36 "$NetBSD: machfb.c,v 1.26 2005/05/02 16:02:43 macallan Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/callout.h> 44 45 #ifdef __sparc__ 46 #include <machine/promlib.h> 47 #endif 48 49 #ifdef __powerpc__ 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_pci.h> 52 #endif 53 54 #include <dev/ic/videomode.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 #include <dev/pci/pciio.h> 60 #include <dev/pci/machfbreg.h> 61 62 #include <dev/wscons/wsdisplayvar.h> 63 #include <dev/wscons/wsconsio.h> 64 #include <dev/wsfont/wsfont.h> 65 #include <dev/rasops/rasops.h> 66 67 #define MACH64_REG_SIZE 1024 68 #define MACH64_REG_OFF 0x7ffc00 69 70 #define NBARS 3 /* number of Mach64 PCI BARs */ 71 72 struct vga_bar { 73 bus_addr_t vb_base; 74 pcireg_t vb_busaddr; 75 bus_size_t vb_size; 76 pcireg_t vb_type; 77 int vb_flags; 78 }; 79 80 struct mach64_softc { 81 struct device sc_dev; 82 pci_chipset_tag_t sc_pc; 83 pcitag_t sc_pcitag; 84 85 struct vga_bar sc_bars[NBARS]; 86 struct vga_bar sc_rom; 87 88 #define sc_aperbase sc_bars[0].vb_base 89 #define sc_apersize sc_bars[0].vb_size 90 #define sc_aperphys sc_bars[0].vb_busaddr 91 92 #define sc_iobase sc_bars[1].vb_base 93 #define sc_iosize sc_bars[1].vb_size 94 95 #define sc_regbase sc_bars[2].vb_base 96 #define sc_regsize sc_bars[2].vb_size 97 #define sc_regphys sc_bars[2].vb_busaddr 98 99 bus_space_tag_t sc_regt; 100 bus_space_tag_t sc_memt; 101 bus_space_handle_t sc_regh; 102 bus_space_handle_t sc_memh; 103 104 size_t memsize; 105 int memtype; 106 107 int sc_mode; 108 int sc_bg; 109 110 int has_dsp; 111 int bits_per_pixel; 112 int max_x; 113 int max_y; 114 int virt_x; 115 int virt_y; 116 int color_depth; 117 118 int mem_freq; 119 int ramdac_freq; 120 int ref_freq; 121 122 int ref_div; 123 int log2_vclk_post_div; 124 int vclk_post_div; 125 int vclk_fb_div; 126 int mclk_post_div; 127 int mclk_fb_div; 128 129 struct mach64screen *wanted; 130 struct mach64screen *active; 131 void (*switchcb)(void *, int, int); 132 void *switchcbarg; 133 struct callout switch_callout; 134 LIST_HEAD(, mach64screen) screens; 135 const struct wsscreen_descr *currenttype; 136 u_char sc_cmap_red[256]; 137 u_char sc_cmap_green[256]; 138 u_char sc_cmap_blue[256]; 139 int sc_dacw; 140 }; 141 142 struct mach64screen { 143 struct rasops_info ri; 144 LIST_ENTRY(mach64screen) next; 145 struct mach64_softc *sc; 146 const struct wsscreen_descr *type; 147 int active; 148 u_int *chars; 149 long *attrs; 150 int dispoffset; 151 int mindispoffset; 152 int maxdispoffset; 153 154 int cursoron; 155 int cursorcol; 156 int cursorrow; 157 int cursordrawn; 158 }; 159 160 struct mach64_crtcregs { 161 u_int32_t h_total_disp; 162 u_int32_t h_sync_strt_wid; 163 u_int32_t v_total_disp; 164 u_int32_t v_sync_strt_wid; 165 u_int32_t gen_cntl; 166 u_int32_t clock_cntl; 167 u_int32_t color_depth; 168 u_int32_t dot_clock; 169 }; 170 171 struct { 172 u_int16_t chip_id; 173 u_int32_t ramdac_freq; 174 } mach64_info[] = { 175 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 184 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 189 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 193 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 195 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 196 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 197 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 198 }; 199 200 static int mach64_chip_id, mach64_chip_rev; 201 static struct videomode default_mode; 202 static struct mach64screen mach64_console_screen; 203 204 static char *mach64_memtype_names[] = { 205 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 206 "(unknown type)" 207 }; 208 209 struct videomode mach64_modes[] = { 210 /* 640x400 @ 70 Hz, 31.5 kHz */ 211 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 212 /* 640x480 @ 72 Hz, 36.5 kHz */ 213 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 214 /* 800x600 @ 72 Hz, 48.0 kHz */ 215 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 216 VID_PHSYNC | VID_PVSYNC }, 217 /* 1024x768 @ 70 Hz, 56.5 kHz */ 218 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 219 VID_NHSYNC | VID_NVSYNC }, 220 /* 1152x864 @ 70 Hz, 62.4 kHz */ 221 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 222 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 223 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 224 VID_NHSYNC | VID_NVSYNC } 225 }; 226 227 extern const u_char rasops_cmap[768]; 228 229 int mach64_match(struct device *, struct cfdata *, void *); 230 void mach64_attach(struct device *, struct device *, void *); 231 232 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 233 NULL, NULL); 234 235 void mach64_init(struct mach64_softc *); 236 int mach64_get_memsize(struct mach64_softc *); 237 int mach64_get_max_ramdac(struct mach64_softc *); 238 void mach64_get_mode(struct mach64_softc *, struct videomode *); 239 int mach64_calc_crtcregs(struct mach64_softc *, struct mach64_crtcregs *, 240 struct videomode *); 241 void mach64_set_crtcregs(struct mach64_softc *, struct mach64_crtcregs *); 242 int mach64_modeswitch(struct mach64_softc *, struct videomode *); 243 void mach64_set_dsp(struct mach64_softc *); 244 void mach64_set_pll(struct mach64_softc *, int); 245 void mach64_reset_engine(struct mach64_softc *); 246 void mach64_init_engine(struct mach64_softc *); 247 void mach64_adjust_frame(struct mach64_softc *, int, int); 248 void mach64_init_lut(struct mach64_softc *); 249 void mach64_switch_screen(struct mach64_softc *); 250 void mach64_init_screen(struct mach64_softc *, struct mach64screen *, 251 const struct wsscreen_descr *, int, long *, int); 252 void mach64_restore_screen(struct mach64screen *, 253 const struct wsscreen_descr *, u_int *); 254 int mach64_set_screentype(struct mach64_softc *, 255 const struct wsscreen_descr *); 256 int mach64_is_console(struct pci_attach_args *); 257 258 void mach64_cursor(void *, int, int, int); 259 int mach64_mapchar(void *, int, u_int *); 260 void mach64_putchar(void *, int, int, u_int, long); 261 void mach64_copycols(void *, int, int, int, int); 262 void mach64_erasecols(void *, int, int, int, long); 263 void mach64_copyrows(void *, int, int, int); 264 void mach64_eraserows(void *, int, int, long); 265 int mach64_allocattr(void *, int, int, int, long *); 266 void mach64_clearscreen(struct mach64_softc *); 267 268 void mach64_scroll(void *, void *, int); 269 270 int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 271 int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 272 int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, uint8_t, 273 uint8_t); 274 void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, int, int, 275 int) ; 276 void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 277 void mach64_setup_mono(struct mach64_softc *, int, int, int, int, uint32_t, 278 uint32_t); 279 void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 280 void mach64_showpal(struct mach64_softc *); 281 int mach64_getwschar(void *, struct wsdisplay_char *); 282 int mach64_putwschar(void *, struct wsdisplay_char *); 283 284 void set_address(struct rasops_info *, bus_addr_t); 285 286 #if 0 287 const struct wsdisplay_emulops mach64_emulops = { 288 mach64_cursor, 289 mach64_mapchar, 290 mach64_putchar, 291 mach64_copycols, 292 mach64_erasecols, 293 mach64_copyrows, 294 mach64_eraserows, 295 mach64_allocattr, 296 }; 297 #endif 298 299 struct wsscreen_descr mach64_defaultscreen = { 300 "default", 301 0, 0, 302 &mach64_console_screen.ri.ri_ops, 303 8, 16, 304 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 305 &default_mode 306 }, mach64_80x25_screen = { 307 "80x25", 80, 25, 308 &mach64_console_screen.ri.ri_ops, 309 8, 16, 310 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 311 &mach64_modes[0] 312 }, mach64_80x30_screen = { 313 "80x30", 80, 30, 314 &mach64_console_screen.ri.ri_ops, 315 8, 16, 316 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 317 &mach64_modes[1] 318 }, mach64_80x40_screen = { 319 "80x40", 80, 40, 320 &mach64_console_screen.ri.ri_ops, 321 8, 10, 322 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 323 &mach64_modes[0] 324 }, mach64_80x50_screen = { 325 "80x50", 80, 50, 326 &mach64_console_screen.ri.ri_ops, 327 8, 8, 328 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 329 &mach64_modes[0] 330 }, mach64_100x37_screen = { 331 "100x37", 100, 37, 332 &mach64_console_screen.ri.ri_ops, 333 8, 16, 334 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 335 &mach64_modes[2] 336 }, mach64_128x48_screen = { 337 "128x48", 128, 48, 338 &mach64_console_screen.ri.ri_ops, 339 8, 16, 340 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 341 &mach64_modes[3] 342 }, mach64_144x54_screen = { 343 "144x54", 144, 54, 344 &mach64_console_screen.ri.ri_ops, 345 8, 16, 346 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 347 &mach64_modes[4] 348 }, mach64_160x64_screen = { 349 "160x54", 160, 64, 350 &mach64_console_screen.ri.ri_ops, 351 8, 16, 352 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 353 &mach64_modes[5] 354 }; 355 356 const struct wsscreen_descr *_mach64_scrlist[] = { 357 &mach64_defaultscreen, 358 &mach64_80x25_screen, 359 &mach64_80x30_screen, 360 &mach64_80x40_screen, 361 &mach64_80x50_screen, 362 &mach64_100x37_screen, 363 &mach64_128x48_screen, 364 &mach64_144x54_screen, 365 &mach64_160x64_screen 366 }; 367 368 struct wsscreen_list mach64_screenlist = { 369 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 370 _mach64_scrlist 371 }; 372 373 int mach64_ioctl(void *, u_long, caddr_t, int, struct proc *); 374 paddr_t mach64_mmap(void *, off_t, int); 375 int mach64_alloc_screen(void *, const struct wsscreen_descr *, void **, 376 int *, int *, long *); 377 void mach64_free_screen(void *, void *); 378 int mach64_show_screen(void *, void *, int, void (*)(void *, int, int), 379 void *); 380 int mach64_load_font(void *, void *, struct wsdisplay_font *); 381 382 struct wsdisplay_accessops mach64_accessops = { 383 mach64_ioctl, 384 mach64_mmap, 385 mach64_alloc_screen, 386 mach64_free_screen, 387 mach64_show_screen, 388 NULL, /* load_font */ 389 NULL, /* polls */ 390 mach64_getwschar, /* getwschar */ 391 mach64_putwschar, /* putwschar */ 392 NULL, /* scroll */ 393 NULL, /* getborder */ 394 NULL /* setborder */ 395 }; 396 397 /* 398 * Inline functions for getting access to register aperture. 399 */ 400 static inline u_int32_t regr(struct mach64_softc *, u_int32_t); 401 static inline u_int8_t regrb(struct mach64_softc *, u_int32_t); 402 static inline void regw(struct mach64_softc *, u_int32_t, u_int32_t); 403 static inline void regwb(struct mach64_softc *, u_int32_t, u_int8_t); 404 static inline void regwb_pll(struct mach64_softc *, u_int32_t, u_int8_t); 405 406 static inline u_int32_t 407 regr(struct mach64_softc *sc, u_int32_t index) 408 { 409 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 410 } 411 412 static inline u_int8_t 413 regrb(struct mach64_softc *sc, u_int32_t index) 414 { 415 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 416 } 417 418 static inline void 419 regw(struct mach64_softc *sc, u_int32_t index, u_int32_t data) 420 { 421 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 422 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 423 BUS_SPACE_BARRIER_WRITE); 424 } 425 426 static inline void 427 regwb(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 428 { 429 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 430 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 431 BUS_SPACE_BARRIER_WRITE); 432 } 433 434 static inline void 435 regwb_pll(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 436 { 437 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 438 regwb(sc, CLOCK_CNTL + 2, data); 439 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 440 } 441 442 static inline void 443 wait_for_fifo(struct mach64_softc *sc, u_int8_t v) 444 { 445 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 446 ; 447 } 448 449 static inline void 450 wait_for_idle(struct mach64_softc *sc) 451 { 452 wait_for_fifo(sc, 16); 453 while ((regr(sc, GUI_STAT) & 1) != 0) 454 ; 455 } 456 457 int 458 mach64_match(struct device *parent, struct cfdata *match, void *aux) 459 { 460 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 461 int i; 462 463 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 464 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 465 return 0; 466 467 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 468 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 469 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 470 mach64_chip_rev = PCI_REVISION(pa->pa_class); 471 return 100; 472 } 473 474 return 0; 475 } 476 477 void 478 mach64_attach(struct device *parent, struct device *self, void *aux) 479 { 480 struct mach64_softc *sc = (void *)self; 481 struct pci_attach_args *pa = aux; 482 char devinfo[256]; 483 int bar, reg, id; 484 struct wsemuldisplaydev_attach_args aa; 485 long defattr; 486 int setmode, console; 487 pcireg_t screg; 488 489 sc->sc_pc = pa->pa_pc; 490 sc->sc_pcitag = pa->pa_tag; 491 sc->sc_dacw = -1; 492 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 493 494 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 495 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 496 497 /* enable memory and IO access */ 498 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 499 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 500 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 501 502 for (bar = 0; bar < NBARS; bar++) { 503 reg = PCI_MAPREG_START + (bar * 4); 504 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 505 sc->sc_pcitag, reg); 506 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 507 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 508 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 509 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 510 sc->sc_pcitag, reg)&0xfffffff0; 511 } 512 sc->sc_memt = pa->pa_memt; 513 514 mach64_init(sc); 515 516 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 517 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 518 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 519 (u_int)sc->sc_regphys); 520 521 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 522 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 523 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 524 (mach64_chip_rev & 0x07) == 0)) 525 sc->has_dsp = 0; 526 else 527 sc->has_dsp = 1; 528 529 sc->memsize = mach64_get_memsize(sc); 530 if (sc->memsize == 8192) 531 /* The last page is used as register aperture. */ 532 sc->memsize -= 4; 533 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 534 535 /* XXX is there any way to calculate reference frequency from 536 known values? */ 537 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 538 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 539 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 540 printf("ref_freq=29.498MHz\n"); 541 sc->ref_freq = 29498; 542 } else 543 sc->ref_freq = 14318; 544 545 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 546 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 547 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 548 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 549 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 550 (sc->ref_div * 2); 551 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 552 (sc->mem_freq * sc->ref_div); 553 sc->ramdac_freq = mach64_get_max_ramdac(sc); 554 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 555 sc->sc_dev.dv_xname, (u_long)sc->memsize, 556 mach64_memtype_names[sc->memtype], 557 sc->mem_freq / 1000, sc->mem_freq % 1000, 558 sc->ramdac_freq / 1000); 559 560 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 561 if (id != mach64_chip_id) { 562 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 563 sc->sc_dev.dv_xname, id, mach64_chip_id); 564 return; 565 } 566 567 console = mach64_is_console(pa); 568 569 #if defined(__sparc__) || defined(__powerpc__) 570 if (console) { 571 mach64_get_mode(sc, &default_mode); 572 setmode = 0; 573 } else { 574 memcpy(&default_mode, &mach64_modes[4], sizeof(struct 575 videomode)); 576 setmode = 1; 577 } 578 #else 579 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)); 580 setmode = 1; 581 #endif 582 583 sc->bits_per_pixel = 8; 584 sc->virt_x = default_mode.hdisplay; 585 sc->virt_y = default_mode.vdisplay; 586 sc->max_x = sc->virt_x - 1; 587 sc->max_y = (sc->memsize * 1024) / 588 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 589 590 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 591 592 mach64_init_engine(sc); 593 #if 0 594 mach64_adjust_frame(0, 0); 595 if (sc->bits_per_pixel == 8) 596 mach64_init_lut(sc); 597 #endif 598 599 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 600 default_mode.hdisplay, default_mode.vdisplay, 601 sc->bits_per_pixel); 602 603 mach64_console_screen.ri.ri_hw = &mach64_console_screen; 604 mach64_console_screen.ri.ri_depth = sc->bits_per_pixel; 605 mach64_console_screen.ri.ri_width = default_mode.hdisplay; 606 mach64_console_screen.ri.ri_height = default_mode.vdisplay; 607 mach64_console_screen.ri.ri_stride = mach64_console_screen.ri.ri_width; 608 609 mach64_console_screen.ri.ri_bits=(void *)(uintptr_t)sc->sc_aperbase; 610 611 mach64_console_screen.ri.ri_flg = RI_CENTER; 612 mach64_console_screen.active = 1; 613 sc->active = &mach64_console_screen; 614 615 /* XXX width/height are nonsense, we only want to pick a font */ 616 rasops_init(&mach64_console_screen.ri, 617 mach64_console_screen.ri.ri_height / 16, 618 mach64_console_screen.ri.ri_width / 8); 619 620 /* now get the real values */ 621 rasops_reconfig(&mach64_console_screen.ri, 622 mach64_console_screen.ri.ri_height / 623 mach64_console_screen.ri.ri_font->fontheight, 624 mach64_console_screen.ri.ri_width / 625 mach64_console_screen.ri.ri_font->fontwidth); 626 627 set_address(&mach64_console_screen.ri, sc->sc_aperbase); 628 629 /* enable acceleration */ 630 mach64_console_screen.ri.ri_ops.copyrows = mach64_copyrows; 631 mach64_console_screen.ri.ri_ops.eraserows = mach64_eraserows; 632 mach64_console_screen.ri.ri_ops.copycols = mach64_copycols; 633 mach64_console_screen.ri.ri_ops.erasecols = mach64_erasecols; 634 mach64_console_screen.ri.ri_ops.putchar = mach64_putchar; 635 mach64_console_screen.ri.ri_ops.cursor = mach64_cursor; 636 637 mach64_defaultscreen.nrows = mach64_console_screen.ri.ri_rows; 638 mach64_defaultscreen.ncols = mach64_console_screen.ri.ri_cols; 639 640 mach64_allocattr(&mach64_console_screen.ri, WS_DEFAULT_FG, 641 WS_DEFAULT_BG, 0, &defattr); 642 643 sc->sc_bg=WS_DEFAULT_BG; 644 645 /* really necessary? */ 646 mach64_defaultscreen.capabilities = mach64_console_screen.ri.ri_caps; 647 mach64_defaultscreen.textops = &mach64_console_screen.ri.ri_ops; 648 649 /* Initialize fonts */ 650 /* XXX shouldn't that happen /before/ we call rasops_init()? */ 651 wsfont_init(); 652 653 if (console) { 654 mach64_init_screen(sc, &mach64_console_screen, 655 &mach64_defaultscreen, 1, &defattr, setmode); 656 wsdisplay_cnattach(&mach64_defaultscreen, 657 &mach64_console_screen.ri, 0, 0, defattr); 658 } 659 660 mach64_init_lut(sc); 661 mach64_clearscreen(sc); 662 663 aa.console = console; 664 aa.scrdata = &mach64_screenlist; 665 aa.accessops = &mach64_accessops; 666 aa.accesscookie = sc; 667 668 config_found(self, &aa, wsemuldisplaydevprint); 669 } 670 671 void 672 mach64_init_screen(struct mach64_softc *sc, struct mach64screen *scr, 673 const struct wsscreen_descr *type, int existing, long *attrp, int setmode) 674 { 675 struct rasops_info *ri=&scr->ri; 676 int cnt; 677 678 scr->sc = sc; 679 scr->type = type; 680 scr->mindispoffset = 0; 681 scr->maxdispoffset = sc->memsize * 1024; 682 scr->dispoffset = 0; 683 scr->cursorcol = 0; 684 scr->cursorrow = 0; 685 686 cnt=type->nrows * type->ncols; 687 scr->attrs = (long *)malloc(cnt * (sizeof(long) + sizeof(u_int)), 688 M_DEVBUF, M_WAITOK); 689 scr->chars = (u_int *)&scr->attrs[cnt]; 690 691 /* 692 * we allocate both chars and attributes in one chunk, attributes first 693 * because they have the (potentially) bigger alignment 694 */ 695 ri->ri_depth = sc->bits_per_pixel; 696 ri->ri_width = default_mode.hdisplay; 697 ri->ri_height = default_mode.vdisplay; 698 ri->ri_stride = ri->ri_width; 699 ri->ri_flg = RI_CENTER; 700 701 if (existing) { 702 scr->active = 1; 703 ri->ri_flg |= RI_CLEAR; 704 if (setmode && mach64_set_screentype(sc, type)) { 705 panic("%s: failed to switch video mode", 706 sc->sc_dev.dv_xname); 707 } 708 } else { 709 scr->active = 0; 710 } 711 712 LIST_INSERT_HEAD(&sc->screens, scr, next); 713 } 714 715 void 716 mach64_init(struct mach64_softc *sc) 717 { 718 u_int32_t *p32, saved_value; 719 u_int8_t *p; 720 int need_swap; 721 722 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 723 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 724 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 725 } 726 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 727 728 sc->sc_regt = sc->sc_memt; 729 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 730 sc->sc_regsize, &sc->sc_regh); 731 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 732 733 /* 734 * Test wether the aperture is byte swapped or not 735 */ 736 p32 = (u_int32_t*)(u_long)sc->sc_aperbase; 737 saved_value = *p32; 738 p = (u_int8_t*)(u_long)sc->sc_aperbase; 739 *p32 = 0x12345678; 740 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 741 need_swap = 0; 742 else 743 need_swap = 1; 744 if (need_swap) { 745 sc->sc_aperbase += 0x800000; 746 sc->sc_apersize -= 0x800000; 747 } 748 *p32 = saved_value; 749 750 LIST_INIT(&sc->screens); 751 sc->active = NULL; 752 sc->currenttype = &mach64_defaultscreen; 753 callout_init(&sc->switch_callout); 754 } 755 756 int 757 mach64_get_memsize(struct mach64_softc *sc) 758 { 759 int tmp, memsize; 760 int mem_tab[] = { 761 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 762 }; 763 764 tmp = regr(sc, MEM_CNTL); 765 printf("memctl: %08x\n",tmp); 766 if (sc->has_dsp) { 767 tmp &= 0x0000000f; 768 if (tmp < 8) 769 memsize = (tmp + 1) * 512; 770 else if (tmp < 12) 771 memsize = (tmp - 3) * 1024; 772 else 773 memsize = (tmp - 7) * 2048; 774 } else { 775 memsize = mem_tab[tmp & 0x07]; 776 } 777 778 return memsize; 779 } 780 781 int 782 mach64_get_max_ramdac(struct mach64_softc *sc) 783 { 784 int i; 785 786 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 787 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 788 (mach64_chip_rev & 0x07)) 789 return 170000; 790 791 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 792 if (mach64_chip_id == mach64_info[i].chip_id) 793 return mach64_info[i].ramdac_freq; 794 795 if (sc->bits_per_pixel == 8) 796 return 135000; 797 else 798 return 80000; 799 } 800 801 void 802 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 803 { 804 struct mach64_crtcregs crtc; 805 806 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 807 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 808 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 809 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 810 811 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 812 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 813 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 814 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 815 mode->hsync_start; 816 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 817 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 818 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 819 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 820 821 #ifdef DEBUG_MACHFB 822 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 823 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 824 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 825 #endif 826 } 827 828 int 829 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 830 struct videomode *mode) 831 { 832 833 if (mode->dot_clock > sc->ramdac_freq) 834 /* Clock too high. */ 835 return 1; 836 837 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 838 ((mode->htotal >> 3) - 1); 839 crtc->h_sync_strt_wid = 840 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 841 ((mode->hsync_start >> 3) - 1); 842 843 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 844 (mode->vtotal - 1); 845 crtc->v_sync_strt_wid = 846 ((mode->vsync_end - mode->vsync_start) << 16) | 847 (mode->vsync_start - 1); 848 849 if (mode->flags & VID_NVSYNC) 850 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 851 852 switch (sc->bits_per_pixel) { 853 case 8: 854 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 855 break; 856 case 16: 857 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 858 break; 859 case 32: 860 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 861 break; 862 } 863 864 crtc->gen_cntl = 0; 865 if (mode->flags & VID_INTERLACE) 866 crtc->gen_cntl |= CRTC_INTERLACE_EN; 867 if (mode->flags & VID_CSYNC) 868 crtc->gen_cntl |= CRTC_CSYNC_EN; 869 870 crtc->dot_clock = mode->dot_clock; 871 872 return 0; 873 } 874 875 void 876 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 877 { 878 879 mach64_set_pll(sc, crtc->dot_clock); 880 881 if (sc->has_dsp) 882 mach64_set_dsp(sc); 883 884 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 885 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 886 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 887 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 888 889 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 890 891 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 892 893 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 894 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 895 } 896 897 int 898 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 899 { 900 struct mach64_crtcregs crtc; 901 902 if (mach64_calc_crtcregs(sc, &crtc, mode)) 903 return 1; 904 905 mach64_set_crtcregs(sc, &crtc); 906 return 0; 907 } 908 909 void 910 mach64_reset_engine(struct mach64_softc *sc) 911 { 912 913 /* Reset engine.*/ 914 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 915 916 /* Enable engine. */ 917 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 918 919 /* Ensure engine is not locked up by clearing any FIFO or 920 host errors. */ 921 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 922 BUS_FIFO_ERR_ACK); 923 } 924 925 void 926 mach64_init_engine(struct mach64_softc *sc) 927 { 928 u_int32_t pitch_value; 929 930 pitch_value = sc->virt_x; 931 932 if (sc->bits_per_pixel == 24) 933 pitch_value *= 3; 934 935 mach64_reset_engine(sc); 936 937 wait_for_fifo(sc, 14); 938 939 regw(sc, CONTEXT_MASK, 0xffffffff); 940 941 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 942 943 regw(sc, DST_Y_X, 0); 944 regw(sc, DST_HEIGHT, 0); 945 regw(sc, DST_BRES_ERR, 0); 946 regw(sc, DST_BRES_INC, 0); 947 regw(sc, DST_BRES_DEC, 0); 948 949 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 950 DST_Y_TOP_TO_BOTTOM); 951 952 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 953 954 regw(sc, SRC_Y_X, 0); 955 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 956 regw(sc, SRC_Y_X_START, 0); 957 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 958 959 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 960 961 wait_for_fifo(sc, 13); 962 regw(sc, HOST_CNTL, 0); 963 964 regw(sc, PAT_REG0, 0); 965 regw(sc, PAT_REG1, 0); 966 regw(sc, PAT_CNTL, 0); 967 968 regw(sc, SC_LEFT, 0); 969 regw(sc, SC_TOP, 0); 970 regw(sc, SC_BOTTOM, default_mode.vdisplay - 1); 971 regw(sc, SC_RIGHT, pitch_value - 1); 972 973 regw(sc, DP_BKGD_CLR, 0); 974 regw(sc, DP_FRGD_CLR, 0xffffffff); 975 regw(sc, DP_WRITE_MASK, 0xffffffff); 976 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 977 978 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 979 980 wait_for_fifo(sc, 3); 981 regw(sc, CLR_CMP_CLR, 0); 982 regw(sc, CLR_CMP_MASK, 0xffffffff); 983 regw(sc, CLR_CMP_CNTL, 0); 984 985 wait_for_fifo(sc, 2); 986 switch (sc->bits_per_pixel) { 987 case 8: 988 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 989 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 990 /* We want 8 bit per channel */ 991 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 992 break; 993 #if 0 994 case 32: 995 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 996 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 997 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 998 break; 999 #endif 1000 } 1001 1002 wait_for_fifo(sc, 5); 1003 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1004 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1005 1006 wait_for_idle(sc); 1007 } 1008 1009 void 1010 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1011 { 1012 int offset; 1013 1014 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1015 1016 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1017 offset); 1018 } 1019 1020 void 1021 mach64_set_dsp(struct mach64_softc *sc) 1022 { 1023 u_int32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1024 u_int32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1025 u_int32_t xclks_per_qw, y; 1026 u_int32_t fifo_off, fifo_on; 1027 1028 printf("initializing the DSP\n"); 1029 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1030 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1031 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1032 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1033 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1034 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1035 dsp_loop_latency = 0; 1036 fifo_depth = 24; 1037 } else { 1038 dsp_loop_latency = 2; 1039 fifo_depth = 32; 1040 } 1041 1042 dsp_precision = 0; 1043 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1044 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1045 y = (xclks_per_qw * fifo_depth) >> 11; 1046 while (y) { 1047 y >>= 1; 1048 dsp_precision++; 1049 } 1050 dsp_precision -= 5; 1051 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1052 1053 switch (sc->memtype) { 1054 case DRAM: 1055 case EDO_DRAM: 1056 case PSEUDO_EDO: 1057 if (sc->memsize > 1024) { 1058 page_size = 9; 1059 dsp_loop_latency += 6; 1060 } else { 1061 page_size = 10; 1062 if (sc->memtype == DRAM) 1063 dsp_loop_latency += 8; 1064 else 1065 dsp_loop_latency += 7; 1066 } 1067 break; 1068 case SDRAM: 1069 case SGRAM: 1070 if (sc->memsize > 1024) { 1071 page_size = 8; 1072 dsp_loop_latency += 8; 1073 } else { 1074 page_size = 10; 1075 dsp_loop_latency += 9; 1076 } 1077 break; 1078 default: 1079 page_size = 10; 1080 dsp_loop_latency += 9; 1081 break; 1082 } 1083 1084 if (xclks_per_qw >= (page_size << 11)) 1085 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1086 else 1087 fifo_on = (3 * page_size + 2) << 6; 1088 1089 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1090 dsp_on = fifo_on >> dsp_precision; 1091 dsp_off = fifo_off >> dsp_precision; 1092 1093 #ifdef DEBUG_MACHFB 1094 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1095 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1096 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1097 "mclk_post_div = %d, vclk_post_div = %d\n", 1098 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1099 sc->mclk_fb_div, sc->vclk_fb_div, 1100 sc->mclk_post_div, sc->vclk_post_div); 1101 #endif 1102 1103 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1104 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1105 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1106 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1107 } 1108 1109 void 1110 mach64_set_pll(struct mach64_softc *sc, int clock) 1111 { 1112 int q; 1113 1114 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1115 #ifdef DEBUG_MACHFB 1116 printf("q = %d\n", q); 1117 #endif 1118 if (q > 25500) { 1119 printf("Warning: q > 25500\n"); 1120 q = 25500; 1121 sc->vclk_post_div = 1; 1122 sc->log2_vclk_post_div = 0; 1123 } else if (q > 12750) { 1124 sc->vclk_post_div = 1; 1125 sc->log2_vclk_post_div = 0; 1126 } else if (q > 6350) { 1127 sc->vclk_post_div = 2; 1128 sc->log2_vclk_post_div = 1; 1129 } else if (q > 3150) { 1130 sc->vclk_post_div = 4; 1131 sc->log2_vclk_post_div = 2; 1132 } else if (q >= 1600) { 1133 sc->vclk_post_div = 8; 1134 sc->log2_vclk_post_div = 3; 1135 } else { 1136 printf("Warning: q < 1600\n"); 1137 sc->vclk_post_div = 8; 1138 sc->log2_vclk_post_div = 3; 1139 } 1140 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1141 1142 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1143 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1144 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1145 } 1146 1147 void 1148 mach64_init_lut(struct mach64_softc *sc) 1149 { 1150 int i,idx; 1151 1152 idx = 0; 1153 for (i = 0; i < 256; i++) { 1154 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1155 rasops_cmap[idx + 2]); 1156 idx += 3; 1157 } 1158 } 1159 1160 int 1161 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1162 uint8_t b) 1163 { 1164 sc->sc_cmap_red[index] = r; 1165 sc->sc_cmap_green[index] = g; 1166 sc->sc_cmap_blue[index] = b; 1167 /* 1168 * writing the dac index takes a while, in theory we can poll some 1169 * register to see when it's ready - but we better avoid writing it 1170 * unnecessarily 1171 */ 1172 if (index != sc->sc_dacw) 1173 { 1174 regwb(sc, DAC_MASK, 0xff); 1175 regwb(sc, DAC_WINDEX, index); 1176 } 1177 sc->sc_dacw = index + 1; 1178 regwb(sc, DAC_DATA, r); 1179 regwb(sc, DAC_DATA, g); 1180 regwb(sc, DAC_DATA, b); 1181 return 0; 1182 } 1183 1184 int 1185 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1186 { 1187 u_int index = cm->index; 1188 u_int count = cm->count; 1189 int i, error; 1190 u_char rbuf[256], gbuf[256], bbuf[256]; 1191 u_char *r, *g, *b; 1192 1193 printf("putcmap: %d %d\n",index, count); 1194 if (cm->index >= 256 || cm->count > 256 || 1195 (cm->index + cm->count) > 256) 1196 return EINVAL; 1197 error = copyin(cm->red, &rbuf[index], count); 1198 if (error) 1199 return error; 1200 error = copyin(cm->green, &gbuf[index], count); 1201 if (error) 1202 return error; 1203 error = copyin(cm->blue, &bbuf[index], count); 1204 if (error) 1205 return error; 1206 1207 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1208 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1209 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1210 1211 r = &sc->sc_cmap_red[index]; 1212 g = &sc->sc_cmap_green[index]; 1213 b = &sc->sc_cmap_blue[index]; 1214 1215 for (i = 0; i < count; i++) { 1216 mach64_putpalreg(sc, index, *r, *g, *b); 1217 index++; 1218 r++, g++, b++; 1219 } 1220 return 0; 1221 } 1222 1223 int 1224 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1225 { 1226 u_int index = cm->index; 1227 u_int count = cm->count; 1228 int error; 1229 1230 if (index >= 255 || count > 256 || index + count > 256) 1231 return EINVAL; 1232 1233 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1234 if (error) 1235 return error; 1236 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1237 if (error) 1238 return error; 1239 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1240 if (error) 1241 return error; 1242 1243 return 0; 1244 } 1245 1246 int 1247 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1248 { 1249 struct mach64_crtcregs regs; 1250 1251 if (mach64_calc_crtcregs(sc, ®s, 1252 (struct videomode *)des->modecookie)) 1253 return 1; 1254 1255 mach64_set_crtcregs(sc, ®s); 1256 return 0; 1257 } 1258 1259 int 1260 mach64_is_console(struct pci_attach_args *pa) 1261 { 1262 #ifdef __sparc__ 1263 int node; 1264 1265 node = PCITAG_NODE(pa->pa_tag); 1266 if (node == -1) 1267 return 0; 1268 1269 return (node == prom_instance_to_package(prom_stdout())); 1270 #elif defined(__powerpc__) 1271 /* check if we're the /chosen console device */ 1272 int chosen, stdout, node, us; 1273 1274 us = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1275 chosen = OF_finddevice("/chosen"); 1276 OF_getprop(chosen, "stdout", &stdout, 4); 1277 node = OF_instance_to_package(stdout); 1278 return (us == node); 1279 #else 1280 return 1; 1281 #endif 1282 } 1283 1284 /* 1285 * wsdisplay_emulops 1286 */ 1287 1288 void 1289 mach64_cursor(void *cookie, int on, int row, int col) 1290 { 1291 struct rasops_info *ri=cookie; 1292 struct mach64screen *scr=ri->ri_hw; 1293 struct mach64_softc *sc=scr->sc; 1294 int x, y, wi,he; 1295 1296 wi = ri->ri_font->fontwidth; 1297 he = ri->ri_font->fontheight; 1298 1299 if (scr->active) { 1300 x = scr->cursorcol * wi + ri->ri_xorigin; 1301 y = scr->cursorrow * he + ri->ri_yorigin; 1302 if (scr->cursordrawn) { 1303 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1304 0xff); 1305 scr->cursordrawn=0; 1306 } 1307 scr->cursorrow = row; 1308 scr->cursorcol = col; 1309 if ((scr->cursoron = on) != 0) 1310 { 1311 x = scr->cursorcol * wi + ri->ri_xorigin; 1312 y = scr->cursorrow * he + ri->ri_yorigin; 1313 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1314 0xff); 1315 scr->cursordrawn = 1; 1316 } 1317 } else { 1318 scr->cursoron = on; 1319 scr->cursorrow = row; 1320 scr->cursorcol = col; 1321 scr->cursordrawn = 0; 1322 } 1323 } 1324 1325 #if 0 1326 int 1327 mach64_mapchar(void *cookie, int uni, u_int *index) 1328 { 1329 return 0; 1330 } 1331 #endif 1332 1333 void 1334 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1335 { 1336 struct rasops_info *ri=cookie; 1337 struct mach64screen *scr=ri->ri_hw; 1338 struct mach64_softc *sc=scr->sc; 1339 int offset=ri->ri_cols*row+col; 1340 1341 scr->attrs[offset] = attr; 1342 scr->chars[offset] = c; 1343 if ((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1344 int fg, bg, uc; 1345 uint8_t *data; 1346 int x, y, wi, he; 1347 wi = ri->ri_font->fontwidth; 1348 he = ri->ri_font->fontheight; 1349 1350 /*scr->putchar(cookie,row,col,c,attr);*/ 1351 if (!CHAR_IN_FONT(c, ri->ri_font)) 1352 return; 1353 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1354 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1355 x = ri->ri_xorigin + col * wi; 1356 y = ri->ri_yorigin + row * he; 1357 if (c == 0x20) { 1358 mach64_rectfill(sc, x, y, wi, he, bg); 1359 } else { 1360 uc = c-ri->ri_font->firstchar; 1361 data = (uint8_t *)ri->ri_font->data + uc * 1362 ri->ri_fontscale; 1363 1364 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1365 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1366 } 1367 } 1368 } 1369 1370 1371 void 1372 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1373 { 1374 struct rasops_info *ri=cookie; 1375 struct mach64screen *scr=ri->ri_hw; 1376 struct mach64_softc *sc=scr->sc; 1377 int32_t xs,xd,y,width,height; 1378 int from, to; 1379 1380 from = srccol + row * ri->ri_cols; 1381 to = dstcol + row * ri->ri_cols; 1382 1383 memmove(&scr->attrs[to], &scr->attrs[from], ncols * sizeof(long)); 1384 memmove(&scr->chars[to], &scr->chars[from], ncols * sizeof(u_int)); 1385 1386 if ((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1387 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1388 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1389 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1390 width = ri->ri_font->fontwidth * ncols; 1391 height = ri->ri_font->fontheight; 1392 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1393 } 1394 } 1395 1396 void 1397 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1398 { 1399 struct rasops_info *ri=cookie; 1400 struct mach64screen *scr=ri->ri_hw; 1401 struct mach64_softc *sc=scr->sc; 1402 int32_t x, y, width, height, fg, bg, ul; 1403 int start, end, i; 1404 1405 start = startcol + row * ri->ri_cols; 1406 end = start + ncols; 1407 1408 for (i = start; i < end; i++) { 1409 scr->attrs[i] = fillattr; 1410 scr->chars[i] = 0x20; 1411 } 1412 if ((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1413 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1414 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1415 width = ri->ri_font->fontwidth * ncols; 1416 height = ri->ri_font->fontheight; 1417 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1418 1419 mach64_rectfill(sc, x, y, width, height, bg); 1420 } 1421 } 1422 1423 void 1424 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1425 { 1426 struct rasops_info *ri=cookie; 1427 struct mach64screen *scr=ri->ri_hw; 1428 struct mach64_softc *sc=scr->sc; 1429 int32_t x, ys, yd, width, height; 1430 int from, to, len; 1431 1432 from = ri->ri_cols * srcrow; 1433 to = ri->ri_cols * dstrow; 1434 len = ri->ri_cols * nrows; 1435 1436 memmove(&scr->attrs[to], &scr->attrs[from], len*sizeof(long)); 1437 memmove(&scr->chars[to], &scr->chars[from], len*sizeof(u_int)); 1438 1439 if ((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1440 x = ri->ri_xorigin; 1441 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1442 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1443 width = ri->ri_emuwidth; 1444 height = ri->ri_font->fontheight*nrows; 1445 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1446 } 1447 } 1448 1449 void 1450 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1451 { 1452 struct rasops_info *ri=cookie; 1453 struct mach64screen *scr=ri->ri_hw; 1454 struct mach64_softc *sc=scr->sc; 1455 int32_t x,y,width,height,fg,bg,ul; 1456 int start, end, i; 1457 1458 start = ri->ri_cols * row; 1459 end = ri->ri_cols * (row + nrows); 1460 1461 for (i=start;i<end;i++) { 1462 scr->attrs[i] = fillattr; 1463 scr->chars[i] = 0x20; 1464 } 1465 1466 if ((scr->active) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1467 x = ri->ri_xorigin; 1468 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1469 width = ri->ri_emuwidth; 1470 height = ri->ri_font->fontheight * nrows; 1471 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1472 1473 mach64_rectfill(sc, x, y, width, height, bg); 1474 } 1475 } 1476 1477 void 1478 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1479 { 1480 uint32_t dest_ctl = 0; 1481 1482 wait_for_idle(sc); 1483 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1484 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1485 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1486 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1487 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1488 if (yd < ys) { 1489 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1490 } else { 1491 ys += height - 1; 1492 yd += height - 1; 1493 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1494 } 1495 if (xd < xs) { 1496 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1497 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1498 } else { 1499 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1500 xs += width - 1; 1501 xd += width - 1; 1502 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1503 } 1504 regw(sc, DST_CNTL, dest_ctl); 1505 1506 regw(sc, SRC_Y_X, (xs << 16) | ys); 1507 regw(sc, SRC_WIDTH1, width); 1508 regw(sc, DST_Y_X, (xd << 16) | yd); 1509 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1510 } 1511 1512 void 1513 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1514 int height, uint32_t fg, uint32_t bg) 1515 { 1516 wait_for_idle(sc); 1517 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1518 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1519 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1520 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1521 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1522 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1523 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1524 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1525 regw(sc, DP_BKGD_CLR, bg); 1526 regw(sc, DP_FRGD_CLR, fg); 1527 regw(sc, SRC_Y_X, 0); 1528 regw(sc, SRC_WIDTH1, width); 1529 regw(sc, DST_Y_X, (xd << 16) | yd); 1530 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1531 /* now feed the data into the chip */ 1532 } 1533 1534 void 1535 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1536 { 1537 int i; 1538 uint32_t latch = 0, bork; 1539 int shift = 0; 1540 int reg = 0; 1541 1542 for (i=0;i<count;i++) { 1543 bork = data[i]; 1544 latch |= (bork << shift); 1545 if (shift == 24) { 1546 regw(sc, HOST_DATA0 + reg, latch); 1547 latch = 0; 1548 shift = 0; 1549 reg = (reg + 4) & 0x3c; 1550 } else 1551 shift += 8; 1552 } 1553 if (shift != 0) /* 24 */ 1554 regw(sc, HOST_DATA0 + reg, latch); 1555 } 1556 1557 1558 void 1559 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1560 int colour) 1561 { 1562 wait_for_idle(sc); 1563 regw(sc, DP_WRITE_MASK, 0xff); 1564 regw(sc, DP_FRGD_CLR, colour); 1565 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1566 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1567 regw(sc, DP_MIX, MIX_SRC << 16); 1568 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1569 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1570 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1571 1572 regw(sc, SRC_Y_X, (x << 16) | y); 1573 regw(sc, SRC_WIDTH1, width); 1574 regw(sc, DST_Y_X, (x << 16) | y); 1575 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1576 } 1577 1578 void 1579 mach64_clearscreen(struct mach64_softc *sc) 1580 { 1581 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1582 } 1583 1584 1585 void 1586 mach64_showpal(struct mach64_softc *sc) 1587 { 1588 int i, x = 0; 1589 1590 for (i = 0; i < 16; i++) { 1591 mach64_rectfill(sc, x, 0, 64, 64, i); 1592 x += 64; 1593 } 1594 } 1595 1596 int 1597 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1598 { 1599 if ((fg == 0) && (bg == 0)) 1600 { 1601 fg = WS_DEFAULT_FG; 1602 bg = WS_DEFAULT_BG; 1603 } 1604 *attrp = (fg & 0xf) << 24 | (bg & 0xf) << 16 | (flags & 0xff) << 8; 1605 return 0; 1606 } 1607 1608 /* 1609 * wsdisplay_accessops 1610 */ 1611 1612 int 1613 mach64_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 1614 { 1615 struct mach64_softc *sc = v; 1616 struct wsdisplay_fbinfo *wdf; 1617 struct mach64screen *ms=sc->active; 1618 1619 switch (cmd) { 1620 case WSDISPLAYIO_GTYPE: 1621 /* XXX is this the right type to return? */ 1622 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1623 return 0; 1624 1625 case WSDISPLAYIO_GINFO: 1626 wdf = (void *)data; 1627 wdf->height = ms->ri.ri_height; 1628 wdf->width = ms->ri.ri_width; 1629 wdf->depth = ms->ri.ri_depth; 1630 wdf->cmsize = 256; 1631 return 0; 1632 1633 case WSDISPLAYIO_GETCMAP: 1634 return mach64_getcmap(sc, 1635 (struct wsdisplay_cmap *)data); 1636 1637 case WSDISPLAYIO_PUTCMAP: 1638 return mach64_putcmap(sc, 1639 (struct wsdisplay_cmap *)data); 1640 1641 /* PCI config read/write passthrough. */ 1642 case PCI_IOC_CFGREAD: 1643 case PCI_IOC_CFGWRITE: 1644 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1645 cmd, data, flag, p)); 1646 1647 case WSDISPLAYIO_SMODE: 1648 { 1649 int new_mode = *(int*)data; 1650 1651 if (new_mode != sc->sc_mode) 1652 { 1653 sc->sc_mode = new_mode; 1654 if (new_mode == WSDISPLAYIO_MODE_EMUL) 1655 { 1656 /* 1657 * reset a few things the 1658 * Xserver might have screwed up 1659 */ 1660 mach64_restore_screen(ms, 1661 ms->type, ms->chars); 1662 mach64_cursor(ms, ms->cursoron, 1663 ms->cursorrow, 1664 ms->cursorcol); 1665 } 1666 } 1667 } 1668 return 0; 1669 1670 case WSDISPLAYIO_GETWSCHAR: 1671 return mach64_getwschar(sc, 1672 (struct wsdisplay_char *)data); 1673 1674 case WSDISPLAYIO_PUTWSCHAR: 1675 return mach64_putwschar(sc, 1676 (struct wsdisplay_char *)data); 1677 } 1678 return EPASSTHROUGH; 1679 } 1680 1681 paddr_t 1682 mach64_mmap(void *v, off_t offset, int prot) 1683 { 1684 struct mach64_softc *sc = v; 1685 paddr_t pa; 1686 1687 /* 'regular' framebuffer mmap()ing */ 1688 if (offset<sc->sc_apersize) { 1689 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase+offset, 0, 1690 prot, BUS_SPACE_MAP_LINEAR); 1691 return pa; 1692 } 1693 #if 0 1694 /* evil hack to allow mmap()ing other devices as well */ 1695 if ((offset > 0x80000000) && (offset <= 0xffffffff)) { 1696 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1697 BUS_SPACE_MAP_LINEAR); 1698 return pa; 1699 } 1700 #endif 1701 1702 if ((offset >= sc->sc_aperphys) && 1703 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1704 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1705 BUS_SPACE_MAP_LINEAR); 1706 return pa; 1707 } 1708 1709 if ((offset >= sc->sc_regphys) && 1710 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1711 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1712 BUS_SPACE_MAP_LINEAR); 1713 return pa; 1714 } 1715 1716 return -1; 1717 } 1718 1719 int 1720 mach64_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 1721 int *curxp, int *curyp, long *defattrp) 1722 { 1723 struct mach64_softc *sc = v; 1724 struct mach64screen *scr; 1725 struct rasops_info *ri; 1726 int cnt=type->nrows * type->ncols; 1727 1728 scr = malloc(sizeof(struct mach64screen), M_DEVBUF, M_WAITOK | M_ZERO); 1729 mach64_init_screen(sc, scr, type, 0, defattrp, sc->active == NULL); 1730 ri = &scr->ri; 1731 1732 ri->ri_hw = scr; 1733 /*ri->ri_bits=(void *)sc->sc_aperbase;*/ 1734 rasops_init(ri, mach64_console_screen.ri.ri_height / 8, 1735 mach64_console_screen.ri.ri_width / 8); 1736 1737 rasops_reconfig(ri, ri->ri_height / ri->ri_font->fontheight, 1738 ri->ri_width / ri->ri_font->fontwidth); 1739 set_address(ri, sc->sc_aperbase); 1740 mach64_allocattr(ri, WS_DEFAULT_FG, WS_DEFAULT_BG, 0, defattrp); 1741 1742 scr->ri.ri_ops.copyrows = mach64_copyrows; 1743 scr->ri.ri_ops.eraserows = mach64_eraserows; 1744 scr->ri.ri_ops.copycols = mach64_copycols; 1745 scr->ri.ri_ops.erasecols = mach64_erasecols; 1746 scr->ri.ri_ops.putchar = mach64_putchar; 1747 scr->ri.ri_ops.cursor = mach64_cursor; 1748 1749 scr->attrs = (long *)malloc(cnt * (sizeof(long) + sizeof(u_int)), 1750 M_DEVBUF, M_WAITOK); 1751 scr->chars = (u_int *)&scr->attrs[cnt]; 1752 mach64_eraserows(ri, 0, ri->ri_rows, *defattrp); 1753 1754 if (sc->active == NULL) { 1755 scr->active = 1; 1756 sc->active = scr; 1757 sc->currenttype = type; 1758 } 1759 1760 *cookiep = scr; 1761 *curxp = scr->cursorcol; 1762 *curyp = scr->cursorrow; 1763 1764 return 0; 1765 } 1766 1767 void 1768 mach64_free_screen(void *v, void *cookie) 1769 { 1770 struct mach64_softc *sc = v; 1771 struct mach64screen *scr = cookie; 1772 1773 LIST_REMOVE(scr, next); 1774 if (scr != &mach64_console_screen) { 1775 free(scr->attrs, M_DEVBUF); 1776 free(scr, M_DEVBUF); 1777 } else 1778 panic("mach64_free_screen: console"); 1779 1780 if (sc->active == scr) 1781 sc->active = 0; 1782 } 1783 1784 int 1785 mach64_show_screen(void *v, void *cookie, int waitok, 1786 void (*cb)(void *, int, int), void *cbarg) 1787 { 1788 struct mach64_softc *sc = v; 1789 struct mach64screen *scr, *oldscr; 1790 1791 scr = cookie; 1792 oldscr = sc->active; 1793 if (scr == oldscr) 1794 return 0; 1795 1796 sc->wanted = scr; 1797 sc->switchcb = cb; 1798 sc->switchcbarg = cbarg; 1799 if (cb) { 1800 callout_reset(&sc->switch_callout, 0, 1801 (void(*)(void *))mach64_switch_screen, sc); 1802 return EAGAIN; 1803 } 1804 1805 mach64_switch_screen(sc); 1806 1807 return 0; 1808 } 1809 1810 void 1811 mach64_switch_screen(struct mach64_softc *sc) 1812 { 1813 struct mach64screen *scr, *oldscr; 1814 const struct wsscreen_descr *type; 1815 1816 scr = sc->wanted; 1817 if (!scr) { 1818 printf("mach64_switch_screen: disappeared\n"); 1819 (*sc->switchcb)(sc->switchcbarg, EIO, 0); 1820 return; 1821 } 1822 type = scr->type; 1823 oldscr = sc->active; /* can be NULL! */ 1824 #ifdef DIAGNOSTIC 1825 if (oldscr) { 1826 if (!oldscr->active) 1827 panic("mach64_switch_screen: not active"); 1828 if (oldscr->type != sc->currenttype) 1829 panic("mach64_switch_screen: bad type"); 1830 } 1831 #endif 1832 if (scr == oldscr) 1833 return; 1834 1835 #ifdef DIAGNOSTIC 1836 /* XXX: this one bites us at reboot */ 1837 /* if (scr->active) 1838 panic("mach64_switch_screen: active");*/ 1839 #endif 1840 1841 if (oldscr) 1842 oldscr->active = 0; 1843 1844 if (sc->currenttype != type) { 1845 mach64_set_screentype(sc, type); 1846 sc->currenttype = type; 1847 } 1848 1849 scr->dispoffset = scr->mindispoffset; 1850 1851 if (!oldscr || (scr->dispoffset != oldscr->dispoffset)) { 1852 1853 } 1854 1855 /* Clear the entire screen. */ 1856 1857 scr->active = 1; 1858 mach64_restore_screen(scr, type, scr->chars); 1859 1860 sc->active = scr; 1861 1862 scr->ri.ri_ops.cursor(scr, scr->cursoron, scr->cursorrow, 1863 scr->cursorcol); 1864 1865 sc->wanted = 0; 1866 if (sc->switchcb) 1867 (*sc->switchcb)(sc->switchcbarg, 0, 0); 1868 } 1869 1870 void 1871 mach64_restore_screen(struct mach64screen *scr, 1872 const struct wsscreen_descr *type, u_int *mem) 1873 { 1874 int i, j, offset = 0; 1875 /*struct rasops_info *ri=&scr->ri;*/ 1876 u_int *charptr = scr->chars; 1877 long *attrptr = scr->attrs; 1878 1879 mach64_clearscreen(scr->sc); 1880 for (i = 0; i < scr->ri.ri_rows; i++) { 1881 for (j = 0; j < scr->ri.ri_cols; j++) { 1882 mach64_putchar(scr, i, j, charptr[offset], 1883 attrptr[offset]); 1884 offset++; 1885 } 1886 } 1887 scr->cursordrawn = 0; 1888 } 1889 1890 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1891 void 1892 set_address(struct rasops_info *ri, bus_addr_t fb) 1893 { 1894 /*printf(" %d %d %d\n",ri->ri_xorigin,ri->ri_yorigin,ri->ri_stride);*/ 1895 ri->ri_bits = (void *)((u_long)fb + ri->ri_stride * ri->ri_yorigin + 1896 ri->ri_xorigin); 1897 } 1898 1899 int 1900 mach64_getwschar(void *cookie, struct wsdisplay_char *wsc) 1901 { 1902 struct mach64_softc *sc = cookie; 1903 struct mach64screen *scr = sc->active; 1904 int fg, bg, fl; 1905 1906 if (scr){ 1907 if ((wsc->col >= 0) && (wsc->col < scr->ri.ri_cols) && 1908 (wsc->row >= 0) && (wsc->row < scr->ri.ri_rows)) { 1909 int pos = scr->ri.ri_cols * wsc->row + wsc->col; 1910 1911 wsc->letter = scr->chars[pos]; 1912 rasops_unpack_attr(scr->attrs[pos], &fg, &bg, &fl); 1913 wsc->foreground = fg; 1914 wsc->background = bg; 1915 wsc->flags = fl; 1916 return 0; 1917 } 1918 } 1919 return EINVAL; 1920 } 1921 1922 int 1923 mach64_putwschar(void *cookie, struct wsdisplay_char *wsc) 1924 { 1925 struct mach64_softc *sc=cookie; 1926 struct mach64screen *scr=sc->active; 1927 long attr; 1928 1929 if (scr){ 1930 if ((wsc->col >= 0) && (wsc->col < scr->ri.ri_cols) && 1931 (wsc->row >= 0) && (wsc->row < scr->ri.ri_rows)) { 1932 mach64_allocattr(&scr->ri, wsc->foreground, 1933 wsc->background, wsc->flags,&attr); 1934 mach64_putchar(&scr->ri, wsc->row, wsc->col, 1935 wsc->letter, attr); 1936 return 0; 1937 } 1938 } 1939 return EINVAL; 1940 } 1941 1942 #if 0 1943 int 1944 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1945 { 1946 1947 return 0; 1948 } 1949 #endif 1950 1951
Indexes created Thu Oct 02 14:10:14 GMT 2025