machfb.c revision 1.4
1 /* $NetBSD: machfb.c,v 1.4 2002/10/25 18:57:06 junyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/callout.h> 42 43 #ifdef __sparc__ 44 #include <machine/openfirm.h> 45 #endif 46 47 #include <dev/ic/videomode.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/pciio.h> 53 #include <dev/pci/machfbreg.h> 54 55 #include <dev/wscons/wsdisplayvar.h> 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/rasops/rasops.h> 59 60 #define MACH64_REG_SIZE 1024 61 #define MACH64_REG_OFF 0x7ffc00 62 63 #define NBARS 3 /* number of Mach64 PCI BARs */ 64 65 #ifdef __sparc__ 66 int sparc_screen_is_console(struct pci_attach_args *); 67 #endif 68 69 struct vga_bar { 70 bus_addr_t vb_base; 71 bus_size_t vb_size; 72 pcireg_t vb_type; 73 int vb_flags; 74 }; 75 76 struct mach64_softc { 77 struct device sc_dev; 78 pci_chipset_tag_t sc_pc; 79 pcitag_t sc_pcitag; 80 81 struct vga_bar sc_bars[NBARS]; 82 struct vga_bar sc_rom; 83 84 #define sc_aperbase sc_bars[0].vb_base 85 #define sc_apersize sc_bars[0].vb_size 86 87 #define sc_iobase sc_bars[1].vb_base 88 #define sc_iosize sc_bars[1].vb_size 89 90 #define sc_regbase sc_bars[2].vb_base 91 #define sc_regsize sc_bars[2].vb_size 92 93 bus_space_tag_t sc_regt; 94 bus_space_tag_t sc_memt; 95 bus_space_handle_t sc_regh; 96 bus_space_handle_t sc_memh; 97 98 size_t memsize; 99 int memtype; 100 101 int has_dsp; 102 int bits_per_pixel; 103 int max_x, max_y; 104 int virt_x, virt_y; 105 int color_depth; 106 107 int mem_freq; 108 int ramdac_freq; 109 int ref_freq; 110 111 int ref_div; 112 int log2_vclk_post_div; 113 int vclk_post_div; 114 int vclk_fb_div; 115 int mclk_post_div; 116 int mclk_fb_div; 117 118 struct mach64screen *wanted; 119 struct mach64screen *active; 120 void (*switchcb)(void *, int, int); 121 void *switchcbarg; 122 struct callout switch_callout; 123 int nscreens; 124 LIST_HEAD(, mach64screen) screens; 125 const struct wsscreen_descr *currenttype; 126 }; 127 128 struct mach64screen { 129 LIST_ENTRY(mach64screen) next; 130 struct mach64_softc *sc; 131 const struct wsscreen_descr *type; 132 int active; 133 u_int16_t *mem; 134 int dispoffset; 135 int mindispoffset; 136 int maxdispoffset; 137 138 int cursoron; 139 int cursorcol; 140 int cursorrow; 141 u_int16_t cursortmp; 142 }; 143 144 struct mach64_crtcregs { 145 u_int32_t h_total_disp; 146 u_int32_t h_sync_strt_wid; 147 u_int32_t v_total_disp; 148 u_int32_t v_sync_strt_wid; 149 u_int32_t gen_cntl; 150 u_int32_t clock_cntl; 151 u_int32_t color_depth; 152 u_int32_t dot_clock; 153 }; 154 155 struct { 156 u_int16_t chip_id; 157 u_int32_t ramdac_freq; 158 } mach64_info[] = { 159 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 160 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 161 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 162 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 163 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 164 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 165 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 166 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 167 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 168 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 169 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 179 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 180 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 181 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 182 }; 183 184 static int mach64_chip_id, mach64_chip_rev; 185 static struct videomode default_mode; 186 struct rasops_info mach64_rasops_info; 187 static struct mach64screen mach64_console_screen; 188 189 static char *mach64_memtype_names[] = { 190 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 191 "(unknown type)" 192 }; 193 194 struct videomode mach64_modes[] = { 195 /* 640x400 @ 70 Hz, 31.5 kHz */ 196 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 197 /* 640x480 @ 72 Hz, 36.5 kHz */ 198 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 199 /* 800x600 @ 72 Hz, 48.0 kHz */ 200 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 201 VID_PHSYNC | VID_PVSYNC }, 202 /* 1024x768 @ 70 Hz, 56.5 kHz */ 203 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 204 VID_NHSYNC | VID_NVSYNC }, 205 /* 1152x864 @ 70 Hz, 62.4 kHz */ 206 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 207 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 208 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 209 VID_NHSYNC | VID_NVSYNC } 210 }; 211 212 /* FIXME values are wrong! */ 213 const u_char mach64_cmap[16 * 3] = { 214 0x00, 0x00, 0x00, /* black */ 215 0x7f, 0x00, 0x00, /* red */ 216 0x00, 0x7f, 0x00, /* green */ 217 0x7f, 0x7f, 0x00, /* brown */ 218 0x00, 0x00, 0x7f, /* blue */ 219 0x7f, 0x00, 0x7f, /* magenta */ 220 0x00, 0x7f, 0x7f, /* cyan */ 221 0xff, 0xff, 0xff, /* white */ 222 223 0x7f, 0x7f, 0x7f, /* black */ 224 0xff, 0x00, 0x00, /* red */ 225 0x00, 0xff, 0x00, /* green */ 226 0xff, 0xff, 0x00, /* brown */ 227 0x00, 0x00, 0xff, /* blue */ 228 0xff, 0x00, 0xff, /* magenta */ 229 0x00, 0xff, 0xff, /* cyan */ 230 0xff, 0xff, 0xff, /* white */ 231 }; 232 233 int mach64_match(struct device *, struct cfdata *, void *); 234 void mach64_attach(struct device *, struct device *, void *); 235 236 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 237 NULL, NULL); 238 239 void mach64_init(struct mach64_softc *); 240 int mach64_get_memsize(struct mach64_softc *); 241 int mach64_get_max_ramdac(struct mach64_softc *); 242 void mach64_get_mode(struct mach64_softc *, struct videomode *); 243 int mach64_calc_crtcregs(struct mach64_softc *, struct mach64_crtcregs *, 244 struct videomode *); 245 void mach64_set_crtcregs(struct mach64_softc *, struct mach64_crtcregs *); 246 int mach64_modeswitch(struct mach64_softc *, struct videomode *); 247 void mach64_set_dsp(struct mach64_softc *); 248 void mach64_set_pll(struct mach64_softc *, int); 249 void mach64_reset_engine(struct mach64_softc *); 250 void mach64_init_engine(struct mach64_softc *); 251 void mach64_adjust_frame(struct mach64_softc *, int, int); 252 void mach64_init_lut(struct mach64_softc *); 253 void mach64_switch_screen(struct mach64_softc *); 254 void mach64_init_screen(struct mach64_softc *, struct mach64screen *, 255 const struct wsscreen_descr *, int, long *); 256 void mach64_restore_screen(struct mach64screen *, 257 const struct wsscreen_descr *, u_int16_t *); 258 void mach64_set_screentype(struct mach64_softc *, 259 const struct wsscreen_descr *); 260 261 void mach64_cursor(void *, int, int, int); 262 int mach64_mapchar(void *, int, u_int *); 263 void mach64_putchar(void *, int, int, u_int, long); 264 void mach64_copycols(void *, int, int, int, int); 265 void mach64_erasecols(void *, int, int, int, long); 266 void mach64_copyrows(void *, int, int, int); 267 void mach64_eraserows(void *, int, int, long); 268 int mach64_allocattr(void *, int, int, int, long *); 269 270 const struct wsdisplay_emulops mach64_emulops = { 271 mach64_cursor, 272 mach64_mapchar, 273 mach64_putchar, 274 mach64_copycols, 275 mach64_erasecols, 276 mach64_copyrows, 277 mach64_eraserows, 278 mach64_allocattr, 279 }; 280 281 struct wsscreen_descr mach64_defaultscreen = { 282 "default", 283 0, 0, 284 &mach64_rasops_info.ri_ops, 285 8, 16, 286 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 287 &default_mode 288 }, mach64_80x25_screen = { 289 "80x25", 80, 25, 290 &mach64_rasops_info.ri_ops, 291 8, 16, 292 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 293 &mach64_modes[0] 294 }, mach64_80x30_screen = { 295 "80x30", 80, 30, 296 &mach64_rasops_info.ri_ops, 297 8, 16, 298 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 299 &mach64_modes[1] 300 }, mach64_80x40_screen = { 301 "80x40", 80, 40, 302 &mach64_rasops_info.ri_ops, 303 8, 10, 304 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 305 &mach64_modes[0] 306 }, mach64_80x50_screen = { 307 "80x50", 80, 50, 308 &mach64_rasops_info.ri_ops, 309 8, 8, 310 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 311 &mach64_modes[0] 312 }, mach64_100x37_screen = { 313 "100x37", 100, 37, 314 &mach64_rasops_info.ri_ops, 315 8, 16, 316 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 317 &mach64_modes[2] 318 }, mach64_128x48_screen = { 319 "128x48", 128, 48, 320 &mach64_rasops_info.ri_ops, 321 8, 16, 322 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 323 &mach64_modes[3] 324 }, mach64_144x54_screen = { 325 "144x54", 144, 54, 326 &mach64_rasops_info.ri_ops, 327 8, 16, 328 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 329 &mach64_modes[4] 330 }, mach64_160x64_screen = { 331 "160x54", 160, 64, 332 &mach64_rasops_info.ri_ops, 333 8, 16, 334 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 335 &mach64_modes[5] 336 }; 337 338 const struct wsscreen_descr *_mach64_scrlist[] = { 339 &mach64_defaultscreen, 340 &mach64_80x25_screen, 341 &mach64_80x30_screen, 342 &mach64_80x40_screen, 343 &mach64_80x50_screen, 344 &mach64_100x37_screen, 345 &mach64_128x48_screen, 346 &mach64_144x54_screen, 347 &mach64_160x64_screen 348 }; 349 350 struct wsscreen_list mach64_screenlist = { 351 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 352 _mach64_scrlist 353 }; 354 355 int mach64_ioctl(void *, u_long, caddr_t, int, struct proc *); 356 paddr_t mach64_mmap(void *, off_t, int); 357 int mach64_alloc_screen(void *, const struct wsscreen_descr *, void **, 358 int *, int *, long *); 359 void mach64_free_screen(void *, void *); 360 int mach64_show_screen(void *, void *, int, void (*)(void *, int, int), 361 void *); 362 int mach64_load_font(void *, void *, struct wsdisplay_font *); 363 364 struct wsdisplay_accessops mach64_accessops = { 365 mach64_ioctl, 366 mach64_mmap, 367 mach64_alloc_screen, 368 mach64_free_screen, 369 mach64_show_screen, 370 NULL 371 }; 372 373 /* 374 * Inline functions for getting access to register aperture. 375 */ 376 static inline u_int32_t regr(struct mach64_softc *, u_int32_t); 377 static inline u_int8_t regrb(struct mach64_softc *, u_int32_t); 378 static inline void regw(struct mach64_softc *, u_int32_t, u_int32_t); 379 static inline void regwb(struct mach64_softc *, u_int32_t, u_int8_t); 380 static inline void regwb_pll(struct mach64_softc *, u_int32_t, u_int8_t); 381 382 static inline u_int32_t 383 regr(struct mach64_softc *sc, u_int32_t index) 384 { 385 386 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 387 } 388 389 static inline u_int8_t 390 regrb(struct mach64_softc *sc, u_int32_t index) 391 { 392 393 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 394 } 395 396 static inline void 397 regw(struct mach64_softc *sc, u_int32_t index, u_int32_t data) 398 { 399 400 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 401 } 402 403 static inline void 404 regwb(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 405 { 406 407 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 408 } 409 410 static inline void 411 regwb_pll(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 412 { 413 414 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 415 regwb(sc, CLOCK_CNTL + 2, data); 416 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 417 } 418 419 static inline void 420 wait_for_fifo(struct mach64_softc *sc, u_int8_t v) 421 { 422 423 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 424 ; 425 } 426 427 static inline void 428 wait_for_idle(struct mach64_softc *sc) 429 { 430 431 wait_for_fifo(sc, 16); 432 while ((regr(sc, GUI_STAT) & 1) != 0) 433 ; 434 } 435 436 int 437 mach64_match(struct device *parent, struct cfdata *match, void *aux) 438 { 439 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 440 int i; 441 442 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 443 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 444 return 0; 445 446 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 447 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 448 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 449 mach64_chip_rev = PCI_REVISION(pa->pa_class); 450 return 1; 451 } 452 453 return 0; 454 } 455 456 void 457 mach64_attach(struct device *parent, struct device *self, void *aux) 458 { 459 struct mach64_softc *sc = (void *)self; 460 struct pci_attach_args *pa = aux; 461 char devinfo[256]; 462 int bar, reg, id; 463 struct wsemuldisplaydev_attach_args aa; 464 int console; 465 long defattr; 466 467 sc->sc_pc = pa->pa_pc; 468 sc->sc_pcitag = pa->pa_tag; 469 470 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 471 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 472 473 for (bar = 0; bar < NBARS; bar++) { 474 reg = PCI_MAPREG_START + (bar * 4); 475 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 476 sc->sc_pcitag, reg); 477 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 478 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 479 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 480 } 481 sc->sc_memt = pa->pa_memt; 482 483 mach64_init(sc); 484 485 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 486 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 487 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 488 (u_int)sc->sc_regbase); 489 490 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 491 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 492 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 493 (mach64_chip_rev & 0x07) == 0)) 494 sc->has_dsp = 0; 495 else 496 sc->has_dsp = 1; 497 498 sc->memsize = mach64_get_memsize(sc); 499 if (sc->memsize == 8192) 500 /* The last page is used as register aperture. */ 501 sc->memsize -= 4; 502 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 503 504 /* XXX is there any way to calculate reference frequency from 505 known values? */ 506 if (mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) 507 sc->ref_freq = 29498; 508 else 509 sc->ref_freq = 14318; 510 511 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 512 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 513 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 514 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 515 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 516 (sc->ref_div * 2); 517 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 518 (sc->mem_freq * sc->ref_div); 519 sc->ramdac_freq = mach64_get_max_ramdac(sc); 520 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 521 sc->sc_dev.dv_xname, (u_long)sc->memsize, 522 mach64_memtype_names[sc->memtype], 523 sc->mem_freq / 1000, sc->mem_freq % 1000, 524 sc->ramdac_freq / 1000); 525 526 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 527 if (id != mach64_chip_id) { 528 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 529 sc->sc_dev.dv_xname, id, mach64_chip_id); 530 return; 531 } 532 533 #ifdef __sparc__ 534 mach64_get_mode(sc, &default_mode); 535 #else 536 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)) ; 537 #endif 538 539 sc->bits_per_pixel = 8; 540 sc->virt_x = default_mode.hdisplay; 541 sc->virt_y = default_mode.vdisplay; 542 sc->max_x = sc->virt_x - 1; 543 sc->max_y = (sc->memsize * 1024) / 544 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 545 546 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 547 548 mach64_init_engine(sc); 549 #if 0 550 mach64_adjust_frame(0, 0); 551 if (sc->bits_per_pixel == 8) 552 mach64_init_lut(sc); 553 #endif 554 555 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 556 default_mode.hdisplay, default_mode.vdisplay, 557 sc->bits_per_pixel); 558 559 mach64_rasops_info.ri_depth = sc->bits_per_pixel; 560 mach64_rasops_info.ri_bits = (void *)sc->sc_aperbase; 561 mach64_rasops_info.ri_width = default_mode.hdisplay; 562 mach64_rasops_info.ri_height = default_mode.vdisplay; 563 mach64_rasops_info.ri_stride = mach64_rasops_info.ri_width; 564 mach64_rasops_info.ri_flg = RI_CLEAR; 565 566 rasops_init(&mach64_rasops_info, mach64_rasops_info.ri_height / 16, 567 mach64_rasops_info.ri_width / 8); 568 569 mach64_defaultscreen.nrows = mach64_rasops_info.ri_rows; 570 mach64_defaultscreen.ncols = mach64_rasops_info.ri_cols; 571 572 mach64_init_screen(sc, &mach64_console_screen, 573 &mach64_defaultscreen, 1, &defattr); 574 575 mach64_rasops_info.ri_ops.allocattr(&mach64_rasops_info, 0, 0, 0, 576 &defattr); 577 578 #ifdef __sparc__ 579 console = sparc_screen_is_console(pa); 580 #else 581 console = 1; 582 #endif 583 if (console) 584 wsdisplay_cnattach(&mach64_defaultscreen, &mach64_rasops_info, 585 0, 0, defattr); 586 587 aa.console = console; 588 aa.scrdata = &mach64_screenlist; 589 aa.accessops = &mach64_accessops; 590 aa.accesscookie = sc; 591 592 config_found(self, &aa, wsemuldisplaydevprint); 593 } 594 595 void 596 mach64_init_screen(struct mach64_softc *sc, struct mach64screen *scr, 597 const struct wsscreen_descr *type, int existing, long *attrp) 598 { 599 #if !defined(__sparc__) 600 struct videomode *mode = (struct videomode *)type->modecookie; 601 #endif 602 603 scr->sc = sc; 604 scr->type = type; 605 scr->mindispoffset = 0; 606 scr->maxdispoffset = sc->memsize * 1024; 607 scr->dispoffset = 0; 608 scr->cursorcol = 0; 609 scr->cursorrow = 0; 610 611 if (existing) { 612 scr->mem = (u_int16_t *)malloc(type->nrows * type->ncols * 2, 613 M_DEVBUF, M_WAITOK); 614 scr->active = 1; 615 616 #if !defined(__sparc__) 617 if (mach64_modeswitch(sc, mode)) { 618 panic("%s: failed to switch video mode", 619 sc->sc_dev.dv_xname); 620 } 621 #endif 622 } else { 623 scr->active = 0; 624 scr->mem = NULL; 625 } 626 627 wsfont_init(); 628 629 sc->nscreens++; 630 LIST_INSERT_HEAD(&sc->screens, scr, next); 631 } 632 633 void 634 mach64_init(struct mach64_softc *sc) 635 { 636 637 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 638 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 639 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 640 } 641 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 642 643 sc->sc_regt = sc->sc_memt; 644 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 645 sc->sc_regsize, &sc->sc_regh); 646 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 647 648 #if _BYTE_ORDER == _BIG_ENDIAN 649 sc->sc_aperbase += 0x800000; 650 sc->sc_apersize -= 0x800000; 651 #endif 652 653 sc->nscreens = 0; 654 LIST_INIT(&sc->screens); 655 sc->active = NULL; 656 sc->currenttype = &mach64_defaultscreen; 657 callout_init(&sc->switch_callout); 658 } 659 660 int 661 mach64_get_memsize(struct mach64_softc *sc) 662 { 663 int tmp, memsize; 664 int mem_tab[] = { 665 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 666 }; 667 668 tmp = regr(sc, MEM_CNTL); 669 if (sc->has_dsp) { 670 tmp &= 0x0000000f; 671 if (tmp < 8) 672 memsize = (tmp + 1) * 512; 673 else if (tmp < 12) 674 memsize = (tmp - 3) * 1024; 675 else 676 memsize = (tmp - 7) * 2048; 677 } else { 678 memsize = mem_tab[tmp & 0x07]; 679 } 680 681 return memsize; 682 } 683 684 int 685 mach64_get_max_ramdac(struct mach64_softc *sc) 686 { 687 int i; 688 689 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 690 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 691 (mach64_chip_rev & 0x07)) 692 return 170000; 693 694 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 695 if (mach64_chip_id == mach64_info[i].chip_id) 696 return mach64_info[i].ramdac_freq; 697 698 if (sc->bits_per_pixel == 8) 699 return 135000; 700 else 701 return 80000; 702 } 703 704 void 705 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 706 { 707 struct mach64_crtcregs crtc; 708 709 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 710 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 711 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 712 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 713 714 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 715 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 716 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 717 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 718 mode->hsync_start; 719 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 720 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 721 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 722 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 723 724 #ifdef MACH64_DEBUG 725 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 726 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 727 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 728 #endif 729 } 730 731 int 732 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 733 struct videomode *mode) 734 { 735 736 if (mode->dot_clock > sc->ramdac_freq) 737 /* Clock too high. */ 738 return 1; 739 740 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 741 ((mode->htotal >> 3) - 1); 742 crtc->h_sync_strt_wid = 743 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 744 ((mode->hsync_start >> 3) - 1); 745 746 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 747 (mode->vtotal - 1); 748 crtc->v_sync_strt_wid = 749 ((mode->vsync_end - mode->vsync_start) << 16) | 750 (mode->vsync_start - 1); 751 752 if (mode->flags & VID_NVSYNC) 753 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 754 755 switch (sc->bits_per_pixel) { 756 case 8: 757 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 758 break; 759 case 16: 760 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 761 break; 762 case 32: 763 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 764 break; 765 } 766 767 crtc->gen_cntl = 0; 768 if (mode->flags & VID_INTERLACE) 769 crtc->gen_cntl |= CRTC_INTERLACE_EN; 770 if (mode->flags & VID_CSYNC) 771 crtc->gen_cntl |= CRTC_CSYNC_EN; 772 773 crtc->dot_clock = mode->dot_clock; 774 775 return 0; 776 } 777 778 void 779 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 780 { 781 782 mach64_set_pll(sc, crtc->dot_clock); 783 784 if (sc->has_dsp) 785 mach64_set_dsp(sc); 786 787 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 788 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 789 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 790 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 791 792 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 793 794 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 795 796 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 797 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 798 } 799 800 int 801 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 802 { 803 struct mach64_crtcregs crtc; 804 805 if (mach64_calc_crtcregs(sc, &crtc, mode)) 806 return 1; 807 808 mach64_set_crtcregs(sc, &crtc); 809 return 0; 810 } 811 812 void 813 mach64_reset_engine(struct mach64_softc *sc) 814 { 815 816 /* Reset engine.*/ 817 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 818 819 /* Enable engine. */ 820 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 821 822 /* Ensure engine is not locked up by clearing any FIFO or 823 host errors. */ 824 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 825 BUS_FIFO_ERR_ACK); 826 } 827 828 void 829 mach64_init_engine(struct mach64_softc *sc) 830 { 831 u_int32_t pitch_value; 832 833 pitch_value = sc->virt_x; 834 835 if (sc->bits_per_pixel == 24) 836 pitch_value *= 3; 837 838 mach64_reset_engine(sc); 839 840 wait_for_fifo(sc, 14); 841 842 regw(sc, CONTEXT_MASK, 0xffffffff); 843 844 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 845 846 regw(sc, DST_Y_X, 0); 847 regw(sc, DST_HEIGHT, 0); 848 regw(sc, DST_BRES_ERR, 0); 849 regw(sc, DST_BRES_INC, 0); 850 regw(sc, DST_BRES_DEC, 0); 851 852 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 853 DST_Y_TOP_TO_BOTTOM); 854 855 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 856 857 regw(sc, SRC_Y_X, 0); 858 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 859 regw(sc, SRC_Y_X_START, 0); 860 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 861 862 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 863 864 wait_for_fifo(sc, 13); 865 regw(sc, HOST_CNTL, 0); 866 867 regw(sc, PAT_REG0, 0); 868 regw(sc, PAT_REG1, 0); 869 regw(sc, PAT_CNTL, 0); 870 871 regw(sc, SC_LEFT, 0); 872 regw(sc, SC_TOP, 0); 873 regw(sc, SC_BOTTOM, default_mode.vdisplay - 1); 874 regw(sc, SC_RIGHT, pitch_value - 1); 875 876 regw(sc, DP_BKGD_CLR, 0); 877 regw(sc, DP_FRGD_CLR, 0xffffffff); 878 regw(sc, DP_WRITE_MASK, 0xffffffff); 879 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 880 881 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 882 883 wait_for_fifo(sc, 3); 884 regw(sc, CLR_CMP_CLR, 0); 885 regw(sc, CLR_CMP_MASK, 0xffffffff); 886 regw(sc, CLR_CMP_CNTL, 0); 887 888 wait_for_fifo(sc, 2); 889 switch (sc->bits_per_pixel) { 890 case 8: 891 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 892 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 893 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) & ~DAC_8BIT_EN); 894 break; 895 #if 0 896 case 32: 897 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 898 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 899 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 900 break; 901 #endif 902 } 903 904 wait_for_fifo(sc, 5); 905 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 906 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 907 908 wait_for_idle(sc); 909 } 910 911 void 912 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 913 { 914 int offset; 915 916 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 917 918 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 919 offset); 920 } 921 922 void 923 mach64_set_dsp(struct mach64_softc *sc) 924 { 925 u_int32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 926 u_int32_t dsp_off, dsp_on, dsp_xclks_per_qw; 927 u_int32_t xclks_per_qw, y; 928 u_int32_t fifo_off, fifo_on; 929 930 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 931 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 932 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 933 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 934 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 935 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 936 dsp_loop_latency = 0; 937 fifo_depth = 24; 938 } else { 939 dsp_loop_latency = 2; 940 fifo_depth = 32; 941 } 942 943 dsp_precision = 0; 944 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 945 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 946 y = (xclks_per_qw * fifo_depth) >> 11; 947 while (y) { 948 y >>= 1; 949 dsp_precision++; 950 } 951 dsp_precision -= 5; 952 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 953 954 switch (sc->memtype) { 955 case DRAM: 956 case EDO_DRAM: 957 case PSEUDO_EDO: 958 if (sc->memsize > 1024) { 959 page_size = 9; 960 dsp_loop_latency += 6; 961 } else { 962 page_size = 10; 963 if (sc->memtype == DRAM) 964 dsp_loop_latency += 8; 965 else 966 dsp_loop_latency += 7; 967 } 968 break; 969 case SDRAM: 970 case SGRAM: 971 if (sc->memsize > 1024) { 972 page_size = 8; 973 dsp_loop_latency += 8; 974 } else { 975 page_size = 10; 976 dsp_loop_latency += 9; 977 } 978 break; 979 default: 980 page_size = 10; 981 dsp_loop_latency += 9; 982 break; 983 } 984 985 if (xclks_per_qw >= (page_size << 11)) 986 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 987 else 988 fifo_on = (3 * page_size + 2) << 6; 989 990 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 991 dsp_on = fifo_on >> dsp_precision; 992 dsp_off = fifo_off >> dsp_precision; 993 994 #ifdef MACH64_DEBUG 995 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 996 "dsp_precision = %d, dsp_loop_latency = %d,\n" 997 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 998 "mclk_post_div = %d, vclk_post_div = %d\n", 999 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1000 sc->mclk_fb_div, sc->vclk_fb_div, 1001 sc->mclk_post_div, sc->vclk_post_div); 1002 #endif 1003 1004 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1005 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1006 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1007 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1008 } 1009 1010 void 1011 mach64_set_pll(struct mach64_softc *sc, int clock) 1012 { 1013 int q; 1014 1015 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1016 #ifdef MACH64_DEBUG 1017 printf("q = %d\n", q); 1018 #endif 1019 if (q > 25500) { 1020 printf("Warning: q > 25500\n"); 1021 q = 25500; 1022 sc->vclk_post_div = 1; 1023 sc->log2_vclk_post_div = 0; 1024 } else if (q > 12750) { 1025 sc->vclk_post_div = 1; 1026 sc->log2_vclk_post_div = 0; 1027 } else if (q > 6350) { 1028 sc->vclk_post_div = 2; 1029 sc->log2_vclk_post_div = 1; 1030 } else if (q > 3150) { 1031 sc->vclk_post_div = 4; 1032 sc->log2_vclk_post_div = 2; 1033 } else if (q >= 1600) { 1034 sc->vclk_post_div = 8; 1035 sc->log2_vclk_post_div = 3; 1036 } else { 1037 printf("Warning: q < 1600\n"); 1038 sc->vclk_post_div = 8; 1039 sc->log2_vclk_post_div = 3; 1040 } 1041 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1042 1043 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1044 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1045 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1046 } 1047 1048 void 1049 mach64_init_lut(struct mach64_softc *sc) 1050 { 1051 int i; 1052 1053 regwb(sc, DAC_REGS, 0); 1054 1055 for (i = 0; i < 16; i++) { 1056 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3]); 1057 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3 + 1]); 1058 regwb(sc, DAC_REGS + 1, mach64_cmap[i + 3 + 2]); 1059 } 1060 } 1061 1062 void 1063 mach64_switch_screen(struct mach64_softc *sc) 1064 { 1065 struct mach64screen *scr, *oldscr; 1066 const struct wsscreen_descr *type; 1067 1068 scr = sc->wanted; 1069 if (!scr) { 1070 printf("mach64_switch_screen: disappeared\n"); 1071 (*sc->switchcb)(sc->switchcbarg, EIO, 0); 1072 return; 1073 } 1074 type = scr->type; 1075 oldscr = sc->active; /* can be NULL! */ 1076 #ifdef DIAGNOSTIC 1077 if (oldscr) { 1078 if (!oldscr->active) 1079 panic("mach64_switch_screen: not active"); 1080 if (oldscr->type != vc->currenttype) 1081 panic("mach64_switch_screen: bad type"); 1082 } 1083 #endif 1084 if (scr == oldscr) 1085 return; 1086 1087 #ifdef DIAGNOSTIC 1088 if (scr->active) 1089 panic("mach64_switch_screen: active"); 1090 #endif 1091 1092 if (oldscr) 1093 oldscr->active = 0; 1094 1095 if (sc->currenttype != type) { 1096 mach64_set_screentype(sc, type); 1097 sc->currenttype = type; 1098 } 1099 1100 scr->dispoffset = scr->mindispoffset; 1101 1102 if (!oldscr || (scr->dispoffset != oldscr->dispoffset)) { 1103 1104 } 1105 1106 /* Clear the entire screen. */ 1107 1108 scr->active = 1; 1109 mach64_restore_screen(scr, type, scr->mem); 1110 1111 sc->active = scr; 1112 1113 mach64_cursor(scr, scr->cursoron, scr->cursorrow, scr->cursorcol); 1114 1115 sc->wanted = 0; 1116 if (sc->switchcb) 1117 (*sc->switchcb)(sc->switchcbarg, 0, 0); 1118 } 1119 1120 void 1121 mach64_restore_screen(struct mach64screen *scr, 1122 const struct wsscreen_descr *type, u_int16_t *mem) 1123 { 1124 1125 } 1126 1127 void 1128 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1129 { 1130 1131 } 1132 1133 /* 1134 * wsdisplay_emulops 1135 */ 1136 1137 void 1138 mach64_cursor(void *cookie, int on, int row, int col) 1139 { 1140 1141 } 1142 1143 int 1144 mach64_mapchar(void *cookie, int uni, u_int *index) 1145 { 1146 1147 return 0; 1148 } 1149 1150 void 1151 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1152 { 1153 1154 } 1155 1156 void 1157 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1158 { 1159 1160 } 1161 1162 void 1163 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1164 { 1165 1166 } 1167 1168 void 1169 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1170 { 1171 1172 } 1173 1174 void 1175 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1176 { 1177 1178 } 1179 1180 int 1181 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1182 { 1183 1184 return 0; 1185 } 1186 1187 /* 1188 * wsdisplay_accessops 1189 */ 1190 1191 int 1192 mach64_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 1193 { 1194 1195 return ENOTTY; 1196 } 1197 1198 paddr_t 1199 mach64_mmap(void *v, off_t offset, int prot) 1200 { 1201 1202 return -1; 1203 } 1204 1205 int 1206 mach64_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 1207 int *curxp, int *curyp, long *defattrp) 1208 { 1209 struct mach64_softc *sc = v; 1210 struct mach64screen *scr; 1211 1212 if (sc->nscreens == 1) 1213 sc->screens.lh_first->mem = scr->mem; 1214 1215 scr = malloc(sizeof(struct mach64screen), M_DEVBUF, M_WAITOK); 1216 mach64_init_screen(sc, scr, type, 0, defattrp); 1217 1218 if (sc->nscreens == 1) { 1219 scr->active = 1; 1220 sc->active = scr; 1221 sc->currenttype = type; 1222 } else { 1223 scr->mem = malloc(type->ncols * type->nrows * 2, M_DEVBUF, 1224 M_WAITOK); 1225 mach64_eraserows(sc, 0, type->nrows, *defattrp); 1226 } 1227 1228 *cookiep = scr; 1229 *curxp = scr->cursorcol; 1230 *curyp = scr->cursorrow; 1231 1232 return 0; 1233 } 1234 1235 void 1236 mach64_free_screen(void *v, void *cookie) 1237 { 1238 struct mach64_softc *sc = v; 1239 struct mach64screen *scr = cookie; 1240 1241 LIST_REMOVE(scr, next); 1242 if (scr != &mach64_console_screen) 1243 free(scr, M_DEVBUF); 1244 else 1245 panic("mach64_free_screen: console"); 1246 1247 if (sc->active == scr) 1248 sc->active = 0; 1249 } 1250 1251 int 1252 mach64_show_screen(void *v, void *cookie, int waitok, 1253 void (*cb)(void *, int, int), void *cbarg) 1254 { 1255 struct mach64_softc *sc = v; 1256 struct mach64screen *scr, *oldscr; 1257 1258 scr = cookie; 1259 oldscr = sc->active; 1260 if (scr == oldscr) 1261 return 0; 1262 1263 sc->wanted = scr; 1264 sc->switchcb = cb; 1265 sc->switchcbarg = cbarg; 1266 if (cb) { 1267 callout_reset(&sc->switch_callout, 0, 1268 (void(*)(void *))mach64_switch_screen, sc); 1269 return EAGAIN; 1270 } 1271 1272 mach64_switch_screen(sc); 1273 1274 return 0; 1275 } 1276 1277 int 1278 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1279 { 1280 1281 return 0; 1282 } 1283 1284 #ifdef __sparc__ 1285 int 1286 sparc_screen_is_console(struct pci_attach_args *pa) 1287 { 1288 int node; 1289 1290 node = PCITAG_NODE(pa->pa_tag); 1291 if (node == -1) 1292 return 0; 1293 1294 return (node == OF_instance_to_package(OF_stdout())); 1295 } 1296 #endif 1297
Indexes created Thu Oct 02 14:10:14 GMT 2025