machfb.c revision 1.41
1 /* $NetBSD: machfb.c,v 1.41 2006/04/12 20:35:42 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, 36 "$NetBSD: machfb.c,v 1.41 2006/04/12 20:35:42 macallan Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/callout.h> 44 45 #ifdef __sparc__ 46 #include <machine/promlib.h> 47 #endif 48 49 #ifdef __powerpc__ 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_pci.h> 52 #endif 53 54 #include <dev/videomode/videomode.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 #include <dev/pci/pciio.h> 60 #include <dev/pci/machfbreg.h> 61 62 #ifdef __sparc__ 63 #include <dev/sun/fbio.h> 64 #include <dev/sun/fbvar.h> 65 #include <sys/conf.h> 66 #else 67 #include <dev/wscons/wsdisplayvar.h> 68 #endif 69 70 #include <dev/wscons/wsconsio.h> 71 #include <dev/wsfont/wsfont.h> 72 #include <dev/rasops/rasops.h> 73 74 #include <dev/wscons/wsdisplay_vconsvar.h> 75 76 #define MACH64_REG_SIZE 1024 77 #define MACH64_REG_OFF 0x7ffc00 78 79 #define NBARS 3 /* number of Mach64 PCI BARs */ 80 81 struct vga_bar { 82 bus_addr_t vb_base; 83 pcireg_t vb_busaddr; 84 bus_size_t vb_size; 85 pcireg_t vb_type; 86 int vb_flags; 87 }; 88 89 struct mach64_softc { 90 struct device sc_dev; 91 #ifdef __sparc__ 92 struct fbdevice sc_fb; 93 #endif 94 pci_chipset_tag_t sc_pc; 95 pcitag_t sc_pcitag; 96 97 struct vga_bar sc_bars[NBARS]; 98 struct vga_bar sc_rom; 99 100 #define sc_aperbase sc_bars[0].vb_base 101 #define sc_apersize sc_bars[0].vb_size 102 #define sc_aperphys sc_bars[0].vb_busaddr 103 104 #define sc_iobase sc_bars[1].vb_base 105 #define sc_iosize sc_bars[1].vb_size 106 107 #define sc_regbase sc_bars[2].vb_base 108 #define sc_regsize sc_bars[2].vb_size 109 #define sc_regphys sc_bars[2].vb_busaddr 110 111 bus_space_tag_t sc_regt; 112 bus_space_tag_t sc_memt; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 uint32_t sc_nbus, sc_ndev, sc_nfunc; 116 size_t memsize; 117 int memtype; 118 119 int sc_mode; 120 int sc_bg; 121 int sc_locked; 122 123 int has_dsp; 124 int bits_per_pixel; 125 int max_x; 126 int max_y; 127 int virt_x; 128 int virt_y; 129 int color_depth; 130 131 int mem_freq; 132 int ramdac_freq; 133 int ref_freq; 134 135 int ref_div; 136 int log2_vclk_post_div; 137 int vclk_post_div; 138 int vclk_fb_div; 139 int mclk_post_div; 140 int mclk_fb_div; 141 142 struct videomode *sc_my_mode; 143 u_char sc_cmap_red[256]; 144 u_char sc_cmap_green[256]; 145 u_char sc_cmap_blue[256]; 146 int sc_dacw, sc_blanked, sc_console; 147 struct vcons_data vd; 148 }; 149 150 struct mach64_crtcregs { 151 uint32_t h_total_disp; 152 uint32_t h_sync_strt_wid; 153 uint32_t v_total_disp; 154 uint32_t v_sync_strt_wid; 155 uint32_t gen_cntl; 156 uint32_t clock_cntl; 157 uint32_t color_depth; 158 uint32_t dot_clock; 159 }; 160 161 struct { 162 uint16_t chip_id; 163 uint32_t ramdac_freq; 164 } static const mach64_info[] = { 165 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 166 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 167 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 168 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 169 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 174 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 175 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 185 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 186 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 187 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 188 }; 189 190 static int mach64_chip_id, mach64_chip_rev; 191 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 192 193 static const char *mach64_memtype_names[] = { 194 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 195 "(unknown type)" 196 }; 197 198 static struct videomode mach64_modes[] = { 199 /* 640x400 @ 70 Hz, 31.5 kHz */ 200 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 201 /* 640x480 @ 72 Hz, 36.5 kHz */ 202 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 203 /* 800x600 @ 72 Hz, 48.0 kHz */ 204 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 205 VID_PHSYNC | VID_PVSYNC }, 206 /* 1024x768 @ 70 Hz, 56.5 kHz */ 207 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 208 VID_NHSYNC | VID_NVSYNC }, 209 /* 1152x864 @ 70 Hz, 62.4 kHz */ 210 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 211 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 212 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 213 VID_NHSYNC | VID_NVSYNC } 214 }; 215 216 extern const u_char rasops_cmap[768]; 217 218 static int mach64_match(struct device *, struct cfdata *, void *); 219 static void mach64_attach(struct device *, struct device *, void *); 220 221 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 222 NULL, NULL); 223 224 static void mach64_init(struct mach64_softc *); 225 static int mach64_get_memsize(struct mach64_softc *); 226 static int mach64_get_max_ramdac(struct mach64_softc *); 227 228 #if defined(__sparc__) || defined(__powerpc__) 229 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 230 #endif 231 232 static int mach64_calc_crtcregs(struct mach64_softc *, 233 struct mach64_crtcregs *, 234 struct videomode *); 235 static void mach64_set_crtcregs(struct mach64_softc *, 236 struct mach64_crtcregs *); 237 238 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 239 static void mach64_set_dsp(struct mach64_softc *); 240 static void mach64_set_pll(struct mach64_softc *, int); 241 static void mach64_reset_engine(struct mach64_softc *); 242 static void mach64_init_engine(struct mach64_softc *); 243 #if 0 244 static void mach64_adjust_frame(struct mach64_softc *, int, int); 245 #endif 246 static void mach64_init_lut(struct mach64_softc *); 247 248 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 249 static int mach64_set_screentype(struct mach64_softc *, 250 const struct wsscreen_descr *); 251 static int mach64_is_console(struct pci_attach_args *); 252 253 static void mach64_cursor(void *, int, int, int); 254 #if 0 255 static int mach64_mapchar(void *, int, u_int *); 256 #endif 257 static void mach64_putchar(void *, int, int, u_int, long); 258 static void mach64_copycols(void *, int, int, int, int); 259 static void mach64_erasecols(void *, int, int, int, long); 260 static void mach64_copyrows(void *, int, int, int); 261 static void mach64_eraserows(void *, int, int, long); 262 static int mach64_allocattr(void *, int, int, int, long *); 263 static void mach64_clearscreen(struct mach64_softc *); 264 265 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 266 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 267 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 268 uint8_t, uint8_t); 269 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 270 int, int, int) ; 271 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 272 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 273 uint32_t, uint32_t); 274 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 275 #if 0 276 static void mach64_showpal(struct mach64_softc *); 277 #endif 278 279 static void set_address(struct rasops_info *, bus_addr_t); 280 static void machfb_blank(struct mach64_softc *, int); 281 282 #if 0 283 static const struct wsdisplay_emulops mach64_emulops = { 284 mach64_cursor, 285 mach64_mapchar, 286 mach64_putchar, 287 mach64_copycols, 288 mach64_erasecols, 289 mach64_copyrows, 290 mach64_eraserows, 291 mach64_allocattr, 292 }; 293 #endif 294 295 static struct wsscreen_descr mach64_defaultscreen = { 296 "default", 297 80, 30, 298 NULL, 299 8, 16, 300 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 301 &default_mode 302 }, mach64_80x25_screen = { 303 "80x25", 80, 25, 304 NULL, 305 8, 16, 306 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 307 &mach64_modes[0] 308 }, mach64_80x30_screen = { 309 "80x30", 80, 30, 310 NULL, 311 8, 16, 312 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 313 &mach64_modes[1] 314 }, mach64_80x40_screen = { 315 "80x40", 80, 40, 316 NULL, 317 8, 10, 318 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 319 &mach64_modes[0] 320 }, mach64_80x50_screen = { 321 "80x50", 80, 50, 322 NULL, 323 8, 8, 324 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 325 &mach64_modes[0] 326 }, mach64_100x37_screen = { 327 "100x37", 100, 37, 328 NULL, 329 8, 16, 330 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 331 &mach64_modes[2] 332 }, mach64_128x48_screen = { 333 "128x48", 128, 48, 334 NULL, 335 8, 16, 336 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 337 &mach64_modes[3] 338 }, mach64_144x54_screen = { 339 "144x54", 144, 54, 340 NULL, 341 8, 16, 342 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 343 &mach64_modes[4] 344 }, mach64_160x64_screen = { 345 "160x54", 160, 64, 346 NULL, 347 8, 16, 348 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 349 &mach64_modes[5] 350 }; 351 352 static const struct wsscreen_descr *_mach64_scrlist[] = { 353 &mach64_defaultscreen, 354 &mach64_80x25_screen, 355 &mach64_80x30_screen, 356 &mach64_80x40_screen, 357 &mach64_80x50_screen, 358 &mach64_100x37_screen, 359 &mach64_128x48_screen, 360 &mach64_144x54_screen, 361 &mach64_160x64_screen 362 }; 363 364 static struct wsscreen_list mach64_screenlist = { 365 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 366 _mach64_scrlist 367 }; 368 369 static int mach64_ioctl(void *, void *, u_long, caddr_t, int, 370 struct lwp *); 371 static paddr_t mach64_mmap(void *, void *, off_t, int); 372 373 #if 0 374 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 375 #endif 376 377 static struct wsdisplay_accessops mach64_accessops = { 378 mach64_ioctl, 379 mach64_mmap, 380 NULL, /* vcons_alloc_screen */ 381 NULL, /* vcons_free_screen */ 382 NULL, /* vcons_show_screen */ 383 NULL, /* load_font */ 384 NULL, /* polls */ 385 NULL, /* getwschar */ 386 NULL, /* putwschar */ 387 NULL, /* scroll */ 388 }; 389 390 static struct vcons_screen mach64_console_screen; 391 392 /* framebuffer device, SPARC-only so far */ 393 #ifdef __sparc__ 394 395 static void machfb_unblank(struct device *); 396 static void machfb_fbattach(struct mach64_softc *); 397 398 extern struct cfdriver machfb_cd; 399 400 dev_type_open(machfb_fbopen); 401 dev_type_close(machfb_fbclose); 402 dev_type_ioctl(machfb_fbioctl); 403 dev_type_mmap(machfb_fbmmap); 404 405 /* frame buffer generic driver */ 406 static struct fbdriver machfb_fbdriver = { 407 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 408 machfb_fbmmap, nokqfilter 409 }; 410 411 #endif /* __sparc__ */ 412 413 /* 414 * Inline functions for getting access to register aperture. 415 */ 416 417 static inline uint32_t 418 regr(struct mach64_softc *sc, uint32_t index) 419 { 420 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 421 } 422 423 static inline uint8_t 424 regrb(struct mach64_softc *sc, uint32_t index) 425 { 426 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 427 } 428 429 static inline void 430 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 431 { 432 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 433 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 434 BUS_SPACE_BARRIER_WRITE); 435 } 436 437 static inline void 438 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 439 { 440 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 441 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 442 BUS_SPACE_BARRIER_WRITE); 443 } 444 445 static inline void 446 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 447 { 448 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 449 regwb(sc, CLOCK_CNTL + 2, data); 450 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 451 } 452 453 static inline void 454 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 455 { 456 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 457 continue; 458 } 459 460 static inline void 461 wait_for_idle(struct mach64_softc *sc) 462 { 463 wait_for_fifo(sc, 16); 464 while ((regr(sc, GUI_STAT) & 1) != 0) 465 continue; 466 } 467 468 static int 469 mach64_match(struct device *parent, struct cfdata *match, void *aux) 470 { 471 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 472 int i; 473 474 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 475 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 476 return 0; 477 478 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 479 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 480 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 481 mach64_chip_rev = PCI_REVISION(pa->pa_class); 482 return 100; 483 } 484 485 return 0; 486 } 487 488 static void 489 mach64_attach(struct device *parent, struct device *self, void *aux) 490 { 491 struct mach64_softc *sc = (void *)self; 492 struct pci_attach_args *pa = aux; 493 struct rasops_info *ri; 494 char devinfo[256]; 495 int bar, reg, id; 496 struct wsemuldisplaydev_attach_args aa; 497 long defattr; 498 int setmode; 499 pcireg_t screg; 500 501 sc->sc_pc = pa->pa_pc; 502 sc->sc_pcitag = pa->pa_tag; 503 sc->sc_dacw = -1; 504 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 505 sc->sc_nbus = pa->pa_bus; 506 sc->sc_ndev = pa->pa_device; 507 sc->sc_nfunc = pa->pa_function; 508 sc->sc_locked = 0; 509 510 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 511 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 512 513 /* enable memory and IO access */ 514 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 515 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 516 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 517 518 for (bar = 0; bar < NBARS; bar++) { 519 reg = PCI_MAPREG_START + (bar * 4); 520 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 521 sc->sc_pcitag, reg); 522 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 523 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 524 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 525 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 526 sc->sc_pcitag, reg)&0xfffffff0; 527 } 528 sc->sc_memt = pa->pa_memt; 529 530 mach64_init(sc); 531 532 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 533 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 534 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 535 (u_int)sc->sc_regphys); 536 537 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 538 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 539 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 540 (mach64_chip_rev & 0x07) == 0)) 541 sc->has_dsp = 0; 542 else 543 sc->has_dsp = 1; 544 545 sc->memsize = mach64_get_memsize(sc); 546 if (sc->memsize == 8192) 547 /* The last page is used as register aperture. */ 548 sc->memsize -= 4; 549 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 550 551 /* XXX is there any way to calculate reference frequency from 552 known values? */ 553 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 554 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 555 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 556 printf("%s: ref_freq=29.498MHz\n", sc->sc_dev.dv_xname); 557 sc->ref_freq = 29498; 558 } else 559 sc->ref_freq = 14318; 560 561 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 562 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 563 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 564 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 565 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 566 (sc->ref_div * 2); 567 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 568 (sc->mem_freq * sc->ref_div); 569 sc->ramdac_freq = mach64_get_max_ramdac(sc); 570 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 571 sc->sc_dev.dv_xname, (u_long)sc->memsize, 572 mach64_memtype_names[sc->memtype], 573 sc->mem_freq / 1000, sc->mem_freq % 1000, 574 sc->ramdac_freq / 1000); 575 576 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 577 if (id != mach64_chip_id) { 578 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 579 sc->sc_dev.dv_xname, id, mach64_chip_id); 580 return; 581 } 582 583 sc->sc_console = mach64_is_console(pa); 584 #ifdef DIAGNOSTIC 585 printf("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 586 #endif 587 #if defined(__sparc__) || defined(__powerpc__) 588 if (sc->sc_console) { 589 mach64_get_mode(sc, &default_mode); 590 setmode = 0; 591 sc->sc_my_mode = &default_mode; 592 } else { 593 /* fill in default_mode if it's empty */ 594 mach64_get_mode(sc, &default_mode); 595 if (default_mode.dot_clock == 0) { 596 memcpy(&default_mode, &mach64_modes[4], 597 sizeof(default_mode)); 598 } 599 sc->sc_my_mode = &default_mode; 600 setmode = 1; 601 } 602 #else 603 if (default_mode.dot_clock == 0) { 604 memcpy(&default_mode, &mach64_modes[0], 605 sizeof(default_mode)); 606 } 607 sc->sc_my_mode = &mach64_modes[0]; 608 setmode = 1; 609 #endif 610 611 sc->bits_per_pixel = 8; 612 sc->virt_x = sc->sc_my_mode->hdisplay; 613 sc->virt_y = sc->sc_my_mode->vdisplay; 614 sc->max_x = sc->virt_x - 1; 615 sc->max_y = (sc->memsize * 1024) / 616 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 617 618 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 619 620 mach64_init_engine(sc); 621 #if 0 622 mach64_adjust_frame(0, 0); 623 if (sc->bits_per_pixel == 8) 624 mach64_init_lut(sc); 625 #endif 626 627 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 628 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 629 sc->bits_per_pixel); 630 631 #ifdef __sparc__ 632 machfb_fbattach(sc); 633 #endif 634 635 wsfont_init(); 636 637 sc->sc_bg = WS_DEFAULT_BG; 638 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 639 sc->vd.init_screen = mach64_init_screen; 640 641 if (sc->sc_console) { 642 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 643 &defattr); 644 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 645 646 ri = &mach64_console_screen.scr_ri; 647 mach64_defaultscreen.textops = &ri->ri_ops; 648 mach64_defaultscreen.capabilities = ri->ri_caps; 649 mach64_defaultscreen.nrows = ri->ri_rows; 650 mach64_defaultscreen.ncols = ri->ri_cols; 651 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 652 } else { 653 /* 654 * since we're not the console we can postpone the rest 655 * until someone actually allocates a screen for us 656 */ 657 mach64_modeswitch(sc, sc->sc_my_mode); 658 } 659 660 mach64_init_lut(sc); 661 mach64_clearscreen(sc); 662 machfb_blank(sc, 0); /* unblank the screen */ 663 664 aa.console = sc->sc_console; 665 aa.scrdata = &mach64_screenlist; 666 aa.accessops = &mach64_accessops; 667 aa.accesscookie = &sc->vd; 668 669 config_found(self, &aa, wsemuldisplaydevprint); 670 } 671 672 static void 673 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 674 long *defattr) 675 { 676 struct mach64_softc *sc = cookie; 677 struct rasops_info *ri = &scr->scr_ri; 678 679 /* XXX for now */ 680 #define setmode 0 681 682 ri->ri_depth = sc->bits_per_pixel; 683 ri->ri_width = sc->sc_my_mode->hdisplay; 684 ri->ri_height = sc->sc_my_mode->vdisplay; 685 ri->ri_stride = ri->ri_width; 686 ri->ri_flg = RI_CENTER; 687 set_address(ri, sc->sc_aperbase); 688 689 if (existing) { 690 ri->ri_flg |= RI_CLEAR; 691 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 692 panic("%s: failed to switch video mode", 693 sc->sc_dev.dv_xname); 694 } 695 } 696 697 rasops_init(ri, sc->sc_my_mode->vdisplay/8, 698 sc->sc_my_mode->hdisplay/8); 699 ri->ri_caps = WSSCREEN_WSCOLORS; 700 701 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 702 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 703 704 /* enable acceleration */ 705 ri->ri_hw = scr; 706 ri->ri_ops.copyrows = mach64_copyrows; 707 ri->ri_ops.copycols = mach64_copycols; 708 ri->ri_ops.eraserows = mach64_eraserows; 709 ri->ri_ops.erasecols = mach64_erasecols; 710 ri->ri_ops.cursor = mach64_cursor; 711 ri->ri_ops.putchar = mach64_putchar; 712 ri->ri_ops.allocattr = mach64_allocattr; 713 } 714 715 static void 716 mach64_init(struct mach64_softc *sc) 717 { 718 uint32_t *p32, saved_value; 719 uint8_t *p; 720 int need_swap; 721 722 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 723 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 724 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 725 } 726 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 727 728 sc->sc_regt = sc->sc_memt; 729 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 730 sc->sc_regsize, &sc->sc_regh); 731 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 732 733 /* 734 * Test wether the aperture is byte swapped or not 735 */ 736 p32 = (uint32_t*)(u_long)sc->sc_aperbase; 737 saved_value = *p32; 738 p = (uint8_t*)(u_long)sc->sc_aperbase; 739 *p32 = 0x12345678; 740 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 741 need_swap = 0; 742 else 743 need_swap = 1; 744 if (need_swap) { 745 sc->sc_aperbase += 0x800000; 746 sc->sc_apersize -= 0x800000; 747 } 748 *p32 = saved_value; 749 750 sc->sc_blanked = 0; 751 } 752 753 static int 754 mach64_get_memsize(struct mach64_softc *sc) 755 { 756 int tmp, memsize; 757 int mem_tab[] = { 758 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 759 }; 760 tmp = regr(sc, MEM_CNTL); 761 #ifdef DIAGNOSTIC 762 printf("%s: memctl %08x\n", sc->sc_dev.dv_xname, tmp); 763 #endif 764 if (sc->has_dsp) { 765 tmp &= 0x0000000f; 766 if (tmp < 8) 767 memsize = (tmp + 1) * 512; 768 else if (tmp < 12) 769 memsize = (tmp - 3) * 1024; 770 else 771 memsize = (tmp - 7) * 2048; 772 } else { 773 memsize = mem_tab[tmp & 0x07]; 774 } 775 776 return memsize; 777 } 778 779 static int 780 mach64_get_max_ramdac(struct mach64_softc *sc) 781 { 782 int i; 783 784 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 785 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 786 (mach64_chip_rev & 0x07)) 787 return 170000; 788 789 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 790 if (mach64_chip_id == mach64_info[i].chip_id) 791 return mach64_info[i].ramdac_freq; 792 793 if (sc->bits_per_pixel == 8) 794 return 135000; 795 else 796 return 80000; 797 } 798 799 #if defined(__sparc__) || defined(__powerpc__) 800 static void 801 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 802 { 803 struct mach64_crtcregs crtc; 804 805 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 806 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 807 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 808 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 809 810 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 811 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 812 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 813 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 814 mode->hsync_start; 815 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 816 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 817 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 818 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 819 820 #ifndef DEBUG_MACHFB 821 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 822 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 823 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 824 #endif 825 } 826 #endif 827 828 static int 829 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 830 struct videomode *mode) 831 { 832 833 if (mode->dot_clock > sc->ramdac_freq) 834 /* Clock too high. */ 835 return 1; 836 837 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 838 ((mode->htotal >> 3) - 1); 839 crtc->h_sync_strt_wid = 840 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 841 ((mode->hsync_start >> 3) - 1); 842 843 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 844 (mode->vtotal - 1); 845 crtc->v_sync_strt_wid = 846 ((mode->vsync_end - mode->vsync_start) << 16) | 847 (mode->vsync_start - 1); 848 849 if (mode->flags & VID_NVSYNC) 850 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 851 852 switch (sc->bits_per_pixel) { 853 case 8: 854 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 855 break; 856 case 16: 857 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 858 break; 859 case 32: 860 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 861 break; 862 } 863 864 crtc->gen_cntl = 0; 865 if (mode->flags & VID_INTERLACE) 866 crtc->gen_cntl |= CRTC_INTERLACE_EN; 867 868 if (mode->flags & VID_CSYNC) 869 crtc->gen_cntl |= CRTC_CSYNC_EN; 870 871 crtc->dot_clock = mode->dot_clock; 872 873 return 0; 874 } 875 876 static void 877 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 878 { 879 880 mach64_set_pll(sc, crtc->dot_clock); 881 882 if (sc->has_dsp) 883 mach64_set_dsp(sc); 884 885 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 886 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 887 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 888 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 889 890 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 891 892 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 893 894 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 895 /* XXX this unconditionally enables composite sync on SPARC */ 896 #ifdef __sparc__ 897 CRTC_CSYNC_EN | 898 #endif 899 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 900 } 901 902 static int 903 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 904 { 905 struct mach64_crtcregs crtc; 906 907 if (mach64_calc_crtcregs(sc, &crtc, mode)) 908 return 1; 909 910 mach64_set_crtcregs(sc, &crtc); 911 return 0; 912 } 913 914 static void 915 mach64_reset_engine(struct mach64_softc *sc) 916 { 917 918 /* Reset engine.*/ 919 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 920 921 /* Enable engine. */ 922 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 923 924 /* Ensure engine is not locked up by clearing any FIFO or 925 host errors. */ 926 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 927 BUS_FIFO_ERR_ACK); 928 } 929 930 static void 931 mach64_init_engine(struct mach64_softc *sc) 932 { 933 uint32_t pitch_value; 934 935 pitch_value = sc->virt_x; 936 937 if (sc->bits_per_pixel == 24) 938 pitch_value *= 3; 939 940 mach64_reset_engine(sc); 941 942 wait_for_fifo(sc, 14); 943 944 regw(sc, CONTEXT_MASK, 0xffffffff); 945 946 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 947 948 regw(sc, DST_Y_X, 0); 949 regw(sc, DST_HEIGHT, 0); 950 regw(sc, DST_BRES_ERR, 0); 951 regw(sc, DST_BRES_INC, 0); 952 regw(sc, DST_BRES_DEC, 0); 953 954 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 955 DST_Y_TOP_TO_BOTTOM); 956 957 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 958 959 regw(sc, SRC_Y_X, 0); 960 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 961 regw(sc, SRC_Y_X_START, 0); 962 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 963 964 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 965 966 wait_for_fifo(sc, 13); 967 regw(sc, HOST_CNTL, 0); 968 969 regw(sc, PAT_REG0, 0); 970 regw(sc, PAT_REG1, 0); 971 regw(sc, PAT_CNTL, 0); 972 973 regw(sc, SC_LEFT, 0); 974 regw(sc, SC_TOP, 0); 975 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 976 regw(sc, SC_RIGHT, pitch_value - 1); 977 978 regw(sc, DP_BKGD_CLR, 0); 979 regw(sc, DP_FRGD_CLR, 0xffffffff); 980 regw(sc, DP_WRITE_MASK, 0xffffffff); 981 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 982 983 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 984 985 wait_for_fifo(sc, 3); 986 regw(sc, CLR_CMP_CLR, 0); 987 regw(sc, CLR_CMP_MASK, 0xffffffff); 988 regw(sc, CLR_CMP_CNTL, 0); 989 990 wait_for_fifo(sc, 2); 991 switch (sc->bits_per_pixel) { 992 case 8: 993 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 994 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 995 /* We want 8 bit per channel */ 996 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 997 break; 998 #if 0 999 case 32: 1000 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 1001 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1002 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1003 break; 1004 #endif 1005 } 1006 1007 wait_for_fifo(sc, 5); 1008 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1009 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1010 1011 wait_for_idle(sc); 1012 } 1013 1014 #if 0 1015 static void 1016 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1017 { 1018 int offset; 1019 1020 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1021 1022 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1023 offset); 1024 } 1025 #endif 1026 1027 static void 1028 mach64_set_dsp(struct mach64_softc *sc) 1029 { 1030 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1031 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1032 uint32_t xclks_per_qw, y; 1033 uint32_t fifo_off, fifo_on; 1034 1035 printf("%s: initializing the DSP\n", sc->sc_dev.dv_xname); 1036 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1037 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1038 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1039 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1040 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1041 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1042 dsp_loop_latency = 0; 1043 fifo_depth = 24; 1044 } else { 1045 dsp_loop_latency = 2; 1046 fifo_depth = 32; 1047 } 1048 1049 dsp_precision = 0; 1050 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1051 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1052 y = (xclks_per_qw * fifo_depth) >> 11; 1053 while (y) { 1054 y >>= 1; 1055 dsp_precision++; 1056 } 1057 dsp_precision -= 5; 1058 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1059 1060 switch (sc->memtype) { 1061 case DRAM: 1062 case EDO_DRAM: 1063 case PSEUDO_EDO: 1064 if (sc->memsize > 1024) { 1065 page_size = 9; 1066 dsp_loop_latency += 6; 1067 } else { 1068 page_size = 10; 1069 if (sc->memtype == DRAM) 1070 dsp_loop_latency += 8; 1071 else 1072 dsp_loop_latency += 7; 1073 } 1074 break; 1075 case SDRAM: 1076 case SGRAM: 1077 if (sc->memsize > 1024) { 1078 page_size = 8; 1079 dsp_loop_latency += 8; 1080 } else { 1081 page_size = 10; 1082 dsp_loop_latency += 9; 1083 } 1084 break; 1085 default: 1086 page_size = 10; 1087 dsp_loop_latency += 9; 1088 break; 1089 } 1090 1091 if (xclks_per_qw >= (page_size << 11)) 1092 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1093 else 1094 fifo_on = (3 * page_size + 2) << 6; 1095 1096 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1097 dsp_on = fifo_on >> dsp_precision; 1098 dsp_off = fifo_off >> dsp_precision; 1099 1100 #ifdef DEBUG_MACHFB 1101 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1102 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1103 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1104 "mclk_post_div = %d, vclk_post_div = %d\n", 1105 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1106 sc->mclk_fb_div, sc->vclk_fb_div, 1107 sc->mclk_post_div, sc->vclk_post_div); 1108 #endif 1109 1110 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1111 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1112 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1113 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1114 } 1115 1116 static void 1117 mach64_set_pll(struct mach64_softc *sc, int clock) 1118 { 1119 int q; 1120 1121 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1122 #ifdef DEBUG_MACHFB 1123 printf("q = %d\n", q); 1124 #endif 1125 if (q > 25500) { 1126 printf("Warning: q > 25500\n"); 1127 q = 25500; 1128 sc->vclk_post_div = 1; 1129 sc->log2_vclk_post_div = 0; 1130 } else if (q > 12750) { 1131 sc->vclk_post_div = 1; 1132 sc->log2_vclk_post_div = 0; 1133 } else if (q > 6350) { 1134 sc->vclk_post_div = 2; 1135 sc->log2_vclk_post_div = 1; 1136 } else if (q > 3150) { 1137 sc->vclk_post_div = 4; 1138 sc->log2_vclk_post_div = 2; 1139 } else if (q >= 1600) { 1140 sc->vclk_post_div = 8; 1141 sc->log2_vclk_post_div = 3; 1142 } else { 1143 printf("Warning: q < 1600\n"); 1144 sc->vclk_post_div = 8; 1145 sc->log2_vclk_post_div = 3; 1146 } 1147 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1148 1149 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1150 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1151 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1152 } 1153 1154 static void 1155 mach64_init_lut(struct mach64_softc *sc) 1156 { 1157 int i, idx; 1158 1159 idx = 0; 1160 for (i = 0; i < 256; i++) { 1161 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1162 rasops_cmap[idx + 2]); 1163 idx += 3; 1164 } 1165 } 1166 1167 static int 1168 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1169 uint8_t b) 1170 { 1171 sc->sc_cmap_red[index] = r; 1172 sc->sc_cmap_green[index] = g; 1173 sc->sc_cmap_blue[index] = b; 1174 /* 1175 * writing the dac index takes a while, in theory we can poll some 1176 * register to see when it's ready - but we better avoid writing it 1177 * unnecessarily 1178 */ 1179 if (index != sc->sc_dacw) { 1180 regwb(sc, DAC_MASK, 0xff); 1181 regwb(sc, DAC_WINDEX, index); 1182 } 1183 sc->sc_dacw = index + 1; 1184 regwb(sc, DAC_DATA, r); 1185 regwb(sc, DAC_DATA, g); 1186 regwb(sc, DAC_DATA, b); 1187 return 0; 1188 } 1189 1190 static int 1191 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1192 { 1193 uint index = cm->index; 1194 uint count = cm->count; 1195 int i, error; 1196 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1197 uint8_t *r, *g, *b; 1198 1199 if (cm->index >= 256 || cm->count > 256 || 1200 (cm->index + cm->count) > 256) 1201 return EINVAL; 1202 error = copyin(cm->red, &rbuf[index], count); 1203 if (error) 1204 return error; 1205 error = copyin(cm->green, &gbuf[index], count); 1206 if (error) 1207 return error; 1208 error = copyin(cm->blue, &bbuf[index], count); 1209 if (error) 1210 return error; 1211 1212 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1213 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1214 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1215 1216 r = &sc->sc_cmap_red[index]; 1217 g = &sc->sc_cmap_green[index]; 1218 b = &sc->sc_cmap_blue[index]; 1219 1220 for (i = 0; i < count; i++) { 1221 mach64_putpalreg(sc, index, *r, *g, *b); 1222 index++; 1223 r++, g++, b++; 1224 } 1225 return 0; 1226 } 1227 1228 static int 1229 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1230 { 1231 u_int index = cm->index; 1232 u_int count = cm->count; 1233 int error; 1234 1235 if (index >= 255 || count > 256 || index + count > 256) 1236 return EINVAL; 1237 1238 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1239 if (error) 1240 return error; 1241 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1242 if (error) 1243 return error; 1244 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1245 if (error) 1246 return error; 1247 1248 return 0; 1249 } 1250 1251 static int 1252 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1253 { 1254 struct mach64_crtcregs regs; 1255 1256 if (mach64_calc_crtcregs(sc, ®s, 1257 (struct videomode *)des->modecookie)) 1258 return 1; 1259 1260 mach64_set_crtcregs(sc, ®s); 1261 return 0; 1262 } 1263 1264 static int 1265 mach64_is_console(struct pci_attach_args *pa) 1266 { 1267 #ifdef __sparc__ 1268 int node; 1269 1270 node = PCITAG_NODE(pa->pa_tag); 1271 if (node == -1) 1272 return 0; 1273 1274 return (node == prom_instance_to_package(prom_stdout())); 1275 #elif defined(__powerpc__) 1276 /* check if we're the /chosen console device */ 1277 int chosen, stdout, node, us; 1278 1279 us = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1280 chosen = OF_finddevice("/chosen"); 1281 OF_getprop(chosen, "stdout", &stdout, 4); 1282 node = OF_instance_to_package(stdout); 1283 return (us == node); 1284 #else 1285 return 1; 1286 #endif 1287 } 1288 1289 /* 1290 * wsdisplay_emulops 1291 */ 1292 1293 static void 1294 mach64_cursor(void *cookie, int on, int row, int col) 1295 { 1296 struct rasops_info *ri = cookie; 1297 struct vcons_screen *scr = ri->ri_hw; 1298 struct mach64_softc *sc = scr->scr_cookie; 1299 int x, y, wi, he; 1300 1301 wi = ri->ri_font->fontwidth; 1302 he = ri->ri_font->fontheight; 1303 1304 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1305 x = ri->ri_ccol * wi + ri->ri_xorigin; 1306 y = ri->ri_crow * he + ri->ri_yorigin; 1307 if (ri->ri_flg & RI_CURSOR) { 1308 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1309 0xff); 1310 ri->ri_flg &= ~RI_CURSOR; 1311 } 1312 ri->ri_crow = row; 1313 ri->ri_ccol = col; 1314 if (on) { 1315 x = ri->ri_ccol * wi + ri->ri_xorigin; 1316 y = ri->ri_crow * he + ri->ri_yorigin; 1317 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1318 0xff); 1319 ri->ri_flg |= RI_CURSOR;; 1320 } 1321 } else { 1322 scr->scr_ri.ri_crow = row; 1323 scr->scr_ri.ri_ccol = col; 1324 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1325 } 1326 } 1327 1328 #if 0 1329 static int 1330 mach64_mapchar(void *cookie, int uni, u_int *index) 1331 { 1332 return 0; 1333 } 1334 #endif 1335 1336 static void 1337 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1338 { 1339 struct rasops_info *ri = cookie; 1340 struct vcons_screen *scr = ri->ri_hw; 1341 struct mach64_softc *sc = scr->scr_cookie; 1342 1343 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1344 int fg, bg, uc; 1345 uint8_t *data; 1346 int x, y, wi, he; 1347 wi = ri->ri_font->fontwidth; 1348 he = ri->ri_font->fontheight; 1349 1350 if (!CHAR_IN_FONT(c, ri->ri_font)) 1351 return; 1352 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1353 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1354 x = ri->ri_xorigin + col * wi; 1355 y = ri->ri_yorigin + row * he; 1356 if (c == 0x20) { 1357 mach64_rectfill(sc, x, y, wi, he, bg); 1358 } else { 1359 uc = c-ri->ri_font->firstchar; 1360 data = (uint8_t *)ri->ri_font->data + uc * 1361 ri->ri_fontscale; 1362 1363 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1364 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1365 } 1366 } 1367 } 1368 1369 1370 static void 1371 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1372 { 1373 struct rasops_info *ri = cookie; 1374 struct vcons_screen *scr = ri->ri_hw; 1375 struct mach64_softc *sc = scr->scr_cookie; 1376 int32_t xs, xd, y, width, height; 1377 1378 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1379 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1380 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1381 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1382 width = ri->ri_font->fontwidth * ncols; 1383 height = ri->ri_font->fontheight; 1384 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1385 } 1386 } 1387 1388 static void 1389 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1390 { 1391 struct rasops_info *ri = cookie; 1392 struct vcons_screen *scr = ri->ri_hw; 1393 struct mach64_softc *sc = scr->scr_cookie; 1394 int32_t x, y, width, height, fg, bg, ul; 1395 1396 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1397 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1398 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1399 width = ri->ri_font->fontwidth * ncols; 1400 height = ri->ri_font->fontheight; 1401 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1402 1403 mach64_rectfill(sc, x, y, width, height, bg); 1404 } 1405 } 1406 1407 static void 1408 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1409 { 1410 struct rasops_info *ri = cookie; 1411 struct vcons_screen *scr = ri->ri_hw; 1412 struct mach64_softc *sc = scr->scr_cookie; 1413 int32_t x, ys, yd, width, height; 1414 1415 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1416 x = ri->ri_xorigin; 1417 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1418 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1419 width = ri->ri_emuwidth; 1420 height = ri->ri_font->fontheight*nrows; 1421 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1422 } 1423 } 1424 1425 static void 1426 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1427 { 1428 struct rasops_info *ri = cookie; 1429 struct vcons_screen *scr = ri->ri_hw; 1430 struct mach64_softc *sc = scr->scr_cookie; 1431 int32_t x, y, width, height, fg, bg, ul; 1432 1433 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1434 x = ri->ri_xorigin; 1435 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1436 width = ri->ri_emuwidth; 1437 height = ri->ri_font->fontheight * nrows; 1438 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1439 1440 mach64_rectfill(sc, x, y, width, height, bg); 1441 } 1442 } 1443 1444 static void 1445 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1446 { 1447 uint32_t dest_ctl = 0; 1448 1449 wait_for_idle(sc); 1450 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1451 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1452 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1453 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1454 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1455 if (yd < ys) { 1456 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1457 } else { 1458 ys += height - 1; 1459 yd += height - 1; 1460 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1461 } 1462 if (xd < xs) { 1463 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1464 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1465 } else { 1466 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1467 xs += width - 1; 1468 xd += width - 1; 1469 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1470 } 1471 regw(sc, DST_CNTL, dest_ctl); 1472 1473 regw(sc, SRC_Y_X, (xs << 16) | ys); 1474 regw(sc, SRC_WIDTH1, width); 1475 regw(sc, DST_Y_X, (xd << 16) | yd); 1476 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1477 } 1478 1479 static void 1480 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1481 int height, uint32_t fg, uint32_t bg) 1482 { 1483 wait_for_idle(sc); 1484 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1485 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1486 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1487 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1488 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1489 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1490 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1491 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1492 regw(sc, DP_BKGD_CLR, bg); 1493 regw(sc, DP_FRGD_CLR, fg); 1494 regw(sc, SRC_Y_X, 0); 1495 regw(sc, SRC_WIDTH1, width); 1496 regw(sc, DST_Y_X, (xd << 16) | yd); 1497 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1498 /* now feed the data into the chip */ 1499 } 1500 1501 static void 1502 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1503 { 1504 int i; 1505 uint32_t latch = 0, bork; 1506 int shift = 0; 1507 int reg = 0; 1508 1509 for (i=0;i<count;i++) { 1510 bork = data[i]; 1511 latch |= (bork << shift); 1512 if (shift == 24) { 1513 regw(sc, HOST_DATA0 + reg, latch); 1514 latch = 0; 1515 shift = 0; 1516 reg = (reg + 4) & 0x3c; 1517 } else 1518 shift += 8; 1519 } 1520 if (shift != 0) /* 24 */ 1521 regw(sc, HOST_DATA0 + reg, latch); 1522 } 1523 1524 1525 static void 1526 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1527 int colour) 1528 { 1529 wait_for_idle(sc); 1530 regw(sc, DP_WRITE_MASK, 0xff); 1531 regw(sc, DP_FRGD_CLR, colour); 1532 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1533 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1534 regw(sc, DP_MIX, MIX_SRC << 16); 1535 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1536 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1537 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1538 1539 regw(sc, SRC_Y_X, (x << 16) | y); 1540 regw(sc, SRC_WIDTH1, width); 1541 regw(sc, DST_Y_X, (x << 16) | y); 1542 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1543 } 1544 1545 static void 1546 mach64_clearscreen(struct mach64_softc *sc) 1547 { 1548 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1549 } 1550 1551 1552 #if 0 1553 static void 1554 mach64_showpal(struct mach64_softc *sc) 1555 { 1556 int i, x = 0; 1557 1558 for (i = 0; i < 16; i++) { 1559 mach64_rectfill(sc, x, 0, 64, 64, i); 1560 x += 64; 1561 } 1562 } 1563 #endif 1564 1565 static int 1566 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1567 { 1568 if ((fg == 0) && (bg == 0)) 1569 { 1570 fg = WS_DEFAULT_FG; 1571 bg = WS_DEFAULT_BG; 1572 } 1573 *attrp = (fg & 0xf) << 24 | (bg & 0xf) << 16 | (flags & 0xff) << 8; 1574 return 0; 1575 } 1576 1577 /* 1578 * wsdisplay_accessops 1579 */ 1580 1581 static int 1582 mach64_ioctl(void *v, void *vs, u_long cmd, caddr_t data, int flag, 1583 struct lwp *l) 1584 { 1585 struct vcons_data *vd = v; 1586 struct mach64_softc *sc = vd->cookie; 1587 struct wsdisplay_fbinfo *wdf; 1588 struct vcons_screen *ms = vd->active; 1589 1590 switch (cmd) { 1591 case WSDISPLAYIO_GTYPE: 1592 /* XXX is this the right type to return? */ 1593 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1594 return 0; 1595 1596 case WSDISPLAYIO_GINFO: 1597 wdf = (void *)data; 1598 wdf->height = sc->virt_y; 1599 wdf->width = sc->virt_x; 1600 wdf->depth = sc->color_depth; 1601 wdf->cmsize = 256; 1602 return 0; 1603 1604 case WSDISPLAYIO_GETCMAP: 1605 return mach64_getcmap(sc, 1606 (struct wsdisplay_cmap *)data); 1607 1608 case WSDISPLAYIO_PUTCMAP: 1609 return mach64_putcmap(sc, 1610 (struct wsdisplay_cmap *)data); 1611 1612 /* PCI config read/write passthrough. */ 1613 case PCI_IOC_CFGREAD: 1614 case PCI_IOC_CFGWRITE: 1615 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1616 cmd, data, flag, l)); 1617 1618 case WSDISPLAYIO_SMODE: 1619 { 1620 int new_mode = *(int*)data; 1621 1622 if (new_mode != sc->sc_mode) 1623 { 1624 sc->sc_mode = new_mode; 1625 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1626 && (ms != NULL)) 1627 { 1628 vcons_redraw_screen(ms); 1629 } 1630 } 1631 } 1632 return 0; 1633 1634 } 1635 return EPASSTHROUGH; 1636 } 1637 1638 static paddr_t 1639 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1640 { 1641 struct vcons_data *vd = v; 1642 struct mach64_softc *sc = vd->cookie; 1643 paddr_t pa; 1644 pcireg_t reg; 1645 1646 #ifndef __sparc64__ 1647 /* 1648 *'regular' framebuffer mmap()ing 1649 * disabled on sparc64 because some ATI firmware likes to map some PCI 1650 * resources to addresses that would collide with this ( like some Rage 1651 * IIc which uses 0x2000 for the 2nd register block ) 1652 * Other 64bit architectures might run into similar problems. 1653 */ 1654 if (offset<sc->sc_apersize) { 1655 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase+offset, 0, 1656 prot, BUS_SPACE_MAP_LINEAR); 1657 return pa; 1658 } 1659 #endif 1660 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1661 if (reg != sc->sc_regphys) { 1662 #ifdef DIAGNOSTIC 1663 printf("%s: BAR 0x18 changed! (%x %x)\n", 1664 sc->sc_dev.dv_xname, (uint32_t)sc->sc_regphys, 1665 (uint32_t)reg); 1666 #endif 1667 sc->sc_regphys = reg; 1668 } 1669 1670 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1671 if (reg != sc->sc_aperphys) { 1672 #ifdef DIAGNOSTIC 1673 printf("%s: BAR 0x10 changed! (%x %x)\n", 1674 sc->sc_dev.dv_xname, (uint32_t)sc->sc_aperphys, 1675 (uint32_t)reg); 1676 #endif 1677 sc->sc_aperphys = reg; 1678 } 1679 1680 #if 0 1681 /* evil hack to allow mmap()ing other devices as well */ 1682 if ((offset > 0x80000000) && (offset <= 0xffffffff)) { 1683 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1684 BUS_SPACE_MAP_LINEAR); 1685 return pa; 1686 } 1687 #endif 1688 1689 if ((offset >= sc->sc_aperphys) && 1690 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1691 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1692 BUS_SPACE_MAP_LINEAR); 1693 return pa; 1694 } 1695 1696 if ((offset >= sc->sc_regphys) && 1697 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1698 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1699 BUS_SPACE_MAP_LINEAR); 1700 return pa; 1701 } 1702 1703 return -1; 1704 } 1705 1706 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1707 static void 1708 set_address(struct rasops_info *ri, bus_addr_t fb) 1709 { 1710 #ifdef notdef 1711 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1712 #endif 1713 ri->ri_bits = (void *)((u_long)fb + ri->ri_stride * ri->ri_yorigin + 1714 ri->ri_xorigin); 1715 } 1716 1717 #if 0 1718 static int 1719 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1720 { 1721 1722 return 0; 1723 } 1724 #endif 1725 1726 void 1727 machfb_blank(struct mach64_softc *sc, int blank) 1728 { 1729 uint32_t reg; 1730 1731 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1732 1733 switch (blank) 1734 { 1735 case 0: 1736 reg = regr(sc, CRTC_GEN_CNTL); 1737 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1738 sc->sc_blanked = 0; 1739 break; 1740 case 1: 1741 reg = regr(sc, CRTC_GEN_CNTL); 1742 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1743 sc->sc_blanked = 1; 1744 break; 1745 default: 1746 break; 1747 } 1748 } 1749 1750 /* framebuffer device support */ 1751 #ifdef __sparc__ 1752 1753 static void 1754 machfb_unblank(struct device *dev) 1755 { 1756 struct mach64_softc *sc = (struct mach64_softc *)dev; 1757 1758 machfb_blank(sc, 0); 1759 } 1760 1761 static void 1762 machfb_fbattach(struct mach64_softc *sc) 1763 { 1764 struct fbdevice *fb = &sc->sc_fb; 1765 1766 fb->fb_device = &sc->sc_dev; 1767 fb->fb_driver = &machfb_fbdriver; 1768 1769 fb->fb_type.fb_cmsize = 256; 1770 fb->fb_type.fb_size = sc->memsize; 1771 1772 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1773 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags & FB_USERMASK; 1774 fb->fb_type.fb_depth = sc->bits_per_pixel; 1775 fb->fb_type.fb_width = sc->virt_x; 1776 fb->fb_type.fb_height = sc->virt_y; 1777 1778 fb->fb_pixels = (void *)sc->sc_aperbase; 1779 fb_attach(fb, sc->sc_console); 1780 } 1781 1782 int 1783 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1784 { 1785 struct mach64_softc *sc; 1786 int unit = minor(dev); 1787 1788 sc = machfb_cd.cd_devs[unit]; 1789 sc->sc_locked = 1; 1790 1791 #ifdef DEBUG_MACHFB 1792 printf("machfb_fbopen(%d)\n", unit); 1793 #endif 1794 if (unit > machfb_cd.cd_ndevs || machfb_cd.cd_devs[unit] == NULL) 1795 return ENXIO; 1796 return 0; 1797 } 1798 1799 int 1800 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1801 { 1802 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1803 1804 #ifdef DEBUG_MACHFB 1805 printf("machfb_fbclose()\n"); 1806 #endif 1807 mach64_init_engine(sc); 1808 mach64_init_lut(sc); 1809 sc->sc_locked = 0; 1810 return 0; 1811 } 1812 1813 int 1814 machfb_fbioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct lwp *l) 1815 { 1816 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1817 1818 #ifdef DEBUG_MACHFB 1819 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1820 #endif 1821 switch (cmd) { 1822 case FBIOGTYPE: 1823 *(struct fbtype *)data = sc->sc_fb.fb_type; 1824 break; 1825 1826 case FBIOGATTR: 1827 #define fba ((struct fbgattr *)data) 1828 fba->real_type = sc->sc_fb.fb_type.fb_type; 1829 fba->owner = 0; /* XXX ??? */ 1830 fba->fbtype = sc->sc_fb.fb_type; 1831 fba->sattr.flags = 0; 1832 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1833 fba->sattr.dev_specific[0] = sc->sc_nbus; 1834 fba->sattr.dev_specific[1] = sc->sc_ndev; 1835 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1836 fba->sattr.dev_specific[3] = -1; 1837 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1838 fba->emu_types[1] = -1; 1839 #undef fba 1840 break; 1841 1842 #if 0 1843 case FBIOGETCMAP: 1844 #define p ((struct fbcmap *)data) 1845 return (bt_getcmap(p, &sc->sc_cmap, 256, 1)); 1846 1847 case FBIOPUTCMAP: 1848 /* copy to software map */ 1849 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1850 if (error) 1851 return error; 1852 /* now blast them into the chip */ 1853 /* XXX should use retrace interrupt */ 1854 cg6_loadcmap(sc, p->index, p->count); 1855 #undef p 1856 break; 1857 #endif 1858 case FBIOGVIDEO: 1859 *(int *)data = sc->sc_blanked; 1860 break; 1861 1862 case FBIOSVIDEO: 1863 machfb_blank(sc, *(int *)data); 1864 break; 1865 1866 #if 0 1867 case FBIOGCURSOR: 1868 break; 1869 1870 case FBIOSCURSOR: 1871 break; 1872 1873 case FBIOGCURPOS: 1874 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 1875 break; 1876 1877 case FBIOSCURPOS: 1878 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 1879 break; 1880 1881 case FBIOGCURMAX: 1882 /* max cursor size is 32x32 */ 1883 ((struct fbcurpos *)data)->x = 32; 1884 ((struct fbcurpos *)data)->y = 32; 1885 break; 1886 #endif 1887 case PCI_IOC_CFGREAD: 1888 case PCI_IOC_CFGWRITE: 1889 { 1890 int ret; 1891 1892 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1893 cmd, data, flags, l); 1894 1895 #ifdef DEBUG_MACHFB 1896 printf("pci_devioctl: %d\n", ret); 1897 #endif 1898 return ret; 1899 } 1900 default: 1901 #ifdef DEBUG_MACHFB 1902 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 1903 p->p_comm, p->p_pid); 1904 #endif 1905 return ENOTTY; 1906 } 1907 #ifdef DEBUG_MACHFB 1908 printf("machfb_fbioctl done\n"); 1909 #endif 1910 return 0; 1911 } 1912 1913 paddr_t 1914 machfb_fbmmap(dev_t dev, off_t off, int prot) 1915 { 1916 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1917 1918 if (sc != NULL) 1919 return mach64_mmap(&sc->vd, NULL, off, prot); 1920 1921 return 0; 1922 } 1923 1924 #endif /* __sparc__ */ 1925
Indexes created Thu Oct 02 14:10:14 GMT 2025