machfb.c revision 1.42
1 /* $NetBSD: machfb.c,v 1.42 2006/04/15 17:48:23 jmmv Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, 36 "$NetBSD: machfb.c,v 1.42 2006/04/15 17:48:23 jmmv Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/callout.h> 44 45 #ifdef __sparc__ 46 #include <machine/promlib.h> 47 #endif 48 49 #ifdef __powerpc__ 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_pci.h> 52 #endif 53 54 #include <dev/videomode/videomode.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 #include <dev/pci/pciio.h> 60 #include <dev/pci/machfbreg.h> 61 62 #ifdef __sparc__ 63 #include <dev/sun/fbio.h> 64 #include <dev/sun/fbvar.h> 65 #include <sys/conf.h> 66 #else 67 #include <dev/wscons/wsdisplayvar.h> 68 #endif 69 70 #include <dev/wscons/wsconsio.h> 71 #include <dev/wsfont/wsfont.h> 72 #include <dev/rasops/rasops.h> 73 74 #include <dev/wscons/wsdisplay_vconsvar.h> 75 76 #define MACH64_REG_SIZE 1024 77 #define MACH64_REG_OFF 0x7ffc00 78 79 #define NBARS 3 /* number of Mach64 PCI BARs */ 80 81 struct vga_bar { 82 bus_addr_t vb_base; 83 pcireg_t vb_busaddr; 84 bus_size_t vb_size; 85 pcireg_t vb_type; 86 int vb_flags; 87 }; 88 89 struct mach64_softc { 90 struct device sc_dev; 91 #ifdef __sparc__ 92 struct fbdevice sc_fb; 93 #endif 94 pci_chipset_tag_t sc_pc; 95 pcitag_t sc_pcitag; 96 97 struct vga_bar sc_bars[NBARS]; 98 struct vga_bar sc_rom; 99 100 #define sc_aperbase sc_bars[0].vb_base 101 #define sc_apersize sc_bars[0].vb_size 102 #define sc_aperphys sc_bars[0].vb_busaddr 103 104 #define sc_iobase sc_bars[1].vb_base 105 #define sc_iosize sc_bars[1].vb_size 106 107 #define sc_regbase sc_bars[2].vb_base 108 #define sc_regsize sc_bars[2].vb_size 109 #define sc_regphys sc_bars[2].vb_busaddr 110 111 bus_space_tag_t sc_regt; 112 bus_space_tag_t sc_memt; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 uint32_t sc_nbus, sc_ndev, sc_nfunc; 116 size_t memsize; 117 int memtype; 118 119 int sc_mode; 120 int sc_bg; 121 int sc_locked; 122 123 int has_dsp; 124 int bits_per_pixel; 125 int max_x; 126 int max_y; 127 int virt_x; 128 int virt_y; 129 int color_depth; 130 131 int mem_freq; 132 int ramdac_freq; 133 int ref_freq; 134 135 int ref_div; 136 int log2_vclk_post_div; 137 int vclk_post_div; 138 int vclk_fb_div; 139 int mclk_post_div; 140 int mclk_fb_div; 141 142 struct videomode *sc_my_mode; 143 u_char sc_cmap_red[256]; 144 u_char sc_cmap_green[256]; 145 u_char sc_cmap_blue[256]; 146 int sc_dacw, sc_blanked, sc_console; 147 struct vcons_data vd; 148 }; 149 150 struct mach64_crtcregs { 151 uint32_t h_total_disp; 152 uint32_t h_sync_strt_wid; 153 uint32_t v_total_disp; 154 uint32_t v_sync_strt_wid; 155 uint32_t gen_cntl; 156 uint32_t clock_cntl; 157 uint32_t color_depth; 158 uint32_t dot_clock; 159 }; 160 161 struct { 162 uint16_t chip_id; 163 uint32_t ramdac_freq; 164 } static const mach64_info[] = { 165 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 166 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 167 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 168 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 169 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 174 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 175 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 185 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 186 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 187 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 188 }; 189 190 static int mach64_chip_id, mach64_chip_rev; 191 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 192 193 static const char *mach64_memtype_names[] = { 194 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 195 "(unknown type)" 196 }; 197 198 static struct videomode mach64_modes[] = { 199 /* 640x400 @ 70 Hz, 31.5 kHz */ 200 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 201 /* 640x480 @ 72 Hz, 36.5 kHz */ 202 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 203 /* 800x600 @ 72 Hz, 48.0 kHz */ 204 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 205 VID_PHSYNC | VID_PVSYNC }, 206 /* 1024x768 @ 70 Hz, 56.5 kHz */ 207 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 208 VID_NHSYNC | VID_NVSYNC }, 209 /* 1152x864 @ 70 Hz, 62.4 kHz */ 210 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 211 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 212 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 213 VID_NHSYNC | VID_NVSYNC } 214 }; 215 216 extern const u_char rasops_cmap[768]; 217 218 static int mach64_match(struct device *, struct cfdata *, void *); 219 static void mach64_attach(struct device *, struct device *, void *); 220 221 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 222 NULL, NULL); 223 224 static void mach64_init(struct mach64_softc *); 225 static int mach64_get_memsize(struct mach64_softc *); 226 static int mach64_get_max_ramdac(struct mach64_softc *); 227 228 #if defined(__sparc__) || defined(__powerpc__) 229 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 230 #endif 231 232 static int mach64_calc_crtcregs(struct mach64_softc *, 233 struct mach64_crtcregs *, 234 struct videomode *); 235 static void mach64_set_crtcregs(struct mach64_softc *, 236 struct mach64_crtcregs *); 237 238 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 239 static void mach64_set_dsp(struct mach64_softc *); 240 static void mach64_set_pll(struct mach64_softc *, int); 241 static void mach64_reset_engine(struct mach64_softc *); 242 static void mach64_init_engine(struct mach64_softc *); 243 #if 0 244 static void mach64_adjust_frame(struct mach64_softc *, int, int); 245 #endif 246 static void mach64_init_lut(struct mach64_softc *); 247 248 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 249 static int mach64_set_screentype(struct mach64_softc *, 250 const struct wsscreen_descr *); 251 static int mach64_is_console(struct pci_attach_args *); 252 253 static void mach64_cursor(void *, int, int, int); 254 #if 0 255 static int mach64_mapchar(void *, int, u_int *); 256 #endif 257 static void mach64_putchar(void *, int, int, u_int, long); 258 static void mach64_copycols(void *, int, int, int, int); 259 static void mach64_erasecols(void *, int, int, int, long); 260 static void mach64_copyrows(void *, int, int, int); 261 static void mach64_eraserows(void *, int, int, long); 262 static int mach64_allocattr(void *, int, int, int, long *); 263 static void mach64_clearscreen(struct mach64_softc *); 264 265 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 266 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 267 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 268 uint8_t, uint8_t); 269 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 270 int, int, int) ; 271 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 272 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 273 uint32_t, uint32_t); 274 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 275 #if 0 276 static void mach64_showpal(struct mach64_softc *); 277 #endif 278 279 static void set_address(struct rasops_info *, bus_addr_t); 280 static void machfb_blank(struct mach64_softc *, int); 281 282 #if 0 283 static const struct wsdisplay_emulops mach64_emulops = { 284 mach64_cursor, 285 mach64_mapchar, 286 mach64_putchar, 287 mach64_copycols, 288 mach64_erasecols, 289 mach64_copyrows, 290 mach64_eraserows, 291 mach64_allocattr, 292 }; 293 #endif 294 295 static struct wsscreen_descr mach64_defaultscreen = { 296 "default", 297 80, 30, 298 NULL, 299 8, 16, 300 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 301 &default_mode 302 }, mach64_80x25_screen = { 303 "80x25", 80, 25, 304 NULL, 305 8, 16, 306 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 307 &mach64_modes[0] 308 }, mach64_80x30_screen = { 309 "80x30", 80, 30, 310 NULL, 311 8, 16, 312 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 313 &mach64_modes[1] 314 }, mach64_80x40_screen = { 315 "80x40", 80, 40, 316 NULL, 317 8, 10, 318 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 319 &mach64_modes[0] 320 }, mach64_80x50_screen = { 321 "80x50", 80, 50, 322 NULL, 323 8, 8, 324 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 325 &mach64_modes[0] 326 }, mach64_100x37_screen = { 327 "100x37", 100, 37, 328 NULL, 329 8, 16, 330 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 331 &mach64_modes[2] 332 }, mach64_128x48_screen = { 333 "128x48", 128, 48, 334 NULL, 335 8, 16, 336 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 337 &mach64_modes[3] 338 }, mach64_144x54_screen = { 339 "144x54", 144, 54, 340 NULL, 341 8, 16, 342 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 343 &mach64_modes[4] 344 }, mach64_160x64_screen = { 345 "160x54", 160, 64, 346 NULL, 347 8, 16, 348 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 349 &mach64_modes[5] 350 }; 351 352 static const struct wsscreen_descr *_mach64_scrlist[] = { 353 &mach64_defaultscreen, 354 &mach64_80x25_screen, 355 &mach64_80x30_screen, 356 &mach64_80x40_screen, 357 &mach64_80x50_screen, 358 &mach64_100x37_screen, 359 &mach64_128x48_screen, 360 &mach64_144x54_screen, 361 &mach64_160x64_screen 362 }; 363 364 static struct wsscreen_list mach64_screenlist = { 365 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 366 _mach64_scrlist 367 }; 368 369 static int mach64_ioctl(void *, void *, u_long, caddr_t, int, 370 struct lwp *); 371 static paddr_t mach64_mmap(void *, void *, off_t, int); 372 373 #if 0 374 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 375 #endif 376 377 static struct wsdisplay_accessops mach64_accessops = { 378 mach64_ioctl, 379 mach64_mmap, 380 NULL, /* vcons_alloc_screen */ 381 NULL, /* vcons_free_screen */ 382 NULL, /* vcons_show_screen */ 383 NULL, /* load_font */ 384 NULL, /* polls */ 385 NULL, /* scroll */ 386 }; 387 388 static struct vcons_screen mach64_console_screen; 389 390 /* framebuffer device, SPARC-only so far */ 391 #ifdef __sparc__ 392 393 static void machfb_unblank(struct device *); 394 static void machfb_fbattach(struct mach64_softc *); 395 396 extern struct cfdriver machfb_cd; 397 398 dev_type_open(machfb_fbopen); 399 dev_type_close(machfb_fbclose); 400 dev_type_ioctl(machfb_fbioctl); 401 dev_type_mmap(machfb_fbmmap); 402 403 /* frame buffer generic driver */ 404 static struct fbdriver machfb_fbdriver = { 405 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 406 machfb_fbmmap, nokqfilter 407 }; 408 409 #endif /* __sparc__ */ 410 411 /* 412 * Inline functions for getting access to register aperture. 413 */ 414 415 static inline uint32_t 416 regr(struct mach64_softc *sc, uint32_t index) 417 { 418 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 419 } 420 421 static inline uint8_t 422 regrb(struct mach64_softc *sc, uint32_t index) 423 { 424 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 425 } 426 427 static inline void 428 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 429 { 430 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 431 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 432 BUS_SPACE_BARRIER_WRITE); 433 } 434 435 static inline void 436 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 437 { 438 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 439 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 440 BUS_SPACE_BARRIER_WRITE); 441 } 442 443 static inline void 444 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 445 { 446 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 447 regwb(sc, CLOCK_CNTL + 2, data); 448 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 449 } 450 451 static inline void 452 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 453 { 454 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 455 continue; 456 } 457 458 static inline void 459 wait_for_idle(struct mach64_softc *sc) 460 { 461 wait_for_fifo(sc, 16); 462 while ((regr(sc, GUI_STAT) & 1) != 0) 463 continue; 464 } 465 466 static int 467 mach64_match(struct device *parent, struct cfdata *match, void *aux) 468 { 469 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 470 int i; 471 472 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 473 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 474 return 0; 475 476 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 477 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 478 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 479 mach64_chip_rev = PCI_REVISION(pa->pa_class); 480 return 100; 481 } 482 483 return 0; 484 } 485 486 static void 487 mach64_attach(struct device *parent, struct device *self, void *aux) 488 { 489 struct mach64_softc *sc = (void *)self; 490 struct pci_attach_args *pa = aux; 491 struct rasops_info *ri; 492 char devinfo[256]; 493 int bar, reg, id; 494 struct wsemuldisplaydev_attach_args aa; 495 long defattr; 496 int setmode; 497 pcireg_t screg; 498 499 sc->sc_pc = pa->pa_pc; 500 sc->sc_pcitag = pa->pa_tag; 501 sc->sc_dacw = -1; 502 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 503 sc->sc_nbus = pa->pa_bus; 504 sc->sc_ndev = pa->pa_device; 505 sc->sc_nfunc = pa->pa_function; 506 sc->sc_locked = 0; 507 508 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 509 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 510 511 /* enable memory and IO access */ 512 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 513 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 514 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 515 516 for (bar = 0; bar < NBARS; bar++) { 517 reg = PCI_MAPREG_START + (bar * 4); 518 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 519 sc->sc_pcitag, reg); 520 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 521 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 522 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 523 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 524 sc->sc_pcitag, reg)&0xfffffff0; 525 } 526 sc->sc_memt = pa->pa_memt; 527 528 mach64_init(sc); 529 530 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 531 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 532 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 533 (u_int)sc->sc_regphys); 534 535 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 536 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 537 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 538 (mach64_chip_rev & 0x07) == 0)) 539 sc->has_dsp = 0; 540 else 541 sc->has_dsp = 1; 542 543 sc->memsize = mach64_get_memsize(sc); 544 if (sc->memsize == 8192) 545 /* The last page is used as register aperture. */ 546 sc->memsize -= 4; 547 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 548 549 /* XXX is there any way to calculate reference frequency from 550 known values? */ 551 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 552 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 553 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 554 printf("%s: ref_freq=29.498MHz\n", sc->sc_dev.dv_xname); 555 sc->ref_freq = 29498; 556 } else 557 sc->ref_freq = 14318; 558 559 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 560 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 561 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 562 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 563 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 564 (sc->ref_div * 2); 565 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 566 (sc->mem_freq * sc->ref_div); 567 sc->ramdac_freq = mach64_get_max_ramdac(sc); 568 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 569 sc->sc_dev.dv_xname, (u_long)sc->memsize, 570 mach64_memtype_names[sc->memtype], 571 sc->mem_freq / 1000, sc->mem_freq % 1000, 572 sc->ramdac_freq / 1000); 573 574 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 575 if (id != mach64_chip_id) { 576 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 577 sc->sc_dev.dv_xname, id, mach64_chip_id); 578 return; 579 } 580 581 sc->sc_console = mach64_is_console(pa); 582 #ifdef DIAGNOSTIC 583 printf("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 584 #endif 585 #if defined(__sparc__) || defined(__powerpc__) 586 if (sc->sc_console) { 587 mach64_get_mode(sc, &default_mode); 588 setmode = 0; 589 sc->sc_my_mode = &default_mode; 590 } else { 591 /* fill in default_mode if it's empty */ 592 mach64_get_mode(sc, &default_mode); 593 if (default_mode.dot_clock == 0) { 594 memcpy(&default_mode, &mach64_modes[4], 595 sizeof(default_mode)); 596 } 597 sc->sc_my_mode = &default_mode; 598 setmode = 1; 599 } 600 #else 601 if (default_mode.dot_clock == 0) { 602 memcpy(&default_mode, &mach64_modes[0], 603 sizeof(default_mode)); 604 } 605 sc->sc_my_mode = &mach64_modes[0]; 606 setmode = 1; 607 #endif 608 609 sc->bits_per_pixel = 8; 610 sc->virt_x = sc->sc_my_mode->hdisplay; 611 sc->virt_y = sc->sc_my_mode->vdisplay; 612 sc->max_x = sc->virt_x - 1; 613 sc->max_y = (sc->memsize * 1024) / 614 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 615 616 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 617 618 mach64_init_engine(sc); 619 #if 0 620 mach64_adjust_frame(0, 0); 621 if (sc->bits_per_pixel == 8) 622 mach64_init_lut(sc); 623 #endif 624 625 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 626 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 627 sc->bits_per_pixel); 628 629 #ifdef __sparc__ 630 machfb_fbattach(sc); 631 #endif 632 633 wsfont_init(); 634 635 sc->sc_bg = WS_DEFAULT_BG; 636 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 637 sc->vd.init_screen = mach64_init_screen; 638 639 if (sc->sc_console) { 640 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 641 &defattr); 642 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 643 644 ri = &mach64_console_screen.scr_ri; 645 mach64_defaultscreen.textops = &ri->ri_ops; 646 mach64_defaultscreen.capabilities = ri->ri_caps; 647 mach64_defaultscreen.nrows = ri->ri_rows; 648 mach64_defaultscreen.ncols = ri->ri_cols; 649 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 650 } else { 651 /* 652 * since we're not the console we can postpone the rest 653 * until someone actually allocates a screen for us 654 */ 655 mach64_modeswitch(sc, sc->sc_my_mode); 656 } 657 658 mach64_init_lut(sc); 659 mach64_clearscreen(sc); 660 machfb_blank(sc, 0); /* unblank the screen */ 661 662 aa.console = sc->sc_console; 663 aa.scrdata = &mach64_screenlist; 664 aa.accessops = &mach64_accessops; 665 aa.accesscookie = &sc->vd; 666 667 config_found(self, &aa, wsemuldisplaydevprint); 668 } 669 670 static void 671 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 672 long *defattr) 673 { 674 struct mach64_softc *sc = cookie; 675 struct rasops_info *ri = &scr->scr_ri; 676 677 /* XXX for now */ 678 #define setmode 0 679 680 ri->ri_depth = sc->bits_per_pixel; 681 ri->ri_width = sc->sc_my_mode->hdisplay; 682 ri->ri_height = sc->sc_my_mode->vdisplay; 683 ri->ri_stride = ri->ri_width; 684 ri->ri_flg = RI_CENTER; 685 set_address(ri, sc->sc_aperbase); 686 687 if (existing) { 688 ri->ri_flg |= RI_CLEAR; 689 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 690 panic("%s: failed to switch video mode", 691 sc->sc_dev.dv_xname); 692 } 693 } 694 695 rasops_init(ri, sc->sc_my_mode->vdisplay/8, 696 sc->sc_my_mode->hdisplay/8); 697 ri->ri_caps = WSSCREEN_WSCOLORS; 698 699 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 700 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 701 702 /* enable acceleration */ 703 ri->ri_hw = scr; 704 ri->ri_ops.copyrows = mach64_copyrows; 705 ri->ri_ops.copycols = mach64_copycols; 706 ri->ri_ops.eraserows = mach64_eraserows; 707 ri->ri_ops.erasecols = mach64_erasecols; 708 ri->ri_ops.cursor = mach64_cursor; 709 ri->ri_ops.putchar = mach64_putchar; 710 ri->ri_ops.allocattr = mach64_allocattr; 711 } 712 713 static void 714 mach64_init(struct mach64_softc *sc) 715 { 716 uint32_t *p32, saved_value; 717 uint8_t *p; 718 int need_swap; 719 720 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 721 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 722 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 723 } 724 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 725 726 sc->sc_regt = sc->sc_memt; 727 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 728 sc->sc_regsize, &sc->sc_regh); 729 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 730 731 /* 732 * Test wether the aperture is byte swapped or not 733 */ 734 p32 = (uint32_t*)(u_long)sc->sc_aperbase; 735 saved_value = *p32; 736 p = (uint8_t*)(u_long)sc->sc_aperbase; 737 *p32 = 0x12345678; 738 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 739 need_swap = 0; 740 else 741 need_swap = 1; 742 if (need_swap) { 743 sc->sc_aperbase += 0x800000; 744 sc->sc_apersize -= 0x800000; 745 } 746 *p32 = saved_value; 747 748 sc->sc_blanked = 0; 749 } 750 751 static int 752 mach64_get_memsize(struct mach64_softc *sc) 753 { 754 int tmp, memsize; 755 int mem_tab[] = { 756 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 757 }; 758 tmp = regr(sc, MEM_CNTL); 759 #ifdef DIAGNOSTIC 760 printf("%s: memctl %08x\n", sc->sc_dev.dv_xname, tmp); 761 #endif 762 if (sc->has_dsp) { 763 tmp &= 0x0000000f; 764 if (tmp < 8) 765 memsize = (tmp + 1) * 512; 766 else if (tmp < 12) 767 memsize = (tmp - 3) * 1024; 768 else 769 memsize = (tmp - 7) * 2048; 770 } else { 771 memsize = mem_tab[tmp & 0x07]; 772 } 773 774 return memsize; 775 } 776 777 static int 778 mach64_get_max_ramdac(struct mach64_softc *sc) 779 { 780 int i; 781 782 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 783 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 784 (mach64_chip_rev & 0x07)) 785 return 170000; 786 787 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 788 if (mach64_chip_id == mach64_info[i].chip_id) 789 return mach64_info[i].ramdac_freq; 790 791 if (sc->bits_per_pixel == 8) 792 return 135000; 793 else 794 return 80000; 795 } 796 797 #if defined(__sparc__) || defined(__powerpc__) 798 static void 799 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 800 { 801 struct mach64_crtcregs crtc; 802 803 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 804 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 805 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 806 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 807 808 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 809 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 810 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 811 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 812 mode->hsync_start; 813 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 814 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 815 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 816 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 817 818 #ifndef DEBUG_MACHFB 819 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 820 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 821 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 822 #endif 823 } 824 #endif 825 826 static int 827 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 828 struct videomode *mode) 829 { 830 831 if (mode->dot_clock > sc->ramdac_freq) 832 /* Clock too high. */ 833 return 1; 834 835 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 836 ((mode->htotal >> 3) - 1); 837 crtc->h_sync_strt_wid = 838 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 839 ((mode->hsync_start >> 3) - 1); 840 841 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 842 (mode->vtotal - 1); 843 crtc->v_sync_strt_wid = 844 ((mode->vsync_end - mode->vsync_start) << 16) | 845 (mode->vsync_start - 1); 846 847 if (mode->flags & VID_NVSYNC) 848 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 849 850 switch (sc->bits_per_pixel) { 851 case 8: 852 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 853 break; 854 case 16: 855 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 856 break; 857 case 32: 858 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 859 break; 860 } 861 862 crtc->gen_cntl = 0; 863 if (mode->flags & VID_INTERLACE) 864 crtc->gen_cntl |= CRTC_INTERLACE_EN; 865 866 if (mode->flags & VID_CSYNC) 867 crtc->gen_cntl |= CRTC_CSYNC_EN; 868 869 crtc->dot_clock = mode->dot_clock; 870 871 return 0; 872 } 873 874 static void 875 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 876 { 877 878 mach64_set_pll(sc, crtc->dot_clock); 879 880 if (sc->has_dsp) 881 mach64_set_dsp(sc); 882 883 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 884 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 885 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 886 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 887 888 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 889 890 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 891 892 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 893 /* XXX this unconditionally enables composite sync on SPARC */ 894 #ifdef __sparc__ 895 CRTC_CSYNC_EN | 896 #endif 897 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 898 } 899 900 static int 901 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 902 { 903 struct mach64_crtcregs crtc; 904 905 if (mach64_calc_crtcregs(sc, &crtc, mode)) 906 return 1; 907 908 mach64_set_crtcregs(sc, &crtc); 909 return 0; 910 } 911 912 static void 913 mach64_reset_engine(struct mach64_softc *sc) 914 { 915 916 /* Reset engine.*/ 917 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 918 919 /* Enable engine. */ 920 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 921 922 /* Ensure engine is not locked up by clearing any FIFO or 923 host errors. */ 924 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 925 BUS_FIFO_ERR_ACK); 926 } 927 928 static void 929 mach64_init_engine(struct mach64_softc *sc) 930 { 931 uint32_t pitch_value; 932 933 pitch_value = sc->virt_x; 934 935 if (sc->bits_per_pixel == 24) 936 pitch_value *= 3; 937 938 mach64_reset_engine(sc); 939 940 wait_for_fifo(sc, 14); 941 942 regw(sc, CONTEXT_MASK, 0xffffffff); 943 944 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 945 946 regw(sc, DST_Y_X, 0); 947 regw(sc, DST_HEIGHT, 0); 948 regw(sc, DST_BRES_ERR, 0); 949 regw(sc, DST_BRES_INC, 0); 950 regw(sc, DST_BRES_DEC, 0); 951 952 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 953 DST_Y_TOP_TO_BOTTOM); 954 955 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 956 957 regw(sc, SRC_Y_X, 0); 958 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 959 regw(sc, SRC_Y_X_START, 0); 960 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 961 962 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 963 964 wait_for_fifo(sc, 13); 965 regw(sc, HOST_CNTL, 0); 966 967 regw(sc, PAT_REG0, 0); 968 regw(sc, PAT_REG1, 0); 969 regw(sc, PAT_CNTL, 0); 970 971 regw(sc, SC_LEFT, 0); 972 regw(sc, SC_TOP, 0); 973 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 974 regw(sc, SC_RIGHT, pitch_value - 1); 975 976 regw(sc, DP_BKGD_CLR, 0); 977 regw(sc, DP_FRGD_CLR, 0xffffffff); 978 regw(sc, DP_WRITE_MASK, 0xffffffff); 979 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 980 981 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 982 983 wait_for_fifo(sc, 3); 984 regw(sc, CLR_CMP_CLR, 0); 985 regw(sc, CLR_CMP_MASK, 0xffffffff); 986 regw(sc, CLR_CMP_CNTL, 0); 987 988 wait_for_fifo(sc, 2); 989 switch (sc->bits_per_pixel) { 990 case 8: 991 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 992 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 993 /* We want 8 bit per channel */ 994 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 995 break; 996 #if 0 997 case 32: 998 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 999 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1000 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1001 break; 1002 #endif 1003 } 1004 1005 wait_for_fifo(sc, 5); 1006 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1007 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1008 1009 wait_for_idle(sc); 1010 } 1011 1012 #if 0 1013 static void 1014 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1015 { 1016 int offset; 1017 1018 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1019 1020 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1021 offset); 1022 } 1023 #endif 1024 1025 static void 1026 mach64_set_dsp(struct mach64_softc *sc) 1027 { 1028 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1029 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1030 uint32_t xclks_per_qw, y; 1031 uint32_t fifo_off, fifo_on; 1032 1033 printf("%s: initializing the DSP\n", sc->sc_dev.dv_xname); 1034 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1035 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1036 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1037 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1038 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1039 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1040 dsp_loop_latency = 0; 1041 fifo_depth = 24; 1042 } else { 1043 dsp_loop_latency = 2; 1044 fifo_depth = 32; 1045 } 1046 1047 dsp_precision = 0; 1048 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1049 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1050 y = (xclks_per_qw * fifo_depth) >> 11; 1051 while (y) { 1052 y >>= 1; 1053 dsp_precision++; 1054 } 1055 dsp_precision -= 5; 1056 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1057 1058 switch (sc->memtype) { 1059 case DRAM: 1060 case EDO_DRAM: 1061 case PSEUDO_EDO: 1062 if (sc->memsize > 1024) { 1063 page_size = 9; 1064 dsp_loop_latency += 6; 1065 } else { 1066 page_size = 10; 1067 if (sc->memtype == DRAM) 1068 dsp_loop_latency += 8; 1069 else 1070 dsp_loop_latency += 7; 1071 } 1072 break; 1073 case SDRAM: 1074 case SGRAM: 1075 if (sc->memsize > 1024) { 1076 page_size = 8; 1077 dsp_loop_latency += 8; 1078 } else { 1079 page_size = 10; 1080 dsp_loop_latency += 9; 1081 } 1082 break; 1083 default: 1084 page_size = 10; 1085 dsp_loop_latency += 9; 1086 break; 1087 } 1088 1089 if (xclks_per_qw >= (page_size << 11)) 1090 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1091 else 1092 fifo_on = (3 * page_size + 2) << 6; 1093 1094 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1095 dsp_on = fifo_on >> dsp_precision; 1096 dsp_off = fifo_off >> dsp_precision; 1097 1098 #ifdef DEBUG_MACHFB 1099 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1100 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1101 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1102 "mclk_post_div = %d, vclk_post_div = %d\n", 1103 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1104 sc->mclk_fb_div, sc->vclk_fb_div, 1105 sc->mclk_post_div, sc->vclk_post_div); 1106 #endif 1107 1108 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1109 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1110 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1111 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1112 } 1113 1114 static void 1115 mach64_set_pll(struct mach64_softc *sc, int clock) 1116 { 1117 int q; 1118 1119 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1120 #ifdef DEBUG_MACHFB 1121 printf("q = %d\n", q); 1122 #endif 1123 if (q > 25500) { 1124 printf("Warning: q > 25500\n"); 1125 q = 25500; 1126 sc->vclk_post_div = 1; 1127 sc->log2_vclk_post_div = 0; 1128 } else if (q > 12750) { 1129 sc->vclk_post_div = 1; 1130 sc->log2_vclk_post_div = 0; 1131 } else if (q > 6350) { 1132 sc->vclk_post_div = 2; 1133 sc->log2_vclk_post_div = 1; 1134 } else if (q > 3150) { 1135 sc->vclk_post_div = 4; 1136 sc->log2_vclk_post_div = 2; 1137 } else if (q >= 1600) { 1138 sc->vclk_post_div = 8; 1139 sc->log2_vclk_post_div = 3; 1140 } else { 1141 printf("Warning: q < 1600\n"); 1142 sc->vclk_post_div = 8; 1143 sc->log2_vclk_post_div = 3; 1144 } 1145 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1146 1147 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1148 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1149 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1150 } 1151 1152 static void 1153 mach64_init_lut(struct mach64_softc *sc) 1154 { 1155 int i, idx; 1156 1157 idx = 0; 1158 for (i = 0; i < 256; i++) { 1159 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1160 rasops_cmap[idx + 2]); 1161 idx += 3; 1162 } 1163 } 1164 1165 static int 1166 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1167 uint8_t b) 1168 { 1169 sc->sc_cmap_red[index] = r; 1170 sc->sc_cmap_green[index] = g; 1171 sc->sc_cmap_blue[index] = b; 1172 /* 1173 * writing the dac index takes a while, in theory we can poll some 1174 * register to see when it's ready - but we better avoid writing it 1175 * unnecessarily 1176 */ 1177 if (index != sc->sc_dacw) { 1178 regwb(sc, DAC_MASK, 0xff); 1179 regwb(sc, DAC_WINDEX, index); 1180 } 1181 sc->sc_dacw = index + 1; 1182 regwb(sc, DAC_DATA, r); 1183 regwb(sc, DAC_DATA, g); 1184 regwb(sc, DAC_DATA, b); 1185 return 0; 1186 } 1187 1188 static int 1189 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1190 { 1191 uint index = cm->index; 1192 uint count = cm->count; 1193 int i, error; 1194 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1195 uint8_t *r, *g, *b; 1196 1197 if (cm->index >= 256 || cm->count > 256 || 1198 (cm->index + cm->count) > 256) 1199 return EINVAL; 1200 error = copyin(cm->red, &rbuf[index], count); 1201 if (error) 1202 return error; 1203 error = copyin(cm->green, &gbuf[index], count); 1204 if (error) 1205 return error; 1206 error = copyin(cm->blue, &bbuf[index], count); 1207 if (error) 1208 return error; 1209 1210 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1211 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1212 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1213 1214 r = &sc->sc_cmap_red[index]; 1215 g = &sc->sc_cmap_green[index]; 1216 b = &sc->sc_cmap_blue[index]; 1217 1218 for (i = 0; i < count; i++) { 1219 mach64_putpalreg(sc, index, *r, *g, *b); 1220 index++; 1221 r++, g++, b++; 1222 } 1223 return 0; 1224 } 1225 1226 static int 1227 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1228 { 1229 u_int index = cm->index; 1230 u_int count = cm->count; 1231 int error; 1232 1233 if (index >= 255 || count > 256 || index + count > 256) 1234 return EINVAL; 1235 1236 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1237 if (error) 1238 return error; 1239 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1240 if (error) 1241 return error; 1242 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1243 if (error) 1244 return error; 1245 1246 return 0; 1247 } 1248 1249 static int 1250 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1251 { 1252 struct mach64_crtcregs regs; 1253 1254 if (mach64_calc_crtcregs(sc, ®s, 1255 (struct videomode *)des->modecookie)) 1256 return 1; 1257 1258 mach64_set_crtcregs(sc, ®s); 1259 return 0; 1260 } 1261 1262 static int 1263 mach64_is_console(struct pci_attach_args *pa) 1264 { 1265 #ifdef __sparc__ 1266 int node; 1267 1268 node = PCITAG_NODE(pa->pa_tag); 1269 if (node == -1) 1270 return 0; 1271 1272 return (node == prom_instance_to_package(prom_stdout())); 1273 #elif defined(__powerpc__) 1274 /* check if we're the /chosen console device */ 1275 int chosen, stdout, node, us; 1276 1277 us = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1278 chosen = OF_finddevice("/chosen"); 1279 OF_getprop(chosen, "stdout", &stdout, 4); 1280 node = OF_instance_to_package(stdout); 1281 return (us == node); 1282 #else 1283 return 1; 1284 #endif 1285 } 1286 1287 /* 1288 * wsdisplay_emulops 1289 */ 1290 1291 static void 1292 mach64_cursor(void *cookie, int on, int row, int col) 1293 { 1294 struct rasops_info *ri = cookie; 1295 struct vcons_screen *scr = ri->ri_hw; 1296 struct mach64_softc *sc = scr->scr_cookie; 1297 int x, y, wi, he; 1298 1299 wi = ri->ri_font->fontwidth; 1300 he = ri->ri_font->fontheight; 1301 1302 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1303 x = ri->ri_ccol * wi + ri->ri_xorigin; 1304 y = ri->ri_crow * he + ri->ri_yorigin; 1305 if (ri->ri_flg & RI_CURSOR) { 1306 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1307 0xff); 1308 ri->ri_flg &= ~RI_CURSOR; 1309 } 1310 ri->ri_crow = row; 1311 ri->ri_ccol = col; 1312 if (on) { 1313 x = ri->ri_ccol * wi + ri->ri_xorigin; 1314 y = ri->ri_crow * he + ri->ri_yorigin; 1315 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1316 0xff); 1317 ri->ri_flg |= RI_CURSOR;; 1318 } 1319 } else { 1320 scr->scr_ri.ri_crow = row; 1321 scr->scr_ri.ri_ccol = col; 1322 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1323 } 1324 } 1325 1326 #if 0 1327 static int 1328 mach64_mapchar(void *cookie, int uni, u_int *index) 1329 { 1330 return 0; 1331 } 1332 #endif 1333 1334 static void 1335 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1336 { 1337 struct rasops_info *ri = cookie; 1338 struct vcons_screen *scr = ri->ri_hw; 1339 struct mach64_softc *sc = scr->scr_cookie; 1340 1341 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1342 int fg, bg, uc; 1343 uint8_t *data; 1344 int x, y, wi, he; 1345 wi = ri->ri_font->fontwidth; 1346 he = ri->ri_font->fontheight; 1347 1348 if (!CHAR_IN_FONT(c, ri->ri_font)) 1349 return; 1350 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1351 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1352 x = ri->ri_xorigin + col * wi; 1353 y = ri->ri_yorigin + row * he; 1354 if (c == 0x20) { 1355 mach64_rectfill(sc, x, y, wi, he, bg); 1356 } else { 1357 uc = c-ri->ri_font->firstchar; 1358 data = (uint8_t *)ri->ri_font->data + uc * 1359 ri->ri_fontscale; 1360 1361 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1362 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1363 } 1364 } 1365 } 1366 1367 1368 static void 1369 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1370 { 1371 struct rasops_info *ri = cookie; 1372 struct vcons_screen *scr = ri->ri_hw; 1373 struct mach64_softc *sc = scr->scr_cookie; 1374 int32_t xs, xd, y, width, height; 1375 1376 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1377 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1378 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1379 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1380 width = ri->ri_font->fontwidth * ncols; 1381 height = ri->ri_font->fontheight; 1382 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1383 } 1384 } 1385 1386 static void 1387 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1388 { 1389 struct rasops_info *ri = cookie; 1390 struct vcons_screen *scr = ri->ri_hw; 1391 struct mach64_softc *sc = scr->scr_cookie; 1392 int32_t x, y, width, height, fg, bg, ul; 1393 1394 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1395 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1396 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1397 width = ri->ri_font->fontwidth * ncols; 1398 height = ri->ri_font->fontheight; 1399 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1400 1401 mach64_rectfill(sc, x, y, width, height, bg); 1402 } 1403 } 1404 1405 static void 1406 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1407 { 1408 struct rasops_info *ri = cookie; 1409 struct vcons_screen *scr = ri->ri_hw; 1410 struct mach64_softc *sc = scr->scr_cookie; 1411 int32_t x, ys, yd, width, height; 1412 1413 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1414 x = ri->ri_xorigin; 1415 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1416 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1417 width = ri->ri_emuwidth; 1418 height = ri->ri_font->fontheight*nrows; 1419 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1420 } 1421 } 1422 1423 static void 1424 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1425 { 1426 struct rasops_info *ri = cookie; 1427 struct vcons_screen *scr = ri->ri_hw; 1428 struct mach64_softc *sc = scr->scr_cookie; 1429 int32_t x, y, width, height, fg, bg, ul; 1430 1431 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1432 x = ri->ri_xorigin; 1433 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1434 width = ri->ri_emuwidth; 1435 height = ri->ri_font->fontheight * nrows; 1436 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1437 1438 mach64_rectfill(sc, x, y, width, height, bg); 1439 } 1440 } 1441 1442 static void 1443 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1444 { 1445 uint32_t dest_ctl = 0; 1446 1447 wait_for_idle(sc); 1448 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1449 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1450 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1451 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1452 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1453 if (yd < ys) { 1454 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1455 } else { 1456 ys += height - 1; 1457 yd += height - 1; 1458 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1459 } 1460 if (xd < xs) { 1461 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1462 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1463 } else { 1464 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1465 xs += width - 1; 1466 xd += width - 1; 1467 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1468 } 1469 regw(sc, DST_CNTL, dest_ctl); 1470 1471 regw(sc, SRC_Y_X, (xs << 16) | ys); 1472 regw(sc, SRC_WIDTH1, width); 1473 regw(sc, DST_Y_X, (xd << 16) | yd); 1474 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1475 } 1476 1477 static void 1478 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1479 int height, uint32_t fg, uint32_t bg) 1480 { 1481 wait_for_idle(sc); 1482 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1483 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1484 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1485 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1486 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1487 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1488 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1489 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1490 regw(sc, DP_BKGD_CLR, bg); 1491 regw(sc, DP_FRGD_CLR, fg); 1492 regw(sc, SRC_Y_X, 0); 1493 regw(sc, SRC_WIDTH1, width); 1494 regw(sc, DST_Y_X, (xd << 16) | yd); 1495 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1496 /* now feed the data into the chip */ 1497 } 1498 1499 static void 1500 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1501 { 1502 int i; 1503 uint32_t latch = 0, bork; 1504 int shift = 0; 1505 int reg = 0; 1506 1507 for (i=0;i<count;i++) { 1508 bork = data[i]; 1509 latch |= (bork << shift); 1510 if (shift == 24) { 1511 regw(sc, HOST_DATA0 + reg, latch); 1512 latch = 0; 1513 shift = 0; 1514 reg = (reg + 4) & 0x3c; 1515 } else 1516 shift += 8; 1517 } 1518 if (shift != 0) /* 24 */ 1519 regw(sc, HOST_DATA0 + reg, latch); 1520 } 1521 1522 1523 static void 1524 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1525 int colour) 1526 { 1527 wait_for_idle(sc); 1528 regw(sc, DP_WRITE_MASK, 0xff); 1529 regw(sc, DP_FRGD_CLR, colour); 1530 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1531 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1532 regw(sc, DP_MIX, MIX_SRC << 16); 1533 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1534 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1535 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1536 1537 regw(sc, SRC_Y_X, (x << 16) | y); 1538 regw(sc, SRC_WIDTH1, width); 1539 regw(sc, DST_Y_X, (x << 16) | y); 1540 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1541 } 1542 1543 static void 1544 mach64_clearscreen(struct mach64_softc *sc) 1545 { 1546 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1547 } 1548 1549 1550 #if 0 1551 static void 1552 mach64_showpal(struct mach64_softc *sc) 1553 { 1554 int i, x = 0; 1555 1556 for (i = 0; i < 16; i++) { 1557 mach64_rectfill(sc, x, 0, 64, 64, i); 1558 x += 64; 1559 } 1560 } 1561 #endif 1562 1563 static int 1564 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1565 { 1566 if ((fg == 0) && (bg == 0)) 1567 { 1568 fg = WS_DEFAULT_FG; 1569 bg = WS_DEFAULT_BG; 1570 } 1571 *attrp = (fg & 0xf) << 24 | (bg & 0xf) << 16 | (flags & 0xff) << 8; 1572 return 0; 1573 } 1574 1575 /* 1576 * wsdisplay_accessops 1577 */ 1578 1579 static int 1580 mach64_ioctl(void *v, void *vs, u_long cmd, caddr_t data, int flag, 1581 struct lwp *l) 1582 { 1583 struct vcons_data *vd = v; 1584 struct mach64_softc *sc = vd->cookie; 1585 struct wsdisplay_fbinfo *wdf; 1586 struct vcons_screen *ms = vd->active; 1587 1588 switch (cmd) { 1589 case WSDISPLAYIO_GTYPE: 1590 /* XXX is this the right type to return? */ 1591 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1592 return 0; 1593 1594 case WSDISPLAYIO_GINFO: 1595 wdf = (void *)data; 1596 wdf->height = sc->virt_y; 1597 wdf->width = sc->virt_x; 1598 wdf->depth = sc->color_depth; 1599 wdf->cmsize = 256; 1600 return 0; 1601 1602 case WSDISPLAYIO_GETCMAP: 1603 return mach64_getcmap(sc, 1604 (struct wsdisplay_cmap *)data); 1605 1606 case WSDISPLAYIO_PUTCMAP: 1607 return mach64_putcmap(sc, 1608 (struct wsdisplay_cmap *)data); 1609 1610 /* PCI config read/write passthrough. */ 1611 case PCI_IOC_CFGREAD: 1612 case PCI_IOC_CFGWRITE: 1613 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1614 cmd, data, flag, l)); 1615 1616 case WSDISPLAYIO_SMODE: 1617 { 1618 int new_mode = *(int*)data; 1619 1620 if (new_mode != sc->sc_mode) 1621 { 1622 sc->sc_mode = new_mode; 1623 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1624 && (ms != NULL)) 1625 { 1626 vcons_redraw_screen(ms); 1627 } 1628 } 1629 } 1630 return 0; 1631 1632 } 1633 return EPASSTHROUGH; 1634 } 1635 1636 static paddr_t 1637 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1638 { 1639 struct vcons_data *vd = v; 1640 struct mach64_softc *sc = vd->cookie; 1641 paddr_t pa; 1642 pcireg_t reg; 1643 1644 #ifndef __sparc64__ 1645 /* 1646 *'regular' framebuffer mmap()ing 1647 * disabled on sparc64 because some ATI firmware likes to map some PCI 1648 * resources to addresses that would collide with this ( like some Rage 1649 * IIc which uses 0x2000 for the 2nd register block ) 1650 * Other 64bit architectures might run into similar problems. 1651 */ 1652 if (offset<sc->sc_apersize) { 1653 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase+offset, 0, 1654 prot, BUS_SPACE_MAP_LINEAR); 1655 return pa; 1656 } 1657 #endif 1658 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1659 if (reg != sc->sc_regphys) { 1660 #ifdef DIAGNOSTIC 1661 printf("%s: BAR 0x18 changed! (%x %x)\n", 1662 sc->sc_dev.dv_xname, (uint32_t)sc->sc_regphys, 1663 (uint32_t)reg); 1664 #endif 1665 sc->sc_regphys = reg; 1666 } 1667 1668 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1669 if (reg != sc->sc_aperphys) { 1670 #ifdef DIAGNOSTIC 1671 printf("%s: BAR 0x10 changed! (%x %x)\n", 1672 sc->sc_dev.dv_xname, (uint32_t)sc->sc_aperphys, 1673 (uint32_t)reg); 1674 #endif 1675 sc->sc_aperphys = reg; 1676 } 1677 1678 #if 0 1679 /* evil hack to allow mmap()ing other devices as well */ 1680 if ((offset > 0x80000000) && (offset <= 0xffffffff)) { 1681 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1682 BUS_SPACE_MAP_LINEAR); 1683 return pa; 1684 } 1685 #endif 1686 1687 if ((offset >= sc->sc_aperphys) && 1688 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1689 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1690 BUS_SPACE_MAP_LINEAR); 1691 return pa; 1692 } 1693 1694 if ((offset >= sc->sc_regphys) && 1695 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1696 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1697 BUS_SPACE_MAP_LINEAR); 1698 return pa; 1699 } 1700 1701 return -1; 1702 } 1703 1704 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1705 static void 1706 set_address(struct rasops_info *ri, bus_addr_t fb) 1707 { 1708 #ifdef notdef 1709 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1710 #endif 1711 ri->ri_bits = (void *)((u_long)fb + ri->ri_stride * ri->ri_yorigin + 1712 ri->ri_xorigin); 1713 } 1714 1715 #if 0 1716 static int 1717 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1718 { 1719 1720 return 0; 1721 } 1722 #endif 1723 1724 void 1725 machfb_blank(struct mach64_softc *sc, int blank) 1726 { 1727 uint32_t reg; 1728 1729 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1730 1731 switch (blank) 1732 { 1733 case 0: 1734 reg = regr(sc, CRTC_GEN_CNTL); 1735 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1736 sc->sc_blanked = 0; 1737 break; 1738 case 1: 1739 reg = regr(sc, CRTC_GEN_CNTL); 1740 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1741 sc->sc_blanked = 1; 1742 break; 1743 default: 1744 break; 1745 } 1746 } 1747 1748 /* framebuffer device support */ 1749 #ifdef __sparc__ 1750 1751 static void 1752 machfb_unblank(struct device *dev) 1753 { 1754 struct mach64_softc *sc = (struct mach64_softc *)dev; 1755 1756 machfb_blank(sc, 0); 1757 } 1758 1759 static void 1760 machfb_fbattach(struct mach64_softc *sc) 1761 { 1762 struct fbdevice *fb = &sc->sc_fb; 1763 1764 fb->fb_device = &sc->sc_dev; 1765 fb->fb_driver = &machfb_fbdriver; 1766 1767 fb->fb_type.fb_cmsize = 256; 1768 fb->fb_type.fb_size = sc->memsize; 1769 1770 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1771 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags & FB_USERMASK; 1772 fb->fb_type.fb_depth = sc->bits_per_pixel; 1773 fb->fb_type.fb_width = sc->virt_x; 1774 fb->fb_type.fb_height = sc->virt_y; 1775 1776 fb->fb_pixels = (void *)sc->sc_aperbase; 1777 fb_attach(fb, sc->sc_console); 1778 } 1779 1780 int 1781 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1782 { 1783 struct mach64_softc *sc; 1784 int unit = minor(dev); 1785 1786 sc = machfb_cd.cd_devs[unit]; 1787 sc->sc_locked = 1; 1788 1789 #ifdef DEBUG_MACHFB 1790 printf("machfb_fbopen(%d)\n", unit); 1791 #endif 1792 if (unit > machfb_cd.cd_ndevs || machfb_cd.cd_devs[unit] == NULL) 1793 return ENXIO; 1794 return 0; 1795 } 1796 1797 int 1798 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1799 { 1800 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1801 1802 #ifdef DEBUG_MACHFB 1803 printf("machfb_fbclose()\n"); 1804 #endif 1805 mach64_init_engine(sc); 1806 mach64_init_lut(sc); 1807 sc->sc_locked = 0; 1808 return 0; 1809 } 1810 1811 int 1812 machfb_fbioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct lwp *l) 1813 { 1814 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1815 1816 #ifdef DEBUG_MACHFB 1817 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1818 #endif 1819 switch (cmd) { 1820 case FBIOGTYPE: 1821 *(struct fbtype *)data = sc->sc_fb.fb_type; 1822 break; 1823 1824 case FBIOGATTR: 1825 #define fba ((struct fbgattr *)data) 1826 fba->real_type = sc->sc_fb.fb_type.fb_type; 1827 fba->owner = 0; /* XXX ??? */ 1828 fba->fbtype = sc->sc_fb.fb_type; 1829 fba->sattr.flags = 0; 1830 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1831 fba->sattr.dev_specific[0] = sc->sc_nbus; 1832 fba->sattr.dev_specific[1] = sc->sc_ndev; 1833 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1834 fba->sattr.dev_specific[3] = -1; 1835 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1836 fba->emu_types[1] = -1; 1837 #undef fba 1838 break; 1839 1840 #if 0 1841 case FBIOGETCMAP: 1842 #define p ((struct fbcmap *)data) 1843 return (bt_getcmap(p, &sc->sc_cmap, 256, 1)); 1844 1845 case FBIOPUTCMAP: 1846 /* copy to software map */ 1847 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1848 if (error) 1849 return error; 1850 /* now blast them into the chip */ 1851 /* XXX should use retrace interrupt */ 1852 cg6_loadcmap(sc, p->index, p->count); 1853 #undef p 1854 break; 1855 #endif 1856 case FBIOGVIDEO: 1857 *(int *)data = sc->sc_blanked; 1858 break; 1859 1860 case FBIOSVIDEO: 1861 machfb_blank(sc, *(int *)data); 1862 break; 1863 1864 #if 0 1865 case FBIOGCURSOR: 1866 break; 1867 1868 case FBIOSCURSOR: 1869 break; 1870 1871 case FBIOGCURPOS: 1872 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 1873 break; 1874 1875 case FBIOSCURPOS: 1876 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 1877 break; 1878 1879 case FBIOGCURMAX: 1880 /* max cursor size is 32x32 */ 1881 ((struct fbcurpos *)data)->x = 32; 1882 ((struct fbcurpos *)data)->y = 32; 1883 break; 1884 #endif 1885 case PCI_IOC_CFGREAD: 1886 case PCI_IOC_CFGWRITE: 1887 { 1888 int ret; 1889 1890 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1891 cmd, data, flags, l); 1892 1893 #ifdef DEBUG_MACHFB 1894 printf("pci_devioctl: %d\n", ret); 1895 #endif 1896 return ret; 1897 } 1898 default: 1899 #ifdef DEBUG_MACHFB 1900 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 1901 p->p_comm, p->p_pid); 1902 #endif 1903 return ENOTTY; 1904 } 1905 #ifdef DEBUG_MACHFB 1906 printf("machfb_fbioctl done\n"); 1907 #endif 1908 return 0; 1909 } 1910 1911 paddr_t 1912 machfb_fbmmap(dev_t dev, off_t off, int prot) 1913 { 1914 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1915 1916 if (sc != NULL) 1917 return mach64_mmap(&sc->vd, NULL, off, prot); 1918 1919 return 0; 1920 } 1921 1922 #endif /* __sparc__ */ 1923
Indexes created Thu Oct 02 14:10:14 GMT 2025