machfb.c revision 1.44
1 /* $NetBSD: machfb.c,v 1.44 2006/04/19 17:41:24 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, 36 "$NetBSD: machfb.c,v 1.44 2006/04/19 17:41:24 macallan Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/callout.h> 44 45 #ifdef __sparc__ 46 #include <machine/promlib.h> 47 #endif 48 49 #ifdef __powerpc__ 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_pci.h> 52 #endif 53 54 #include <dev/videomode/videomode.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 #include <dev/pci/pciio.h> 60 #include <dev/pci/machfbreg.h> 61 62 #ifdef __sparc__ 63 #include <dev/sun/fbio.h> 64 #include <dev/sun/fbvar.h> 65 #include <sys/conf.h> 66 #else 67 #include <dev/wscons/wsdisplayvar.h> 68 #endif 69 70 #include <dev/wscons/wsconsio.h> 71 #include <dev/wsfont/wsfont.h> 72 #include <dev/rasops/rasops.h> 73 74 #include <dev/wscons/wsdisplay_vconsvar.h> 75 76 #define MACH64_REG_SIZE 1024 77 #define MACH64_REG_OFF 0x7ffc00 78 79 #define NBARS 3 /* number of Mach64 PCI BARs */ 80 81 struct vga_bar { 82 bus_addr_t vb_base; 83 pcireg_t vb_busaddr; 84 bus_size_t vb_size; 85 pcireg_t vb_type; 86 int vb_flags; 87 }; 88 89 struct mach64_softc { 90 struct device sc_dev; 91 #ifdef __sparc__ 92 struct fbdevice sc_fb; 93 #endif 94 pci_chipset_tag_t sc_pc; 95 pcitag_t sc_pcitag; 96 97 struct vga_bar sc_bars[NBARS]; 98 struct vga_bar sc_rom; 99 100 #define sc_aperbase sc_bars[0].vb_base 101 #define sc_apersize sc_bars[0].vb_size 102 #define sc_aperphys sc_bars[0].vb_busaddr 103 104 #define sc_iobase sc_bars[1].vb_base 105 #define sc_iosize sc_bars[1].vb_size 106 107 #define sc_regbase sc_bars[2].vb_base 108 #define sc_regsize sc_bars[2].vb_size 109 #define sc_regphys sc_bars[2].vb_busaddr 110 111 bus_space_tag_t sc_regt; 112 bus_space_tag_t sc_memt; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 caddr_t sc_aperture; /* mapped aperture vaddr */ 116 caddr_t sc_registers; /* mapped registers vaddr */ 117 118 uint32_t sc_nbus, sc_ndev, sc_nfunc; 119 size_t memsize; 120 int memtype; 121 122 int sc_mode; 123 int sc_bg; 124 int sc_locked; 125 126 int has_dsp; 127 int bits_per_pixel; 128 int max_x; 129 int max_y; 130 int virt_x; 131 int virt_y; 132 int color_depth; 133 134 int mem_freq; 135 int ramdac_freq; 136 int ref_freq; 137 138 int ref_div; 139 int log2_vclk_post_div; 140 int vclk_post_div; 141 int vclk_fb_div; 142 int mclk_post_div; 143 int mclk_fb_div; 144 145 struct videomode *sc_my_mode; 146 u_char sc_cmap_red[256]; 147 u_char sc_cmap_green[256]; 148 u_char sc_cmap_blue[256]; 149 int sc_dacw, sc_blanked, sc_console; 150 struct vcons_data vd; 151 }; 152 153 struct mach64_crtcregs { 154 uint32_t h_total_disp; 155 uint32_t h_sync_strt_wid; 156 uint32_t v_total_disp; 157 uint32_t v_sync_strt_wid; 158 uint32_t gen_cntl; 159 uint32_t clock_cntl; 160 uint32_t color_depth; 161 uint32_t dot_clock; 162 }; 163 164 struct { 165 uint16_t chip_id; 166 uint32_t ramdac_freq; 167 } static const mach64_info[] = { 168 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 169 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 177 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 178 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 188 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 189 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 190 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 191 }; 192 193 static int mach64_chip_id, mach64_chip_rev; 194 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 195 196 static const char *mach64_memtype_names[] = { 197 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 198 "(unknown type)" 199 }; 200 201 static struct videomode mach64_modes[] = { 202 /* 640x400 @ 70 Hz, 31.5 kHz */ 203 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 204 /* 640x480 @ 72 Hz, 36.5 kHz */ 205 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 206 /* 800x600 @ 72 Hz, 48.0 kHz */ 207 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 208 VID_PHSYNC | VID_PVSYNC }, 209 /* 1024x768 @ 70 Hz, 56.5 kHz */ 210 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 211 VID_NHSYNC | VID_NVSYNC }, 212 /* 1152x864 @ 70 Hz, 62.4 kHz */ 213 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 214 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 215 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 216 VID_NHSYNC | VID_NVSYNC } 217 }; 218 219 extern const u_char rasops_cmap[768]; 220 221 static int mach64_match(struct device *, struct cfdata *, void *); 222 static void mach64_attach(struct device *, struct device *, void *); 223 224 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 225 NULL, NULL); 226 227 static void mach64_init(struct mach64_softc *); 228 static int mach64_get_memsize(struct mach64_softc *); 229 static int mach64_get_max_ramdac(struct mach64_softc *); 230 231 #if defined(__sparc__) || defined(__powerpc__) 232 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 233 #endif 234 235 static int mach64_calc_crtcregs(struct mach64_softc *, 236 struct mach64_crtcregs *, 237 struct videomode *); 238 static void mach64_set_crtcregs(struct mach64_softc *, 239 struct mach64_crtcregs *); 240 241 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 242 static void mach64_set_dsp(struct mach64_softc *); 243 static void mach64_set_pll(struct mach64_softc *, int); 244 static void mach64_reset_engine(struct mach64_softc *); 245 static void mach64_init_engine(struct mach64_softc *); 246 #if 0 247 static void mach64_adjust_frame(struct mach64_softc *, int, int); 248 #endif 249 static void mach64_init_lut(struct mach64_softc *); 250 251 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 252 static int mach64_set_screentype(struct mach64_softc *, 253 const struct wsscreen_descr *); 254 static int mach64_is_console(struct pci_attach_args *); 255 256 static void mach64_cursor(void *, int, int, int); 257 #if 0 258 static int mach64_mapchar(void *, int, u_int *); 259 #endif 260 static void mach64_putchar(void *, int, int, u_int, long); 261 static void mach64_copycols(void *, int, int, int, int); 262 static void mach64_erasecols(void *, int, int, int, long); 263 static void mach64_copyrows(void *, int, int, int); 264 static void mach64_eraserows(void *, int, int, long); 265 static int mach64_allocattr(void *, int, int, int, long *); 266 static void mach64_clearscreen(struct mach64_softc *); 267 268 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 269 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 270 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 271 uint8_t, uint8_t); 272 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 273 int, int, int) ; 274 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 275 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 276 uint32_t, uint32_t); 277 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 278 #if 0 279 static void mach64_showpal(struct mach64_softc *); 280 #endif 281 282 static void set_address(struct rasops_info *, caddr_t); 283 static void machfb_blank(struct mach64_softc *, int); 284 285 #if 0 286 static const struct wsdisplay_emulops mach64_emulops = { 287 mach64_cursor, 288 mach64_mapchar, 289 mach64_putchar, 290 mach64_copycols, 291 mach64_erasecols, 292 mach64_copyrows, 293 mach64_eraserows, 294 mach64_allocattr, 295 }; 296 #endif 297 298 static struct wsscreen_descr mach64_defaultscreen = { 299 "default", 300 80, 30, 301 NULL, 302 8, 16, 303 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 304 &default_mode 305 }, mach64_80x25_screen = { 306 "80x25", 80, 25, 307 NULL, 308 8, 16, 309 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 310 &mach64_modes[0] 311 }, mach64_80x30_screen = { 312 "80x30", 80, 30, 313 NULL, 314 8, 16, 315 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 316 &mach64_modes[1] 317 }, mach64_80x40_screen = { 318 "80x40", 80, 40, 319 NULL, 320 8, 10, 321 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 322 &mach64_modes[0] 323 }, mach64_80x50_screen = { 324 "80x50", 80, 50, 325 NULL, 326 8, 8, 327 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 328 &mach64_modes[0] 329 }, mach64_100x37_screen = { 330 "100x37", 100, 37, 331 NULL, 332 8, 16, 333 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 334 &mach64_modes[2] 335 }, mach64_128x48_screen = { 336 "128x48", 128, 48, 337 NULL, 338 8, 16, 339 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 340 &mach64_modes[3] 341 }, mach64_144x54_screen = { 342 "144x54", 144, 54, 343 NULL, 344 8, 16, 345 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 346 &mach64_modes[4] 347 }, mach64_160x64_screen = { 348 "160x54", 160, 64, 349 NULL, 350 8, 16, 351 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 352 &mach64_modes[5] 353 }; 354 355 static const struct wsscreen_descr *_mach64_scrlist[] = { 356 &mach64_defaultscreen, 357 &mach64_80x25_screen, 358 &mach64_80x30_screen, 359 &mach64_80x40_screen, 360 &mach64_80x50_screen, 361 &mach64_100x37_screen, 362 &mach64_128x48_screen, 363 &mach64_144x54_screen, 364 &mach64_160x64_screen 365 }; 366 367 static struct wsscreen_list mach64_screenlist = { 368 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 369 _mach64_scrlist 370 }; 371 372 static int mach64_ioctl(void *, void *, u_long, caddr_t, int, 373 struct lwp *); 374 static paddr_t mach64_mmap(void *, void *, off_t, int); 375 376 #if 0 377 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 378 #endif 379 380 static struct wsdisplay_accessops mach64_accessops = { 381 mach64_ioctl, 382 mach64_mmap, 383 NULL, /* vcons_alloc_screen */ 384 NULL, /* vcons_free_screen */ 385 NULL, /* vcons_show_screen */ 386 NULL, /* load_font */ 387 NULL, /* polls */ 388 NULL, /* scroll */ 389 }; 390 391 static struct vcons_screen mach64_console_screen; 392 393 /* framebuffer device, SPARC-only so far */ 394 #ifdef __sparc__ 395 396 static void machfb_unblank(struct device *); 397 static void machfb_fbattach(struct mach64_softc *); 398 399 extern struct cfdriver machfb_cd; 400 401 dev_type_open(machfb_fbopen); 402 dev_type_close(machfb_fbclose); 403 dev_type_ioctl(machfb_fbioctl); 404 dev_type_mmap(machfb_fbmmap); 405 406 /* frame buffer generic driver */ 407 static struct fbdriver machfb_fbdriver = { 408 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 409 machfb_fbmmap, nokqfilter 410 }; 411 412 #endif /* __sparc__ */ 413 414 /* 415 * Inline functions for getting access to register aperture. 416 */ 417 418 static inline uint32_t 419 regr(struct mach64_softc *sc, uint32_t index) 420 { 421 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 422 } 423 424 static inline uint8_t 425 regrb(struct mach64_softc *sc, uint32_t index) 426 { 427 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 428 } 429 430 static inline void 431 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 432 { 433 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 434 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 435 BUS_SPACE_BARRIER_WRITE); 436 } 437 438 static inline void 439 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 440 { 441 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 442 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 443 BUS_SPACE_BARRIER_WRITE); 444 } 445 446 static inline void 447 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 448 { 449 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 450 regwb(sc, CLOCK_CNTL + 2, data); 451 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 452 } 453 454 static inline void 455 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 456 { 457 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 458 continue; 459 } 460 461 static inline void 462 wait_for_idle(struct mach64_softc *sc) 463 { 464 wait_for_fifo(sc, 16); 465 while ((regr(sc, GUI_STAT) & 1) != 0) 466 continue; 467 } 468 469 static int 470 mach64_match(struct device *parent, struct cfdata *match, void *aux) 471 { 472 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 473 int i; 474 475 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 476 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 477 return 0; 478 479 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 480 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 481 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 482 mach64_chip_rev = PCI_REVISION(pa->pa_class); 483 return 100; 484 } 485 486 return 0; 487 } 488 489 static void 490 mach64_attach(struct device *parent, struct device *self, void *aux) 491 { 492 struct mach64_softc *sc = (void *)self; 493 struct pci_attach_args *pa = aux; 494 struct rasops_info *ri; 495 char devinfo[256]; 496 int bar, reg, id; 497 struct wsemuldisplaydev_attach_args aa; 498 long defattr; 499 int setmode; 500 pcireg_t screg; 501 502 sc->sc_pc = pa->pa_pc; 503 sc->sc_pcitag = pa->pa_tag; 504 sc->sc_dacw = -1; 505 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 506 sc->sc_nbus = pa->pa_bus; 507 sc->sc_ndev = pa->pa_device; 508 sc->sc_nfunc = pa->pa_function; 509 sc->sc_locked = 0; 510 511 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 512 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 513 514 /* enable memory and IO access */ 515 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 516 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 517 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 518 519 for (bar = 0; bar < NBARS; bar++) { 520 reg = PCI_MAPREG_START + (bar * 4); 521 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 522 sc->sc_pcitag, reg); 523 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 524 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 525 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 526 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 527 sc->sc_pcitag, reg)&0xfffffff0; 528 } 529 sc->sc_memt = pa->pa_memt; 530 531 mach64_init(sc); 532 533 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 534 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 535 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 536 (u_int)sc->sc_regphys); 537 538 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 539 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 540 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 541 (mach64_chip_rev & 0x07) == 0)) 542 sc->has_dsp = 0; 543 else 544 sc->has_dsp = 1; 545 546 sc->memsize = mach64_get_memsize(sc); 547 if (sc->memsize == 8192) 548 /* The last page is used as register aperture. */ 549 sc->memsize -= 4; 550 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 551 552 /* XXX is there any way to calculate reference frequency from 553 known values? */ 554 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 555 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 556 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 557 printf("%s: ref_freq=29.498MHz\n", sc->sc_dev.dv_xname); 558 sc->ref_freq = 29498; 559 } else 560 sc->ref_freq = 14318; 561 562 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 563 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 564 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 565 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 566 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 567 (sc->ref_div * 2); 568 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 569 (sc->mem_freq * sc->ref_div); 570 sc->ramdac_freq = mach64_get_max_ramdac(sc); 571 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 572 sc->sc_dev.dv_xname, (u_long)sc->memsize, 573 mach64_memtype_names[sc->memtype], 574 sc->mem_freq / 1000, sc->mem_freq % 1000, 575 sc->ramdac_freq / 1000); 576 577 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 578 if (id != mach64_chip_id) { 579 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 580 sc->sc_dev.dv_xname, id, mach64_chip_id); 581 return; 582 } 583 584 sc->sc_console = mach64_is_console(pa); 585 #ifdef DIAGNOSTIC 586 printf("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 587 #endif 588 #if defined(__sparc__) || defined(__powerpc__) 589 if (sc->sc_console) { 590 mach64_get_mode(sc, &default_mode); 591 setmode = 0; 592 sc->sc_my_mode = &default_mode; 593 } else { 594 /* fill in default_mode if it's empty */ 595 mach64_get_mode(sc, &default_mode); 596 if (default_mode.dot_clock == 0) { 597 memcpy(&default_mode, &mach64_modes[4], 598 sizeof(default_mode)); 599 } 600 sc->sc_my_mode = &default_mode; 601 setmode = 1; 602 } 603 #else 604 if (default_mode.dot_clock == 0) { 605 memcpy(&default_mode, &mach64_modes[0], 606 sizeof(default_mode)); 607 } 608 sc->sc_my_mode = &mach64_modes[0]; 609 setmode = 1; 610 #endif 611 612 sc->bits_per_pixel = 8; 613 sc->virt_x = sc->sc_my_mode->hdisplay; 614 sc->virt_y = sc->sc_my_mode->vdisplay; 615 sc->max_x = sc->virt_x - 1; 616 sc->max_y = (sc->memsize * 1024) / 617 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 618 619 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 620 621 mach64_init_engine(sc); 622 #if 0 623 mach64_adjust_frame(0, 0); 624 if (sc->bits_per_pixel == 8) 625 mach64_init_lut(sc); 626 #endif 627 628 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 629 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 630 sc->bits_per_pixel); 631 632 #ifdef __sparc__ 633 machfb_fbattach(sc); 634 #endif 635 636 wsfont_init(); 637 638 sc->sc_bg = WS_DEFAULT_BG; 639 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 640 sc->vd.init_screen = mach64_init_screen; 641 642 if (sc->sc_console) { 643 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 644 &defattr); 645 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 646 647 ri = &mach64_console_screen.scr_ri; 648 mach64_defaultscreen.textops = &ri->ri_ops; 649 mach64_defaultscreen.capabilities = ri->ri_caps; 650 mach64_defaultscreen.nrows = ri->ri_rows; 651 mach64_defaultscreen.ncols = ri->ri_cols; 652 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 653 } else { 654 /* 655 * since we're not the console we can postpone the rest 656 * until someone actually allocates a screen for us 657 */ 658 mach64_modeswitch(sc, sc->sc_my_mode); 659 } 660 661 mach64_init_lut(sc); 662 mach64_clearscreen(sc); 663 machfb_blank(sc, 0); /* unblank the screen */ 664 665 aa.console = sc->sc_console; 666 aa.scrdata = &mach64_screenlist; 667 aa.accessops = &mach64_accessops; 668 aa.accesscookie = &sc->vd; 669 670 config_found(self, &aa, wsemuldisplaydevprint); 671 } 672 673 static void 674 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 675 long *defattr) 676 { 677 struct mach64_softc *sc = cookie; 678 struct rasops_info *ri = &scr->scr_ri; 679 680 /* XXX for now */ 681 #define setmode 0 682 683 ri->ri_depth = sc->bits_per_pixel; 684 ri->ri_width = sc->sc_my_mode->hdisplay; 685 ri->ri_height = sc->sc_my_mode->vdisplay; 686 ri->ri_stride = ri->ri_width; 687 ri->ri_flg = RI_CENTER; 688 set_address(ri, sc->sc_aperture); 689 690 if (existing) { 691 ri->ri_flg |= RI_CLEAR; 692 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 693 panic("%s: failed to switch video mode", 694 sc->sc_dev.dv_xname); 695 } 696 } 697 698 rasops_init(ri, sc->sc_my_mode->vdisplay/8, 699 sc->sc_my_mode->hdisplay/8); 700 ri->ri_caps = WSSCREEN_WSCOLORS; 701 702 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 703 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 704 705 /* enable acceleration */ 706 ri->ri_hw = scr; 707 ri->ri_ops.copyrows = mach64_copyrows; 708 ri->ri_ops.copycols = mach64_copycols; 709 ri->ri_ops.eraserows = mach64_eraserows; 710 ri->ri_ops.erasecols = mach64_erasecols; 711 ri->ri_ops.cursor = mach64_cursor; 712 ri->ri_ops.putchar = mach64_putchar; 713 ri->ri_ops.allocattr = mach64_allocattr; 714 } 715 716 static void 717 mach64_init(struct mach64_softc *sc) 718 { 719 uint32_t *p32, saved_value; 720 uint8_t *p; 721 int need_swap; 722 723 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 724 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 725 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 726 } 727 sc->sc_aperture = (caddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 728 729 sc->sc_regt = sc->sc_memt; 730 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 731 sc->sc_regsize, &sc->sc_regh); 732 sc->sc_registers = sc->sc_aperture + 0x7ffc00; 733 734 /* 735 * Test wether the aperture is byte swapped or not 736 */ 737 p32 = (uint32_t*)sc->sc_aperture; 738 saved_value = *p32; 739 p = (uint8_t*)(u_long)sc->sc_aperture; 740 *p32 = 0x12345678; 741 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 742 need_swap = 0; 743 else 744 need_swap = 1; 745 if (need_swap) { 746 sc->sc_aperture += 0x800000; 747 sc->sc_aperbase += 0x800000; 748 sc->sc_apersize -= 0x800000; 749 } 750 *p32 = saved_value; 751 752 sc->sc_blanked = 0; 753 } 754 755 static int 756 mach64_get_memsize(struct mach64_softc *sc) 757 { 758 int tmp, memsize; 759 int mem_tab[] = { 760 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 761 }; 762 tmp = regr(sc, MEM_CNTL); 763 #ifdef DIAGNOSTIC 764 printf("%s: memctl %08x\n", sc->sc_dev.dv_xname, tmp); 765 #endif 766 if (sc->has_dsp) { 767 tmp &= 0x0000000f; 768 if (tmp < 8) 769 memsize = (tmp + 1) * 512; 770 else if (tmp < 12) 771 memsize = (tmp - 3) * 1024; 772 else 773 memsize = (tmp - 7) * 2048; 774 } else { 775 memsize = mem_tab[tmp & 0x07]; 776 } 777 778 return memsize; 779 } 780 781 static int 782 mach64_get_max_ramdac(struct mach64_softc *sc) 783 { 784 int i; 785 786 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 787 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 788 (mach64_chip_rev & 0x07)) 789 return 170000; 790 791 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 792 if (mach64_chip_id == mach64_info[i].chip_id) 793 return mach64_info[i].ramdac_freq; 794 795 if (sc->bits_per_pixel == 8) 796 return 135000; 797 else 798 return 80000; 799 } 800 801 #if defined(__sparc__) || defined(__powerpc__) 802 static void 803 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 804 { 805 struct mach64_crtcregs crtc; 806 807 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 808 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 809 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 810 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 811 812 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 813 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 814 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 815 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 816 mode->hsync_start; 817 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 818 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 819 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 820 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 821 822 #ifndef DEBUG_MACHFB 823 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 824 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 825 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 826 #endif 827 } 828 #endif 829 830 static int 831 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 832 struct videomode *mode) 833 { 834 835 if (mode->dot_clock > sc->ramdac_freq) 836 /* Clock too high. */ 837 return 1; 838 839 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 840 ((mode->htotal >> 3) - 1); 841 crtc->h_sync_strt_wid = 842 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 843 ((mode->hsync_start >> 3) - 1); 844 845 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 846 (mode->vtotal - 1); 847 crtc->v_sync_strt_wid = 848 ((mode->vsync_end - mode->vsync_start) << 16) | 849 (mode->vsync_start - 1); 850 851 if (mode->flags & VID_NVSYNC) 852 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 853 854 switch (sc->bits_per_pixel) { 855 case 8: 856 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 857 break; 858 case 16: 859 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 860 break; 861 case 32: 862 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 863 break; 864 } 865 866 crtc->gen_cntl = 0; 867 if (mode->flags & VID_INTERLACE) 868 crtc->gen_cntl |= CRTC_INTERLACE_EN; 869 870 if (mode->flags & VID_CSYNC) 871 crtc->gen_cntl |= CRTC_CSYNC_EN; 872 873 crtc->dot_clock = mode->dot_clock; 874 875 return 0; 876 } 877 878 static void 879 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 880 { 881 882 mach64_set_pll(sc, crtc->dot_clock); 883 884 if (sc->has_dsp) 885 mach64_set_dsp(sc); 886 887 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 888 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 889 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 890 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 891 892 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 893 894 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 895 896 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 897 /* XXX this unconditionally enables composite sync on SPARC */ 898 #ifdef __sparc__ 899 CRTC_CSYNC_EN | 900 #endif 901 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 902 } 903 904 static int 905 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 906 { 907 struct mach64_crtcregs crtc; 908 909 if (mach64_calc_crtcregs(sc, &crtc, mode)) 910 return 1; 911 912 mach64_set_crtcregs(sc, &crtc); 913 return 0; 914 } 915 916 static void 917 mach64_reset_engine(struct mach64_softc *sc) 918 { 919 920 /* Reset engine.*/ 921 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 922 923 /* Enable engine. */ 924 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 925 926 /* Ensure engine is not locked up by clearing any FIFO or 927 host errors. */ 928 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 929 BUS_FIFO_ERR_ACK); 930 } 931 932 static void 933 mach64_init_engine(struct mach64_softc *sc) 934 { 935 uint32_t pitch_value; 936 937 pitch_value = sc->virt_x; 938 939 if (sc->bits_per_pixel == 24) 940 pitch_value *= 3; 941 942 mach64_reset_engine(sc); 943 944 wait_for_fifo(sc, 14); 945 946 regw(sc, CONTEXT_MASK, 0xffffffff); 947 948 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 949 950 regw(sc, DST_Y_X, 0); 951 regw(sc, DST_HEIGHT, 0); 952 regw(sc, DST_BRES_ERR, 0); 953 regw(sc, DST_BRES_INC, 0); 954 regw(sc, DST_BRES_DEC, 0); 955 956 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 957 DST_Y_TOP_TO_BOTTOM); 958 959 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 960 961 regw(sc, SRC_Y_X, 0); 962 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 963 regw(sc, SRC_Y_X_START, 0); 964 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 965 966 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 967 968 wait_for_fifo(sc, 13); 969 regw(sc, HOST_CNTL, 0); 970 971 regw(sc, PAT_REG0, 0); 972 regw(sc, PAT_REG1, 0); 973 regw(sc, PAT_CNTL, 0); 974 975 regw(sc, SC_LEFT, 0); 976 regw(sc, SC_TOP, 0); 977 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 978 regw(sc, SC_RIGHT, pitch_value - 1); 979 980 regw(sc, DP_BKGD_CLR, 0); 981 regw(sc, DP_FRGD_CLR, 0xffffffff); 982 regw(sc, DP_WRITE_MASK, 0xffffffff); 983 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 984 985 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 986 987 wait_for_fifo(sc, 3); 988 regw(sc, CLR_CMP_CLR, 0); 989 regw(sc, CLR_CMP_MASK, 0xffffffff); 990 regw(sc, CLR_CMP_CNTL, 0); 991 992 wait_for_fifo(sc, 2); 993 switch (sc->bits_per_pixel) { 994 case 8: 995 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 996 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 997 /* We want 8 bit per channel */ 998 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 999 break; 1000 #if 0 1001 case 32: 1002 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 1003 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1004 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1005 break; 1006 #endif 1007 } 1008 1009 wait_for_fifo(sc, 5); 1010 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1011 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1012 1013 wait_for_idle(sc); 1014 } 1015 1016 #if 0 1017 static void 1018 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1019 { 1020 int offset; 1021 1022 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1023 1024 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1025 offset); 1026 } 1027 #endif 1028 1029 static void 1030 mach64_set_dsp(struct mach64_softc *sc) 1031 { 1032 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1033 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1034 uint32_t xclks_per_qw, y; 1035 uint32_t fifo_off, fifo_on; 1036 1037 printf("%s: initializing the DSP\n", sc->sc_dev.dv_xname); 1038 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1039 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1040 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1041 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1042 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1043 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1044 dsp_loop_latency = 0; 1045 fifo_depth = 24; 1046 } else { 1047 dsp_loop_latency = 2; 1048 fifo_depth = 32; 1049 } 1050 1051 dsp_precision = 0; 1052 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1053 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1054 y = (xclks_per_qw * fifo_depth) >> 11; 1055 while (y) { 1056 y >>= 1; 1057 dsp_precision++; 1058 } 1059 dsp_precision -= 5; 1060 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1061 1062 switch (sc->memtype) { 1063 case DRAM: 1064 case EDO_DRAM: 1065 case PSEUDO_EDO: 1066 if (sc->memsize > 1024) { 1067 page_size = 9; 1068 dsp_loop_latency += 6; 1069 } else { 1070 page_size = 10; 1071 if (sc->memtype == DRAM) 1072 dsp_loop_latency += 8; 1073 else 1074 dsp_loop_latency += 7; 1075 } 1076 break; 1077 case SDRAM: 1078 case SGRAM: 1079 if (sc->memsize > 1024) { 1080 page_size = 8; 1081 dsp_loop_latency += 8; 1082 } else { 1083 page_size = 10; 1084 dsp_loop_latency += 9; 1085 } 1086 break; 1087 default: 1088 page_size = 10; 1089 dsp_loop_latency += 9; 1090 break; 1091 } 1092 1093 if (xclks_per_qw >= (page_size << 11)) 1094 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1095 else 1096 fifo_on = (3 * page_size + 2) << 6; 1097 1098 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1099 dsp_on = fifo_on >> dsp_precision; 1100 dsp_off = fifo_off >> dsp_precision; 1101 1102 #ifdef DEBUG_MACHFB 1103 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1104 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1105 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1106 "mclk_post_div = %d, vclk_post_div = %d\n", 1107 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1108 sc->mclk_fb_div, sc->vclk_fb_div, 1109 sc->mclk_post_div, sc->vclk_post_div); 1110 #endif 1111 1112 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1113 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1114 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1115 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1116 } 1117 1118 static void 1119 mach64_set_pll(struct mach64_softc *sc, int clock) 1120 { 1121 int q; 1122 1123 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1124 #ifdef DEBUG_MACHFB 1125 printf("q = %d\n", q); 1126 #endif 1127 if (q > 25500) { 1128 printf("Warning: q > 25500\n"); 1129 q = 25500; 1130 sc->vclk_post_div = 1; 1131 sc->log2_vclk_post_div = 0; 1132 } else if (q > 12750) { 1133 sc->vclk_post_div = 1; 1134 sc->log2_vclk_post_div = 0; 1135 } else if (q > 6350) { 1136 sc->vclk_post_div = 2; 1137 sc->log2_vclk_post_div = 1; 1138 } else if (q > 3150) { 1139 sc->vclk_post_div = 4; 1140 sc->log2_vclk_post_div = 2; 1141 } else if (q >= 1600) { 1142 sc->vclk_post_div = 8; 1143 sc->log2_vclk_post_div = 3; 1144 } else { 1145 printf("Warning: q < 1600\n"); 1146 sc->vclk_post_div = 8; 1147 sc->log2_vclk_post_div = 3; 1148 } 1149 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1150 1151 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1152 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1153 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1154 } 1155 1156 static void 1157 mach64_init_lut(struct mach64_softc *sc) 1158 { 1159 int i, idx; 1160 1161 idx = 0; 1162 for (i = 0; i < 256; i++) { 1163 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1164 rasops_cmap[idx + 2]); 1165 idx += 3; 1166 } 1167 } 1168 1169 static int 1170 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1171 uint8_t b) 1172 { 1173 sc->sc_cmap_red[index] = r; 1174 sc->sc_cmap_green[index] = g; 1175 sc->sc_cmap_blue[index] = b; 1176 /* 1177 * writing the dac index takes a while, in theory we can poll some 1178 * register to see when it's ready - but we better avoid writing it 1179 * unnecessarily 1180 */ 1181 if (index != sc->sc_dacw) { 1182 regwb(sc, DAC_MASK, 0xff); 1183 regwb(sc, DAC_WINDEX, index); 1184 } 1185 sc->sc_dacw = index + 1; 1186 regwb(sc, DAC_DATA, r); 1187 regwb(sc, DAC_DATA, g); 1188 regwb(sc, DAC_DATA, b); 1189 return 0; 1190 } 1191 1192 static int 1193 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1194 { 1195 uint index = cm->index; 1196 uint count = cm->count; 1197 int i, error; 1198 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1199 uint8_t *r, *g, *b; 1200 1201 if (cm->index >= 256 || cm->count > 256 || 1202 (cm->index + cm->count) > 256) 1203 return EINVAL; 1204 error = copyin(cm->red, &rbuf[index], count); 1205 if (error) 1206 return error; 1207 error = copyin(cm->green, &gbuf[index], count); 1208 if (error) 1209 return error; 1210 error = copyin(cm->blue, &bbuf[index], count); 1211 if (error) 1212 return error; 1213 1214 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1215 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1216 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1217 1218 r = &sc->sc_cmap_red[index]; 1219 g = &sc->sc_cmap_green[index]; 1220 b = &sc->sc_cmap_blue[index]; 1221 1222 for (i = 0; i < count; i++) { 1223 mach64_putpalreg(sc, index, *r, *g, *b); 1224 index++; 1225 r++, g++, b++; 1226 } 1227 return 0; 1228 } 1229 1230 static int 1231 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1232 { 1233 u_int index = cm->index; 1234 u_int count = cm->count; 1235 int error; 1236 1237 if (index >= 255 || count > 256 || index + count > 256) 1238 return EINVAL; 1239 1240 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1241 if (error) 1242 return error; 1243 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1244 if (error) 1245 return error; 1246 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1247 if (error) 1248 return error; 1249 1250 return 0; 1251 } 1252 1253 static int 1254 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1255 { 1256 struct mach64_crtcregs regs; 1257 1258 if (mach64_calc_crtcregs(sc, ®s, 1259 (struct videomode *)des->modecookie)) 1260 return 1; 1261 1262 mach64_set_crtcregs(sc, ®s); 1263 return 0; 1264 } 1265 1266 static int 1267 mach64_is_console(struct pci_attach_args *pa) 1268 { 1269 #ifdef __sparc__ 1270 int node; 1271 1272 node = PCITAG_NODE(pa->pa_tag); 1273 if (node == -1) 1274 return 0; 1275 1276 return (node == prom_instance_to_package(prom_stdout())); 1277 #elif defined(__powerpc__) 1278 /* check if we're the /chosen console device */ 1279 int chosen, stdout, node, us; 1280 1281 us = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1282 chosen = OF_finddevice("/chosen"); 1283 OF_getprop(chosen, "stdout", &stdout, 4); 1284 node = OF_instance_to_package(stdout); 1285 return (us == node); 1286 #else 1287 return 1; 1288 #endif 1289 } 1290 1291 /* 1292 * wsdisplay_emulops 1293 */ 1294 1295 static void 1296 mach64_cursor(void *cookie, int on, int row, int col) 1297 { 1298 struct rasops_info *ri = cookie; 1299 struct vcons_screen *scr = ri->ri_hw; 1300 struct mach64_softc *sc = scr->scr_cookie; 1301 int x, y, wi, he; 1302 1303 wi = ri->ri_font->fontwidth; 1304 he = ri->ri_font->fontheight; 1305 1306 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1307 x = ri->ri_ccol * wi + ri->ri_xorigin; 1308 y = ri->ri_crow * he + ri->ri_yorigin; 1309 if (ri->ri_flg & RI_CURSOR) { 1310 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1311 0xff); 1312 ri->ri_flg &= ~RI_CURSOR; 1313 } 1314 ri->ri_crow = row; 1315 ri->ri_ccol = col; 1316 if (on) { 1317 x = ri->ri_ccol * wi + ri->ri_xorigin; 1318 y = ri->ri_crow * he + ri->ri_yorigin; 1319 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1320 0xff); 1321 ri->ri_flg |= RI_CURSOR;; 1322 } 1323 } else { 1324 scr->scr_ri.ri_crow = row; 1325 scr->scr_ri.ri_ccol = col; 1326 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1327 } 1328 } 1329 1330 #if 0 1331 static int 1332 mach64_mapchar(void *cookie, int uni, u_int *index) 1333 { 1334 return 0; 1335 } 1336 #endif 1337 1338 static void 1339 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1340 { 1341 struct rasops_info *ri = cookie; 1342 struct vcons_screen *scr = ri->ri_hw; 1343 struct mach64_softc *sc = scr->scr_cookie; 1344 1345 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1346 int fg, bg, uc; 1347 uint8_t *data; 1348 int x, y, wi, he; 1349 wi = ri->ri_font->fontwidth; 1350 he = ri->ri_font->fontheight; 1351 1352 if (!CHAR_IN_FONT(c, ri->ri_font)) 1353 return; 1354 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1355 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1356 x = ri->ri_xorigin + col * wi; 1357 y = ri->ri_yorigin + row * he; 1358 if (c == 0x20) { 1359 mach64_rectfill(sc, x, y, wi, he, bg); 1360 } else { 1361 uc = c-ri->ri_font->firstchar; 1362 data = (uint8_t *)ri->ri_font->data + uc * 1363 ri->ri_fontscale; 1364 1365 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1366 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1367 } 1368 } 1369 } 1370 1371 1372 static void 1373 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1374 { 1375 struct rasops_info *ri = cookie; 1376 struct vcons_screen *scr = ri->ri_hw; 1377 struct mach64_softc *sc = scr->scr_cookie; 1378 int32_t xs, xd, y, width, height; 1379 1380 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1381 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1382 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1383 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1384 width = ri->ri_font->fontwidth * ncols; 1385 height = ri->ri_font->fontheight; 1386 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1387 } 1388 } 1389 1390 static void 1391 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1392 { 1393 struct rasops_info *ri = cookie; 1394 struct vcons_screen *scr = ri->ri_hw; 1395 struct mach64_softc *sc = scr->scr_cookie; 1396 int32_t x, y, width, height, fg, bg, ul; 1397 1398 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1399 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1400 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1401 width = ri->ri_font->fontwidth * ncols; 1402 height = ri->ri_font->fontheight; 1403 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1404 1405 mach64_rectfill(sc, x, y, width, height, bg); 1406 } 1407 } 1408 1409 static void 1410 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1411 { 1412 struct rasops_info *ri = cookie; 1413 struct vcons_screen *scr = ri->ri_hw; 1414 struct mach64_softc *sc = scr->scr_cookie; 1415 int32_t x, ys, yd, width, height; 1416 1417 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1418 x = ri->ri_xorigin; 1419 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1420 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1421 width = ri->ri_emuwidth; 1422 height = ri->ri_font->fontheight*nrows; 1423 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1424 } 1425 } 1426 1427 static void 1428 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1429 { 1430 struct rasops_info *ri = cookie; 1431 struct vcons_screen *scr = ri->ri_hw; 1432 struct mach64_softc *sc = scr->scr_cookie; 1433 int32_t x, y, width, height, fg, bg, ul; 1434 1435 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1436 x = ri->ri_xorigin; 1437 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1438 width = ri->ri_emuwidth; 1439 height = ri->ri_font->fontheight * nrows; 1440 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1441 1442 mach64_rectfill(sc, x, y, width, height, bg); 1443 } 1444 } 1445 1446 static void 1447 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1448 { 1449 uint32_t dest_ctl = 0; 1450 1451 wait_for_idle(sc); 1452 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1453 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1454 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1455 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1456 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1457 if (yd < ys) { 1458 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1459 } else { 1460 ys += height - 1; 1461 yd += height - 1; 1462 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1463 } 1464 if (xd < xs) { 1465 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1466 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1467 } else { 1468 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1469 xs += width - 1; 1470 xd += width - 1; 1471 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1472 } 1473 regw(sc, DST_CNTL, dest_ctl); 1474 1475 regw(sc, SRC_Y_X, (xs << 16) | ys); 1476 regw(sc, SRC_WIDTH1, width); 1477 regw(sc, DST_Y_X, (xd << 16) | yd); 1478 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1479 } 1480 1481 static void 1482 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1483 int height, uint32_t fg, uint32_t bg) 1484 { 1485 wait_for_idle(sc); 1486 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1487 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1488 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1489 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1490 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1491 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1492 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1493 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1494 regw(sc, DP_BKGD_CLR, bg); 1495 regw(sc, DP_FRGD_CLR, fg); 1496 regw(sc, SRC_Y_X, 0); 1497 regw(sc, SRC_WIDTH1, width); 1498 regw(sc, DST_Y_X, (xd << 16) | yd); 1499 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1500 /* now feed the data into the chip */ 1501 } 1502 1503 static void 1504 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1505 { 1506 int i; 1507 uint32_t latch = 0, bork; 1508 int shift = 0; 1509 int reg = 0; 1510 1511 for (i=0;i<count;i++) { 1512 bork = data[i]; 1513 latch |= (bork << shift); 1514 if (shift == 24) { 1515 regw(sc, HOST_DATA0 + reg, latch); 1516 latch = 0; 1517 shift = 0; 1518 reg = (reg + 4) & 0x3c; 1519 } else 1520 shift += 8; 1521 } 1522 if (shift != 0) /* 24 */ 1523 regw(sc, HOST_DATA0 + reg, latch); 1524 } 1525 1526 1527 static void 1528 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1529 int colour) 1530 { 1531 wait_for_idle(sc); 1532 regw(sc, DP_WRITE_MASK, 0xff); 1533 regw(sc, DP_FRGD_CLR, colour); 1534 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1535 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1536 regw(sc, DP_MIX, MIX_SRC << 16); 1537 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1538 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1539 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1540 1541 regw(sc, SRC_Y_X, (x << 16) | y); 1542 regw(sc, SRC_WIDTH1, width); 1543 regw(sc, DST_Y_X, (x << 16) | y); 1544 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1545 } 1546 1547 static void 1548 mach64_clearscreen(struct mach64_softc *sc) 1549 { 1550 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1551 } 1552 1553 1554 #if 0 1555 static void 1556 mach64_showpal(struct mach64_softc *sc) 1557 { 1558 int i, x = 0; 1559 1560 for (i = 0; i < 16; i++) { 1561 mach64_rectfill(sc, x, 0, 64, 64, i); 1562 x += 64; 1563 } 1564 } 1565 #endif 1566 1567 static int 1568 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1569 { 1570 if ((fg == 0) && (bg == 0)) 1571 { 1572 fg = WS_DEFAULT_FG; 1573 bg = WS_DEFAULT_BG; 1574 } 1575 *attrp = (fg & 0xf) << 24 | (bg & 0xf) << 16 | (flags & 0xff) << 8; 1576 return 0; 1577 } 1578 1579 /* 1580 * wsdisplay_accessops 1581 */ 1582 1583 static int 1584 mach64_ioctl(void *v, void *vs, u_long cmd, caddr_t data, int flag, 1585 struct lwp *l) 1586 { 1587 struct vcons_data *vd = v; 1588 struct mach64_softc *sc = vd->cookie; 1589 struct wsdisplay_fbinfo *wdf; 1590 struct vcons_screen *ms = vd->active; 1591 1592 switch (cmd) { 1593 case WSDISPLAYIO_GTYPE: 1594 /* XXX is this the right type to return? */ 1595 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1596 return 0; 1597 1598 case WSDISPLAYIO_GINFO: 1599 wdf = (void *)data; 1600 wdf->height = sc->virt_y; 1601 wdf->width = sc->virt_x; 1602 wdf->depth = sc->color_depth; 1603 wdf->cmsize = 256; 1604 return 0; 1605 1606 case WSDISPLAYIO_GETCMAP: 1607 return mach64_getcmap(sc, 1608 (struct wsdisplay_cmap *)data); 1609 1610 case WSDISPLAYIO_PUTCMAP: 1611 return mach64_putcmap(sc, 1612 (struct wsdisplay_cmap *)data); 1613 1614 /* PCI config read/write passthrough. */ 1615 case PCI_IOC_CFGREAD: 1616 case PCI_IOC_CFGWRITE: 1617 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1618 cmd, data, flag, l)); 1619 1620 case WSDISPLAYIO_SMODE: 1621 { 1622 int new_mode = *(int*)data; 1623 1624 if (new_mode != sc->sc_mode) 1625 { 1626 sc->sc_mode = new_mode; 1627 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1628 && (ms != NULL)) 1629 { 1630 vcons_redraw_screen(ms); 1631 } 1632 } 1633 } 1634 return 0; 1635 1636 } 1637 return EPASSTHROUGH; 1638 } 1639 1640 static paddr_t 1641 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1642 { 1643 struct vcons_data *vd = v; 1644 struct mach64_softc *sc = vd->cookie; 1645 paddr_t pa; 1646 pcireg_t reg; 1647 1648 #ifndef __sparc64__ 1649 /* 1650 *'regular' framebuffer mmap()ing 1651 * disabled on sparc64 because some ATI firmware likes to map some PCI 1652 * resources to addresses that would collide with this ( like some Rage 1653 * IIc which uses 0x2000 for the 2nd register block ) 1654 * Other 64bit architectures might run into similar problems. 1655 */ 1656 if (offset<sc->sc_apersize) { 1657 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1658 prot, BUS_SPACE_MAP_LINEAR); 1659 return pa; 1660 } 1661 #endif 1662 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1663 if (reg != sc->sc_regphys) { 1664 #ifdef DIAGNOSTIC 1665 printf("%s: BAR 0x18 changed! (%x %x)\n", 1666 sc->sc_dev.dv_xname, (uint32_t)sc->sc_regphys, 1667 (uint32_t)reg); 1668 #endif 1669 sc->sc_regphys = reg; 1670 } 1671 1672 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1673 if (reg != sc->sc_aperphys) { 1674 #ifdef DIAGNOSTIC 1675 printf("%s: BAR 0x10 changed! (%x %x)\n", 1676 sc->sc_dev.dv_xname, (uint32_t)sc->sc_aperphys, 1677 (uint32_t)reg); 1678 #endif 1679 sc->sc_aperphys = reg; 1680 } 1681 1682 #if 0 1683 /* evil hack to allow mmap()ing other devices as well */ 1684 if ((offset > 0x80000000) && (offset <= 0xffffffff)) { 1685 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1686 BUS_SPACE_MAP_LINEAR); 1687 return pa; 1688 } 1689 #endif 1690 1691 if ((offset >= sc->sc_aperphys) && 1692 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1693 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1694 BUS_SPACE_MAP_LINEAR); 1695 return pa; 1696 } 1697 1698 if ((offset >= sc->sc_regphys) && 1699 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1700 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1701 BUS_SPACE_MAP_LINEAR); 1702 return pa; 1703 } 1704 1705 return -1; 1706 } 1707 1708 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1709 static void 1710 set_address(struct rasops_info *ri, caddr_t fb) 1711 { 1712 #ifdef notdef 1713 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1714 #endif 1715 ri->ri_bits = (void *)(fb + ri->ri_stride * ri->ri_yorigin + 1716 ri->ri_xorigin); 1717 } 1718 1719 #if 0 1720 static int 1721 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1722 { 1723 1724 return 0; 1725 } 1726 #endif 1727 1728 void 1729 machfb_blank(struct mach64_softc *sc, int blank) 1730 { 1731 uint32_t reg; 1732 1733 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1734 1735 switch (blank) 1736 { 1737 case 0: 1738 reg = regr(sc, CRTC_GEN_CNTL); 1739 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1740 sc->sc_blanked = 0; 1741 break; 1742 case 1: 1743 reg = regr(sc, CRTC_GEN_CNTL); 1744 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1745 sc->sc_blanked = 1; 1746 break; 1747 default: 1748 break; 1749 } 1750 } 1751 1752 /* framebuffer device support */ 1753 #ifdef __sparc__ 1754 1755 static void 1756 machfb_unblank(struct device *dev) 1757 { 1758 struct mach64_softc *sc = (struct mach64_softc *)dev; 1759 1760 machfb_blank(sc, 0); 1761 } 1762 1763 static void 1764 machfb_fbattach(struct mach64_softc *sc) 1765 { 1766 struct fbdevice *fb = &sc->sc_fb; 1767 1768 fb->fb_device = &sc->sc_dev; 1769 fb->fb_driver = &machfb_fbdriver; 1770 1771 fb->fb_type.fb_cmsize = 256; 1772 fb->fb_type.fb_size = sc->memsize; 1773 1774 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1775 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags & FB_USERMASK; 1776 fb->fb_type.fb_depth = sc->bits_per_pixel; 1777 fb->fb_type.fb_width = sc->virt_x; 1778 fb->fb_type.fb_height = sc->virt_y; 1779 1780 fb->fb_pixels = sc->sc_aperture; 1781 fb_attach(fb, sc->sc_console); 1782 } 1783 1784 int 1785 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1786 { 1787 struct mach64_softc *sc; 1788 int unit = minor(dev); 1789 1790 sc = machfb_cd.cd_devs[unit]; 1791 sc->sc_locked = 1; 1792 1793 #ifdef DEBUG_MACHFB 1794 printf("machfb_fbopen(%d)\n", unit); 1795 #endif 1796 if (unit > machfb_cd.cd_ndevs || machfb_cd.cd_devs[unit] == NULL) 1797 return ENXIO; 1798 return 0; 1799 } 1800 1801 int 1802 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1803 { 1804 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1805 1806 #ifdef DEBUG_MACHFB 1807 printf("machfb_fbclose()\n"); 1808 #endif 1809 mach64_init_engine(sc); 1810 mach64_init_lut(sc); 1811 sc->sc_locked = 0; 1812 return 0; 1813 } 1814 1815 int 1816 machfb_fbioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct lwp *l) 1817 { 1818 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1819 1820 #ifdef DEBUG_MACHFB 1821 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1822 #endif 1823 switch (cmd) { 1824 case FBIOGTYPE: 1825 *(struct fbtype *)data = sc->sc_fb.fb_type; 1826 break; 1827 1828 case FBIOGATTR: 1829 #define fba ((struct fbgattr *)data) 1830 fba->real_type = sc->sc_fb.fb_type.fb_type; 1831 fba->owner = 0; /* XXX ??? */ 1832 fba->fbtype = sc->sc_fb.fb_type; 1833 fba->sattr.flags = 0; 1834 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1835 fba->sattr.dev_specific[0] = sc->sc_nbus; 1836 fba->sattr.dev_specific[1] = sc->sc_ndev; 1837 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1838 fba->sattr.dev_specific[3] = -1; 1839 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1840 fba->emu_types[1] = -1; 1841 #undef fba 1842 break; 1843 1844 #if 0 1845 case FBIOGETCMAP: 1846 #define p ((struct fbcmap *)data) 1847 return (bt_getcmap(p, &sc->sc_cmap, 256, 1)); 1848 1849 case FBIOPUTCMAP: 1850 /* copy to software map */ 1851 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1852 if (error) 1853 return error; 1854 /* now blast them into the chip */ 1855 /* XXX should use retrace interrupt */ 1856 cg6_loadcmap(sc, p->index, p->count); 1857 #undef p 1858 break; 1859 #endif 1860 case FBIOGVIDEO: 1861 *(int *)data = sc->sc_blanked; 1862 break; 1863 1864 case FBIOSVIDEO: 1865 machfb_blank(sc, *(int *)data); 1866 break; 1867 1868 #if 0 1869 case FBIOGCURSOR: 1870 break; 1871 1872 case FBIOSCURSOR: 1873 break; 1874 1875 case FBIOGCURPOS: 1876 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 1877 break; 1878 1879 case FBIOSCURPOS: 1880 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 1881 break; 1882 1883 case FBIOGCURMAX: 1884 /* max cursor size is 32x32 */ 1885 ((struct fbcurpos *)data)->x = 32; 1886 ((struct fbcurpos *)data)->y = 32; 1887 break; 1888 #endif 1889 case PCI_IOC_CFGREAD: 1890 case PCI_IOC_CFGWRITE: 1891 { 1892 int ret; 1893 1894 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1895 cmd, data, flags, l); 1896 1897 #ifdef DEBUG_MACHFB 1898 printf("pci_devioctl: %d\n", ret); 1899 #endif 1900 return ret; 1901 } 1902 default: 1903 #ifdef DEBUG_MACHFB 1904 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 1905 p->p_comm, p->p_pid); 1906 #endif 1907 return ENOTTY; 1908 } 1909 #ifdef DEBUG_MACHFB 1910 printf("machfb_fbioctl done\n"); 1911 #endif 1912 return 0; 1913 } 1914 1915 paddr_t 1916 machfb_fbmmap(dev_t dev, off_t off, int prot) 1917 { 1918 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1919 1920 if (sc != NULL) 1921 return mach64_mmap(&sc->vd, NULL, off, prot); 1922 1923 return 0; 1924 } 1925 1926 #endif /* __sparc__ */ 1927
Indexes created Thu Oct 02 14:10:14 GMT 2025